drivers/gpu/drm/tilcdc/tilcdc_crtc.c

   1 /*
   2  * Copyright (C) 2012 Texas Instruments
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <drm/drm_atomic.h>
  19 #include <drm/drm_atomic_helper.h>
  20 #include <drm/drm_crtc.h>
  21 #include <drm/drm_flip_work.h>
  22 #include <drm/drm_plane_helper.h>
  23 #include <linux/workqueue.h>
  24 #include <linux/completion.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/of_graph.h>
  27 #include <linux/math64.h>
  28
  29 #include "tilcdc_drv.h"
  30 #include "tilcdc_regs.h"
  31
  32 #define TILCDC_VBLANK_SAFETY_THRESHOLD_US       1000
  33 #define TILCDC_PALETTE_SIZE                     32
  34 #define TILCDC_PALETTE_FIRST_ENTRY              0x4000
  35
  36 struct tilcdc_crtc {
  37         struct drm_crtc base;
  38
  39         struct drm_plane primary;
  40         const struct tilcdc_panel_info *info;
  41         struct drm_pending_vblank_event *event;
  42         struct mutex enable_lock;
  43         bool enabled;
  44         bool shutdown;
  45         wait_queue_head_t frame_done_wq;
  46         bool frame_done;
  47         spinlock_t irq_lock;
  48
  49         unsigned int lcd_fck_rate;
  50
  51         ktime_t last_vblank;
  52         unsigned int hvtotal_us;
  53
  54         struct drm_framebuffer *curr_fb;
  55         struct drm_framebuffer *next_fb;
  56
  57         /* for deferred fb unref's: */
  58         struct drm_flip_work unref_work;
  59
  60         /* Only set if an external encoder is connected */
  61         bool simulate_vesa_sync;
  62
  63         int sync_lost_count;
  64         bool frame_intact;
  65         struct work_struct recover_work;
  66
  67         dma_addr_t palette_dma_handle;
  68         u16 *palette_base;
  69         struct completion palette_loaded;
  70 };
  71 #define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base)
  72
  73 static void unref_worker(struct drm_flip_work *work, void *val)
  74 {
  75         struct tilcdc_crtc *tilcdc_crtc =
  76                 container_of(work, struct tilcdc_crtc, unref_work);
  77         struct drm_device *dev = tilcdc_crtc->base.dev;
  78
  79         mutex_lock(&dev->mode_config.mutex);
  80         drm_framebuffer_unreference(val);
  81         mutex_unlock(&dev->mode_config.mutex);
  82 }
  83
  84 static void set_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb)
  85 {
  86         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
  87         struct drm_device *dev = crtc->dev;
  88         struct tilcdc_drm_private *priv = dev->dev_private;
  89         struct drm_gem_cma_object *gem;
  90         dma_addr_t start, end;
  91         u64 dma_base_and_ceiling;
  92
  93         gem = drm_fb_cma_get_gem_obj(fb, 0);
  94
  95         start = gem->paddr + fb->offsets[0] +
  96                 crtc->y * fb->pitches[0] +
  97                 crtc->x * fb->format->cpp[0];
  98
  99         end = start + (crtc->mode.vdisplay * fb->pitches[0]);
 100
 101         /* Write LCDC_DMA_FB_BASE_ADDR_0_REG and LCDC_DMA_FB_CEILING_ADDR_0_REG
 102          * with a single insruction, if available. This should make it more
 103          * unlikely that LCDC would fetch the DMA addresses in the middle of
 104          * an update.
 105          */
 106         if (priv->rev == 1)
 107                 end -= 1;
 108
 109         dma_base_and_ceiling = (u64)end << 32 | start;
 110         tilcdc_write64(dev, LCDC_DMA_FB_BASE_ADDR_0_REG, dma_base_and_ceiling);
 111
 112         if (tilcdc_crtc->curr_fb)
 113                 drm_flip_work_queue(&tilcdc_crtc->unref_work,
 114                         tilcdc_crtc->curr_fb);
 115
 116         tilcdc_crtc->curr_fb = fb;
 117 }
 118
 119 /*
 120  * The driver currently only supports only true color formats. For
 121  * true color the palette block is bypassed, but a 32 byte palette
 122  * should still be loaded. The first 16-bit entry must be 0x4000 while
 123  * all other entries must be zeroed.
 124  */
 125 static void tilcdc_crtc_load_palette(struct drm_crtc *crtc)
 126 {
 127         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 128         struct drm_device *dev = crtc->dev;
 129         struct tilcdc_drm_private *priv = dev->dev_private;
 130         int ret;
 131
 132         reinit_completion(&tilcdc_crtc->palette_loaded);
 133
 134         /* Tell the LCDC where the palette is located. */
 135         tilcdc_write(dev, LCDC_DMA_FB_BASE_ADDR_0_REG,
 136                      tilcdc_crtc->palette_dma_handle);
 137         tilcdc_write(dev, LCDC_DMA_FB_CEILING_ADDR_0_REG,
 138                      (u32) tilcdc_crtc->palette_dma_handle +
 139                      TILCDC_PALETTE_SIZE - 1);
 140
 141         /* Set dma load mode for palette loading only. */
 142         tilcdc_write_mask(dev, LCDC_RASTER_CTRL_REG,
 143                           LCDC_PALETTE_LOAD_MODE(PALETTE_ONLY),
 144                           LCDC_PALETTE_LOAD_MODE_MASK);
 145
 146         /* Enable DMA Palette Loaded Interrupt */
 147         if (priv->rev == 1)
 148                 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_PL_INT_ENA);
 149         else
 150                 tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG, LCDC_V2_PL_INT_ENA);
 151
 152         /* Enable LCDC DMA and wait for palette to be loaded. */
 153         tilcdc_clear_irqstatus(dev, 0xffffffff);
 154         tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
 155
 156         ret = wait_for_completion_timeout(&tilcdc_crtc->palette_loaded,
 157                                           msecs_to_jiffies(50));
 158         if (ret == 0)
 159                 dev_err(dev->dev, "%s: Palette loading timeout", __func__);
 160
 161         /* Disable LCDC DMA and DMA Palette Loaded Interrupt. */
 162         tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
 163         if (priv->rev == 1)
 164                 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_PL_INT_ENA);
 165         else
 166                 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG, LCDC_V2_PL_INT_ENA);
 167 }
 168
 169 static void tilcdc_crtc_enable_irqs(struct drm_device *dev)
 170 {
 171         struct tilcdc_drm_private *priv = dev->dev_private;
 172
 173         tilcdc_clear_irqstatus(dev, 0xffffffff);
 174
 175         if (priv->rev == 1) {
 176                 tilcdc_set(dev, LCDC_RASTER_CTRL_REG,
 177                         LCDC_V1_SYNC_LOST_INT_ENA | LCDC_V1_FRAME_DONE_INT_ENA |
 178                         LCDC_V1_UNDERFLOW_INT_ENA);
 179                 tilcdc_set(dev, LCDC_DMA_CTRL_REG,
 180                         LCDC_V1_END_OF_FRAME_INT_ENA);
 181         } else {
 182                 tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG,
 183                         LCDC_V2_UNDERFLOW_INT_ENA |
 184                         LCDC_V2_END_OF_FRAME0_INT_ENA |
 185                         LCDC_FRAME_DONE | LCDC_SYNC_LOST);
 186         }
 187 }
 188
 189 static void tilcdc_crtc_disable_irqs(struct drm_device *dev)
 190 {
 191         struct tilcdc_drm_private *priv = dev->dev_private;
 192
 193         /* disable irqs that we might have enabled: */
 194         if (priv->rev == 1) {
 195                 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
 196                         LCDC_V1_SYNC_LOST_INT_ENA | LCDC_V1_FRAME_DONE_INT_ENA |
 197                         LCDC_V1_UNDERFLOW_INT_ENA | LCDC_V1_PL_INT_ENA);
 198                 tilcdc_clear(dev, LCDC_DMA_CTRL_REG,
 199                         LCDC_V1_END_OF_FRAME_INT_ENA);
 200         } else {
 201                 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,
 202                         LCDC_V2_UNDERFLOW_INT_ENA | LCDC_V2_PL_INT_ENA |
 203                         LCDC_V2_END_OF_FRAME0_INT_ENA |
 204                         LCDC_FRAME_DONE | LCDC_SYNC_LOST);
 205         }
 206 }
 207
 208 static void reset(struct drm_crtc *crtc)
 209 {
 210         struct drm_device *dev = crtc->dev;
 211         struct tilcdc_drm_private *priv = dev->dev_private;
 212
 213         if (priv->rev != 2)
 214                 return;
 215
 216         tilcdc_set(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
 217         usleep_range(250, 1000);
 218         tilcdc_clear(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
 219 }
 220
 221 /*
 222  * Calculate the percentage difference between the requested pixel clock rate
 223  * and the effective rate resulting from calculating the clock divider value.
 224  */
 225 static unsigned int tilcdc_pclk_diff(unsigned long rate,
 226                                      unsigned long real_rate)
 227 {
 228         int r = rate / 100, rr = real_rate / 100;
 229
 230         return (unsigned int)(abs(((rr - r) * 100) / r));
 231 }
 232
 233 static void tilcdc_crtc_set_clk(struct drm_crtc *crtc)
 234 {
 235         struct drm_device *dev = crtc->dev;
 236         struct tilcdc_drm_private *priv = dev->dev_private;
 237         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 238         unsigned long clk_rate, real_rate, req_rate;
 239         unsigned int clkdiv;
 240         int ret;
 241
 242         clkdiv = 2; /* first try using a standard divider of 2 */
 243
 244         /* mode.clock is in KHz, set_rate wants parameter in Hz */
 245         req_rate = crtc->mode.clock * 1000;
 246
 247         ret = clk_set_rate(priv->clk, req_rate * clkdiv);
 248         clk_rate = clk_get_rate(priv->clk);
 249         if (ret < 0) {
 250                 /*
 251                  * If we fail to set the clock rate (some architectures don't
 252                  * use the common clock framework yet and may not implement
 253                  * all the clk API calls for every clock), try the next best
 254                  * thing: adjusting the clock divider, unless clk_get_rate()
 255                  * failed as well.
 256                  */
 257                 if (!clk_rate) {
 258                         /* Nothing more we can do. Just bail out. */
 259                         dev_err(dev->dev,
 260                                 "failed to set the pixel clock - unable to read current lcdc clock rate\n");
 261                         return;
 262                 }
 263
 264                 clkdiv = DIV_ROUND_CLOSEST(clk_rate, req_rate);
 265
 266                 /*
 267                  * Emit a warning if the real clock rate resulting from the
 268                  * calculated divider differs much from the requested rate.
 269                  *
 270                  * 5% is an arbitrary value - LCDs are usually quite tolerant
 271                  * about pixel clock rates.
 272                  */
 273                 real_rate = clkdiv * req_rate;
 274
 275                 if (tilcdc_pclk_diff(clk_rate, real_rate) > 5) {
 276                         dev_warn(dev->dev,
 277                                  "effective pixel clock rate (%luHz) differs from the calculated rate (%luHz)\n",
 278                                  clk_rate, real_rate);
 279                 }
 280         }
 281
 282         tilcdc_crtc->lcd_fck_rate = clk_rate;
 283
 284         DBG("lcd_clk=%u, mode clock=%d, div=%u",
 285             tilcdc_crtc->lcd_fck_rate, crtc->mode.clock, clkdiv);
 286
 287         /* Configure the LCD clock divisor. */
 288         tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(clkdiv) |
 289                      LCDC_RASTER_MODE);
 290
 291         if (priv->rev == 2)
 292                 tilcdc_set(dev, LCDC_CLK_ENABLE_REG,
 293                                 LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN |
 294                                 LCDC_V2_CORE_CLK_EN);
 295 }
 296
 297 uint tilcdc_mode_hvtotal(const struct drm_display_mode *mode)
 298 {
 299         return (uint) div_u64(1000llu * mode->htotal * mode->vtotal,
 300                               mode->clock);
 301 }
 302
 303 static void tilcdc_crtc_set_mode(struct drm_crtc *crtc)
 304 {
 305         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 306         struct drm_device *dev = crtc->dev;
 307         struct tilcdc_drm_private *priv = dev->dev_private;
 308         const struct tilcdc_panel_info *info = tilcdc_crtc->info;
 309         uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw;
 310         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 311         struct drm_framebuffer *fb = crtc->primary->state->fb;
 312
 313         if (WARN_ON(!info))
 314                 return;
 315
 316         if (WARN_ON(!fb))
 317                 return;
 318
 319         /* Configure the Burst Size and fifo threshold of DMA: */
 320         reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770;
 321         switch (info->dma_burst_sz) {
 322         case 1:
 323                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1);
 324                 break;
 325         case 2:
 326                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2);
 327                 break;
 328         case 4:
 329                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4);
 330                 break;
 331         case 8:
 332                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8);
 333                 break;
 334         case 16:
 335                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16);
 336                 break;
 337         default:
 338                 dev_err(dev->dev, "invalid burst size\n");
 339                 return;
 340         }
 341         reg |= (info->fifo_th << 8);
 342         tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg);
 343
 344         /* Configure timings: */
 345         hbp = mode->htotal - mode->hsync_end;
 346         hfp = mode->hsync_start - mode->hdisplay;
 347         hsw = mode->hsync_end - mode->hsync_start;
 348         vbp = mode->vtotal - mode->vsync_end;
 349         vfp = mode->vsync_start - mode->vdisplay;
 350         vsw = mode->vsync_end - mode->vsync_start;
 351
 352         DBG("%dx%d, hbp=%u, hfp=%u, hsw=%u, vbp=%u, vfp=%u, vsw=%u",
 353             mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw);
 354
 355         /* Set AC Bias Period and Number of Transitions per Interrupt: */
 356         reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00;
 357         reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) |
 358                 LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt);
 359
 360         /*
 361          * subtract one from hfp, hbp, hsw because the hardware uses
 362          * a value of 0 as 1
 363          */
 364         if (priv->rev == 2) {
 365                 /* clear bits we're going to set */
 366                 reg &= ~0x78000033;
 367                 reg |= ((hfp-1) & 0x300) >> 8;
 368                 reg |= ((hbp-1) & 0x300) >> 4;
 369                 reg |= ((hsw-1) & 0x3c0) << 21;
 370         }
 371         tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg);
 372
 373         reg = (((mode->hdisplay >> 4) - 1) << 4) |
 374                 (((hbp-1) & 0xff) << 24) |
 375                 (((hfp-1) & 0xff) << 16) |
 376                 (((hsw-1) & 0x3f) << 10);
 377         if (priv->rev == 2)
 378                 reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3;
 379         tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg);
 380
 381         reg = ((mode->vdisplay - 1) & 0x3ff) |
 382                 ((vbp & 0xff) << 24) |
 383                 ((vfp & 0xff) << 16) |
 384                 (((vsw-1) & 0x3f) << 10);
 385         tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg);
 386
 387         /*
 388          * be sure to set Bit 10 for the V2 LCDC controller,
 389          * otherwise limited to 1024 pixels width, stopping
 390          * 1920x1080 being supported.
 391          */
 392         if (priv->rev == 2) {
 393                 if ((mode->vdisplay - 1) & 0x400) {
 394                         tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG,
 395                                 LCDC_LPP_B10);
 396                 } else {
 397                         tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG,
 398                                 LCDC_LPP_B10);
 399                 }
 400         }
 401
 402         /* Configure display type: */
 403         reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) &
 404                 ~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE |
 405                   LCDC_V2_TFT_24BPP_MODE | LCDC_V2_TFT_24BPP_UNPACK |
 406                   0x000ff000 /* Palette Loading Delay bits */);
 407         reg |= LCDC_TFT_MODE; /* no monochrome/passive support */
 408         if (info->tft_alt_mode)
 409                 reg |= LCDC_TFT_ALT_ENABLE;
 410         if (priv->rev == 2) {
 411                 switch (fb->format->format) {
 412                 case DRM_FORMAT_BGR565:
 413                 case DRM_FORMAT_RGB565:
 414                         break;
 415                 case DRM_FORMAT_XBGR8888:
 416                 case DRM_FORMAT_XRGB8888:
 417                         reg |= LCDC_V2_TFT_24BPP_UNPACK;
 418                         /* fallthrough */
 419                 case DRM_FORMAT_BGR888:
 420                 case DRM_FORMAT_RGB888:
 421                         reg |= LCDC_V2_TFT_24BPP_MODE;
 422                         break;
 423                 default:
 424                         dev_err(dev->dev, "invalid pixel format\n");
 425                         return;
 426                 }
 427         }
 428         reg |= info->fdd < 12;
 429         tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg);
 430
 431         if (info->invert_pxl_clk)
 432                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
 433         else
 434                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
 435
 436         if (info->sync_ctrl)
 437                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
 438         else
 439                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
 440
 441         if (info->sync_edge)
 442                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
 443         else
 444                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
 445
 446         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 447                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
 448         else
 449                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
 450
 451         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 452                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
 453         else
 454                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
 455
 456         if (info->raster_order)
 457                 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
 458         else
 459                 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
 460
 461         tilcdc_crtc_set_clk(crtc);
 462
 463         tilcdc_crtc_load_palette(crtc);
 464
 465         set_scanout(crtc, fb);
 466
 467         drm_framebuffer_reference(fb);
 468
 469         crtc->hwmode = crtc->state->adjusted_mode;
 470
 471         tilcdc_crtc->hvtotal_us =
 472                 tilcdc_mode_hvtotal(&crtc->hwmode);
 473 }
 474
 475 static void tilcdc_crtc_enable(struct drm_crtc *crtc)
 476 {
 477         struct drm_device *dev = crtc->dev;
 478         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 479         unsigned long flags;
 480
 481         WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
 482         mutex_lock(&tilcdc_crtc->enable_lock);
 483         if (tilcdc_crtc->enabled || tilcdc_crtc->shutdown) {
 484                 mutex_unlock(&tilcdc_crtc->enable_lock);
 485                 return;
 486         }
 487
 488         pm_runtime_get_sync(dev->dev);
 489
 490         reset(crtc);
 491
 492         tilcdc_crtc_set_mode(crtc);
 493
 494         tilcdc_crtc_enable_irqs(dev);
 495
 496         tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE);
 497         tilcdc_write_mask(dev, LCDC_RASTER_CTRL_REG,
 498                           LCDC_PALETTE_LOAD_MODE(DATA_ONLY),
 499                           LCDC_PALETTE_LOAD_MODE_MASK);
 500
 501         /* There is no real chance for a race here as the time stamp
 502          * is taken before the raster DMA is started. The spin-lock is
 503          * taken to have a memory barrier after taking the time-stamp
 504          * and to avoid a context switch between taking the stamp and
 505          * enabling the raster.
 506          */
 507         spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
 508         tilcdc_crtc->last_vblank = ktime_get();
 509         tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
 510         spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
 511
 512         drm_crtc_vblank_on(crtc);
 513
 514         tilcdc_crtc->enabled = true;
 515         mutex_unlock(&tilcdc_crtc->enable_lock);
 516 }
 517
 518 static void tilcdc_crtc_atomic_enable(struct drm_crtc *crtc,
 519                                       struct drm_crtc_state *old_state)
 520 {
 521         tilcdc_crtc_enable(crtc);
 522 }
 523
 524 static void tilcdc_crtc_off(struct drm_crtc *crtc, bool shutdown)
 525 {
 526         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 527         struct drm_device *dev = crtc->dev;
 528         struct tilcdc_drm_private *priv = dev->dev_private;
 529         int ret;
 530
 531         mutex_lock(&tilcdc_crtc->enable_lock);
 532         if (shutdown)
 533                 tilcdc_crtc->shutdown = true;
 534         if (!tilcdc_crtc->enabled) {
 535                 mutex_unlock(&tilcdc_crtc->enable_lock);
 536                 return;
 537         }
 538         tilcdc_crtc->frame_done = false;
 539         tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
 540
 541         /*
 542          * Wait for framedone irq which will still come before putting
 543          * things to sleep..
 544          */
 545         ret = wait_event_timeout(tilcdc_crtc->frame_done_wq,
 546                                  tilcdc_crtc->frame_done,
 547                                  msecs_to_jiffies(500));
 548         if (ret == 0)
 549                 dev_err(dev->dev, "%s: timeout waiting for framedone\n",
 550                         __func__);
 551
 552         drm_crtc_vblank_off(crtc);
 553
 554         tilcdc_crtc_disable_irqs(dev);
 555
 556         pm_runtime_put_sync(dev->dev);
 557
 558         if (tilcdc_crtc->next_fb) {
 559                 drm_flip_work_queue(&tilcdc_crtc->unref_work,
 560                                     tilcdc_crtc->next_fb);
 561                 tilcdc_crtc->next_fb = NULL;
 562         }
 563
 564         if (tilcdc_crtc->curr_fb) {
 565                 drm_flip_work_queue(&tilcdc_crtc->unref_work,
 566                                     tilcdc_crtc->curr_fb);
 567                 tilcdc_crtc->curr_fb = NULL;
 568         }
 569
 570         drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq);
 571
 572         tilcdc_crtc->enabled = false;
 573         mutex_unlock(&tilcdc_crtc->enable_lock);
 574 }
 575
 576 static void tilcdc_crtc_disable(struct drm_crtc *crtc)
 577 {
 578         WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
 579         tilcdc_crtc_off(crtc, false);
 580 }
 581
 582 static void tilcdc_crtc_atomic_disable(struct drm_crtc *crtc,
 583                                        struct drm_crtc_state *old_state)
 584 {
 585         tilcdc_crtc_disable(crtc);
 586 }
 587
 588 void tilcdc_crtc_shutdown(struct drm_crtc *crtc)
 589 {
 590         tilcdc_crtc_off(crtc, true);
 591 }
 592
 593 static bool tilcdc_crtc_is_on(struct drm_crtc *crtc)
 594 {
 595         return crtc->state && crtc->state->enable && crtc->state->active;
 596 }
 597
 598 static void tilcdc_crtc_recover_work(struct work_struct *work)
 599 {
 600         struct tilcdc_crtc *tilcdc_crtc =
 601                 container_of(work, struct tilcdc_crtc, recover_work);
 602         struct drm_crtc *crtc = &tilcdc_crtc->base;
 603
 604         dev_info(crtc->dev->dev, "%s: Reset CRTC", __func__);
 605
 606         drm_modeset_lock(&crtc->mutex, NULL);
 607
 608         if (!tilcdc_crtc_is_on(crtc))
 609                 goto out;
 610
 611         tilcdc_crtc_disable(crtc);
 612         tilcdc_crtc_enable(crtc);
 613 out:
 614         drm_modeset_unlock(&crtc->mutex);
 615 }
 616
 617 static void tilcdc_crtc_destroy(struct drm_crtc *crtc)
 618 {
 619         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 620         struct tilcdc_drm_private *priv = crtc->dev->dev_private;
 621
 622         drm_modeset_lock(&crtc->mutex, NULL);
 623         tilcdc_crtc_disable(crtc);
 624         drm_modeset_unlock(&crtc->mutex);
 625
 626         flush_workqueue(priv->wq);
 627
 628         of_node_put(crtc->port);
 629         drm_crtc_cleanup(crtc);
 630         drm_flip_work_cleanup(&tilcdc_crtc->unref_work);
 631 }
 632
 633 int tilcdc_crtc_update_fb(struct drm_crtc *crtc,
 634                 struct drm_framebuffer *fb,
 635                 struct drm_pending_vblank_event *event)
 636 {
 637         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 638         struct drm_device *dev = crtc->dev;
 639
 640         WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
 641
 642         if (tilcdc_crtc->event) {
 643                 dev_err(dev->dev, "already pending page flip!\n");
 644                 return -EBUSY;
 645         }
 646
 647         drm_framebuffer_reference(fb);
 648
 649         crtc->primary->fb = fb;
 650         tilcdc_crtc->event = event;
 651
 652         mutex_lock(&tilcdc_crtc->enable_lock);
 653
 654         if (tilcdc_crtc->enabled) {
 655                 unsigned long flags;
 656                 ktime_t next_vblank;
 657                 s64 tdiff;
 658
 659                 spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
 660
 661                 next_vblank = ktime_add_us(tilcdc_crtc->last_vblank,
 662                                            tilcdc_crtc->hvtotal_us);
 663                 tdiff = ktime_to_us(ktime_sub(next_vblank, ktime_get()));
 664
 665                 if (tdiff < TILCDC_VBLANK_SAFETY_THRESHOLD_US)
 666                         tilcdc_crtc->next_fb = fb;
 667                 else
 668                         set_scanout(crtc, fb);
 669
 670                 spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
 671         }
 672
 673         mutex_unlock(&tilcdc_crtc->enable_lock);
 674
 675         return 0;
 676 }
 677
 678 static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc,
 679                 const struct drm_display_mode *mode,
 680                 struct drm_display_mode *adjusted_mode)
 681 {
 682         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 683
 684         if (!tilcdc_crtc->simulate_vesa_sync)
 685                 return true;
 686
 687         /*
 688          * tilcdc does not generate VESA-compliant sync but aligns
 689          * VS on the second edge of HS instead of first edge.
 690          * We use adjusted_mode, to fixup sync by aligning both rising
 691          * edges and add HSKEW offset to fix the sync.
 692          */
 693         adjusted_mode->hskew = mode->hsync_end - mode->hsync_start;
 694         adjusted_mode->flags |= DRM_MODE_FLAG_HSKEW;
 695
 696         if (mode->flags & DRM_MODE_FLAG_NHSYNC) {
 697                 adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC;
 698                 adjusted_mode->flags &= ~DRM_MODE_FLAG_NHSYNC;
 699         } else {
 700                 adjusted_mode->flags |= DRM_MODE_FLAG_NHSYNC;
 701                 adjusted_mode->flags &= ~DRM_MODE_FLAG_PHSYNC;
 702         }
 703
 704         return true;
 705 }
 706
 707 static int tilcdc_crtc_atomic_check(struct drm_crtc *crtc,
 708                                     struct drm_crtc_state *state)
 709 {
 710         /* If we are not active we don't care */
 711         if (!state->active)
 712                 return 0;
 713
 714         if (state->state->planes[0].ptr != crtc->primary ||
 715             state->state->planes[0].state == NULL ||
 716             state->state->planes[0].state->crtc != crtc) {
 717                 dev_dbg(crtc->dev->dev, "CRTC primary plane must be present");
 718                 return -EINVAL;
 719         }
 720
 721         return 0;
 722 }
 723
 724 static int tilcdc_crtc_enable_vblank(struct drm_crtc *crtc)
 725 {
 726         return 0;
 727 }
 728
 729 static void tilcdc_crtc_disable_vblank(struct drm_crtc *crtc)
 730 {
 731 }
 732
 733 static const struct drm_crtc_funcs tilcdc_crtc_funcs = {
 734         .destroy        = tilcdc_crtc_destroy,
 735         .set_config     = drm_atomic_helper_set_config,
 736         .page_flip      = drm_atomic_helper_page_flip,
 737         .reset          = drm_atomic_helper_crtc_reset,
 738         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
 739         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
 740         .enable_vblank  = tilcdc_crtc_enable_vblank,
 741         .disable_vblank = tilcdc_crtc_disable_vblank,
 742 };
 743
 744 int tilcdc_crtc_max_width(struct drm_crtc *crtc)
 745 {
 746         struct drm_device *dev = crtc->dev;
 747         struct tilcdc_drm_private *priv = dev->dev_private;
 748         int max_width = 0;
 749
 750         if (priv->rev == 1)
 751                 max_width = 1024;
 752         else if (priv->rev == 2)
 753                 max_width = 2048;
 754
 755         return max_width;
 756 }
 757
 758 static enum drm_mode_status
 759 tilcdc_crtc_mode_valid(struct drm_crtc *crtc,
 760                        const struct drm_display_mode *mode)
 761 {
 762         struct tilcdc_drm_private *priv = crtc->dev->dev_private;
 763         unsigned int bandwidth;
 764         uint32_t hbp, hfp, hsw, vbp, vfp, vsw;
 765
 766         /*
 767          * check to see if the width is within the range that
 768          * the LCD Controller physically supports
 769          */
 770         if (mode->hdisplay > tilcdc_crtc_max_width(crtc))
 771                 return MODE_VIRTUAL_X;
 772
 773         /* width must be multiple of 16 */
 774         if (mode->hdisplay & 0xf)
 775                 return MODE_VIRTUAL_X;
 776
 777         if (mode->vdisplay > 2048)
 778                 return MODE_VIRTUAL_Y;
 779
 780         DBG("Processing mode %dx%d@%d with pixel clock %d",
 781                 mode->hdisplay, mode->vdisplay,
 782                 drm_mode_vrefresh(mode), mode->clock);
 783
 784         hbp = mode->htotal - mode->hsync_end;
 785         hfp = mode->hsync_start - mode->hdisplay;
 786         hsw = mode->hsync_end - mode->hsync_start;
 787         vbp = mode->vtotal - mode->vsync_end;
 788         vfp = mode->vsync_start - mode->vdisplay;
 789         vsw = mode->vsync_end - mode->vsync_start;
 790
 791         if ((hbp-1) & ~0x3ff) {
 792                 DBG("Pruning mode: Horizontal Back Porch out of range");
 793                 return MODE_HBLANK_WIDE;
 794         }
 795
 796         if ((hfp-1) & ~0x3ff) {
 797                 DBG("Pruning mode: Horizontal Front Porch out of range");
 798                 return MODE_HBLANK_WIDE;
 799         }
 800
 801         if ((hsw-1) & ~0x3ff) {
 802                 DBG("Pruning mode: Horizontal Sync Width out of range");
 803                 return MODE_HSYNC_WIDE;
 804         }
 805
 806         if (vbp & ~0xff) {
 807                 DBG("Pruning mode: Vertical Back Porch out of range");
 808                 return MODE_VBLANK_WIDE;
 809         }
 810
 811         if (vfp & ~0xff) {
 812                 DBG("Pruning mode: Vertical Front Porch out of range");
 813                 return MODE_VBLANK_WIDE;
 814         }
 815
 816         if ((vsw-1) & ~0x3f) {
 817                 DBG("Pruning mode: Vertical Sync Width out of range");
 818                 return MODE_VSYNC_WIDE;
 819         }
 820
 821         /*
 822          * some devices have a maximum allowed pixel clock
 823          * configured from the DT
 824          */
 825         if (mode->clock > priv->max_pixelclock) {
 826                 DBG("Pruning mode: pixel clock too high");
 827                 return MODE_CLOCK_HIGH;
 828         }
 829
 830         /*
 831          * some devices further limit the max horizontal resolution
 832          * configured from the DT
 833          */
 834         if (mode->hdisplay > priv->max_width)
 835                 return MODE_BAD_WIDTH;
 836
 837         /* filter out modes that would require too much memory bandwidth: */
 838         bandwidth = mode->hdisplay * mode->vdisplay *
 839                 drm_mode_vrefresh(mode);
 840         if (bandwidth > priv->max_bandwidth) {
 841                 DBG("Pruning mode: exceeds defined bandwidth limit");
 842                 return MODE_BAD;
 843         }
 844
 845         return MODE_OK;
 846 }
 847
 848 static const struct drm_crtc_helper_funcs tilcdc_crtc_helper_funcs = {
 849         .mode_valid     = tilcdc_crtc_mode_valid,
 850         .mode_fixup     = tilcdc_crtc_mode_fixup,
 851         .atomic_check   = tilcdc_crtc_atomic_check,
 852         .atomic_enable  = tilcdc_crtc_atomic_enable,
 853         .atomic_disable = tilcdc_crtc_atomic_disable,
 854 };
 855
 856 void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc,
 857                 const struct tilcdc_panel_info *info)
 858 {
 859         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 860         tilcdc_crtc->info = info;
 861 }
 862
 863 void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc,
 864                                         bool simulate_vesa_sync)
 865 {
 866         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 867
 868         tilcdc_crtc->simulate_vesa_sync = simulate_vesa_sync;
 869 }
 870
 871 void tilcdc_crtc_update_clk(struct drm_crtc *crtc)
 872 {
 873         struct drm_device *dev = crtc->dev;
 874         struct tilcdc_drm_private *priv = dev->dev_private;
 875         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 876
 877         drm_modeset_lock(&crtc->mutex, NULL);
 878         if (tilcdc_crtc->lcd_fck_rate != clk_get_rate(priv->clk)) {
 879                 if (tilcdc_crtc_is_on(crtc)) {
 880                         pm_runtime_get_sync(dev->dev);
 881                         tilcdc_crtc_disable(crtc);
 882
 883                         tilcdc_crtc_set_clk(crtc);
 884
 885                         tilcdc_crtc_enable(crtc);
 886                         pm_runtime_put_sync(dev->dev);
 887                 }
 888         }
 889         drm_modeset_unlock(&crtc->mutex);
 890 }
 891
 892 #define SYNC_LOST_COUNT_LIMIT 50
 893
 894 irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc)
 895 {
 896         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 897         struct drm_device *dev = crtc->dev;
 898         struct tilcdc_drm_private *priv = dev->dev_private;
 899         uint32_t stat, reg;
 900
 901         stat = tilcdc_read_irqstatus(dev);
 902         tilcdc_clear_irqstatus(dev, stat);
 903
 904         if (stat & LCDC_END_OF_FRAME0) {
 905                 unsigned long flags;
 906                 bool skip_event = false;
 907                 ktime_t now;
 908
 909                 now = ktime_get();
 910
 911                 drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq);
 912
 913                 spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
 914
 915                 tilcdc_crtc->last_vblank = now;
 916
 917                 if (tilcdc_crtc->next_fb) {
 918                         set_scanout(crtc, tilcdc_crtc->next_fb);
 919                         tilcdc_crtc->next_fb = NULL;
 920                         skip_event = true;
 921                 }
 922
 923                 spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
 924
 925                 drm_crtc_handle_vblank(crtc);
 926
 927                 if (!skip_event) {
 928                         struct drm_pending_vblank_event *event;
 929
 930                         spin_lock_irqsave(&dev->event_lock, flags);
 931
 932                         event = tilcdc_crtc->event;
 933                         tilcdc_crtc->event = NULL;
 934                         if (event)
 935                                 drm_crtc_send_vblank_event(crtc, event);
 936
 937                         spin_unlock_irqrestore(&dev->event_lock, flags);
 938                 }
 939
 940                 if (tilcdc_crtc->frame_intact)
 941                         tilcdc_crtc->sync_lost_count = 0;
 942                 else
 943                         tilcdc_crtc->frame_intact = true;
 944         }
 945
 946         if (stat & LCDC_FIFO_UNDERFLOW)
 947                 dev_err_ratelimited(dev->dev, "%s(0x%08x): FIFO underflow",
 948                                     __func__, stat);
 949
 950         if (stat & LCDC_PL_LOAD_DONE) {
 951                 complete(&tilcdc_crtc->palette_loaded);
 952                 if (priv->rev == 1)
 953                         tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
 954                                      LCDC_V1_PL_INT_ENA);
 955                 else
 956                         tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,
 957                                      LCDC_V2_PL_INT_ENA);
 958         }
 959
 960         if (stat & LCDC_SYNC_LOST) {
 961                 dev_err_ratelimited(dev->dev, "%s(0x%08x): Sync lost",
 962                                     __func__, stat);
 963                 tilcdc_crtc->frame_intact = false;
 964                 if (priv->rev == 1) {
 965                         reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG);
 966                         if (reg & LCDC_RASTER_ENABLE) {
 967                                 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
 968                                              LCDC_RASTER_ENABLE);
 969                                 tilcdc_set(dev, LCDC_RASTER_CTRL_REG,
 970                                            LCDC_RASTER_ENABLE);
 971                         }
 972                 } else {
 973                         if (tilcdc_crtc->sync_lost_count++ >
 974                             SYNC_LOST_COUNT_LIMIT) {
 975                                 dev_err(dev->dev,
 976                                         "%s(0x%08x): Sync lost flood detected, recovering",
 977                                         __func__, stat);
 978                                 queue_work(system_wq,
 979                                            &tilcdc_crtc->recover_work);
 980                                 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,
 981                                              LCDC_SYNC_LOST);
 982                                 tilcdc_crtc->sync_lost_count = 0;
 983                         }
 984                 }
 985         }
 986
 987         if (stat & LCDC_FRAME_DONE) {
 988                 tilcdc_crtc->frame_done = true;
 989                 wake_up(&tilcdc_crtc->frame_done_wq);
 990                 /* rev 1 lcdc appears to hang if irq is not disbaled here */
 991                 if (priv->rev == 1)
 992                         tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
 993                                      LCDC_V1_FRAME_DONE_INT_ENA);
 994         }
 995
 996         /* For revision 2 only */
 997         if (priv->rev == 2) {
 998                 /* Indicate to LCDC that the interrupt service routine has
 999                  * completed, see 13.3.6.1.6 in AM335x TRM.
1000                  */
1001                 tilcdc_write(dev, LCDC_END_OF_INT_IND_REG, 0);
1002         }
1003
1004         return IRQ_HANDLED;
1005 }
1006
1007 int tilcdc_crtc_create(struct drm_device *dev)
1008 {
1009         struct tilcdc_drm_private *priv = dev->dev_private;
1010         struct tilcdc_crtc *tilcdc_crtc;
1011         struct drm_crtc *crtc;
1012         int ret;
1013
1014         tilcdc_crtc = devm_kzalloc(dev->dev, sizeof(*tilcdc_crtc), GFP_KERNEL);
1015         if (!tilcdc_crtc) {
1016                 dev_err(dev->dev, "allocation failed\n");
1017                 return -ENOMEM;
1018         }
1019
1020         init_completion(&tilcdc_crtc->palette_loaded);
1021         tilcdc_crtc->palette_base = dmam_alloc_coherent(dev->dev,
1022                                         TILCDC_PALETTE_SIZE,
1023                                         &tilcdc_crtc->palette_dma_handle,
1024                                         GFP_KERNEL | __GFP_ZERO);
1025         if (!tilcdc_crtc->palette_base)
1026                 return -ENOMEM;
1027         *tilcdc_crtc->palette_base = TILCDC_PALETTE_FIRST_ENTRY;
1028
1029         crtc = &tilcdc_crtc->base;
1030
1031         ret = tilcdc_plane_init(dev, &tilcdc_crtc->primary);
1032         if (ret < 0)
1033                 goto fail;
1034
1035         mutex_init(&tilcdc_crtc->enable_lock);
1036
1037         init_waitqueue_head(&tilcdc_crtc->frame_done_wq);
1038
1039         drm_flip_work_init(&tilcdc_crtc->unref_work,
1040                         "unref", unref_worker);
1041
1042         spin_lock_init(&tilcdc_crtc->irq_lock);
1043         INIT_WORK(&tilcdc_crtc->recover_work, tilcdc_crtc_recover_work);
1044
1045         ret = drm_crtc_init_with_planes(dev, crtc,
1046                                         &tilcdc_crtc->primary,
1047                                         NULL,
1048                                         &tilcdc_crtc_funcs,
1049                                         "tilcdc crtc");
1050         if (ret < 0)
1051                 goto fail;
1052
1053         drm_crtc_helper_add(crtc, &tilcdc_crtc_helper_funcs);
1054
1055         if (priv->is_componentized) {
1056                 crtc->port = of_graph_get_port_by_id(dev->dev->of_node, 0);
1057                 if (!crtc->port) { /* This should never happen */
1058                         dev_err(dev->dev, "Port node not found in %pOF\n",
1059                                 dev->dev->of_node);
1060                         ret = -EINVAL;
1061                         goto fail;
1062                 }
1063         }
1064
1065         priv->crtc = crtc;
1066         return 0;
1067
1068 fail:
1069         tilcdc_crtc_destroy(crtc);
1070         return ret;
1071 }