drivers/gpu/drm/vc4/vc4_plane.c

   1 /*
   2  * Copyright (C) 2015 Broadcom
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /**
  10  * DOC: VC4 plane module
  11  *
  12  * Each DRM plane is a layer of pixels being scanned out by the HVS.
  13  *
  14  * At atomic modeset check time, we compute the HVS display element
  15  * state that would be necessary for displaying the plane (giving us a
  16  * chance to figure out if a plane configuration is invalid), then at
  17  * atomic flush time the CRTC will ask us to write our element state
  18  * into the region of the HVS that it has allocated for us.
  19  */
  20
  21 #include <drm/drm_atomic.h>
  22 #include <drm/drm_atomic_helper.h>
  23 #include <drm/drm_fb_cma_helper.h>
  24 #include <drm/drm_plane_helper.h>
  25
  26 #include "vc4_drv.h"
  27 #include "vc4_regs.h"
  28
  29 enum vc4_scaling_mode {
  30         VC4_SCALING_NONE,
  31         VC4_SCALING_TPZ,
  32         VC4_SCALING_PPF,
  33 };
  34
  35 struct vc4_plane_state {
  36         struct drm_plane_state base;
  37         /* System memory copy of the display list for this element, computed
  38          * at atomic_check time.
  39          */
  40         u32 *dlist;
  41         u32 dlist_size; /* Number of dwords allocated for the display list */
  42         u32 dlist_count; /* Number of used dwords in the display list. */
  43
  44         /* Offset in the dlist to various words, for pageflip or
  45          * cursor updates.
  46          */
  47         u32 pos0_offset;
  48         u32 pos2_offset;
  49         u32 ptr0_offset;
  50
  51         /* Offset where the plane's dlist was last stored in the
  52          * hardware at vc4_crtc_atomic_flush() time.
  53          */
  54         u32 __iomem *hw_dlist;
  55
  56         /* Clipped coordinates of the plane on the display. */
  57         int crtc_x, crtc_y, crtc_w, crtc_h;
  58         /* Clipped area being scanned from in the FB. */
  59         u32 src_x, src_y;
  60
  61         u32 src_w[2], src_h[2];
  62
  63         /* Scaling selection for the RGB/Y plane and the Cb/Cr planes. */
  64         enum vc4_scaling_mode x_scaling[2], y_scaling[2];
  65         bool is_unity;
  66         bool is_yuv;
  67
  68         /* Offset to start scanning out from the start of the plane's
  69          * BO.
  70          */
  71         u32 offsets[3];
  72
  73         /* Our allocation in LBM for temporary storage during scaling. */
  74         struct drm_mm_node lbm;
  75 };
  76
  77 static inline struct vc4_plane_state *
  78 to_vc4_plane_state(struct drm_plane_state *state)
  79 {
  80         return (struct vc4_plane_state *)state;
  81 }
  82
  83 static const struct hvs_format {
  84         u32 drm; /* DRM_FORMAT_* */
  85         u32 hvs; /* HVS_FORMAT_* */
  86         u32 pixel_order;
  87         bool has_alpha;
  88         bool flip_cbcr;
  89 } hvs_formats[] = {
  90         {
  91                 .drm = DRM_FORMAT_XRGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
  92                 .pixel_order = HVS_PIXEL_ORDER_ABGR, .has_alpha = false,
  93         },
  94         {
  95                 .drm = DRM_FORMAT_ARGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
  96                 .pixel_order = HVS_PIXEL_ORDER_ABGR, .has_alpha = true,
  97         },
  98         {
  99                 .drm = DRM_FORMAT_ABGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
 100                 .pixel_order = HVS_PIXEL_ORDER_ARGB, .has_alpha = true,
 101         },
 102         {
 103                 .drm = DRM_FORMAT_XBGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
 104                 .pixel_order = HVS_PIXEL_ORDER_ARGB, .has_alpha = false,
 105         },
 106         {
 107                 .drm = DRM_FORMAT_RGB565, .hvs = HVS_PIXEL_FORMAT_RGB565,
 108                 .pixel_order = HVS_PIXEL_ORDER_XRGB, .has_alpha = false,
 109         },
 110         {
 111                 .drm = DRM_FORMAT_BGR565, .hvs = HVS_PIXEL_FORMAT_RGB565,
 112                 .pixel_order = HVS_PIXEL_ORDER_XBGR, .has_alpha = false,
 113         },
 114         {
 115                 .drm = DRM_FORMAT_ARGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551,
 116                 .pixel_order = HVS_PIXEL_ORDER_ABGR, .has_alpha = true,
 117         },
 118         {
 119                 .drm = DRM_FORMAT_XRGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551,
 120                 .pixel_order = HVS_PIXEL_ORDER_ABGR, .has_alpha = false,
 121         },
 122         {
 123                 .drm = DRM_FORMAT_YUV422,
 124                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE,
 125         },
 126         {
 127                 .drm = DRM_FORMAT_YVU422,
 128                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE,
 129                 .flip_cbcr = true,
 130         },
 131         {
 132                 .drm = DRM_FORMAT_YUV420,
 133                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE,
 134         },
 135         {
 136                 .drm = DRM_FORMAT_YVU420,
 137                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE,
 138                 .flip_cbcr = true,
 139         },
 140         {
 141                 .drm = DRM_FORMAT_NV12,
 142                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE,
 143         },
 144         {
 145                 .drm = DRM_FORMAT_NV16,
 146                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE,
 147         },
 148 };
 149
 150 static const struct hvs_format *vc4_get_hvs_format(u32 drm_format)
 151 {
 152         unsigned i;
 153
 154         for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) {
 155                 if (hvs_formats[i].drm == drm_format)
 156                         return &hvs_formats[i];
 157         }
 158
 159         return NULL;
 160 }
 161
 162 static enum vc4_scaling_mode vc4_get_scaling_mode(u32 src, u32 dst)
 163 {
 164         if (dst > src)
 165                 return VC4_SCALING_PPF;
 166         else if (dst < src)
 167                 return VC4_SCALING_TPZ;
 168         else
 169                 return VC4_SCALING_NONE;
 170 }
 171
 172 static bool plane_enabled(struct drm_plane_state *state)
 173 {
 174         return state->fb && state->crtc;
 175 }
 176
 177 static struct drm_plane_state *vc4_plane_duplicate_state(struct drm_plane *plane)
 178 {
 179         struct vc4_plane_state *vc4_state;
 180
 181         if (WARN_ON(!plane->state))
 182                 return NULL;
 183
 184         vc4_state = kmemdup(plane->state, sizeof(*vc4_state), GFP_KERNEL);
 185         if (!vc4_state)
 186                 return NULL;
 187
 188         memset(&vc4_state->lbm, 0, sizeof(vc4_state->lbm));
 189
 190         __drm_atomic_helper_plane_duplicate_state(plane, &vc4_state->base);
 191
 192         if (vc4_state->dlist) {
 193                 vc4_state->dlist = kmemdup(vc4_state->dlist,
 194                                            vc4_state->dlist_count * 4,
 195                                            GFP_KERNEL);
 196                 if (!vc4_state->dlist) {
 197                         kfree(vc4_state);
 198                         return NULL;
 199                 }
 200                 vc4_state->dlist_size = vc4_state->dlist_count;
 201         }
 202
 203         return &vc4_state->base;
 204 }
 205
 206 static void vc4_plane_destroy_state(struct drm_plane *plane,
 207                                     struct drm_plane_state *state)
 208 {
 209         struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
 210         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 211
 212         if (vc4_state->lbm.allocated) {
 213                 unsigned long irqflags;
 214
 215                 spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags);
 216                 drm_mm_remove_node(&vc4_state->lbm);
 217                 spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags);
 218         }
 219
 220         kfree(vc4_state->dlist);
 221         __drm_atomic_helper_plane_destroy_state(&vc4_state->base);
 222         kfree(state);
 223 }
 224
 225 /* Called during init to allocate the plane's atomic state. */
 226 static void vc4_plane_reset(struct drm_plane *plane)
 227 {
 228         struct vc4_plane_state *vc4_state;
 229
 230         WARN_ON(plane->state);
 231
 232         vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
 233         if (!vc4_state)
 234                 return;
 235
 236         plane->state = &vc4_state->base;
 237         vc4_state->base.plane = plane;
 238 }
 239
 240 static void vc4_dlist_write(struct vc4_plane_state *vc4_state, u32 val)
 241 {
 242         if (vc4_state->dlist_count == vc4_state->dlist_size) {
 243                 u32 new_size = max(4u, vc4_state->dlist_count * 2);
 244                 u32 *new_dlist = kmalloc(new_size * 4, GFP_KERNEL);
 245
 246                 if (!new_dlist)
 247                         return;
 248                 memcpy(new_dlist, vc4_state->dlist, vc4_state->dlist_count * 4);
 249
 250                 kfree(vc4_state->dlist);
 251                 vc4_state->dlist = new_dlist;
 252                 vc4_state->dlist_size = new_size;
 253         }
 254
 255         vc4_state->dlist[vc4_state->dlist_count++] = val;
 256 }
 257
 258 /* Returns the scl0/scl1 field based on whether the dimensions need to
 259  * be up/down/non-scaled.
 260  *
 261  * This is a replication of a table from the spec.
 262  */
 263 static u32 vc4_get_scl_field(struct drm_plane_state *state, int plane)
 264 {
 265         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 266
 267         switch (vc4_state->x_scaling[plane] << 2 | vc4_state->y_scaling[plane]) {
 268         case VC4_SCALING_PPF << 2 | VC4_SCALING_PPF:
 269                 return SCALER_CTL0_SCL_H_PPF_V_PPF;
 270         case VC4_SCALING_TPZ << 2 | VC4_SCALING_PPF:
 271                 return SCALER_CTL0_SCL_H_TPZ_V_PPF;
 272         case VC4_SCALING_PPF << 2 | VC4_SCALING_TPZ:
 273                 return SCALER_CTL0_SCL_H_PPF_V_TPZ;
 274         case VC4_SCALING_TPZ << 2 | VC4_SCALING_TPZ:
 275                 return SCALER_CTL0_SCL_H_TPZ_V_TPZ;
 276         case VC4_SCALING_PPF << 2 | VC4_SCALING_NONE:
 277                 return SCALER_CTL0_SCL_H_PPF_V_NONE;
 278         case VC4_SCALING_NONE << 2 | VC4_SCALING_PPF:
 279                 return SCALER_CTL0_SCL_H_NONE_V_PPF;
 280         case VC4_SCALING_NONE << 2 | VC4_SCALING_TPZ:
 281                 return SCALER_CTL0_SCL_H_NONE_V_TPZ;
 282         case VC4_SCALING_TPZ << 2 | VC4_SCALING_NONE:
 283                 return SCALER_CTL0_SCL_H_TPZ_V_NONE;
 284         default:
 285         case VC4_SCALING_NONE << 2 | VC4_SCALING_NONE:
 286                 /* The unity case is independently handled by
 287                  * SCALER_CTL0_UNITY.
 288                  */
 289                 return 0;
 290         }
 291 }
 292
 293 static int vc4_plane_setup_clipping_and_scaling(struct drm_plane_state *state)
 294 {
 295         struct drm_plane *plane = state->plane;
 296         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 297         struct drm_framebuffer *fb = state->fb;
 298         struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0);
 299         u32 subpixel_src_mask = (1 << 16) - 1;
 300         u32 format = fb->format->format;
 301         int num_planes = fb->format->num_planes;
 302         u32 h_subsample = 1;
 303         u32 v_subsample = 1;
 304         int i;
 305
 306         for (i = 0; i < num_planes; i++)
 307                 vc4_state->offsets[i] = bo->paddr + fb->offsets[i];
 308
 309         /* We don't support subpixel source positioning for scaling. */
 310         if ((state->src_x & subpixel_src_mask) ||
 311             (state->src_y & subpixel_src_mask) ||
 312             (state->src_w & subpixel_src_mask) ||
 313             (state->src_h & subpixel_src_mask)) {
 314                 return -EINVAL;
 315         }
 316
 317         vc4_state->src_x = state->src_x >> 16;
 318         vc4_state->src_y = state->src_y >> 16;
 319         vc4_state->src_w[0] = state->src_w >> 16;
 320         vc4_state->src_h[0] = state->src_h >> 16;
 321
 322         vc4_state->crtc_x = state->crtc_x;
 323         vc4_state->crtc_y = state->crtc_y;
 324         vc4_state->crtc_w = state->crtc_w;
 325         vc4_state->crtc_h = state->crtc_h;
 326
 327         vc4_state->x_scaling[0] = vc4_get_scaling_mode(vc4_state->src_w[0],
 328                                                        vc4_state->crtc_w);
 329         vc4_state->y_scaling[0] = vc4_get_scaling_mode(vc4_state->src_h[0],
 330                                                        vc4_state->crtc_h);
 331
 332         vc4_state->is_unity = (vc4_state->x_scaling[0] == VC4_SCALING_NONE &&
 333                                vc4_state->y_scaling[0] == VC4_SCALING_NONE);
 334
 335         if (num_planes > 1) {
 336                 vc4_state->is_yuv = true;
 337
 338                 h_subsample = drm_format_horz_chroma_subsampling(format);
 339                 v_subsample = drm_format_vert_chroma_subsampling(format);
 340                 vc4_state->src_w[1] = vc4_state->src_w[0] / h_subsample;
 341                 vc4_state->src_h[1] = vc4_state->src_h[0] / v_subsample;
 342
 343                 vc4_state->x_scaling[1] =
 344                         vc4_get_scaling_mode(vc4_state->src_w[1],
 345                                              vc4_state->crtc_w);
 346                 vc4_state->y_scaling[1] =
 347                         vc4_get_scaling_mode(vc4_state->src_h[1],
 348                                              vc4_state->crtc_h);
 349
 350                 /* YUV conversion requires that horizontal scaling be enabled
 351                  * on the UV plane even if vc4_get_scaling_mode() returned
 352                  * VC4_SCALING_NONE (which can happen when the down-scaling
 353                  * ratio is 0.5). Let's force it to VC4_SCALING_PPF in this
 354                  * case.
 355                  */
 356                 if (vc4_state->x_scaling[1] == VC4_SCALING_NONE)
 357                         vc4_state->x_scaling[1] = VC4_SCALING_PPF;
 358         } else {
 359                 vc4_state->is_yuv = false;
 360                 vc4_state->x_scaling[1] = VC4_SCALING_NONE;
 361                 vc4_state->y_scaling[1] = VC4_SCALING_NONE;
 362         }
 363
 364         /* No configuring scaling on the cursor plane, since it gets
 365            non-vblank-synced updates, and scaling requires requires
 366            LBM changes which have to be vblank-synced.
 367          */
 368         if (plane->type == DRM_PLANE_TYPE_CURSOR && !vc4_state->is_unity)
 369                 return -EINVAL;
 370
 371         /* Clamp the on-screen start x/y to 0.  The hardware doesn't
 372          * support negative y, and negative x wastes bandwidth.
 373          */
 374         if (vc4_state->crtc_x < 0) {
 375                 for (i = 0; i < num_planes; i++) {
 376                         u32 cpp = fb->format->cpp[i];
 377                         u32 subs = ((i == 0) ? 1 : h_subsample);
 378
 379                         vc4_state->offsets[i] += (cpp *
 380                                                   (-vc4_state->crtc_x) / subs);
 381                 }
 382                 vc4_state->src_w[0] += vc4_state->crtc_x;
 383                 vc4_state->src_w[1] += vc4_state->crtc_x / h_subsample;
 384                 vc4_state->crtc_x = 0;
 385         }
 386
 387         if (vc4_state->crtc_y < 0) {
 388                 for (i = 0; i < num_planes; i++) {
 389                         u32 subs = ((i == 0) ? 1 : v_subsample);
 390
 391                         vc4_state->offsets[i] += (fb->pitches[i] *
 392                                                   (-vc4_state->crtc_y) / subs);
 393                 }
 394                 vc4_state->src_h[0] += vc4_state->crtc_y;
 395                 vc4_state->src_h[1] += vc4_state->crtc_y / v_subsample;
 396                 vc4_state->crtc_y = 0;
 397         }
 398
 399         return 0;
 400 }
 401
 402 static void vc4_write_tpz(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
 403 {
 404         u32 scale, recip;
 405
 406         scale = (1 << 16) * src / dst;
 407
 408         /* The specs note that while the reciprocal would be defined
 409          * as (1<<32)/scale, ~0 is close enough.
 410          */
 411         recip = ~0 / scale;
 412
 413         vc4_dlist_write(vc4_state,
 414                         VC4_SET_FIELD(scale, SCALER_TPZ0_SCALE) |
 415                         VC4_SET_FIELD(0, SCALER_TPZ0_IPHASE));
 416         vc4_dlist_write(vc4_state,
 417                         VC4_SET_FIELD(recip, SCALER_TPZ1_RECIP));
 418 }
 419
 420 static void vc4_write_ppf(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
 421 {
 422         u32 scale = (1 << 16) * src / dst;
 423
 424         vc4_dlist_write(vc4_state,
 425                         SCALER_PPF_AGC |
 426                         VC4_SET_FIELD(scale, SCALER_PPF_SCALE) |
 427                         VC4_SET_FIELD(0, SCALER_PPF_IPHASE));
 428 }
 429
 430 static u32 vc4_lbm_size(struct drm_plane_state *state)
 431 {
 432         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 433         /* This is the worst case number.  One of the two sizes will
 434          * be used depending on the scaling configuration.
 435          */
 436         u32 pix_per_line = max(vc4_state->src_w[0], (u32)vc4_state->crtc_w);
 437         u32 lbm;
 438
 439         if (!vc4_state->is_yuv) {
 440                 if (vc4_state->is_unity)
 441                         return 0;
 442                 else if (vc4_state->y_scaling[0] == VC4_SCALING_TPZ)
 443                         lbm = pix_per_line * 8;
 444                 else {
 445                         /* In special cases, this multiplier might be 12. */
 446                         lbm = pix_per_line * 16;
 447                 }
 448         } else {
 449                 /* There are cases for this going down to a multiplier
 450                  * of 2, but according to the firmware source, the
 451                  * table in the docs is somewhat wrong.
 452                  */
 453                 lbm = pix_per_line * 16;
 454         }
 455
 456         lbm = roundup(lbm, 32);
 457
 458         return lbm;
 459 }
 460
 461 static void vc4_write_scaling_parameters(struct drm_plane_state *state,
 462                                          int channel)
 463 {
 464         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 465
 466         /* Ch0 H-PPF Word 0: Scaling Parameters */
 467         if (vc4_state->x_scaling[channel] == VC4_SCALING_PPF) {
 468                 vc4_write_ppf(vc4_state,
 469                               vc4_state->src_w[channel], vc4_state->crtc_w);
 470         }
 471
 472         /* Ch0 V-PPF Words 0-1: Scaling Parameters, Context */
 473         if (vc4_state->y_scaling[channel] == VC4_SCALING_PPF) {
 474                 vc4_write_ppf(vc4_state,
 475                               vc4_state->src_h[channel], vc4_state->crtc_h);
 476                 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
 477         }
 478
 479         /* Ch0 H-TPZ Words 0-1: Scaling Parameters, Recip */
 480         if (vc4_state->x_scaling[channel] == VC4_SCALING_TPZ) {
 481                 vc4_write_tpz(vc4_state,
 482                               vc4_state->src_w[channel], vc4_state->crtc_w);
 483         }
 484
 485         /* Ch0 V-TPZ Words 0-2: Scaling Parameters, Recip, Context */
 486         if (vc4_state->y_scaling[channel] == VC4_SCALING_TPZ) {
 487                 vc4_write_tpz(vc4_state,
 488                               vc4_state->src_h[channel], vc4_state->crtc_h);
 489                 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
 490         }
 491 }
 492
 493 /* Writes out a full display list for an active plane to the plane's
 494  * private dlist state.
 495  */
 496 static int vc4_plane_mode_set(struct drm_plane *plane,
 497                               struct drm_plane_state *state)
 498 {
 499         struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
 500         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 501         struct drm_framebuffer *fb = state->fb;
 502         u32 ctl0_offset = vc4_state->dlist_count;
 503         const struct hvs_format *format = vc4_get_hvs_format(fb->format->format);
 504         int num_planes = drm_format_num_planes(format->drm);
 505         u32 scl0, scl1, pitch0;
 506         u32 lbm_size, tiling;
 507         unsigned long irqflags;
 508         int ret, i;
 509
 510         ret = vc4_plane_setup_clipping_and_scaling(state);
 511         if (ret)
 512                 return ret;
 513
 514         /* Allocate the LBM memory that the HVS will use for temporary
 515          * storage due to our scaling/format conversion.
 516          */
 517         lbm_size = vc4_lbm_size(state);
 518         if (lbm_size) {
 519                 if (!vc4_state->lbm.allocated) {
 520                         spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags);
 521                         ret = drm_mm_insert_node_generic(&vc4->hvs->lbm_mm,
 522                                                          &vc4_state->lbm,
 523                                                          lbm_size, 32, 0, 0);
 524                         spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags);
 525                 } else {
 526                         WARN_ON_ONCE(lbm_size != vc4_state->lbm.size);
 527                 }
 528         }
 529
 530         if (ret)
 531                 return ret;
 532
 533         /* SCL1 is used for Cb/Cr scaling of planar formats.  For RGB
 534          * and 4:4:4, scl1 should be set to scl0 so both channels of
 535          * the scaler do the same thing.  For YUV, the Y plane needs
 536          * to be put in channel 1 and Cb/Cr in channel 0, so we swap
 537          * the scl fields here.
 538          */
 539         if (num_planes == 1) {
 540                 scl0 = vc4_get_scl_field(state, 0);
 541                 scl1 = scl0;
 542         } else {
 543                 scl0 = vc4_get_scl_field(state, 1);
 544                 scl1 = vc4_get_scl_field(state, 0);
 545         }
 546
 547         switch (fb->modifier) {
 548         case DRM_FORMAT_MOD_LINEAR:
 549                 tiling = SCALER_CTL0_TILING_LINEAR;
 550                 pitch0 = VC4_SET_FIELD(fb->pitches[0], SCALER_SRC_PITCH);
 551                 break;
 552         case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED:
 553                 tiling = SCALER_CTL0_TILING_256B_OR_T;
 554
 555                 pitch0 = (VC4_SET_FIELD(0, SCALER_PITCH0_TILE_Y_OFFSET),
 556                           VC4_SET_FIELD(0, SCALER_PITCH0_TILE_WIDTH_L),
 557                           VC4_SET_FIELD((vc4_state->src_w[0] + 31) >> 5,
 558                                         SCALER_PITCH0_TILE_WIDTH_R));
 559                 break;
 560         default:
 561                 DRM_DEBUG_KMS("Unsupported FB tiling flag 0x%16llx",
 562                               (long long)fb->modifier);
 563                 return -EINVAL;
 564         }
 565
 566         /* Control word */
 567         vc4_dlist_write(vc4_state,
 568                         SCALER_CTL0_VALID |
 569                         (format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
 570                         (format->hvs << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
 571                         VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
 572                         (vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
 573                         VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
 574                         VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1));
 575
 576         /* Position Word 0: Image Positions and Alpha Value */
 577         vc4_state->pos0_offset = vc4_state->dlist_count;
 578         vc4_dlist_write(vc4_state,
 579                         VC4_SET_FIELD(0xff, SCALER_POS0_FIXED_ALPHA) |
 580                         VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) |
 581                         VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y));
 582
 583         /* Position Word 1: Scaled Image Dimensions. */
 584         if (!vc4_state->is_unity) {
 585                 vc4_dlist_write(vc4_state,
 586                                 VC4_SET_FIELD(vc4_state->crtc_w,
 587                                               SCALER_POS1_SCL_WIDTH) |
 588                                 VC4_SET_FIELD(vc4_state->crtc_h,
 589                                               SCALER_POS1_SCL_HEIGHT));
 590         }
 591
 592         /* Position Word 2: Source Image Size, Alpha Mode */
 593         vc4_state->pos2_offset = vc4_state->dlist_count;
 594         vc4_dlist_write(vc4_state,
 595                         VC4_SET_FIELD(format->has_alpha ?
 596                                       SCALER_POS2_ALPHA_MODE_PIPELINE :
 597                                       SCALER_POS2_ALPHA_MODE_FIXED,
 598                                       SCALER_POS2_ALPHA_MODE) |
 599                         VC4_SET_FIELD(vc4_state->src_w[0], SCALER_POS2_WIDTH) |
 600                         VC4_SET_FIELD(vc4_state->src_h[0], SCALER_POS2_HEIGHT));
 601
 602         /* Position Word 3: Context.  Written by the HVS. */
 603         vc4_dlist_write(vc4_state, 0xc0c0c0c0);
 604
 605
 606         /* Pointer Word 0/1/2: RGB / Y / Cb / Cr Pointers
 607          *
 608          * The pointers may be any byte address.
 609          */
 610         vc4_state->ptr0_offset = vc4_state->dlist_count;
 611         if (!format->flip_cbcr) {
 612                 for (i = 0; i < num_planes; i++)
 613                         vc4_dlist_write(vc4_state, vc4_state->offsets[i]);
 614         } else {
 615                 WARN_ON_ONCE(num_planes != 3);
 616                 vc4_dlist_write(vc4_state, vc4_state->offsets[0]);
 617                 vc4_dlist_write(vc4_state, vc4_state->offsets[2]);
 618                 vc4_dlist_write(vc4_state, vc4_state->offsets[1]);
 619         }
 620
 621         /* Pointer Context Word 0/1/2: Written by the HVS */
 622         for (i = 0; i < num_planes; i++)
 623                 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
 624
 625         /* Pitch word 0 */
 626         vc4_dlist_write(vc4_state, pitch0);
 627
 628         /* Pitch word 1/2 */
 629         for (i = 1; i < num_planes; i++) {
 630                 vc4_dlist_write(vc4_state,
 631                                 VC4_SET_FIELD(fb->pitches[i], SCALER_SRC_PITCH));
 632         }
 633
 634         /* Colorspace conversion words */
 635         if (vc4_state->is_yuv) {
 636                 vc4_dlist_write(vc4_state, SCALER_CSC0_ITR_R_601_5);
 637                 vc4_dlist_write(vc4_state, SCALER_CSC1_ITR_R_601_5);
 638                 vc4_dlist_write(vc4_state, SCALER_CSC2_ITR_R_601_5);
 639         }
 640
 641         if (vc4_state->x_scaling[0] != VC4_SCALING_NONE ||
 642             vc4_state->x_scaling[1] != VC4_SCALING_NONE ||
 643             vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
 644             vc4_state->y_scaling[1] != VC4_SCALING_NONE) {
 645                 /* LBM Base Address. */
 646                 if (vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
 647                     vc4_state->y_scaling[1] != VC4_SCALING_NONE) {
 648                         vc4_dlist_write(vc4_state, vc4_state->lbm.start);
 649                 }
 650
 651                 if (num_planes > 1) {
 652                         /* Emit Cb/Cr as channel 0 and Y as channel
 653                          * 1. This matches how we set up scl0/scl1
 654                          * above.
 655                          */
 656                         vc4_write_scaling_parameters(state, 1);
 657                 }
 658                 vc4_write_scaling_parameters(state, 0);
 659
 660                 /* If any PPF setup was done, then all the kernel
 661                  * pointers get uploaded.
 662                  */
 663                 if (vc4_state->x_scaling[0] == VC4_SCALING_PPF ||
 664                     vc4_state->y_scaling[0] == VC4_SCALING_PPF ||
 665                     vc4_state->x_scaling[1] == VC4_SCALING_PPF ||
 666                     vc4_state->y_scaling[1] == VC4_SCALING_PPF) {
 667                         u32 kernel = VC4_SET_FIELD(vc4->hvs->mitchell_netravali_filter.start,
 668                                                    SCALER_PPF_KERNEL_OFFSET);
 669
 670                         /* HPPF plane 0 */
 671                         vc4_dlist_write(vc4_state, kernel);
 672                         /* VPPF plane 0 */
 673                         vc4_dlist_write(vc4_state, kernel);
 674                         /* HPPF plane 1 */
 675                         vc4_dlist_write(vc4_state, kernel);
 676                         /* VPPF plane 1 */
 677                         vc4_dlist_write(vc4_state, kernel);
 678                 }
 679         }
 680
 681         vc4_state->dlist[ctl0_offset] |=
 682                 VC4_SET_FIELD(vc4_state->dlist_count, SCALER_CTL0_SIZE);
 683
 684         return 0;
 685 }
 686
 687 /* If a modeset involves changing the setup of a plane, the atomic
 688  * infrastructure will call this to validate a proposed plane setup.
 689  * However, if a plane isn't getting updated, this (and the
 690  * corresponding vc4_plane_atomic_update) won't get called.  Thus, we
 691  * compute the dlist here and have all active plane dlists get updated
 692  * in the CRTC's flush.
 693  */
 694 static int vc4_plane_atomic_check(struct drm_plane *plane,
 695                                   struct drm_plane_state *state)
 696 {
 697         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 698
 699         vc4_state->dlist_count = 0;
 700
 701         if (plane_enabled(state))
 702                 return vc4_plane_mode_set(plane, state);
 703         else
 704                 return 0;
 705 }
 706
 707 static void vc4_plane_atomic_update(struct drm_plane *plane,
 708                                     struct drm_plane_state *old_state)
 709 {
 710         /* No contents here.  Since we don't know where in the CRTC's
 711          * dlist we should be stored, our dlist is uploaded to the
 712          * hardware with vc4_plane_write_dlist() at CRTC atomic_flush
 713          * time.
 714          */
 715 }
 716
 717 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist)
 718 {
 719         struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state);
 720         int i;
 721
 722         vc4_state->hw_dlist = dlist;
 723
 724         /* Can't memcpy_toio() because it needs to be 32-bit writes. */
 725         for (i = 0; i < vc4_state->dlist_count; i++)
 726                 writel(vc4_state->dlist[i], &dlist[i]);
 727
 728         return vc4_state->dlist_count;
 729 }
 730
 731 u32 vc4_plane_dlist_size(const struct drm_plane_state *state)
 732 {
 733         const struct vc4_plane_state *vc4_state =
 734                 container_of(state, typeof(*vc4_state), base);
 735
 736         return vc4_state->dlist_count;
 737 }
 738
 739 /* Updates the plane to immediately (well, once the FIFO needs
 740  * refilling) scan out from at a new framebuffer.
 741  */
 742 void vc4_plane_async_set_fb(struct drm_plane *plane, struct drm_framebuffer *fb)
 743 {
 744         struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state);
 745         struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0);
 746         uint32_t addr;
 747
 748         /* We're skipping the address adjustment for negative origin,
 749          * because this is only called on the primary plane.
 750          */
 751         WARN_ON_ONCE(plane->state->crtc_x < 0 || plane->state->crtc_y < 0);
 752         addr = bo->paddr + fb->offsets[0];
 753
 754         /* Write the new address into the hardware immediately.  The
 755          * scanout will start from this address as soon as the FIFO
 756          * needs to refill with pixels.
 757          */
 758         writel(addr, &vc4_state->hw_dlist[vc4_state->ptr0_offset]);
 759
 760         /* Also update the CPU-side dlist copy, so that any later
 761          * atomic updates that don't do a new modeset on our plane
 762          * also use our updated address.
 763          */
 764         vc4_state->dlist[vc4_state->ptr0_offset] = addr;
 765 }
 766
 767 static int vc4_prepare_fb(struct drm_plane *plane,
 768                           struct drm_plane_state *state)
 769 {
 770         struct vc4_bo *bo;
 771         struct dma_fence *fence;
 772
 773         if ((plane->state->fb == state->fb) || !state->fb)
 774                 return 0;
 775
 776         bo = to_vc4_bo(&drm_fb_cma_get_gem_obj(state->fb, 0)->base);
 777         fence = reservation_object_get_excl_rcu(bo->resv);
 778         drm_atomic_set_fence_for_plane(state, fence);
 779
 780         return 0;
 781 }
 782
 783 static const struct drm_plane_helper_funcs vc4_plane_helper_funcs = {
 784         .atomic_check = vc4_plane_atomic_check,
 785         .atomic_update = vc4_plane_atomic_update,
 786         .prepare_fb = vc4_prepare_fb,
 787 };
 788
 789 static void vc4_plane_destroy(struct drm_plane *plane)
 790 {
 791         drm_plane_helper_disable(plane);
 792         drm_plane_cleanup(plane);
 793 }
 794
 795 /* Implements immediate (non-vblank-synced) updates of the cursor
 796  * position, or falls back to the atomic helper otherwise.
 797  */
 798 static int
 799 vc4_update_plane(struct drm_plane *plane,
 800                  struct drm_crtc *crtc,
 801                  struct drm_framebuffer *fb,
 802                  int crtc_x, int crtc_y,
 803                  unsigned int crtc_w, unsigned int crtc_h,
 804                  uint32_t src_x, uint32_t src_y,
 805                  uint32_t src_w, uint32_t src_h,
 806                  struct drm_modeset_acquire_ctx *ctx)
 807 {
 808         struct drm_plane_state *plane_state;
 809         struct vc4_plane_state *vc4_state;
 810
 811         if (plane != crtc->cursor)
 812                 goto out;
 813
 814         plane_state = plane->state;
 815         vc4_state = to_vc4_plane_state(plane_state);
 816
 817         if (!plane_state)
 818                 goto out;
 819
 820         /* No configuring new scaling in the fast path. */
 821         if (crtc_w != plane_state->crtc_w ||
 822             crtc_h != plane_state->crtc_h ||
 823             src_w != plane_state->src_w ||
 824             src_h != plane_state->src_h) {
 825                 goto out;
 826         }
 827
 828         if (fb != plane_state->fb) {
 829                 drm_atomic_set_fb_for_plane(plane->state, fb);
 830                 vc4_plane_async_set_fb(plane, fb);
 831         }
 832
 833         /* Set the cursor's position on the screen.  This is the
 834          * expected change from the drm_mode_cursor_universal()
 835          * helper.
 836          */
 837         plane_state->crtc_x = crtc_x;
 838         plane_state->crtc_y = crtc_y;
 839
 840         /* Allow changing the start position within the cursor BO, if
 841          * that matters.
 842          */
 843         plane_state->src_x = src_x;
 844         plane_state->src_y = src_y;
 845
 846         /* Update the display list based on the new crtc_x/y. */
 847         vc4_plane_atomic_check(plane, plane_state);
 848
 849         /* Note that we can't just call vc4_plane_write_dlist()
 850          * because that would smash the context data that the HVS is
 851          * currently using.
 852          */
 853         writel(vc4_state->dlist[vc4_state->pos0_offset],
 854                &vc4_state->hw_dlist[vc4_state->pos0_offset]);
 855         writel(vc4_state->dlist[vc4_state->pos2_offset],
 856                &vc4_state->hw_dlist[vc4_state->pos2_offset]);
 857         writel(vc4_state->dlist[vc4_state->ptr0_offset],
 858                &vc4_state->hw_dlist[vc4_state->ptr0_offset]);
 859
 860         return 0;
 861
 862 out:
 863         return drm_atomic_helper_update_plane(plane, crtc, fb,
 864                                               crtc_x, crtc_y,
 865                                               crtc_w, crtc_h,
 866                                               src_x, src_y,
 867                                               src_w, src_h,
 868                                               ctx);
 869 }
 870
 871 static const struct drm_plane_funcs vc4_plane_funcs = {
 872         .update_plane = vc4_update_plane,
 873         .disable_plane = drm_atomic_helper_disable_plane,
 874         .destroy = vc4_plane_destroy,
 875         .set_property = NULL,
 876         .reset = vc4_plane_reset,
 877         .atomic_duplicate_state = vc4_plane_duplicate_state,
 878         .atomic_destroy_state = vc4_plane_destroy_state,
 879 };
 880
 881 struct drm_plane *vc4_plane_init(struct drm_device *dev,
 882                                  enum drm_plane_type type)
 883 {
 884         struct drm_plane *plane = NULL;
 885         struct vc4_plane *vc4_plane;
 886         u32 formats[ARRAY_SIZE(hvs_formats)];
 887         u32 num_formats = 0;
 888         int ret = 0;
 889         unsigned i;
 890
 891         vc4_plane = devm_kzalloc(dev->dev, sizeof(*vc4_plane),
 892                                  GFP_KERNEL);
 893         if (!vc4_plane)
 894                 return ERR_PTR(-ENOMEM);
 895
 896         for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) {
 897                 /* Don't allow YUV in cursor planes, since that means
 898                  * tuning on the scaler, which we don't allow for the
 899                  * cursor.
 900                  */
 901                 if (type != DRM_PLANE_TYPE_CURSOR ||
 902                     hvs_formats[i].hvs < HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE) {
 903                         formats[num_formats++] = hvs_formats[i].drm;
 904                 }
 905         }
 906         plane = &vc4_plane->base;
 907         ret = drm_universal_plane_init(dev, plane, 0,
 908                                        &vc4_plane_funcs,
 909                                        formats, num_formats,
 910                                        NULL, type, NULL);
 911
 912         drm_plane_helper_add(plane, &vc4_plane_helper_funcs);
 913
 914         return plane;
 915 }