drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

   1 /**************************************************************************
   2  *
   3  * Copyright © 2009-2016 VMware, Inc., Palo Alto, CA., USA
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27 #include <linux/module.h>
  28 #include <linux/console.h>
  29
  30 #include <drm/drmP.h>
  31 #include "vmwgfx_drv.h"
  32 #include "vmwgfx_binding.h"
  33 #include <drm/ttm/ttm_placement.h>
  34 #include <drm/ttm/ttm_bo_driver.h>
  35 #include <drm/ttm/ttm_object.h>
  36 #include <drm/ttm/ttm_module.h>
  37 #include <linux/dma_remapping.h>
  38
  39 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
  40 #define VMWGFX_CHIP_SVGAII 0
  41 #define VMW_FB_RESERVATION 0
  42
  43 #define VMW_MIN_INITIAL_WIDTH 800
  44 #define VMW_MIN_INITIAL_HEIGHT 600
  45
  46 #ifndef VMWGFX_GIT_VERSION
  47 #define VMWGFX_GIT_VERSION "Unknown"
  48 #endif
  49
  50 #define VMWGFX_REPO "In Tree"
  51
  52
  53 /**
  54  * Fully encoded drm commands. Might move to vmw_drm.h
  55  */
  56
  57 #define DRM_IOCTL_VMW_GET_PARAM                                 \
  58         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM,          \
  59                  struct drm_vmw_getparam_arg)
  60 #define DRM_IOCTL_VMW_ALLOC_DMABUF                              \
  61         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF,       \
  62                 union drm_vmw_alloc_dmabuf_arg)
  63 #define DRM_IOCTL_VMW_UNREF_DMABUF                              \
  64         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF,        \
  65                 struct drm_vmw_unref_dmabuf_arg)
  66 #define DRM_IOCTL_VMW_CURSOR_BYPASS                             \
  67         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS,       \
  68                  struct drm_vmw_cursor_bypass_arg)
  69
  70 #define DRM_IOCTL_VMW_CONTROL_STREAM                            \
  71         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM,      \
  72                  struct drm_vmw_control_stream_arg)
  73 #define DRM_IOCTL_VMW_CLAIM_STREAM                              \
  74         DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM,        \
  75                  struct drm_vmw_stream_arg)
  76 #define DRM_IOCTL_VMW_UNREF_STREAM                              \
  77         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM,        \
  78                  struct drm_vmw_stream_arg)
  79
  80 #define DRM_IOCTL_VMW_CREATE_CONTEXT                            \
  81         DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT,      \
  82                 struct drm_vmw_context_arg)
  83 #define DRM_IOCTL_VMW_UNREF_CONTEXT                             \
  84         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT,       \
  85                 struct drm_vmw_context_arg)
  86 #define DRM_IOCTL_VMW_CREATE_SURFACE                            \
  87         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE,     \
  88                  union drm_vmw_surface_create_arg)
  89 #define DRM_IOCTL_VMW_UNREF_SURFACE                             \
  90         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE,       \
  91                  struct drm_vmw_surface_arg)
  92 #define DRM_IOCTL_VMW_REF_SURFACE                               \
  93         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE,        \
  94                  union drm_vmw_surface_reference_arg)
  95 #define DRM_IOCTL_VMW_EXECBUF                                   \
  96         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF,             \
  97                 struct drm_vmw_execbuf_arg)
  98 #define DRM_IOCTL_VMW_GET_3D_CAP                                \
  99         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP,          \
 100                  struct drm_vmw_get_3d_cap_arg)
 101 #define DRM_IOCTL_VMW_FENCE_WAIT                                \
 102         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT,         \
 103                  struct drm_vmw_fence_wait_arg)
 104 #define DRM_IOCTL_VMW_FENCE_SIGNALED                            \
 105         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED,     \
 106                  struct drm_vmw_fence_signaled_arg)
 107 #define DRM_IOCTL_VMW_FENCE_UNREF                               \
 108         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF,         \
 109                  struct drm_vmw_fence_arg)
 110 #define DRM_IOCTL_VMW_FENCE_EVENT                               \
 111         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT,         \
 112                  struct drm_vmw_fence_event_arg)
 113 #define DRM_IOCTL_VMW_PRESENT                                   \
 114         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT,             \
 115                  struct drm_vmw_present_arg)
 116 #define DRM_IOCTL_VMW_PRESENT_READBACK                          \
 117         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK,    \
 118                  struct drm_vmw_present_readback_arg)
 119 #define DRM_IOCTL_VMW_UPDATE_LAYOUT                             \
 120         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT,       \
 121                  struct drm_vmw_update_layout_arg)
 122 #define DRM_IOCTL_VMW_CREATE_SHADER                             \
 123         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER,      \
 124                  struct drm_vmw_shader_create_arg)
 125 #define DRM_IOCTL_VMW_UNREF_SHADER                              \
 126         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER,        \
 127                  struct drm_vmw_shader_arg)
 128 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE                         \
 129         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE,  \
 130                  union drm_vmw_gb_surface_create_arg)
 131 #define DRM_IOCTL_VMW_GB_SURFACE_REF                            \
 132         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF,     \
 133                  union drm_vmw_gb_surface_reference_arg)
 134 #define DRM_IOCTL_VMW_SYNCCPU                                   \
 135         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU,             \
 136                  struct drm_vmw_synccpu_arg)
 137 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT                   \
 138         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT,    \
 139                 struct drm_vmw_context_arg)
 140
 141 /**
 142  * The core DRM version of this macro doesn't account for
 143  * DRM_COMMAND_BASE.
 144  */
 145
 146 #define VMW_IOCTL_DEF(ioctl, func, flags) \
 147   [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func}
 148
 149 /**
 150  * Ioctl definitions.
 151  */
 152
 153 static const struct drm_ioctl_desc vmw_ioctls[] = {
 154         VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
 155                       DRM_AUTH | DRM_RENDER_ALLOW),
 156         VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,
 157                       DRM_AUTH | DRM_RENDER_ALLOW),
 158         VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,
 159                       DRM_RENDER_ALLOW),
 160         VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
 161                       vmw_kms_cursor_bypass_ioctl,
 162                       DRM_MASTER | DRM_CONTROL_ALLOW),
 163
 164         VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
 165                       DRM_MASTER | DRM_CONTROL_ALLOW),
 166         VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
 167                       DRM_MASTER | DRM_CONTROL_ALLOW),
 168         VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
 169                       DRM_MASTER | DRM_CONTROL_ALLOW),
 170
 171         VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
 172                       DRM_AUTH | DRM_RENDER_ALLOW),
 173         VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
 174                       DRM_RENDER_ALLOW),
 175         VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
 176                       DRM_AUTH | DRM_RENDER_ALLOW),
 177         VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
 178                       DRM_RENDER_ALLOW),
 179         VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
 180                       DRM_AUTH | DRM_RENDER_ALLOW),
 181         VMW_IOCTL_DEF(VMW_EXECBUF, NULL, DRM_AUTH |
 182                       DRM_RENDER_ALLOW),
 183         VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
 184                       DRM_RENDER_ALLOW),
 185         VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
 186                       vmw_fence_obj_signaled_ioctl,
 187                       DRM_RENDER_ALLOW),
 188         VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
 189                       DRM_RENDER_ALLOW),
 190         VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl,
 191                       DRM_AUTH | DRM_RENDER_ALLOW),
 192         VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
 193                       DRM_AUTH | DRM_RENDER_ALLOW),
 194
 195         /* these allow direct access to the framebuffers mark as master only */
 196         VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,
 197                       DRM_MASTER | DRM_AUTH),
 198         VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
 199                       vmw_present_readback_ioctl,
 200                       DRM_MASTER | DRM_AUTH),
 201         /*
 202          * The permissions of the below ioctl are overridden in
 203          * vmw_generic_ioctl(). We require either
 204          * DRM_MASTER or capable(CAP_SYS_ADMIN).
 205          */
 206         VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT,
 207                       vmw_kms_update_layout_ioctl,
 208                       DRM_RENDER_ALLOW),
 209         VMW_IOCTL_DEF(VMW_CREATE_SHADER,
 210                       vmw_shader_define_ioctl,
 211                       DRM_AUTH | DRM_RENDER_ALLOW),
 212         VMW_IOCTL_DEF(VMW_UNREF_SHADER,
 213                       vmw_shader_destroy_ioctl,
 214                       DRM_RENDER_ALLOW),
 215         VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE,
 216                       vmw_gb_surface_define_ioctl,
 217                       DRM_AUTH | DRM_RENDER_ALLOW),
 218         VMW_IOCTL_DEF(VMW_GB_SURFACE_REF,
 219                       vmw_gb_surface_reference_ioctl,
 220                       DRM_AUTH | DRM_RENDER_ALLOW),
 221         VMW_IOCTL_DEF(VMW_SYNCCPU,
 222                       vmw_user_dmabuf_synccpu_ioctl,
 223                       DRM_RENDER_ALLOW),
 224         VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT,
 225                       vmw_extended_context_define_ioctl,
 226                       DRM_AUTH | DRM_RENDER_ALLOW),
 227 };
 228
 229 static const struct pci_device_id vmw_pci_id_list[] = {
 230         {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
 231         {0, 0, 0}
 232 };
 233 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list);
 234
 235 static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON);
 236 static int vmw_force_iommu;
 237 static int vmw_restrict_iommu;
 238 static int vmw_force_coherent;
 239 static int vmw_restrict_dma_mask;
 240 static int vmw_assume_16bpp;
 241
 242 static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
 243 static void vmw_master_init(struct vmw_master *);
 244 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
 245                               void *ptr);
 246
 247 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
 248 module_param_named(enable_fbdev, enable_fbdev, int, 0600);
 249 MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages");
 250 module_param_named(force_dma_api, vmw_force_iommu, int, 0600);
 251 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
 252 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600);
 253 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
 254 module_param_named(force_coherent, vmw_force_coherent, int, 0600);
 255 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
 256 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600);
 257 MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes");
 258 module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600);
 259
 260
 261 static void vmw_print_capabilities(uint32_t capabilities)
 262 {
 263         DRM_INFO("Capabilities:\n");
 264         if (capabilities & SVGA_CAP_RECT_COPY)
 265                 DRM_INFO("  Rect copy.\n");
 266         if (capabilities & SVGA_CAP_CURSOR)
 267                 DRM_INFO("  Cursor.\n");
 268         if (capabilities & SVGA_CAP_CURSOR_BYPASS)
 269                 DRM_INFO("  Cursor bypass.\n");
 270         if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
 271                 DRM_INFO("  Cursor bypass 2.\n");
 272         if (capabilities & SVGA_CAP_8BIT_EMULATION)
 273                 DRM_INFO("  8bit emulation.\n");
 274         if (capabilities & SVGA_CAP_ALPHA_CURSOR)
 275                 DRM_INFO("  Alpha cursor.\n");
 276         if (capabilities & SVGA_CAP_3D)
 277                 DRM_INFO("  3D.\n");
 278         if (capabilities & SVGA_CAP_EXTENDED_FIFO)
 279                 DRM_INFO("  Extended Fifo.\n");
 280         if (capabilities & SVGA_CAP_MULTIMON)
 281                 DRM_INFO("  Multimon.\n");
 282         if (capabilities & SVGA_CAP_PITCHLOCK)
 283                 DRM_INFO("  Pitchlock.\n");
 284         if (capabilities & SVGA_CAP_IRQMASK)
 285                 DRM_INFO("  Irq mask.\n");
 286         if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
 287                 DRM_INFO("  Display Topology.\n");
 288         if (capabilities & SVGA_CAP_GMR)
 289                 DRM_INFO("  GMR.\n");
 290         if (capabilities & SVGA_CAP_TRACES)
 291                 DRM_INFO("  Traces.\n");
 292         if (capabilities & SVGA_CAP_GMR2)
 293                 DRM_INFO("  GMR2.\n");
 294         if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
 295                 DRM_INFO("  Screen Object 2.\n");
 296         if (capabilities & SVGA_CAP_COMMAND_BUFFERS)
 297                 DRM_INFO("  Command Buffers.\n");
 298         if (capabilities & SVGA_CAP_CMD_BUFFERS_2)
 299                 DRM_INFO("  Command Buffers 2.\n");
 300         if (capabilities & SVGA_CAP_GBOBJECTS)
 301                 DRM_INFO("  Guest Backed Resources.\n");
 302         if (capabilities & SVGA_CAP_DX)
 303                 DRM_INFO("  DX Features.\n");
 304 }
 305
 306 /**
 307  * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
 308  *
 309  * @dev_priv: A device private structure.
 310  *
 311  * This function creates a small buffer object that holds the query
 312  * result for dummy queries emitted as query barriers.
 313  * The function will then map the first page and initialize a pending
 314  * occlusion query result structure, Finally it will unmap the buffer.
 315  * No interruptible waits are done within this function.
 316  *
 317  * Returns an error if bo creation or initialization fails.
 318  */
 319 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
 320 {
 321         int ret;
 322         struct vmw_dma_buffer *vbo;
 323         struct ttm_bo_kmap_obj map;
 324         volatile SVGA3dQueryResult *result;
 325         bool dummy;
 326
 327         /*
 328          * Create the vbo as pinned, so that a tryreserve will
 329          * immediately succeed. This is because we're the only
 330          * user of the bo currently.
 331          */
 332         vbo = kzalloc(sizeof(*vbo), GFP_KERNEL);
 333         if (!vbo)
 334                 return -ENOMEM;
 335
 336         ret = vmw_dmabuf_init(dev_priv, vbo, PAGE_SIZE,
 337                               &vmw_sys_ne_placement, false,
 338                               &vmw_dmabuf_bo_free);
 339         if (unlikely(ret != 0))
 340                 return ret;
 341
 342         ret = ttm_bo_reserve(&vbo->base, false, true, NULL);
 343         BUG_ON(ret != 0);
 344         vmw_bo_pin_reserved(vbo, true);
 345
 346         ret = ttm_bo_kmap(&vbo->base, 0, 1, &map);
 347         if (likely(ret == 0)) {
 348                 result = ttm_kmap_obj_virtual(&map, &dummy);
 349                 result->totalSize = sizeof(*result);
 350                 result->state = SVGA3D_QUERYSTATE_PENDING;
 351                 result->result32 = 0xff;
 352                 ttm_bo_kunmap(&map);
 353         }
 354         vmw_bo_pin_reserved(vbo, false);
 355         ttm_bo_unreserve(&vbo->base);
 356
 357         if (unlikely(ret != 0)) {
 358                 DRM_ERROR("Dummy query buffer map failed.\n");
 359                 vmw_dmabuf_unreference(&vbo);
 360         } else
 361                 dev_priv->dummy_query_bo = vbo;
 362
 363         return ret;
 364 }
 365
 366 /**
 367  * vmw_request_device_late - Perform late device setup
 368  *
 369  * @dev_priv: Pointer to device private.
 370  *
 371  * This function performs setup of otables and enables large command
 372  * buffer submission. These tasks are split out to a separate function
 373  * because it reverts vmw_release_device_early and is intended to be used
 374  * by an error path in the hibernation code.
 375  */
 376 static int vmw_request_device_late(struct vmw_private *dev_priv)
 377 {
 378         int ret;
 379
 380         if (dev_priv->has_mob) {
 381                 ret = vmw_otables_setup(dev_priv);
 382                 if (unlikely(ret != 0)) {
 383                         DRM_ERROR("Unable to initialize "
 384                                   "guest Memory OBjects.\n");
 385                         return ret;
 386                 }
 387         }
 388
 389         if (dev_priv->cman) {
 390                 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman,
 391                                                256*4096, 2*4096);
 392                 if (ret) {
 393                         struct vmw_cmdbuf_man *man = dev_priv->cman;
 394
 395                         dev_priv->cman = NULL;
 396                         vmw_cmdbuf_man_destroy(man);
 397                 }
 398         }
 399
 400         return 0;
 401 }
 402
 403 static int vmw_request_device(struct vmw_private *dev_priv)
 404 {
 405         int ret;
 406
 407         ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
 408         if (unlikely(ret != 0)) {
 409                 DRM_ERROR("Unable to initialize FIFO.\n");
 410                 return ret;
 411         }
 412         vmw_fence_fifo_up(dev_priv->fman);
 413         dev_priv->cman = vmw_cmdbuf_man_create(dev_priv);
 414         if (IS_ERR(dev_priv->cman)) {
 415                 dev_priv->cman = NULL;
 416                 dev_priv->has_dx = false;
 417         }
 418
 419         ret = vmw_request_device_late(dev_priv);
 420         if (ret)
 421                 goto out_no_mob;
 422
 423         ret = vmw_dummy_query_bo_create(dev_priv);
 424         if (unlikely(ret != 0))
 425                 goto out_no_query_bo;
 426
 427         return 0;
 428
 429 out_no_query_bo:
 430         if (dev_priv->cman)
 431                 vmw_cmdbuf_remove_pool(dev_priv->cman);
 432         if (dev_priv->has_mob) {
 433                 (void) ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB);
 434                 vmw_otables_takedown(dev_priv);
 435         }
 436         if (dev_priv->cman)
 437                 vmw_cmdbuf_man_destroy(dev_priv->cman);
 438 out_no_mob:
 439         vmw_fence_fifo_down(dev_priv->fman);
 440         vmw_fifo_release(dev_priv, &dev_priv->fifo);
 441         return ret;
 442 }
 443
 444 /**
 445  * vmw_release_device_early - Early part of fifo takedown.
 446  *
 447  * @dev_priv: Pointer to device private struct.
 448  *
 449  * This is the first part of command submission takedown, to be called before
 450  * buffer management is taken down.
 451  */
 452 static void vmw_release_device_early(struct vmw_private *dev_priv)
 453 {
 454         /*
 455          * Previous destructions should've released
 456          * the pinned bo.
 457          */
 458
 459         BUG_ON(dev_priv->pinned_bo != NULL);
 460
 461         vmw_dmabuf_unreference(&dev_priv->dummy_query_bo);
 462         if (dev_priv->cman)
 463                 vmw_cmdbuf_remove_pool(dev_priv->cman);
 464
 465         if (dev_priv->has_mob) {
 466                 ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB);
 467                 vmw_otables_takedown(dev_priv);
 468         }
 469 }
 470
 471 /**
 472  * vmw_release_device_late - Late part of fifo takedown.
 473  *
 474  * @dev_priv: Pointer to device private struct.
 475  *
 476  * This is the last part of the command submission takedown, to be called when
 477  * command submission is no longer needed. It may wait on pending fences.
 478  */
 479 static void vmw_release_device_late(struct vmw_private *dev_priv)
 480 {
 481         vmw_fence_fifo_down(dev_priv->fman);
 482         if (dev_priv->cman)
 483                 vmw_cmdbuf_man_destroy(dev_priv->cman);
 484
 485         vmw_fifo_release(dev_priv, &dev_priv->fifo);
 486 }
 487
 488 /**
 489  * Sets the initial_[width|height] fields on the given vmw_private.
 490  *
 491  * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
 492  * clamping the value to fb_max_[width|height] fields and the
 493  * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
 494  * If the values appear to be invalid, set them to
 495  * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
 496  */
 497 static void vmw_get_initial_size(struct vmw_private *dev_priv)
 498 {
 499         uint32_t width;
 500         uint32_t height;
 501
 502         width = vmw_read(dev_priv, SVGA_REG_WIDTH);
 503         height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
 504
 505         width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH);
 506         height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT);
 507
 508         if (width > dev_priv->fb_max_width ||
 509             height > dev_priv->fb_max_height) {
 510
 511                 /*
 512                  * This is a host error and shouldn't occur.
 513                  */
 514
 515                 width = VMW_MIN_INITIAL_WIDTH;
 516                 height = VMW_MIN_INITIAL_HEIGHT;
 517         }
 518
 519         dev_priv->initial_width = width;
 520         dev_priv->initial_height = height;
 521 }
 522
 523 /**
 524  * vmw_dma_select_mode - Determine how DMA mappings should be set up for this
 525  * system.
 526  *
 527  * @dev_priv: Pointer to a struct vmw_private
 528  *
 529  * This functions tries to determine the IOMMU setup and what actions
 530  * need to be taken by the driver to make system pages visible to the
 531  * device.
 532  * If this function decides that DMA is not possible, it returns -EINVAL.
 533  * The driver may then try to disable features of the device that require
 534  * DMA.
 535  */
 536 static int vmw_dma_select_mode(struct vmw_private *dev_priv)
 537 {
 538         static const char *names[vmw_dma_map_max] = {
 539                 [vmw_dma_phys] = "Using physical TTM page addresses.",
 540                 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.",
 541                 [vmw_dma_map_populate] = "Keeping DMA mappings.",
 542                 [vmw_dma_map_bind] = "Giving up DMA mappings early."};
 543 #ifdef CONFIG_X86
 544         const struct dma_map_ops *dma_ops = get_dma_ops(dev_priv->dev->dev);
 545
 546 #ifdef CONFIG_INTEL_IOMMU
 547         if (intel_iommu_enabled) {
 548                 dev_priv->map_mode = vmw_dma_map_populate;
 549                 goto out_fixup;
 550         }
 551 #endif
 552
 553         if (!(vmw_force_iommu || vmw_force_coherent)) {
 554                 dev_priv->map_mode = vmw_dma_phys;
 555                 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
 556                 return 0;
 557         }
 558
 559         dev_priv->map_mode = vmw_dma_map_populate;
 560
 561         if (dma_ops->sync_single_for_cpu)
 562                 dev_priv->map_mode = vmw_dma_alloc_coherent;
 563 #ifdef CONFIG_SWIOTLB
 564         if (swiotlb_nr_tbl() == 0)
 565                 dev_priv->map_mode = vmw_dma_map_populate;
 566 #endif
 567
 568 #ifdef CONFIG_INTEL_IOMMU
 569 out_fixup:
 570 #endif
 571         if (dev_priv->map_mode == vmw_dma_map_populate &&
 572             vmw_restrict_iommu)
 573                 dev_priv->map_mode = vmw_dma_map_bind;
 574
 575         if (vmw_force_coherent)
 576                 dev_priv->map_mode = vmw_dma_alloc_coherent;
 577
 578 #if !defined(CONFIG_SWIOTLB) && !defined(CONFIG_INTEL_IOMMU)
 579         /*
 580          * No coherent page pool
 581          */
 582         if (dev_priv->map_mode == vmw_dma_alloc_coherent)
 583                 return -EINVAL;
 584 #endif
 585
 586 #else /* CONFIG_X86 */
 587         dev_priv->map_mode = vmw_dma_map_populate;
 588 #endif /* CONFIG_X86 */
 589
 590         DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
 591
 592         return 0;
 593 }
 594
 595 /**
 596  * vmw_dma_masks - set required page- and dma masks
 597  *
 598  * @dev: Pointer to struct drm-device
 599  *
 600  * With 32-bit we can only handle 32 bit PFNs. Optionally set that
 601  * restriction also for 64-bit systems.
 602  */
 603 #ifdef CONFIG_INTEL_IOMMU
 604 static int vmw_dma_masks(struct vmw_private *dev_priv)
 605 {
 606         struct drm_device *dev = dev_priv->dev;
 607         int ret = 0;
 608
 609         ret = dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64));
 610         if (dev_priv->map_mode != vmw_dma_phys &&
 611             (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) {
 612                 DRM_INFO("Restricting DMA addresses to 44 bits.\n");
 613                 return dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(44));
 614         }
 615
 616         return ret;
 617 }
 618 #else
 619 static int vmw_dma_masks(struct vmw_private *dev_priv)
 620 {
 621         return 0;
 622 }
 623 #endif
 624
 625 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
 626 {
 627         struct vmw_private *dev_priv;
 628         int ret;
 629         uint32_t svga_id;
 630         enum vmw_res_type i;
 631         bool refuse_dma = false;
 632         char host_log[100] = {0};
 633
 634         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 635         if (unlikely(!dev_priv)) {
 636                 DRM_ERROR("Failed allocating a device private struct.\n");
 637                 return -ENOMEM;
 638         }
 639
 640         pci_set_master(dev->pdev);
 641
 642         dev_priv->dev = dev;
 643         dev_priv->vmw_chipset = chipset;
 644         dev_priv->last_read_seqno = (uint32_t) -100;
 645         mutex_init(&dev_priv->cmdbuf_mutex);
 646         mutex_init(&dev_priv->release_mutex);
 647         mutex_init(&dev_priv->binding_mutex);
 648         mutex_init(&dev_priv->global_kms_state_mutex);
 649         rwlock_init(&dev_priv->resource_lock);
 650         ttm_lock_init(&dev_priv->reservation_sem);
 651         spin_lock_init(&dev_priv->hw_lock);
 652         spin_lock_init(&dev_priv->waiter_lock);
 653         spin_lock_init(&dev_priv->cap_lock);
 654         spin_lock_init(&dev_priv->svga_lock);
 655         spin_lock_init(&dev_priv->cursor_lock);
 656
 657         for (i = vmw_res_context; i < vmw_res_max; ++i) {
 658                 idr_init(&dev_priv->res_idr[i]);
 659                 INIT_LIST_HEAD(&dev_priv->res_lru[i]);
 660         }
 661
 662         mutex_init(&dev_priv->init_mutex);
 663         init_waitqueue_head(&dev_priv->fence_queue);
 664         init_waitqueue_head(&dev_priv->fifo_queue);
 665         dev_priv->fence_queue_waiters = 0;
 666         dev_priv->fifo_queue_waiters = 0;
 667
 668         dev_priv->used_memory_size = 0;
 669
 670         dev_priv->io_start = pci_resource_start(dev->pdev, 0);
 671         dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
 672         dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
 673
 674         dev_priv->assume_16bpp = !!vmw_assume_16bpp;
 675
 676         dev_priv->enable_fb = enable_fbdev;
 677
 678         vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
 679         svga_id = vmw_read(dev_priv, SVGA_REG_ID);
 680         if (svga_id != SVGA_ID_2) {
 681                 ret = -ENOSYS;
 682                 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id);
 683                 goto out_err0;
 684         }
 685
 686         dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
 687         ret = vmw_dma_select_mode(dev_priv);
 688         if (unlikely(ret != 0)) {
 689                 DRM_INFO("Restricting capabilities due to IOMMU setup.\n");
 690                 refuse_dma = true;
 691         }
 692
 693         dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
 694         dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
 695         dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
 696         dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
 697
 698         vmw_get_initial_size(dev_priv);
 699
 700         if (dev_priv->capabilities & SVGA_CAP_GMR2) {
 701                 dev_priv->max_gmr_ids =
 702                         vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
 703                 dev_priv->max_gmr_pages =
 704                         vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
 705                 dev_priv->memory_size =
 706                         vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
 707                 dev_priv->memory_size -= dev_priv->vram_size;
 708         } else {
 709                 /*
 710                  * An arbitrary limit of 512MiB on surface
 711                  * memory. But all HWV8 hardware supports GMR2.
 712                  */
 713                 dev_priv->memory_size = 512*1024*1024;
 714         }
 715         dev_priv->max_mob_pages = 0;
 716         dev_priv->max_mob_size = 0;
 717         if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
 718                 uint64_t mem_size =
 719                         vmw_read(dev_priv,
 720                                  SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB);
 721
 722                 /*
 723                  * Workaround for low memory 2D VMs to compensate for the
 724                  * allocation taken by fbdev
 725                  */
 726                 if (!(dev_priv->capabilities & SVGA_CAP_3D))
 727                         mem_size *= 3;
 728
 729                 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
 730                 dev_priv->prim_bb_mem =
 731                         vmw_read(dev_priv,
 732                                  SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM);
 733                 dev_priv->max_mob_size =
 734                         vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);
 735                 dev_priv->stdu_max_width =
 736                         vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH);
 737                 dev_priv->stdu_max_height =
 738                         vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT);
 739
 740                 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
 741                           SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH);
 742                 dev_priv->texture_max_width = vmw_read(dev_priv,
 743                                                        SVGA_REG_DEV_CAP);
 744                 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
 745                           SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT);
 746                 dev_priv->texture_max_height = vmw_read(dev_priv,
 747                                                         SVGA_REG_DEV_CAP);
 748         } else {
 749                 dev_priv->texture_max_width = 8192;
 750                 dev_priv->texture_max_height = 8192;
 751                 dev_priv->prim_bb_mem = dev_priv->vram_size;
 752         }
 753
 754         vmw_print_capabilities(dev_priv->capabilities);
 755
 756         ret = vmw_dma_masks(dev_priv);
 757         if (unlikely(ret != 0))
 758                 goto out_err0;
 759
 760         if (dev_priv->capabilities & SVGA_CAP_GMR2) {
 761                 DRM_INFO("Max GMR ids is %u\n",
 762                          (unsigned)dev_priv->max_gmr_ids);
 763                 DRM_INFO("Max number of GMR pages is %u\n",
 764                          (unsigned)dev_priv->max_gmr_pages);
 765                 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
 766                          (unsigned)dev_priv->memory_size / 1024);
 767         }
 768         DRM_INFO("Maximum display memory size is %u kiB\n",
 769                  dev_priv->prim_bb_mem / 1024);
 770         DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
 771                  dev_priv->vram_start, dev_priv->vram_size / 1024);
 772         DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
 773                  dev_priv->mmio_start, dev_priv->mmio_size / 1024);
 774
 775         ret = vmw_ttm_global_init(dev_priv);
 776         if (unlikely(ret != 0))
 777                 goto out_err0;
 778
 779
 780         vmw_master_init(&dev_priv->fbdev_master);
 781         ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
 782         dev_priv->active_master = &dev_priv->fbdev_master;
 783
 784         dev_priv->mmio_virt = memremap(dev_priv->mmio_start,
 785                                        dev_priv->mmio_size, MEMREMAP_WB);
 786
 787         if (unlikely(dev_priv->mmio_virt == NULL)) {
 788                 ret = -ENOMEM;
 789                 DRM_ERROR("Failed mapping MMIO.\n");
 790                 goto out_err3;
 791         }
 792
 793         /* Need mmio memory to check for fifo pitchlock cap. */
 794         if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
 795             !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
 796             !vmw_fifo_have_pitchlock(dev_priv)) {
 797                 ret = -ENOSYS;
 798                 DRM_ERROR("Hardware has no pitchlock\n");
 799                 goto out_err4;
 800         }
 801
 802         dev_priv->tdev = ttm_object_device_init
 803                 (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops);
 804
 805         if (unlikely(dev_priv->tdev == NULL)) {
 806                 DRM_ERROR("Unable to initialize TTM object management.\n");
 807                 ret = -ENOMEM;
 808                 goto out_err4;
 809         }
 810
 811         dev->dev_private = dev_priv;
 812
 813         ret = pci_request_regions(dev->pdev, "vmwgfx probe");
 814         dev_priv->stealth = (ret != 0);
 815         if (dev_priv->stealth) {
 816                 /**
 817                  * Request at least the mmio PCI resource.
 818                  */
 819
 820                 DRM_INFO("It appears like vesafb is loaded. "
 821                          "Ignore above error if any.\n");
 822                 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
 823                 if (unlikely(ret != 0)) {
 824                         DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
 825                         goto out_no_device;
 826                 }
 827         }
 828
 829         if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
 830                 ret = vmw_irq_install(dev, dev->pdev->irq);
 831                 if (ret != 0) {
 832                         DRM_ERROR("Failed installing irq: %d\n", ret);
 833                         goto out_no_irq;
 834                 }
 835         }
 836
 837         dev_priv->fman = vmw_fence_manager_init(dev_priv);
 838         if (unlikely(dev_priv->fman == NULL)) {
 839                 ret = -ENOMEM;
 840                 goto out_no_fman;
 841         }
 842
 843         ret = ttm_bo_device_init(&dev_priv->bdev,
 844                                  dev_priv->bo_global_ref.ref.object,
 845                                  &vmw_bo_driver,
 846                                  dev->anon_inode->i_mapping,
 847                                  VMWGFX_FILE_PAGE_OFFSET,
 848                                  false);
 849         if (unlikely(ret != 0)) {
 850                 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
 851                 goto out_no_bdev;
 852         }
 853
 854         /*
 855          * Enable VRAM, but initially don't use it until SVGA is enabled and
 856          * unhidden.
 857          */
 858         ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
 859                              (dev_priv->vram_size >> PAGE_SHIFT));
 860         if (unlikely(ret != 0)) {
 861                 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
 862                 goto out_no_vram;
 863         }
 864         dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
 865
 866         dev_priv->has_gmr = true;
 867         if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||
 868             refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR,
 869                                          VMW_PL_GMR) != 0) {
 870                 DRM_INFO("No GMR memory available. "
 871                          "Graphics memory resources are very limited.\n");
 872                 dev_priv->has_gmr = false;
 873         }
 874
 875         if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
 876                 dev_priv->has_mob = true;
 877                 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB,
 878                                    VMW_PL_MOB) != 0) {
 879                         DRM_INFO("No MOB memory available. "
 880                                  "3D will be disabled.\n");
 881                         dev_priv->has_mob = false;
 882                 }
 883         }
 884
 885         if (dev_priv->has_mob) {
 886                 spin_lock(&dev_priv->cap_lock);
 887                 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DX);
 888                 dev_priv->has_dx = !!vmw_read(dev_priv, SVGA_REG_DEV_CAP);
 889                 spin_unlock(&dev_priv->cap_lock);
 890         }
 891
 892
 893         ret = vmw_kms_init(dev_priv);
 894         if (unlikely(ret != 0))
 895                 goto out_no_kms;
 896         vmw_overlay_init(dev_priv);
 897
 898         ret = vmw_request_device(dev_priv);
 899         if (ret)
 900                 goto out_no_fifo;
 901
 902         DRM_INFO("DX: %s\n", dev_priv->has_dx ? "yes." : "no.");
 903         DRM_INFO("Atomic: %s\n",
 904                  (dev->driver->driver_features & DRIVER_ATOMIC) ? "yes" : "no");
 905
 906         snprintf(host_log, sizeof(host_log), "vmwgfx: %s-%s",
 907                 VMWGFX_REPO, VMWGFX_GIT_VERSION);
 908         vmw_host_log(host_log);
 909
 910         memset(host_log, 0, sizeof(host_log));
 911         snprintf(host_log, sizeof(host_log), "vmwgfx: Module Version: %d.%d.%d",
 912                 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR,
 913                 VMWGFX_DRIVER_PATCHLEVEL);
 914         vmw_host_log(host_log);
 915
 916         if (dev_priv->enable_fb) {
 917                 vmw_fifo_resource_inc(dev_priv);
 918                 vmw_svga_enable(dev_priv);
 919                 vmw_fb_init(dev_priv);
 920         }
 921
 922         dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
 923         register_pm_notifier(&dev_priv->pm_nb);
 924
 925         return 0;
 926
 927 out_no_fifo:
 928         vmw_overlay_close(dev_priv);
 929         vmw_kms_close(dev_priv);
 930 out_no_kms:
 931         if (dev_priv->has_mob)
 932                 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
 933         if (dev_priv->has_gmr)
 934                 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
 935         (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
 936 out_no_vram:
 937         (void)ttm_bo_device_release(&dev_priv->bdev);
 938 out_no_bdev:
 939         vmw_fence_manager_takedown(dev_priv->fman);
 940 out_no_fman:
 941         if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
 942                 vmw_irq_uninstall(dev_priv->dev);
 943 out_no_irq:
 944         if (dev_priv->stealth)
 945                 pci_release_region(dev->pdev, 2);
 946         else
 947                 pci_release_regions(dev->pdev);
 948 out_no_device:
 949         ttm_object_device_release(&dev_priv->tdev);
 950 out_err4:
 951         memunmap(dev_priv->mmio_virt);
 952 out_err3:
 953         vmw_ttm_global_release(dev_priv);
 954 out_err0:
 955         for (i = vmw_res_context; i < vmw_res_max; ++i)
 956                 idr_destroy(&dev_priv->res_idr[i]);
 957
 958         if (dev_priv->ctx.staged_bindings)
 959                 vmw_binding_state_free(dev_priv->ctx.staged_bindings);
 960         kfree(dev_priv);
 961         return ret;
 962 }
 963
 964 static void vmw_driver_unload(struct drm_device *dev)
 965 {
 966         struct vmw_private *dev_priv = vmw_priv(dev);
 967         enum vmw_res_type i;
 968
 969         unregister_pm_notifier(&dev_priv->pm_nb);
 970
 971         if (dev_priv->ctx.res_ht_initialized)
 972                 drm_ht_remove(&dev_priv->ctx.res_ht);
 973         vfree(dev_priv->ctx.cmd_bounce);
 974         if (dev_priv->enable_fb) {
 975                 vmw_fb_off(dev_priv);
 976                 vmw_fb_close(dev_priv);
 977                 vmw_fifo_resource_dec(dev_priv);
 978                 vmw_svga_disable(dev_priv);
 979         }
 980
 981         vmw_kms_close(dev_priv);
 982         vmw_overlay_close(dev_priv);
 983
 984         if (dev_priv->has_gmr)
 985                 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
 986         (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
 987
 988         vmw_release_device_early(dev_priv);
 989         if (dev_priv->has_mob)
 990                 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
 991         (void) ttm_bo_device_release(&dev_priv->bdev);
 992         vmw_release_device_late(dev_priv);
 993         vmw_fence_manager_takedown(dev_priv->fman);
 994         if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
 995                 vmw_irq_uninstall(dev_priv->dev);
 996         if (dev_priv->stealth)
 997                 pci_release_region(dev->pdev, 2);
 998         else
 999                 pci_release_regions(dev->pdev);
1000
1001         ttm_object_device_release(&dev_priv->tdev);
1002         memunmap(dev_priv->mmio_virt);
1003         if (dev_priv->ctx.staged_bindings)
1004                 vmw_binding_state_free(dev_priv->ctx.staged_bindings);
1005         vmw_ttm_global_release(dev_priv);
1006
1007         for (i = vmw_res_context; i < vmw_res_max; ++i)
1008                 idr_destroy(&dev_priv->res_idr[i]);
1009
1010         kfree(dev_priv);
1011 }
1012
1013 static void vmw_postclose(struct drm_device *dev,
1014                          struct drm_file *file_priv)
1015 {
1016         struct vmw_fpriv *vmw_fp;
1017
1018         vmw_fp = vmw_fpriv(file_priv);
1019
1020         if (vmw_fp->locked_master) {
1021                 struct vmw_master *vmaster =
1022                         vmw_master(vmw_fp->locked_master);
1023
1024                 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
1025                 ttm_vt_unlock(&vmaster->lock);
1026                 drm_master_put(&vmw_fp->locked_master);
1027         }
1028
1029         ttm_object_file_release(&vmw_fp->tfile);
1030         kfree(vmw_fp);
1031 }
1032
1033 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1034 {
1035         struct vmw_private *dev_priv = vmw_priv(dev);
1036         struct vmw_fpriv *vmw_fp;
1037         int ret = -ENOMEM;
1038
1039         vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
1040         if (unlikely(!vmw_fp))
1041                 return ret;
1042
1043         vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
1044         if (unlikely(vmw_fp->tfile == NULL))
1045                 goto out_no_tfile;
1046
1047         file_priv->driver_priv = vmw_fp;
1048
1049         return 0;
1050
1051 out_no_tfile:
1052         kfree(vmw_fp);
1053         return ret;
1054 }
1055
1056 static struct vmw_master *vmw_master_check(struct drm_device *dev,
1057                                            struct drm_file *file_priv,
1058                                            unsigned int flags)
1059 {
1060         int ret;
1061         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1062         struct vmw_master *vmaster;
1063
1064         if (!drm_is_primary_client(file_priv) || !(flags & DRM_AUTH))
1065                 return NULL;
1066
1067         ret = mutex_lock_interruptible(&dev->master_mutex);
1068         if (unlikely(ret != 0))
1069                 return ERR_PTR(-ERESTARTSYS);
1070
1071         if (drm_is_current_master(file_priv)) {
1072                 mutex_unlock(&dev->master_mutex);
1073                 return NULL;
1074         }
1075
1076         /*
1077          * Check if we were previously master, but now dropped. In that
1078          * case, allow at least render node functionality.
1079          */
1080         if (vmw_fp->locked_master) {
1081                 mutex_unlock(&dev->master_mutex);
1082
1083                 if (flags & DRM_RENDER_ALLOW)
1084                         return NULL;
1085
1086                 DRM_ERROR("Dropped master trying to access ioctl that "
1087                           "requires authentication.\n");
1088                 return ERR_PTR(-EACCES);
1089         }
1090         mutex_unlock(&dev->master_mutex);
1091
1092         /*
1093          * Take the TTM lock. Possibly sleep waiting for the authenticating
1094          * master to become master again, or for a SIGTERM if the
1095          * authenticating master exits.
1096          */
1097         vmaster = vmw_master(file_priv->master);
1098         ret = ttm_read_lock(&vmaster->lock, true);
1099         if (unlikely(ret != 0))
1100                 vmaster = ERR_PTR(ret);
1101
1102         return vmaster;
1103 }
1104
1105 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd,
1106                               unsigned long arg,
1107                               long (*ioctl_func)(struct file *, unsigned int,
1108                                                  unsigned long))
1109 {
1110         struct drm_file *file_priv = filp->private_data;
1111         struct drm_device *dev = file_priv->minor->dev;
1112         unsigned int nr = DRM_IOCTL_NR(cmd);
1113         struct vmw_master *vmaster;
1114         unsigned int flags;
1115         long ret;
1116
1117         /*
1118          * Do extra checking on driver private ioctls.
1119          */
1120
1121         if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
1122             && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
1123                 const struct drm_ioctl_desc *ioctl =
1124                         &vmw_ioctls[nr - DRM_COMMAND_BASE];
1125
1126                 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) {
1127                         ret = (long) drm_ioctl_permit(ioctl->flags, file_priv);
1128                         if (unlikely(ret != 0))
1129                                 return ret;
1130
1131                         if (unlikely((cmd & (IOC_IN | IOC_OUT)) != IOC_IN))
1132                                 goto out_io_encoding;
1133
1134                         return (long) vmw_execbuf_ioctl(dev, arg, file_priv,
1135                                                         _IOC_SIZE(cmd));
1136                 } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) {
1137                         if (!drm_is_current_master(file_priv) &&
1138                             !capable(CAP_SYS_ADMIN))
1139                                 return -EACCES;
1140                 }
1141
1142                 if (unlikely(ioctl->cmd != cmd))
1143                         goto out_io_encoding;
1144
1145                 flags = ioctl->flags;
1146         } else if (!drm_ioctl_flags(nr, &flags))
1147                 return -EINVAL;
1148
1149         vmaster = vmw_master_check(dev, file_priv, flags);
1150         if (IS_ERR(vmaster)) {
1151                 ret = PTR_ERR(vmaster);
1152
1153                 if (ret != -ERESTARTSYS)
1154                         DRM_INFO("IOCTL ERROR Command %d, Error %ld.\n",
1155                                  nr, ret);
1156                 return ret;
1157         }
1158
1159         ret = ioctl_func(filp, cmd, arg);
1160         if (vmaster)
1161                 ttm_read_unlock(&vmaster->lock);
1162
1163         return ret;
1164
1165 out_io_encoding:
1166         DRM_ERROR("Invalid command format, ioctl %d\n",
1167                   nr - DRM_COMMAND_BASE);
1168
1169         return -EINVAL;
1170 }
1171
1172 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
1173                                unsigned long arg)
1174 {
1175         return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl);
1176 }
1177
1178 #ifdef CONFIG_COMPAT
1179 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd,
1180                              unsigned long arg)
1181 {
1182         return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl);
1183 }
1184 #endif
1185
1186 static void vmw_lastclose(struct drm_device *dev)
1187 {
1188 }
1189
1190 static void vmw_master_init(struct vmw_master *vmaster)
1191 {
1192         ttm_lock_init(&vmaster->lock);
1193 }
1194
1195 static int vmw_master_create(struct drm_device *dev,
1196                              struct drm_master *master)
1197 {
1198         struct vmw_master *vmaster;
1199
1200         vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL);
1201         if (unlikely(!vmaster))
1202                 return -ENOMEM;
1203
1204         vmw_master_init(vmaster);
1205         ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
1206         master->driver_priv = vmaster;
1207
1208         return 0;
1209 }
1210
1211 static void vmw_master_destroy(struct drm_device *dev,
1212                                struct drm_master *master)
1213 {
1214         struct vmw_master *vmaster = vmw_master(master);
1215
1216         master->driver_priv = NULL;
1217         kfree(vmaster);
1218 }
1219
1220 static int vmw_master_set(struct drm_device *dev,
1221                           struct drm_file *file_priv,
1222                           bool from_open)
1223 {
1224         struct vmw_private *dev_priv = vmw_priv(dev);
1225         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1226         struct vmw_master *active = dev_priv->active_master;
1227         struct vmw_master *vmaster = vmw_master(file_priv->master);
1228         int ret = 0;
1229
1230         if (active) {
1231                 BUG_ON(active != &dev_priv->fbdev_master);
1232                 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
1233                 if (unlikely(ret != 0))
1234                         return ret;
1235
1236                 ttm_lock_set_kill(&active->lock, true, SIGTERM);
1237                 dev_priv->active_master = NULL;
1238         }
1239
1240         ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1241         if (!from_open) {
1242                 ttm_vt_unlock(&vmaster->lock);
1243                 BUG_ON(vmw_fp->locked_master != file_priv->master);
1244                 drm_master_put(&vmw_fp->locked_master);
1245         }
1246
1247         dev_priv->active_master = vmaster;
1248
1249         /*
1250          * Inform a new master that the layout may have changed while
1251          * it was gone.
1252          */
1253         if (!from_open)
1254                 drm_sysfs_hotplug_event(dev);
1255
1256         return 0;
1257 }
1258
1259 static void vmw_master_drop(struct drm_device *dev,
1260                             struct drm_file *file_priv)
1261 {
1262         struct vmw_private *dev_priv = vmw_priv(dev);
1263         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1264         struct vmw_master *vmaster = vmw_master(file_priv->master);
1265         int ret;
1266
1267         /**
1268          * Make sure the master doesn't disappear while we have
1269          * it locked.
1270          */
1271
1272         vmw_fp->locked_master = drm_master_get(file_priv->master);
1273         ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
1274         vmw_kms_legacy_hotspot_clear(dev_priv);
1275         if (unlikely((ret != 0))) {
1276                 DRM_ERROR("Unable to lock TTM at VT switch.\n");
1277                 drm_master_put(&vmw_fp->locked_master);
1278         }
1279
1280         ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1281
1282         if (!dev_priv->enable_fb)
1283                 vmw_svga_disable(dev_priv);
1284
1285         dev_priv->active_master = &dev_priv->fbdev_master;
1286         ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
1287         ttm_vt_unlock(&dev_priv->fbdev_master.lock);
1288
1289         if (dev_priv->enable_fb)
1290                 vmw_fb_on(dev_priv);
1291 }
1292
1293 /**
1294  * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1295  *
1296  * @dev_priv: Pointer to device private struct.
1297  * Needs the reservation sem to be held in non-exclusive mode.
1298  */
1299 static void __vmw_svga_enable(struct vmw_private *dev_priv)
1300 {
1301         spin_lock(&dev_priv->svga_lock);
1302         if (!dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1303                 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE);
1304                 dev_priv->bdev.man[TTM_PL_VRAM].use_type = true;
1305         }
1306         spin_unlock(&dev_priv->svga_lock);
1307 }
1308
1309 /**
1310  * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1311  *
1312  * @dev_priv: Pointer to device private struct.
1313  */
1314 void vmw_svga_enable(struct vmw_private *dev_priv)
1315 {
1316         (void) ttm_read_lock(&dev_priv->reservation_sem, false);
1317         __vmw_svga_enable(dev_priv);
1318         ttm_read_unlock(&dev_priv->reservation_sem);
1319 }
1320
1321 /**
1322  * __vmw_svga_disable - Disable SVGA mode and use of VRAM.
1323  *
1324  * @dev_priv: Pointer to device private struct.
1325  * Needs the reservation sem to be held in exclusive mode.
1326  * Will not empty VRAM. VRAM must be emptied by caller.
1327  */
1328 static void __vmw_svga_disable(struct vmw_private *dev_priv)
1329 {
1330         spin_lock(&dev_priv->svga_lock);
1331         if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1332                 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
1333                 vmw_write(dev_priv, SVGA_REG_ENABLE,
1334                           SVGA_REG_ENABLE_HIDE |
1335                           SVGA_REG_ENABLE_ENABLE);
1336         }
1337         spin_unlock(&dev_priv->svga_lock);
1338 }
1339
1340 /**
1341  * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo
1342  * running.
1343  *
1344  * @dev_priv: Pointer to device private struct.
1345  * Will empty VRAM.
1346  */
1347 void vmw_svga_disable(struct vmw_private *dev_priv)
1348 {
1349         /*
1350          * Disabling SVGA will turn off device modesetting capabilities, so
1351          * notify KMS about that so that it doesn't cache atomic state that
1352          * isn't valid anymore, for example crtcs turned on.
1353          * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex),
1354          * but vmw_kms_lost_device() takes the reservation sem and thus we'll
1355          * end up with lock order reversal. Thus, a master may actually perform
1356          * a new modeset just after we call vmw_kms_lost_device() and race with
1357          * vmw_svga_disable(), but that should at worst cause atomic KMS state
1358          * to be inconsistent with the device, causing modesetting problems.
1359          *
1360          */
1361         vmw_kms_lost_device(dev_priv->dev);
1362         ttm_write_lock(&dev_priv->reservation_sem, false);
1363         spin_lock(&dev_priv->svga_lock);
1364         if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1365                 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
1366                 spin_unlock(&dev_priv->svga_lock);
1367                 if (ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM))
1368                         DRM_ERROR("Failed evicting VRAM buffers.\n");
1369                 vmw_write(dev_priv, SVGA_REG_ENABLE,
1370                           SVGA_REG_ENABLE_HIDE |
1371                           SVGA_REG_ENABLE_ENABLE);
1372         } else
1373                 spin_unlock(&dev_priv->svga_lock);
1374         ttm_write_unlock(&dev_priv->reservation_sem);
1375 }
1376
1377 static void vmw_remove(struct pci_dev *pdev)
1378 {
1379         struct drm_device *dev = pci_get_drvdata(pdev);
1380
1381         pci_disable_device(pdev);
1382         drm_put_dev(dev);
1383 }
1384
1385 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
1386                               void *ptr)
1387 {
1388         struct vmw_private *dev_priv =
1389                 container_of(nb, struct vmw_private, pm_nb);
1390
1391         switch (val) {
1392         case PM_HIBERNATION_PREPARE:
1393                 if (dev_priv->enable_fb)
1394                         vmw_fb_off(dev_priv);
1395                 ttm_suspend_lock(&dev_priv->reservation_sem);
1396
1397                 /*
1398                  * This empties VRAM and unbinds all GMR bindings.
1399                  * Buffer contents is moved to swappable memory.
1400                  */
1401                 vmw_execbuf_release_pinned_bo(dev_priv);
1402                 vmw_resource_evict_all(dev_priv);
1403                 vmw_release_device_early(dev_priv);
1404                 ttm_bo_swapout_all(&dev_priv->bdev);
1405                 vmw_fence_fifo_down(dev_priv->fman);
1406                 break;
1407         case PM_POST_HIBERNATION:
1408         case PM_POST_RESTORE:
1409                 vmw_fence_fifo_up(dev_priv->fman);
1410                 ttm_suspend_unlock(&dev_priv->reservation_sem);
1411                 if (dev_priv->enable_fb)
1412                         vmw_fb_on(dev_priv);
1413                 break;
1414         case PM_RESTORE_PREPARE:
1415                 break;
1416         default:
1417                 break;
1418         }
1419         return 0;
1420 }
1421
1422 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1423 {
1424         struct drm_device *dev = pci_get_drvdata(pdev);
1425         struct vmw_private *dev_priv = vmw_priv(dev);
1426
1427         if (dev_priv->refuse_hibernation)
1428                 return -EBUSY;
1429
1430         pci_save_state(pdev);
1431         pci_disable_device(pdev);
1432         pci_set_power_state(pdev, PCI_D3hot);
1433         return 0;
1434 }
1435
1436 static int vmw_pci_resume(struct pci_dev *pdev)
1437 {
1438         pci_set_power_state(pdev, PCI_D0);
1439         pci_restore_state(pdev);
1440         return pci_enable_device(pdev);
1441 }
1442
1443 static int vmw_pm_suspend(struct device *kdev)
1444 {
1445         struct pci_dev *pdev = to_pci_dev(kdev);
1446         struct pm_message dummy;
1447
1448         dummy.event = 0;
1449
1450         return vmw_pci_suspend(pdev, dummy);
1451 }
1452
1453 static int vmw_pm_resume(struct device *kdev)
1454 {
1455         struct pci_dev *pdev = to_pci_dev(kdev);
1456
1457         return vmw_pci_resume(pdev);
1458 }
1459
1460 static int vmw_pm_freeze(struct device *kdev)
1461 {
1462         struct pci_dev *pdev = to_pci_dev(kdev);
1463         struct drm_device *dev = pci_get_drvdata(pdev);
1464         struct vmw_private *dev_priv = vmw_priv(dev);
1465
1466         dev_priv->suspended = true;
1467         if (dev_priv->enable_fb)
1468                 vmw_fifo_resource_dec(dev_priv);
1469
1470         if (atomic_read(&dev_priv->num_fifo_resources) != 0) {
1471                 DRM_ERROR("Can't hibernate while 3D resources are active.\n");
1472                 if (dev_priv->enable_fb)
1473                         vmw_fifo_resource_inc(dev_priv);
1474                 WARN_ON(vmw_request_device_late(dev_priv));
1475                 dev_priv->suspended = false;
1476                 return -EBUSY;
1477         }
1478
1479         if (dev_priv->enable_fb)
1480                 __vmw_svga_disable(dev_priv);
1481
1482         vmw_release_device_late(dev_priv);
1483
1484         return 0;
1485 }
1486
1487 static int vmw_pm_restore(struct device *kdev)
1488 {
1489         struct pci_dev *pdev = to_pci_dev(kdev);
1490         struct drm_device *dev = pci_get_drvdata(pdev);
1491         struct vmw_private *dev_priv = vmw_priv(dev);
1492         int ret;
1493
1494         vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
1495         (void) vmw_read(dev_priv, SVGA_REG_ID);
1496
1497         if (dev_priv->enable_fb)
1498                 vmw_fifo_resource_inc(dev_priv);
1499
1500         ret = vmw_request_device(dev_priv);
1501         if (ret)
1502                 return ret;
1503
1504         if (dev_priv->enable_fb)
1505                 __vmw_svga_enable(dev_priv);
1506
1507         dev_priv->suspended = false;
1508
1509         return 0;
1510 }
1511
1512 static const struct dev_pm_ops vmw_pm_ops = {
1513         .freeze = vmw_pm_freeze,
1514         .thaw = vmw_pm_restore,
1515         .restore = vmw_pm_restore,
1516         .suspend = vmw_pm_suspend,
1517         .resume = vmw_pm_resume,
1518 };
1519
1520 static const struct file_operations vmwgfx_driver_fops = {
1521         .owner = THIS_MODULE,
1522         .open = drm_open,
1523         .release = drm_release,
1524         .unlocked_ioctl = vmw_unlocked_ioctl,
1525         .mmap = vmw_mmap,
1526         .poll = vmw_fops_poll,
1527         .read = vmw_fops_read,
1528 #if defined(CONFIG_COMPAT)
1529         .compat_ioctl = vmw_compat_ioctl,
1530 #endif
1531         .llseek = noop_llseek,
1532 };
1533
1534 static struct drm_driver driver = {
1535         .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
1536         DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER | DRIVER_ATOMIC,
1537         .load = vmw_driver_load,
1538         .unload = vmw_driver_unload,
1539         .lastclose = vmw_lastclose,
1540         .get_vblank_counter = vmw_get_vblank_counter,
1541         .enable_vblank = vmw_enable_vblank,
1542         .disable_vblank = vmw_disable_vblank,
1543         .ioctls = vmw_ioctls,
1544         .num_ioctls = ARRAY_SIZE(vmw_ioctls),
1545         .master_create = vmw_master_create,
1546         .master_destroy = vmw_master_destroy,
1547         .master_set = vmw_master_set,
1548         .master_drop = vmw_master_drop,
1549         .open = vmw_driver_open,
1550         .postclose = vmw_postclose,
1551
1552         .dumb_create = vmw_dumb_create,
1553         .dumb_map_offset = vmw_dumb_map_offset,
1554         .dumb_destroy = vmw_dumb_destroy,
1555
1556         .prime_fd_to_handle = vmw_prime_fd_to_handle,
1557         .prime_handle_to_fd = vmw_prime_handle_to_fd,
1558
1559         .fops = &vmwgfx_driver_fops,
1560         .name = VMWGFX_DRIVER_NAME,
1561         .desc = VMWGFX_DRIVER_DESC,
1562         .date = VMWGFX_DRIVER_DATE,
1563         .major = VMWGFX_DRIVER_MAJOR,
1564         .minor = VMWGFX_DRIVER_MINOR,
1565         .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
1566 };
1567
1568 static struct pci_driver vmw_pci_driver = {
1569         .name = VMWGFX_DRIVER_NAME,
1570         .id_table = vmw_pci_id_list,
1571         .probe = vmw_probe,
1572         .remove = vmw_remove,
1573         .driver = {
1574                 .pm = &vmw_pm_ops
1575         }
1576 };
1577
1578 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1579 {
1580         return drm_get_pci_dev(pdev, ent, &driver);
1581 }
1582
1583 static int __init vmwgfx_init(void)
1584 {
1585         int ret;
1586
1587         if (vgacon_text_force())
1588                 return -EINVAL;
1589
1590         ret = pci_register_driver(&vmw_pci_driver);
1591         if (ret)
1592                 DRM_ERROR("Failed initializing DRM.\n");
1593         return ret;
1594 }
1595
1596 static void __exit vmwgfx_exit(void)
1597 {
1598         pci_unregister_driver(&vmw_pci_driver);
1599 }
1600
1601 module_init(vmwgfx_init);
1602 module_exit(vmwgfx_exit);
1603
1604 MODULE_AUTHOR("VMware Inc. and others");
1605 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1606 MODULE_LICENSE("GPL and additional rights");
1607 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
1608                __stringify(VMWGFX_DRIVER_MINOR) "."
1609                __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
1610                "0");