2 * BCM2835 master mode driver
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/clk.h>
15 #include <linux/completion.h>
16 #include <linux/err.h>
17 #include <linux/i2c.h>
18 #include <linux/interrupt.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/slab.h>
24 #define BCM2835_I2C_C 0x0
25 #define BCM2835_I2C_S 0x4
26 #define BCM2835_I2C_DLEN 0x8
27 #define BCM2835_I2C_A 0xc
28 #define BCM2835_I2C_FIFO 0x10
29 #define BCM2835_I2C_DIV 0x14
30 #define BCM2835_I2C_DEL 0x18
32 * 16-bit field for the number of SCL cycles to wait after rising SCL
33 * before deciding the slave is not responding. 0 disables the
36 #define BCM2835_I2C_CLKT 0x1c
38 #define BCM2835_I2C_C_READ BIT(0)
39 #define BCM2835_I2C_C_CLEAR BIT(4) /* bits 4 and 5 both clear */
40 #define BCM2835_I2C_C_ST BIT(7)
41 #define BCM2835_I2C_C_INTD BIT(8)
42 #define BCM2835_I2C_C_INTT BIT(9)
43 #define BCM2835_I2C_C_INTR BIT(10)
44 #define BCM2835_I2C_C_I2CEN BIT(15)
46 #define BCM2835_I2C_S_TA BIT(0)
47 #define BCM2835_I2C_S_DONE BIT(1)
48 #define BCM2835_I2C_S_TXW BIT(2)
49 #define BCM2835_I2C_S_RXR BIT(3)
50 #define BCM2835_I2C_S_TXD BIT(4)
51 #define BCM2835_I2C_S_RXD BIT(5)
52 #define BCM2835_I2C_S_TXE BIT(6)
53 #define BCM2835_I2C_S_RXF BIT(7)
54 #define BCM2835_I2C_S_ERR BIT(8)
55 #define BCM2835_I2C_S_CLKT BIT(9)
56 #define BCM2835_I2C_S_LEN BIT(10) /* Fake bit for SW error reporting */
58 #define BCM2835_I2C_FEDL_SHIFT 16
59 #define BCM2835_I2C_REDL_SHIFT 0
61 #define BCM2835_I2C_CDIV_MIN 0x0002
62 #define BCM2835_I2C_CDIV_MAX 0xFFFE
64 struct bcm2835_i2c_dev {
70 struct i2c_adapter adapter;
71 struct completion completion;
72 struct i2c_msg *curr_msg;
76 size_t msg_buf_remaining;
79 static inline void bcm2835_i2c_writel(struct bcm2835_i2c_dev *i2c_dev,
82 writel(val, i2c_dev->regs + reg);
85 static inline u32 bcm2835_i2c_readl(struct bcm2835_i2c_dev *i2c_dev, u32 reg)
87 return readl(i2c_dev->regs + reg);
90 static int bcm2835_i2c_set_divider(struct bcm2835_i2c_dev *i2c_dev)
92 u32 divider, redl, fedl;
94 divider = DIV_ROUND_UP(clk_get_rate(i2c_dev->clk),
95 i2c_dev->bus_clk_rate);
97 * Per the datasheet, the register is always interpreted as an even
98 * number, by rounding down. In other words, the LSB is ignored. So,
99 * if the LSB is set, increment the divider to avoid any issue.
103 if ((divider < BCM2835_I2C_CDIV_MIN) ||
104 (divider > BCM2835_I2C_CDIV_MAX)) {
105 dev_err_ratelimited(i2c_dev->dev, "Invalid clock-frequency\n");
109 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DIV, divider);
112 * Number of core clocks to wait after falling edge before
113 * outputting the next data bit. Note that both FEDL and REDL
114 * can't be greater than CDIV/2.
116 fedl = max(divider / 16, 1u);
119 * Number of core clocks to wait after rising edge before
120 * sampling the next incoming data bit.
122 redl = max(divider / 4, 1u);
124 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DEL,
125 (fedl << BCM2835_I2C_FEDL_SHIFT) |
126 (redl << BCM2835_I2C_REDL_SHIFT));
130 static void bcm2835_fill_txfifo(struct bcm2835_i2c_dev *i2c_dev)
134 while (i2c_dev->msg_buf_remaining) {
135 val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
136 if (!(val & BCM2835_I2C_S_TXD))
138 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_FIFO,
141 i2c_dev->msg_buf_remaining--;
145 static void bcm2835_drain_rxfifo(struct bcm2835_i2c_dev *i2c_dev)
149 while (i2c_dev->msg_buf_remaining) {
150 val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
151 if (!(val & BCM2835_I2C_S_RXD))
153 *i2c_dev->msg_buf = bcm2835_i2c_readl(i2c_dev,
156 i2c_dev->msg_buf_remaining--;
161 * Repeated Start Condition (Sr)
162 * The BCM2835 ARM Peripherals datasheet mentions a way to trigger a Sr when it
163 * talks about reading from a slave with 10 bit address. This is achieved by
164 * issuing a write, poll the I2CS.TA flag and wait for it to be set, and then
166 * A comment in https://github.com/raspberrypi/linux/issues/254 shows how the
167 * firmware actually does it using polling and says that it's a workaround for
168 * a problem in the state machine.
169 * It turns out that it is possible to use the TXW interrupt to know when the
170 * transfer is active, provided the FIFO has not been prefilled.
173 static void bcm2835_i2c_start_transfer(struct bcm2835_i2c_dev *i2c_dev)
175 u32 c = BCM2835_I2C_C_ST | BCM2835_I2C_C_I2CEN;
176 struct i2c_msg *msg = i2c_dev->curr_msg;
177 bool last_msg = (i2c_dev->num_msgs == 1);
179 if (!i2c_dev->num_msgs)
183 i2c_dev->msg_buf = msg->buf;
184 i2c_dev->msg_buf_remaining = msg->len;
186 if (msg->flags & I2C_M_RD)
187 c |= BCM2835_I2C_C_READ | BCM2835_I2C_C_INTR;
189 c |= BCM2835_I2C_C_INTT;
192 c |= BCM2835_I2C_C_INTD;
194 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_A, msg->addr);
195 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DLEN, msg->len);
196 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, c);
199 static void bcm2835_i2c_finish_transfer(struct bcm2835_i2c_dev *i2c_dev)
201 i2c_dev->curr_msg = NULL;
202 i2c_dev->num_msgs = 0;
204 i2c_dev->msg_buf = NULL;
205 i2c_dev->msg_buf_remaining = 0;
209 * Note about I2C_C_CLEAR on error:
210 * The I2C_C_CLEAR on errors will take some time to resolve -- if you were in
211 * non-idle state and I2C_C_READ, it sets an abort_rx flag and runs through
212 * the state machine to send a NACK and a STOP. Since we're setting CLEAR
213 * without I2CEN, that NACK will be hanging around queued up for next time
214 * we start the engine.
217 static irqreturn_t bcm2835_i2c_isr(int this_irq, void *data)
219 struct bcm2835_i2c_dev *i2c_dev = data;
222 val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
224 err = val & (BCM2835_I2C_S_CLKT | BCM2835_I2C_S_ERR);
226 i2c_dev->msg_err = err;
230 if (val & BCM2835_I2C_S_DONE) {
231 if (!i2c_dev->curr_msg) {
232 dev_err(i2c_dev->dev, "Got unexpected interrupt (from firmware?)\n");
233 } else if (i2c_dev->curr_msg->flags & I2C_M_RD) {
234 bcm2835_drain_rxfifo(i2c_dev);
235 val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
238 if ((val & BCM2835_I2C_S_RXD) || i2c_dev->msg_buf_remaining)
239 i2c_dev->msg_err = BCM2835_I2C_S_LEN;
241 i2c_dev->msg_err = 0;
245 if (val & BCM2835_I2C_S_TXW) {
246 if (!i2c_dev->msg_buf_remaining) {
247 i2c_dev->msg_err = val | BCM2835_I2C_S_LEN;
251 bcm2835_fill_txfifo(i2c_dev);
253 if (i2c_dev->num_msgs && !i2c_dev->msg_buf_remaining) {
255 bcm2835_i2c_start_transfer(i2c_dev);
261 if (val & BCM2835_I2C_S_RXR) {
262 if (!i2c_dev->msg_buf_remaining) {
263 i2c_dev->msg_err = val | BCM2835_I2C_S_LEN;
267 bcm2835_drain_rxfifo(i2c_dev);
274 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, BCM2835_I2C_C_CLEAR);
275 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_S, BCM2835_I2C_S_CLKT |
276 BCM2835_I2C_S_ERR | BCM2835_I2C_S_DONE);
277 complete(&i2c_dev->completion);
282 static int bcm2835_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
285 struct bcm2835_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
286 unsigned long time_left;
289 for (i = 0; i < (num - 1); i++)
290 if (msgs[i].flags & I2C_M_RD) {
291 dev_warn_once(i2c_dev->dev,
292 "only one read message supported, has to be last\n");
296 ret = bcm2835_i2c_set_divider(i2c_dev);
300 i2c_dev->curr_msg = msgs;
301 i2c_dev->num_msgs = num;
302 reinit_completion(&i2c_dev->completion);
304 bcm2835_i2c_start_transfer(i2c_dev);
306 time_left = wait_for_completion_timeout(&i2c_dev->completion,
309 bcm2835_i2c_finish_transfer(i2c_dev);
312 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C,
313 BCM2835_I2C_C_CLEAR);
314 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
318 if (!i2c_dev->msg_err)
321 dev_dbg(i2c_dev->dev, "i2c transfer failed: %x\n", i2c_dev->msg_err);
323 if (i2c_dev->msg_err & BCM2835_I2C_S_ERR)
329 static u32 bcm2835_i2c_func(struct i2c_adapter *adap)
331 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
334 static const struct i2c_algorithm bcm2835_i2c_algo = {
335 .master_xfer = bcm2835_i2c_xfer,
336 .functionality = bcm2835_i2c_func,
340 * This HW was reported to have problems with clock stretching:
341 * http://www.advamation.com/knowhow/raspberrypi/rpi-i2c-bug.html
342 * https://www.raspberrypi.org/forums/viewtopic.php?p=146272
344 static const struct i2c_adapter_quirks bcm2835_i2c_quirks = {
345 .flags = I2C_AQ_NO_CLK_STRETCH,
348 static int bcm2835_i2c_probe(struct platform_device *pdev)
350 struct bcm2835_i2c_dev *i2c_dev;
351 struct resource *mem, *irq;
353 struct i2c_adapter *adap;
355 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
358 platform_set_drvdata(pdev, i2c_dev);
359 i2c_dev->dev = &pdev->dev;
360 init_completion(&i2c_dev->completion);
362 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
363 i2c_dev->regs = devm_ioremap_resource(&pdev->dev, mem);
364 if (IS_ERR(i2c_dev->regs))
365 return PTR_ERR(i2c_dev->regs);
367 i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
368 if (IS_ERR(i2c_dev->clk)) {
369 if (PTR_ERR(i2c_dev->clk) != -EPROBE_DEFER)
370 dev_err(&pdev->dev, "Could not get clock\n");
371 return PTR_ERR(i2c_dev->clk);
374 ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
375 &i2c_dev->bus_clk_rate);
378 "Could not read clock-frequency property\n");
379 i2c_dev->bus_clk_rate = 100000;
382 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
384 dev_err(&pdev->dev, "No IRQ resource\n");
387 i2c_dev->irq = irq->start;
389 ret = request_irq(i2c_dev->irq, bcm2835_i2c_isr, IRQF_SHARED,
390 dev_name(&pdev->dev), i2c_dev);
392 dev_err(&pdev->dev, "Could not request IRQ\n");
396 adap = &i2c_dev->adapter;
397 i2c_set_adapdata(adap, i2c_dev);
398 adap->owner = THIS_MODULE;
399 adap->class = I2C_CLASS_DEPRECATED;
400 strlcpy(adap->name, "bcm2835 I2C adapter", sizeof(adap->name));
401 adap->algo = &bcm2835_i2c_algo;
402 adap->dev.parent = &pdev->dev;
403 adap->dev.of_node = pdev->dev.of_node;
404 adap->quirks = &bcm2835_i2c_quirks;
407 * Disable the hardware clock stretching timeout. SMBUS
408 * specifies a limit for how long the device can stretch the
409 * clock, but core I2C doesn't.
411 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_CLKT, 0);
412 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, 0);
414 ret = i2c_add_adapter(adap);
416 free_irq(i2c_dev->irq, i2c_dev);
421 static int bcm2835_i2c_remove(struct platform_device *pdev)
423 struct bcm2835_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
425 free_irq(i2c_dev->irq, i2c_dev);
426 i2c_del_adapter(&i2c_dev->adapter);
431 static const struct of_device_id bcm2835_i2c_of_match[] = {
432 { .compatible = "brcm,bcm2835-i2c" },
435 MODULE_DEVICE_TABLE(of, bcm2835_i2c_of_match);
437 static struct platform_driver bcm2835_i2c_driver = {
438 .probe = bcm2835_i2c_probe,
439 .remove = bcm2835_i2c_remove,
441 .name = "i2c-bcm2835",
442 .of_match_table = bcm2835_i2c_of_match,
445 module_platform_driver(bcm2835_i2c_driver);
447 MODULE_AUTHOR("Stephen Warren <swarren@wwwdotorg.org>");
448 MODULE_DESCRIPTION("BCM2835 I2C bus adapter");
449 MODULE_LICENSE("GPL v2");
450 MODULE_ALIAS("platform:i2c-bcm2835");