2 * Intel CHT Whiskey Cove PMIC I2C Master driver
3 * Copyright (C) 2017 Hans de Goede <hdegoede@redhat.com>
5 * Based on various non upstream patches to support the CHT Whiskey Cove PMIC:
6 * Copyright (C) 2011 - 2014 Intel Corporation. All rights reserved.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License version
10 * 2 as published by the Free Software Foundation, or (at your option)
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/completion.h>
20 #include <linux/delay.h>
21 #include <linux/i2c.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/irqdomain.h>
25 #include <linux/mfd/intel_soc_pmic.h>
26 #include <linux/module.h>
27 #include <linux/platform_device.h>
28 #include <linux/slab.h>
30 #define CHT_WC_I2C_CTRL 0x5e24
31 #define CHT_WC_I2C_CTRL_WR BIT(0)
32 #define CHT_WC_I2C_CTRL_RD BIT(1)
33 #define CHT_WC_I2C_CLIENT_ADDR 0x5e25
34 #define CHT_WC_I2C_REG_OFFSET 0x5e26
35 #define CHT_WC_I2C_WRDATA 0x5e27
36 #define CHT_WC_I2C_RDDATA 0x5e28
38 #define CHT_WC_EXTCHGRIRQ 0x6e0a
39 #define CHT_WC_EXTCHGRIRQ_CLIENT_IRQ BIT(0)
40 #define CHT_WC_EXTCHGRIRQ_WRITE_IRQ BIT(1)
41 #define CHT_WC_EXTCHGRIRQ_READ_IRQ BIT(2)
42 #define CHT_WC_EXTCHGRIRQ_NACK_IRQ BIT(3)
43 #define CHT_WC_EXTCHGRIRQ_ADAP_IRQMASK ((u8)GENMASK(3, 1))
44 #define CHT_WC_EXTCHGRIRQ_MSK 0x6e17
46 struct cht_wc_i2c_adap {
47 struct i2c_adapter adapter;
48 wait_queue_head_t wait;
49 struct irq_chip irqchip;
50 struct mutex adap_lock;
51 struct mutex irqchip_lock;
52 struct regmap *regmap;
53 struct irq_domain *irq_domain;
54 struct i2c_client *client;
63 static irqreturn_t cht_wc_i2c_adap_thread_handler(int id, void *data)
65 struct cht_wc_i2c_adap *adap = data;
68 mutex_lock(&adap->adap_lock);
71 ret = regmap_read(adap->regmap, CHT_WC_EXTCHGRIRQ, ®);
73 dev_err(&adap->adapter.dev, "Error reading extchgrirq reg\n");
74 mutex_unlock(&adap->adap_lock);
78 reg &= ~adap->irq_mask;
80 /* Reads must be acked after reading the received data. */
81 ret = regmap_read(adap->regmap, CHT_WC_I2C_RDDATA, &adap->read_data);
83 adap->io_error = true;
86 * Immediately ack IRQs, so that if new IRQs arrives while we're
87 * handling the previous ones our irq will re-trigger when we're done.
89 ret = regmap_write(adap->regmap, CHT_WC_EXTCHGRIRQ, reg);
91 dev_err(&adap->adapter.dev, "Error writing extchgrirq reg\n");
93 if (reg & CHT_WC_EXTCHGRIRQ_ADAP_IRQMASK) {
94 adap->io_error |= !!(reg & CHT_WC_EXTCHGRIRQ_NACK_IRQ);
98 mutex_unlock(&adap->adap_lock);
100 if (reg & CHT_WC_EXTCHGRIRQ_ADAP_IRQMASK)
101 wake_up(&adap->wait);
104 * Do NOT use handle_nested_irq here, the client irq handler will
105 * likely want to do i2c transfers and the i2c controller uses this
106 * interrupt handler as well, so running the client irq handler from
107 * this thread will cause things to lock up.
109 if (reg & CHT_WC_EXTCHGRIRQ_CLIENT_IRQ) {
111 * generic_handle_irq expects local IRQs to be disabled
112 * as normally it is called from interrupt context.
115 generic_handle_irq(adap->client_irq);
122 static u32 cht_wc_i2c_adap_master_func(struct i2c_adapter *adap)
124 /* This i2c adapter only supports SMBUS byte transfers */
125 return I2C_FUNC_SMBUS_BYTE_DATA;
128 static int cht_wc_i2c_adap_smbus_xfer(struct i2c_adapter *_adap, u16 addr,
129 unsigned short flags, char read_write,
130 u8 command, int size,
131 union i2c_smbus_data *data)
133 struct cht_wc_i2c_adap *adap = i2c_get_adapdata(_adap);
136 mutex_lock(&adap->adap_lock);
137 adap->io_error = false;
139 mutex_unlock(&adap->adap_lock);
141 ret = regmap_write(adap->regmap, CHT_WC_I2C_CLIENT_ADDR, addr);
145 if (read_write == I2C_SMBUS_WRITE) {
146 ret = regmap_write(adap->regmap, CHT_WC_I2C_WRDATA, data->byte);
151 ret = regmap_write(adap->regmap, CHT_WC_I2C_REG_OFFSET, command);
155 ret = regmap_write(adap->regmap, CHT_WC_I2C_CTRL,
156 (read_write == I2C_SMBUS_WRITE) ?
157 CHT_WC_I2C_CTRL_WR : CHT_WC_I2C_CTRL_RD);
161 ret = wait_event_timeout(adap->wait, adap->done, msecs_to_jiffies(30));
164 * The CHT GPIO controller serializes all IRQs, sometimes
165 * causing significant delays, check status manually.
167 cht_wc_i2c_adap_thread_handler(0, adap);
173 mutex_lock(&adap->adap_lock);
176 else if (read_write == I2C_SMBUS_READ)
177 data->byte = adap->read_data;
178 mutex_unlock(&adap->adap_lock);
183 static const struct i2c_algorithm cht_wc_i2c_adap_algo = {
184 .functionality = cht_wc_i2c_adap_master_func,
185 .smbus_xfer = cht_wc_i2c_adap_smbus_xfer,
189 * We are an i2c-adapter which itself is part of an i2c-client. This means that
190 * transfers done through us take adapter->bus_lock twice, once for our parent
191 * i2c-adapter and once to take our own bus_lock. Lockdep does not like this
192 * nested locking, to make lockdep happy in the case of busses with muxes, the
193 * i2c-core's i2c_adapter_lock_bus function calls:
194 * rt_mutex_lock_nested(&adapter->bus_lock, i2c_adapter_depth(adapter));
196 * But i2c_adapter_depth only works when the direct parent of the adapter is
197 * another adapter, as it is only meant for muxes. In our case there is an
198 * i2c-client and MFD instantiated platform_device in the parent->child chain
199 * between the 2 devices.
201 * So we override the default i2c_lock_operations and pass a hardcoded
202 * depth of 1 to rt_mutex_lock_nested, to make lockdep happy.
204 * Note that if there were to be a mux attached to our adapter, this would
205 * break things again since the i2c-mux code expects the root-adapter to have
206 * a locking depth of 0. But we always have only 1 client directly attached
207 * in the form of the Charger IC paired with the CHT Whiskey Cove PMIC.
209 static void cht_wc_i2c_adap_lock_bus(struct i2c_adapter *adapter,
212 rt_mutex_lock_nested(&adapter->bus_lock, 1);
215 static int cht_wc_i2c_adap_trylock_bus(struct i2c_adapter *adapter,
218 return rt_mutex_trylock(&adapter->bus_lock);
221 static void cht_wc_i2c_adap_unlock_bus(struct i2c_adapter *adapter,
224 rt_mutex_unlock(&adapter->bus_lock);
227 static const struct i2c_lock_operations cht_wc_i2c_adap_lock_ops = {
228 .lock_bus = cht_wc_i2c_adap_lock_bus,
229 .trylock_bus = cht_wc_i2c_adap_trylock_bus,
230 .unlock_bus = cht_wc_i2c_adap_unlock_bus,
233 /**** irqchip for the client connected to the extchgr i2c adapter ****/
234 static void cht_wc_i2c_irq_lock(struct irq_data *data)
236 struct cht_wc_i2c_adap *adap = irq_data_get_irq_chip_data(data);
238 mutex_lock(&adap->irqchip_lock);
241 static void cht_wc_i2c_irq_sync_unlock(struct irq_data *data)
243 struct cht_wc_i2c_adap *adap = irq_data_get_irq_chip_data(data);
246 if (adap->irq_mask != adap->old_irq_mask) {
247 ret = regmap_write(adap->regmap, CHT_WC_EXTCHGRIRQ_MSK,
250 adap->old_irq_mask = adap->irq_mask;
252 dev_err(&adap->adapter.dev, "Error writing EXTCHGRIRQ_MSK\n");
255 mutex_unlock(&adap->irqchip_lock);
258 static void cht_wc_i2c_irq_enable(struct irq_data *data)
260 struct cht_wc_i2c_adap *adap = irq_data_get_irq_chip_data(data);
262 adap->irq_mask &= ~CHT_WC_EXTCHGRIRQ_CLIENT_IRQ;
265 static void cht_wc_i2c_irq_disable(struct irq_data *data)
267 struct cht_wc_i2c_adap *adap = irq_data_get_irq_chip_data(data);
269 adap->irq_mask |= CHT_WC_EXTCHGRIRQ_CLIENT_IRQ;
272 static const struct irq_chip cht_wc_i2c_irq_chip = {
273 .irq_bus_lock = cht_wc_i2c_irq_lock,
274 .irq_bus_sync_unlock = cht_wc_i2c_irq_sync_unlock,
275 .irq_disable = cht_wc_i2c_irq_disable,
276 .irq_enable = cht_wc_i2c_irq_enable,
277 .name = "cht_wc_ext_chrg_irq_chip",
280 static const struct property_entry bq24190_props[] = {
281 PROPERTY_ENTRY_STRING("extcon-name", "cht_wcove_pwrsrc"),
282 PROPERTY_ENTRY_BOOL("omit-battery-class"),
283 PROPERTY_ENTRY_BOOL("disable-reset"),
287 static int cht_wc_i2c_adap_i2c_probe(struct platform_device *pdev)
289 struct intel_soc_pmic *pmic = dev_get_drvdata(pdev->dev.parent);
290 struct cht_wc_i2c_adap *adap;
291 struct i2c_board_info board_info = {
294 .properties = bq24190_props,
298 irq = platform_get_irq(pdev, 0);
300 dev_err(&pdev->dev, "Error missing irq resource\n");
304 adap = devm_kzalloc(&pdev->dev, sizeof(*adap), GFP_KERNEL);
308 init_waitqueue_head(&adap->wait);
309 mutex_init(&adap->adap_lock);
310 mutex_init(&adap->irqchip_lock);
311 adap->irqchip = cht_wc_i2c_irq_chip;
312 adap->regmap = pmic->regmap;
313 adap->adapter.owner = THIS_MODULE;
314 adap->adapter.class = I2C_CLASS_HWMON;
315 adap->adapter.algo = &cht_wc_i2c_adap_algo;
316 adap->adapter.lock_ops = &cht_wc_i2c_adap_lock_ops;
317 strlcpy(adap->adapter.name, "PMIC I2C Adapter",
318 sizeof(adap->adapter.name));
319 adap->adapter.dev.parent = &pdev->dev;
321 /* Clear and activate i2c-adapter interrupts, disable client IRQ */
322 adap->old_irq_mask = adap->irq_mask = ~CHT_WC_EXTCHGRIRQ_ADAP_IRQMASK;
324 ret = regmap_read(adap->regmap, CHT_WC_I2C_RDDATA, ®);
328 ret = regmap_write(adap->regmap, CHT_WC_EXTCHGRIRQ, ~adap->irq_mask);
332 ret = regmap_write(adap->regmap, CHT_WC_EXTCHGRIRQ_MSK, adap->irq_mask);
336 /* Alloc and register client IRQ */
337 adap->irq_domain = irq_domain_add_linear(pdev->dev.of_node, 1,
338 &irq_domain_simple_ops, NULL);
339 if (!adap->irq_domain)
342 adap->client_irq = irq_create_mapping(adap->irq_domain, 0);
343 if (!adap->client_irq) {
345 goto remove_irq_domain;
348 irq_set_chip_data(adap->client_irq, adap);
349 irq_set_chip_and_handler(adap->client_irq, &adap->irqchip,
352 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
353 cht_wc_i2c_adap_thread_handler,
354 IRQF_ONESHOT, "PMIC I2C Adapter", adap);
356 goto remove_irq_domain;
358 i2c_set_adapdata(&adap->adapter, adap);
359 ret = i2c_add_adapter(&adap->adapter);
361 goto remove_irq_domain;
363 board_info.irq = adap->client_irq;
364 adap->client = i2c_new_device(&adap->adapter, &board_info);
370 platform_set_drvdata(pdev, adap);
374 i2c_del_adapter(&adap->adapter);
376 irq_domain_remove(adap->irq_domain);
380 static int cht_wc_i2c_adap_i2c_remove(struct platform_device *pdev)
382 struct cht_wc_i2c_adap *adap = platform_get_drvdata(pdev);
384 i2c_unregister_device(adap->client);
385 i2c_del_adapter(&adap->adapter);
386 irq_domain_remove(adap->irq_domain);
391 static struct platform_device_id cht_wc_i2c_adap_id_table[] = {
392 { .name = "cht_wcove_ext_chgr" },
395 MODULE_DEVICE_TABLE(platform, cht_wc_i2c_adap_id_table);
397 static struct platform_driver cht_wc_i2c_adap_driver = {
398 .probe = cht_wc_i2c_adap_i2c_probe,
399 .remove = cht_wc_i2c_adap_i2c_remove,
401 .name = "cht_wcove_ext_chgr",
403 .id_table = cht_wc_i2c_adap_id_table,
405 module_platform_driver(cht_wc_i2c_adap_driver);
407 MODULE_DESCRIPTION("Intel CHT Whiskey Cove PMIC I2C Master driver");
408 MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
409 MODULE_LICENSE("GPL");