drivers/i2c/busses/i2c-designware-core.c

   1 /*
   2  * Synopsys DesignWare I2C adapter driver (master only).
   3  *
   4  * Based on the TI DAVINCI I2C adapter driver.
   5  *
   6  * Copyright (C) 2006 Texas Instruments.
   7  * Copyright (C) 2007 MontaVista Software Inc.
   8  * Copyright (C) 2009 Provigent Ltd.
   9  *
  10  * ----------------------------------------------------------------------------
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  * ----------------------------------------------------------------------------
  22  *
  23  */
  24 #include <linux/export.h>
  25 #include <linux/errno.h>
  26 #include <linux/err.h>
  27 #include <linux/i2c.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/io.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/delay.h>
  32 #include <linux/module.h>
  33 #include "i2c-designware-core.h"
  34
  35 /*
  36  * Registers offset
  37  */
  38 #define DW_IC_CON               0x0
  39 #define DW_IC_TAR               0x4
  40 #define DW_IC_DATA_CMD          0x10
  41 #define DW_IC_SS_SCL_HCNT       0x14
  42 #define DW_IC_SS_SCL_LCNT       0x18
  43 #define DW_IC_FS_SCL_HCNT       0x1c
  44 #define DW_IC_FS_SCL_LCNT       0x20
  45 #define DW_IC_HS_SCL_HCNT       0x24
  46 #define DW_IC_HS_SCL_LCNT       0x28
  47 #define DW_IC_INTR_STAT         0x2c
  48 #define DW_IC_INTR_MASK         0x30
  49 #define DW_IC_RAW_INTR_STAT     0x34
  50 #define DW_IC_RX_TL             0x38
  51 #define DW_IC_TX_TL             0x3c
  52 #define DW_IC_CLR_INTR          0x40
  53 #define DW_IC_CLR_RX_UNDER      0x44
  54 #define DW_IC_CLR_RX_OVER       0x48
  55 #define DW_IC_CLR_TX_OVER       0x4c
  56 #define DW_IC_CLR_RD_REQ        0x50
  57 #define DW_IC_CLR_TX_ABRT       0x54
  58 #define DW_IC_CLR_RX_DONE       0x58
  59 #define DW_IC_CLR_ACTIVITY      0x5c
  60 #define DW_IC_CLR_STOP_DET      0x60
  61 #define DW_IC_CLR_START_DET     0x64
  62 #define DW_IC_CLR_GEN_CALL      0x68
  63 #define DW_IC_ENABLE            0x6c
  64 #define DW_IC_STATUS            0x70
  65 #define DW_IC_TXFLR             0x74
  66 #define DW_IC_RXFLR             0x78
  67 #define DW_IC_SDA_HOLD          0x7c
  68 #define DW_IC_TX_ABRT_SOURCE    0x80
  69 #define DW_IC_ENABLE_STATUS     0x9c
  70 #define DW_IC_COMP_PARAM_1      0xf4
  71 #define DW_IC_COMP_VERSION      0xf8
  72 #define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A
  73 #define DW_IC_COMP_TYPE         0xfc
  74 #define DW_IC_COMP_TYPE_VALUE   0x44570140
  75
  76 #define DW_IC_INTR_RX_UNDER     0x001
  77 #define DW_IC_INTR_RX_OVER      0x002
  78 #define DW_IC_INTR_RX_FULL      0x004
  79 #define DW_IC_INTR_TX_OVER      0x008
  80 #define DW_IC_INTR_TX_EMPTY     0x010
  81 #define DW_IC_INTR_RD_REQ       0x020
  82 #define DW_IC_INTR_TX_ABRT      0x040
  83 #define DW_IC_INTR_RX_DONE      0x080
  84 #define DW_IC_INTR_ACTIVITY     0x100
  85 #define DW_IC_INTR_STOP_DET     0x200
  86 #define DW_IC_INTR_START_DET    0x400
  87 #define DW_IC_INTR_GEN_CALL     0x800
  88
  89 #define DW_IC_INTR_DEFAULT_MASK         (DW_IC_INTR_RX_FULL | \
  90                                          DW_IC_INTR_TX_EMPTY | \
  91                                          DW_IC_INTR_TX_ABRT | \
  92                                          DW_IC_INTR_STOP_DET)
  93
  94 #define DW_IC_STATUS_ACTIVITY   0x1
  95
  96 #define DW_IC_SDA_HOLD_RX_SHIFT         16
  97 #define DW_IC_SDA_HOLD_RX_MASK          GENMASK(23, DW_IC_SDA_HOLD_RX_SHIFT)
  98
  99 #define DW_IC_ERR_TX_ABRT       0x1
 100
 101 #define DW_IC_TAR_10BITADDR_MASTER BIT(12)
 102
 103 #define DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH      (BIT(2) | BIT(3))
 104 #define DW_IC_COMP_PARAM_1_SPEED_MODE_MASK      GENMASK(3, 2)
 105
 106 /*
 107  * status codes
 108  */
 109 #define STATUS_IDLE                     0x0
 110 #define STATUS_WRITE_IN_PROGRESS        0x1
 111 #define STATUS_READ_IN_PROGRESS         0x2
 112
 113 #define TIMEOUT                 20 /* ms */
 114
 115 /*
 116  * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register
 117  *
 118  * only expected abort codes are listed here
 119  * refer to the datasheet for the full list
 120  */
 121 #define ABRT_7B_ADDR_NOACK      0
 122 #define ABRT_10ADDR1_NOACK      1
 123 #define ABRT_10ADDR2_NOACK      2
 124 #define ABRT_TXDATA_NOACK       3
 125 #define ABRT_GCALL_NOACK        4
 126 #define ABRT_GCALL_READ         5
 127 #define ABRT_SBYTE_ACKDET       7
 128 #define ABRT_SBYTE_NORSTRT      9
 129 #define ABRT_10B_RD_NORSTRT     10
 130 #define ABRT_MASTER_DIS         11
 131 #define ARB_LOST                12
 132
 133 #define DW_IC_TX_ABRT_7B_ADDR_NOACK     (1UL << ABRT_7B_ADDR_NOACK)
 134 #define DW_IC_TX_ABRT_10ADDR1_NOACK     (1UL << ABRT_10ADDR1_NOACK)
 135 #define DW_IC_TX_ABRT_10ADDR2_NOACK     (1UL << ABRT_10ADDR2_NOACK)
 136 #define DW_IC_TX_ABRT_TXDATA_NOACK      (1UL << ABRT_TXDATA_NOACK)
 137 #define DW_IC_TX_ABRT_GCALL_NOACK       (1UL << ABRT_GCALL_NOACK)
 138 #define DW_IC_TX_ABRT_GCALL_READ        (1UL << ABRT_GCALL_READ)
 139 #define DW_IC_TX_ABRT_SBYTE_ACKDET      (1UL << ABRT_SBYTE_ACKDET)
 140 #define DW_IC_TX_ABRT_SBYTE_NORSTRT     (1UL << ABRT_SBYTE_NORSTRT)
 141 #define DW_IC_TX_ABRT_10B_RD_NORSTRT    (1UL << ABRT_10B_RD_NORSTRT)
 142 #define DW_IC_TX_ABRT_MASTER_DIS        (1UL << ABRT_MASTER_DIS)
 143 #define DW_IC_TX_ARB_LOST               (1UL << ARB_LOST)
 144
 145 #define DW_IC_TX_ABRT_NOACK             (DW_IC_TX_ABRT_7B_ADDR_NOACK | \
 146                                          DW_IC_TX_ABRT_10ADDR1_NOACK | \
 147                                          DW_IC_TX_ABRT_10ADDR2_NOACK | \
 148                                          DW_IC_TX_ABRT_TXDATA_NOACK | \
 149                                          DW_IC_TX_ABRT_GCALL_NOACK)
 150
 151 static char *abort_sources[] = {
 152         [ABRT_7B_ADDR_NOACK] =
 153                 "slave address not acknowledged (7bit mode)",
 154         [ABRT_10ADDR1_NOACK] =
 155                 "first address byte not acknowledged (10bit mode)",
 156         [ABRT_10ADDR2_NOACK] =
 157                 "second address byte not acknowledged (10bit mode)",
 158         [ABRT_TXDATA_NOACK] =
 159                 "data not acknowledged",
 160         [ABRT_GCALL_NOACK] =
 161                 "no acknowledgement for a general call",
 162         [ABRT_GCALL_READ] =
 163                 "read after general call",
 164         [ABRT_SBYTE_ACKDET] =
 165                 "start byte acknowledged",
 166         [ABRT_SBYTE_NORSTRT] =
 167                 "trying to send start byte when restart is disabled",
 168         [ABRT_10B_RD_NORSTRT] =
 169                 "trying to read when restart is disabled (10bit mode)",
 170         [ABRT_MASTER_DIS] =
 171                 "trying to use disabled adapter",
 172         [ARB_LOST] =
 173                 "lost arbitration",
 174 };
 175
 176 static u32 dw_readl(struct dw_i2c_dev *dev, int offset)
 177 {
 178         u32 value;
 179
 180         if (dev->accessor_flags & ACCESS_16BIT)
 181                 value = readw_relaxed(dev->base + offset) |
 182                         (readw_relaxed(dev->base + offset + 2) << 16);
 183         else
 184                 value = readl_relaxed(dev->base + offset);
 185
 186         if (dev->accessor_flags & ACCESS_SWAP)
 187                 return swab32(value);
 188         else
 189                 return value;
 190 }
 191
 192 static void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset)
 193 {
 194         if (dev->accessor_flags & ACCESS_SWAP)
 195                 b = swab32(b);
 196
 197         if (dev->accessor_flags & ACCESS_16BIT) {
 198                 writew_relaxed((u16)b, dev->base + offset);
 199                 writew_relaxed((u16)(b >> 16), dev->base + offset + 2);
 200         } else {
 201                 writel_relaxed(b, dev->base + offset);
 202         }
 203 }
 204
 205 static u32
 206 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset)
 207 {
 208         /*
 209          * DesignWare I2C core doesn't seem to have solid strategy to meet
 210          * the tHD;STA timing spec.  Configuring _HCNT based on tHIGH spec
 211          * will result in violation of the tHD;STA spec.
 212          */
 213         if (cond)
 214                 /*
 215                  * Conditional expression:
 216                  *
 217                  *   IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH
 218                  *
 219                  * This is based on the DW manuals, and represents an ideal
 220                  * configuration.  The resulting I2C bus speed will be
 221                  * faster than any of the others.
 222                  *
 223                  * If your hardware is free from tHD;STA issue, try this one.
 224                  */
 225                 return (ic_clk * tSYMBOL + 500000) / 1000000 - 8 + offset;
 226         else
 227                 /*
 228                  * Conditional expression:
 229                  *
 230                  *   IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf)
 231                  *
 232                  * This is just experimental rule; the tHD;STA period turned
 233                  * out to be proportinal to (_HCNT + 3).  With this setting,
 234                  * we could meet both tHIGH and tHD;STA timing specs.
 235                  *
 236                  * If unsure, you'd better to take this alternative.
 237                  *
 238                  * The reason why we need to take into account "tf" here,
 239                  * is the same as described in i2c_dw_scl_lcnt().
 240                  */
 241                 return (ic_clk * (tSYMBOL + tf) + 500000) / 1000000
 242                         - 3 + offset;
 243 }
 244
 245 static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset)
 246 {
 247         /*
 248          * Conditional expression:
 249          *
 250          *   IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf)
 251          *
 252          * DW I2C core starts counting the SCL CNTs for the LOW period
 253          * of the SCL clock (tLOW) as soon as it pulls the SCL line.
 254          * In order to meet the tLOW timing spec, we need to take into
 255          * account the fall time of SCL signal (tf).  Default tf value
 256          * should be 0.3 us, for safety.
 257          */
 258         return ((ic_clk * (tLOW + tf) + 500000) / 1000000) - 1 + offset;
 259 }
 260
 261 static void __i2c_dw_enable(struct dw_i2c_dev *dev, bool enable)
 262 {
 263         dw_writel(dev, enable, DW_IC_ENABLE);
 264 }
 265
 266 static void __i2c_dw_enable_and_wait(struct dw_i2c_dev *dev, bool enable)
 267 {
 268         int timeout = 100;
 269
 270         do {
 271                 __i2c_dw_enable(dev, enable);
 272                 if ((dw_readl(dev, DW_IC_ENABLE_STATUS) & 1) == enable)
 273                         return;
 274
 275                 /*
 276                  * Wait 10 times the signaling period of the highest I2C
 277                  * transfer supported by the driver (for 400KHz this is
 278                  * 25us) as described in the DesignWare I2C databook.
 279                  */
 280                 usleep_range(25, 250);
 281         } while (timeout--);
 282
 283         dev_warn(dev->dev, "timeout in %sabling adapter\n",
 284                  enable ? "en" : "dis");
 285 }
 286
 287 static unsigned long i2c_dw_clk_rate(struct dw_i2c_dev *dev)
 288 {
 289         /*
 290          * Clock is not necessary if we got LCNT/HCNT values directly from
 291          * the platform code.
 292          */
 293         if (WARN_ON_ONCE(!dev->get_clk_rate_khz))
 294                 return 0;
 295         return dev->get_clk_rate_khz(dev);
 296 }
 297
 298 static int i2c_dw_acquire_lock(struct dw_i2c_dev *dev)
 299 {
 300         int ret;
 301
 302         if (!dev->acquire_lock)
 303                 return 0;
 304
 305         ret = dev->acquire_lock(dev);
 306         if (!ret)
 307                 return 0;
 308
 309         dev_err(dev->dev, "couldn't acquire bus ownership\n");
 310
 311         return ret;
 312 }
 313
 314 static void i2c_dw_release_lock(struct dw_i2c_dev *dev)
 315 {
 316         if (dev->release_lock)
 317                 dev->release_lock(dev);
 318 }
 319
 320 /**
 321  * i2c_dw_init() - initialize the designware i2c master hardware
 322  * @dev: device private data
 323  *
 324  * This functions configures and enables the I2C master.
 325  * This function is called during I2C init function, and in case of timeout at
 326  * run time.
 327  */
 328 int i2c_dw_init(struct dw_i2c_dev *dev)
 329 {
 330         u32 hcnt, lcnt;
 331         u32 reg, comp_param1;
 332         u32 sda_falling_time, scl_falling_time;
 333         int ret;
 334
 335         ret = i2c_dw_acquire_lock(dev);
 336         if (ret)
 337                 return ret;
 338
 339         reg = dw_readl(dev, DW_IC_COMP_TYPE);
 340         if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) {
 341                 /* Configure register endianess access */
 342                 dev->accessor_flags |= ACCESS_SWAP;
 343         } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
 344                 /* Configure register access mode 16bit */
 345                 dev->accessor_flags |= ACCESS_16BIT;
 346         } else if (reg != DW_IC_COMP_TYPE_VALUE) {
 347                 dev_err(dev->dev, "Unknown Synopsys component type: "
 348                         "0x%08x\n", reg);
 349                 i2c_dw_release_lock(dev);
 350                 return -ENODEV;
 351         }
 352
 353         comp_param1 = dw_readl(dev, DW_IC_COMP_PARAM_1);
 354
 355         /* Disable the adapter */
 356         __i2c_dw_enable_and_wait(dev, false);
 357
 358         /* set standard and fast speed deviders for high/low periods */
 359
 360         sda_falling_time = dev->sda_falling_time ?: 300; /* ns */
 361         scl_falling_time = dev->scl_falling_time ?: 300; /* ns */
 362
 363         /* Set SCL timing parameters for standard-mode */
 364         if (dev->ss_hcnt && dev->ss_lcnt) {
 365                 hcnt = dev->ss_hcnt;
 366                 lcnt = dev->ss_lcnt;
 367         } else {
 368                 hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev),
 369                                         4000,   /* tHD;STA = tHIGH = 4.0 us */
 370                                         sda_falling_time,
 371                                         0,      /* 0: DW default, 1: Ideal */
 372                                         0);     /* No offset */
 373                 lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev),
 374                                         4700,   /* tLOW = 4.7 us */
 375                                         scl_falling_time,
 376                                         0);     /* No offset */
 377         }
 378         dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT);
 379         dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT);
 380         dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
 381
 382         /* Set SCL timing parameters for fast-mode or fast-mode plus */
 383         if ((dev->clk_freq == 1000000) && dev->fp_hcnt && dev->fp_lcnt) {
 384                 hcnt = dev->fp_hcnt;
 385                 lcnt = dev->fp_lcnt;
 386         } else if (dev->fs_hcnt && dev->fs_lcnt) {
 387                 hcnt = dev->fs_hcnt;
 388                 lcnt = dev->fs_lcnt;
 389         } else {
 390                 hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev),
 391                                         600,    /* tHD;STA = tHIGH = 0.6 us */
 392                                         sda_falling_time,
 393                                         0,      /* 0: DW default, 1: Ideal */
 394                                         0);     /* No offset */
 395                 lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev),
 396                                         1300,   /* tLOW = 1.3 us */
 397                                         scl_falling_time,
 398                                         0);     /* No offset */
 399         }
 400         dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT);
 401         dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT);
 402         dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
 403
 404         if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) ==
 405                 DW_IC_CON_SPEED_HIGH) {
 406                 if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
 407                         != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) {
 408                         dev_err(dev->dev, "High Speed not supported!\n");
 409                         dev->master_cfg &= ~DW_IC_CON_SPEED_MASK;
 410                         dev->master_cfg |= DW_IC_CON_SPEED_FAST;
 411                 } else if (dev->hs_hcnt && dev->hs_lcnt) {
 412                         hcnt = dev->hs_hcnt;
 413                         lcnt = dev->hs_lcnt;
 414                         dw_writel(dev, hcnt, DW_IC_HS_SCL_HCNT);
 415                         dw_writel(dev, lcnt, DW_IC_HS_SCL_LCNT);
 416                         dev_dbg(dev->dev, "HighSpeed-mode HCNT:LCNT = %d:%d\n",
 417                                 hcnt, lcnt);
 418                 }
 419         }
 420
 421         /* Configure SDA Hold Time if required */
 422         reg = dw_readl(dev, DW_IC_COMP_VERSION);
 423         if (reg >= DW_IC_SDA_HOLD_MIN_VERS) {
 424                 if (!dev->sda_hold_time) {
 425                         /* Keep previous hold time setting if no one set it */
 426                         dev->sda_hold_time = dw_readl(dev, DW_IC_SDA_HOLD);
 427                 }
 428                 /*
 429                  * Workaround for avoiding TX arbitration lost in case I2C
 430                  * slave pulls SDA down "too quickly" after falling egde of
 431                  * SCL by enabling non-zero SDA RX hold. Specification says it
 432                  * extends incoming SDA low to high transition while SCL is
 433                  * high but it apprears to help also above issue.
 434                  */
 435                 if (!(dev->sda_hold_time & DW_IC_SDA_HOLD_RX_MASK))
 436                         dev->sda_hold_time |= 1 << DW_IC_SDA_HOLD_RX_SHIFT;
 437                 dw_writel(dev, dev->sda_hold_time, DW_IC_SDA_HOLD);
 438         } else {
 439                 dev_warn(dev->dev,
 440                         "Hardware too old to adjust SDA hold time.\n");
 441         }
 442
 443         /* Configure Tx/Rx FIFO threshold levels */
 444         dw_writel(dev, dev->tx_fifo_depth / 2, DW_IC_TX_TL);
 445         dw_writel(dev, 0, DW_IC_RX_TL);
 446
 447         /* configure the i2c master */
 448         dw_writel(dev, dev->master_cfg , DW_IC_CON);
 449
 450         i2c_dw_release_lock(dev);
 451
 452         return 0;
 453 }
 454 EXPORT_SYMBOL_GPL(i2c_dw_init);
 455
 456 /*
 457  * Waiting for bus not busy
 458  */
 459 static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
 460 {
 461         int timeout = TIMEOUT;
 462
 463         while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) {
 464                 if (timeout <= 0) {
 465                         dev_warn(dev->dev, "timeout waiting for bus ready\n");
 466                         return -ETIMEDOUT;
 467                 }
 468                 timeout--;
 469                 usleep_range(1000, 1100);
 470         }
 471
 472         return 0;
 473 }
 474
 475 static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
 476 {
 477         struct i2c_msg *msgs = dev->msgs;
 478         u32 ic_con, ic_tar = 0;
 479
 480         /* Disable the adapter */
 481         __i2c_dw_enable_and_wait(dev, false);
 482
 483         /* if the slave address is ten bit address, enable 10BITADDR */
 484         ic_con = dw_readl(dev, DW_IC_CON);
 485         if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) {
 486                 ic_con |= DW_IC_CON_10BITADDR_MASTER;
 487                 /*
 488                  * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing
 489                  * mode has to be enabled via bit 12 of IC_TAR register.
 490                  * We set it always as I2C_DYNAMIC_TAR_UPDATE can't be
 491                  * detected from registers.
 492                  */
 493                 ic_tar = DW_IC_TAR_10BITADDR_MASTER;
 494         } else {
 495                 ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
 496         }
 497
 498         dw_writel(dev, ic_con, DW_IC_CON);
 499
 500         /*
 501          * Set the slave (target) address and enable 10-bit addressing mode
 502          * if applicable.
 503          */
 504         dw_writel(dev, msgs[dev->msg_write_idx].addr | ic_tar, DW_IC_TAR);
 505
 506         /* enforce disabled interrupts (due to HW issues) */
 507         i2c_dw_disable_int(dev);
 508
 509         /* Enable the adapter */
 510         __i2c_dw_enable(dev, true);
 511
 512         /* Dummy read to avoid the register getting stuck on Bay Trail */
 513         dw_readl(dev, DW_IC_ENABLE_STATUS);
 514
 515         /* Clear and enable interrupts */
 516         dw_readl(dev, DW_IC_CLR_INTR);
 517         dw_writel(dev, DW_IC_INTR_DEFAULT_MASK, DW_IC_INTR_MASK);
 518 }
 519
 520 /*
 521  * Initiate (and continue) low level master read/write transaction.
 522  * This function is only called from i2c_dw_isr, and pumping i2c_msg
 523  * messages into the tx buffer.  Even if the size of i2c_msg data is
 524  * longer than the size of the tx buffer, it handles everything.
 525  */
 526 static void
 527 i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
 528 {
 529         struct i2c_msg *msgs = dev->msgs;
 530         u32 intr_mask;
 531         int tx_limit, rx_limit;
 532         u32 addr = msgs[dev->msg_write_idx].addr;
 533         u32 buf_len = dev->tx_buf_len;
 534         u8 *buf = dev->tx_buf;
 535         bool need_restart = false;
 536
 537         intr_mask = DW_IC_INTR_DEFAULT_MASK;
 538
 539         for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
 540                 /*
 541                  * if target address has changed, we need to
 542                  * reprogram the target address in the i2c
 543                  * adapter when we are done with this transfer
 544                  */
 545                 if (msgs[dev->msg_write_idx].addr != addr) {
 546                         dev_err(dev->dev,
 547                                 "%s: invalid target address\n", __func__);
 548                         dev->msg_err = -EINVAL;
 549                         break;
 550                 }
 551
 552                 if (msgs[dev->msg_write_idx].len == 0) {
 553                         dev_err(dev->dev,
 554                                 "%s: invalid message length\n", __func__);
 555                         dev->msg_err = -EINVAL;
 556                         break;
 557                 }
 558
 559                 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
 560                         /* new i2c_msg */
 561                         buf = msgs[dev->msg_write_idx].buf;
 562                         buf_len = msgs[dev->msg_write_idx].len;
 563
 564                         /* If both IC_EMPTYFIFO_HOLD_MASTER_EN and
 565                          * IC_RESTART_EN are set, we must manually
 566                          * set restart bit between messages.
 567                          */
 568                         if ((dev->master_cfg & DW_IC_CON_RESTART_EN) &&
 569                                         (dev->msg_write_idx > 0))
 570                                 need_restart = true;
 571                 }
 572
 573                 tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);
 574                 rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR);
 575
 576                 while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
 577                         u32 cmd = 0;
 578
 579                         /*
 580                          * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must
 581                          * manually set the stop bit. However, it cannot be
 582                          * detected from the registers so we set it always
 583                          * when writing/reading the last byte.
 584                          */
 585                         if (dev->msg_write_idx == dev->msgs_num - 1 &&
 586                             buf_len == 1)
 587                                 cmd |= BIT(9);
 588
 589                         if (need_restart) {
 590                                 cmd |= BIT(10);
 591                                 need_restart = false;
 592                         }
 593
 594                         if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
 595
 596                                 /* avoid rx buffer overrun */
 597                                 if (dev->rx_outstanding >= dev->rx_fifo_depth)
 598                                         break;
 599
 600                                 dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD);
 601                                 rx_limit--;
 602                                 dev->rx_outstanding++;
 603                         } else
 604                                 dw_writel(dev, cmd | *buf++, DW_IC_DATA_CMD);
 605                         tx_limit--; buf_len--;
 606                 }
 607
 608                 dev->tx_buf = buf;
 609                 dev->tx_buf_len = buf_len;
 610
 611                 if (buf_len > 0) {
 612                         /* more bytes to be written */
 613                         dev->status |= STATUS_WRITE_IN_PROGRESS;
 614                         break;
 615                 } else
 616                         dev->status &= ~STATUS_WRITE_IN_PROGRESS;
 617         }
 618
 619         /*
 620          * If i2c_msg index search is completed, we don't need TX_EMPTY
 621          * interrupt any more.
 622          */
 623         if (dev->msg_write_idx == dev->msgs_num)
 624                 intr_mask &= ~DW_IC_INTR_TX_EMPTY;
 625
 626         if (dev->msg_err)
 627                 intr_mask = 0;
 628
 629         dw_writel(dev, intr_mask,  DW_IC_INTR_MASK);
 630 }
 631
 632 static void
 633 i2c_dw_read(struct dw_i2c_dev *dev)
 634 {
 635         struct i2c_msg *msgs = dev->msgs;
 636         int rx_valid;
 637
 638         for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
 639                 u32 len;
 640                 u8 *buf;
 641
 642                 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
 643                         continue;
 644
 645                 if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
 646                         len = msgs[dev->msg_read_idx].len;
 647                         buf = msgs[dev->msg_read_idx].buf;
 648                 } else {
 649                         len = dev->rx_buf_len;
 650                         buf = dev->rx_buf;
 651                 }
 652
 653                 rx_valid = dw_readl(dev, DW_IC_RXFLR);
 654
 655                 for (; len > 0 && rx_valid > 0; len--, rx_valid--) {
 656                         *buf++ = dw_readl(dev, DW_IC_DATA_CMD);
 657                         dev->rx_outstanding--;
 658                 }
 659
 660                 if (len > 0) {
 661                         dev->status |= STATUS_READ_IN_PROGRESS;
 662                         dev->rx_buf_len = len;
 663                         dev->rx_buf = buf;
 664                         return;
 665                 } else
 666                         dev->status &= ~STATUS_READ_IN_PROGRESS;
 667         }
 668 }
 669
 670 static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
 671 {
 672         unsigned long abort_source = dev->abort_source;
 673         int i;
 674
 675         if (abort_source & DW_IC_TX_ABRT_NOACK) {
 676                 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
 677                         dev_dbg(dev->dev,
 678                                 "%s: %s\n", __func__, abort_sources[i]);
 679                 return -EREMOTEIO;
 680         }
 681
 682         for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
 683                 dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]);
 684
 685         if (abort_source & DW_IC_TX_ARB_LOST)
 686                 return -EAGAIN;
 687         else if (abort_source & DW_IC_TX_ABRT_GCALL_READ)
 688                 return -EINVAL; /* wrong msgs[] data */
 689         else
 690                 return -EIO;
 691 }
 692
 693 /*
 694  * Prepare controller for a transaction and call i2c_dw_xfer_msg
 695  */
 696 static int
 697 i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 698 {
 699         struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
 700         int ret;
 701
 702         dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
 703
 704         pm_runtime_get_sync(dev->dev);
 705
 706         reinit_completion(&dev->cmd_complete);
 707         dev->msgs = msgs;
 708         dev->msgs_num = num;
 709         dev->cmd_err = 0;
 710         dev->msg_write_idx = 0;
 711         dev->msg_read_idx = 0;
 712         dev->msg_err = 0;
 713         dev->status = STATUS_IDLE;
 714         dev->abort_source = 0;
 715         dev->rx_outstanding = 0;
 716
 717         ret = i2c_dw_acquire_lock(dev);
 718         if (ret)
 719                 goto done_nolock;
 720
 721         ret = i2c_dw_wait_bus_not_busy(dev);
 722         if (ret < 0)
 723                 goto done;
 724
 725         /* start the transfers */
 726         i2c_dw_xfer_init(dev);
 727
 728         /* wait for tx to complete */
 729         if (!wait_for_completion_timeout(&dev->cmd_complete, adap->timeout)) {
 730                 dev_err(dev->dev, "controller timed out\n");
 731                 /* i2c_dw_init implicitly disables the adapter */
 732                 i2c_dw_init(dev);
 733                 ret = -ETIMEDOUT;
 734                 goto done;
 735         }
 736
 737         /*
 738          * We must disable the adapter before returning and signaling the end
 739          * of the current transfer. Otherwise the hardware might continue
 740          * generating interrupts which in turn causes a race condition with
 741          * the following transfer.  Needs some more investigation if the
 742          * additional interrupts are a hardware bug or this driver doesn't
 743          * handle them correctly yet.
 744          */
 745         __i2c_dw_enable(dev, false);
 746
 747         if (dev->msg_err) {
 748                 ret = dev->msg_err;
 749                 goto done;
 750         }
 751
 752         /* no error */
 753         if (likely(!dev->cmd_err && !dev->status)) {
 754                 ret = num;
 755                 goto done;
 756         }
 757
 758         /* We have an error */
 759         if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
 760                 ret = i2c_dw_handle_tx_abort(dev);
 761                 goto done;
 762         }
 763
 764         if (dev->status)
 765                 dev_err(dev->dev,
 766                         "transfer terminated early - interrupt latency too high?\n");
 767
 768         ret = -EIO;
 769
 770 done:
 771         i2c_dw_release_lock(dev);
 772
 773 done_nolock:
 774         pm_runtime_mark_last_busy(dev->dev);
 775         pm_runtime_put_autosuspend(dev->dev);
 776
 777         return ret;
 778 }
 779
 780 static u32 i2c_dw_func(struct i2c_adapter *adap)
 781 {
 782         struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
 783         return dev->functionality;
 784 }
 785
 786 static struct i2c_algorithm i2c_dw_algo = {
 787         .master_xfer    = i2c_dw_xfer,
 788         .functionality  = i2c_dw_func,
 789 };
 790
 791 static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
 792 {
 793         u32 stat;
 794
 795         /*
 796          * The IC_INTR_STAT register just indicates "enabled" interrupts.
 797          * Ths unmasked raw version of interrupt status bits are available
 798          * in the IC_RAW_INTR_STAT register.
 799          *
 800          * That is,
 801          *   stat = dw_readl(IC_INTR_STAT);
 802          * equals to,
 803          *   stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK);
 804          *
 805          * The raw version might be useful for debugging purposes.
 806          */
 807         stat = dw_readl(dev, DW_IC_INTR_STAT);
 808
 809         /*
 810          * Do not use the IC_CLR_INTR register to clear interrupts, or
 811          * you'll miss some interrupts, triggered during the period from
 812          * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR).
 813          *
 814          * Instead, use the separately-prepared IC_CLR_* registers.
 815          */
 816         if (stat & DW_IC_INTR_RX_UNDER)
 817                 dw_readl(dev, DW_IC_CLR_RX_UNDER);
 818         if (stat & DW_IC_INTR_RX_OVER)
 819                 dw_readl(dev, DW_IC_CLR_RX_OVER);
 820         if (stat & DW_IC_INTR_TX_OVER)
 821                 dw_readl(dev, DW_IC_CLR_TX_OVER);
 822         if (stat & DW_IC_INTR_RD_REQ)
 823                 dw_readl(dev, DW_IC_CLR_RD_REQ);
 824         if (stat & DW_IC_INTR_TX_ABRT) {
 825                 /*
 826                  * The IC_TX_ABRT_SOURCE register is cleared whenever
 827                  * the IC_CLR_TX_ABRT is read.  Preserve it beforehand.
 828                  */
 829                 dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE);
 830                 dw_readl(dev, DW_IC_CLR_TX_ABRT);
 831         }
 832         if (stat & DW_IC_INTR_RX_DONE)
 833                 dw_readl(dev, DW_IC_CLR_RX_DONE);
 834         if (stat & DW_IC_INTR_ACTIVITY)
 835                 dw_readl(dev, DW_IC_CLR_ACTIVITY);
 836         if (stat & DW_IC_INTR_STOP_DET)
 837                 dw_readl(dev, DW_IC_CLR_STOP_DET);
 838         if (stat & DW_IC_INTR_START_DET)
 839                 dw_readl(dev, DW_IC_CLR_START_DET);
 840         if (stat & DW_IC_INTR_GEN_CALL)
 841                 dw_readl(dev, DW_IC_CLR_GEN_CALL);
 842
 843         return stat;
 844 }
 845
 846 /*
 847  * Interrupt service routine. This gets called whenever an I2C interrupt
 848  * occurs.
 849  */
 850 static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
 851 {
 852         struct dw_i2c_dev *dev = dev_id;
 853         u32 stat, enabled;
 854
 855         enabled = dw_readl(dev, DW_IC_ENABLE);
 856         stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
 857         dev_dbg(dev->dev, "%s: enabled=%#x stat=%#x\n", __func__, enabled, stat);
 858         if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
 859                 return IRQ_NONE;
 860
 861         stat = i2c_dw_read_clear_intrbits(dev);
 862
 863         if (stat & DW_IC_INTR_TX_ABRT) {
 864                 dev->cmd_err |= DW_IC_ERR_TX_ABRT;
 865                 dev->status = STATUS_IDLE;
 866
 867                 /*
 868                  * Anytime TX_ABRT is set, the contents of the tx/rx
 869                  * buffers are flushed.  Make sure to skip them.
 870                  */
 871                 dw_writel(dev, 0, DW_IC_INTR_MASK);
 872                 goto tx_aborted;
 873         }
 874
 875         if (stat & DW_IC_INTR_RX_FULL)
 876                 i2c_dw_read(dev);
 877
 878         if (stat & DW_IC_INTR_TX_EMPTY)
 879                 i2c_dw_xfer_msg(dev);
 880
 881         /*
 882          * No need to modify or disable the interrupt mask here.
 883          * i2c_dw_xfer_msg() will take care of it according to
 884          * the current transmit status.
 885          */
 886
 887 tx_aborted:
 888         if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err)
 889                 complete(&dev->cmd_complete);
 890         else if (unlikely(dev->accessor_flags & ACCESS_INTR_MASK)) {
 891                 /* workaround to trigger pending interrupt */
 892                 stat = dw_readl(dev, DW_IC_INTR_MASK);
 893                 i2c_dw_disable_int(dev);
 894                 dw_writel(dev, stat, DW_IC_INTR_MASK);
 895         }
 896
 897         return IRQ_HANDLED;
 898 }
 899
 900 void i2c_dw_disable(struct dw_i2c_dev *dev)
 901 {
 902         /* Disable controller */
 903         __i2c_dw_enable_and_wait(dev, false);
 904
 905         /* Disable all interupts */
 906         dw_writel(dev, 0, DW_IC_INTR_MASK);
 907         dw_readl(dev, DW_IC_CLR_INTR);
 908 }
 909 EXPORT_SYMBOL_GPL(i2c_dw_disable);
 910
 911 void i2c_dw_disable_int(struct dw_i2c_dev *dev)
 912 {
 913         dw_writel(dev, 0, DW_IC_INTR_MASK);
 914 }
 915 EXPORT_SYMBOL_GPL(i2c_dw_disable_int);
 916
 917 u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev)
 918 {
 919         return dw_readl(dev, DW_IC_COMP_PARAM_1);
 920 }
 921 EXPORT_SYMBOL_GPL(i2c_dw_read_comp_param);
 922
 923 int i2c_dw_probe(struct dw_i2c_dev *dev)
 924 {
 925         struct i2c_adapter *adap = &dev->adapter;
 926         int r;
 927
 928         init_completion(&dev->cmd_complete);
 929
 930         r = i2c_dw_init(dev);
 931         if (r)
 932                 return r;
 933
 934         snprintf(adap->name, sizeof(adap->name),
 935                  "Synopsys DesignWare I2C adapter");
 936         adap->retries = 3;
 937         adap->algo = &i2c_dw_algo;
 938         adap->dev.parent = dev->dev;
 939         i2c_set_adapdata(adap, dev);
 940
 941         i2c_dw_disable_int(dev);
 942         r = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr,
 943                              IRQF_SHARED | IRQF_COND_SUSPEND,
 944                              dev_name(dev->dev), dev);
 945         if (r) {
 946                 dev_err(dev->dev, "failure requesting irq %i: %d\n",
 947                         dev->irq, r);
 948                 return r;
 949         }
 950
 951         /*
 952          * Increment PM usage count during adapter registration in order to
 953          * avoid possible spurious runtime suspend when adapter device is
 954          * registered to the device core and immediate resume in case bus has
 955          * registered I2C slaves that do I2C transfers in their probe.
 956          */
 957         pm_runtime_get_noresume(dev->dev);
 958         r = i2c_add_numbered_adapter(adap);
 959         if (r)
 960                 dev_err(dev->dev, "failure adding adapter: %d\n", r);
 961         pm_runtime_put_noidle(dev->dev);
 962
 963         return r;
 964 }
 965 EXPORT_SYMBOL_GPL(i2c_dw_probe);
 966
 967 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core");
 968 MODULE_LICENSE("GPL");