drivers/i2c/busses/i2c-designware-master.c

   1 /*
   2  * Synopsys DesignWare I2C adapter driver (master only).
   3  *
   4  * Based on the TI DAVINCI I2C adapter driver.
   5  *
   6  * Copyright (C) 2006 Texas Instruments.
   7  * Copyright (C) 2007 MontaVista Software Inc.
   8  * Copyright (C) 2009 Provigent Ltd.
   9  *
  10  * ----------------------------------------------------------------------------
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  * ----------------------------------------------------------------------------
  22  *
  23  */
  24 #include <linux/delay.h>
  25 #include <linux/err.h>
  26 #include <linux/errno.h>
  27 #include <linux/export.h>
  28 #include <linux/i2c.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/io.h>
  31 #include <linux/module.h>
  32 #include <linux/pm_runtime.h>
  33
  34 #include "i2c-designware-core.h"
  35
  36 static void i2c_dw_configure_fifo_master(struct dw_i2c_dev *dev)
  37 {
  38         /* Configure Tx/Rx FIFO threshold levels */
  39         dw_writel(dev, dev->tx_fifo_depth / 2, DW_IC_TX_TL);
  40         dw_writel(dev, 0, DW_IC_RX_TL);
  41
  42         /* Configure the I2C master */
  43         dw_writel(dev, dev->master_cfg, DW_IC_CON);
  44 }
  45
  46 /**
  47  * i2c_dw_init() - Initialize the designware I2C master hardware
  48  * @dev: device private data
  49  *
  50  * This functions configures and enables the I2C master.
  51  * This function is called during I2C init function, and in case of timeout at
  52  * run time.
  53  */
  54 static int i2c_dw_init_master(struct dw_i2c_dev *dev)
  55 {
  56         u32 hcnt, lcnt;
  57         u32 reg, comp_param1;
  58         u32 sda_falling_time, scl_falling_time;
  59         int ret;
  60
  61         ret = i2c_dw_acquire_lock(dev);
  62         if (ret)
  63                 return ret;
  64
  65         reg = dw_readl(dev, DW_IC_COMP_TYPE);
  66         if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) {
  67                 /* Configure register endianess access */
  68                 dev->flags |= ACCESS_SWAP;
  69         } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
  70                 /* Configure register access mode 16bit */
  71                 dev->flags |= ACCESS_16BIT;
  72         } else if (reg != DW_IC_COMP_TYPE_VALUE) {
  73                 dev_err(dev->dev,
  74                         "Unknown Synopsys component type: 0x%08x\n", reg);
  75                 i2c_dw_release_lock(dev);
  76                 return -ENODEV;
  77         }
  78
  79         comp_param1 = dw_readl(dev, DW_IC_COMP_PARAM_1);
  80
  81         /* Disable the adapter */
  82         __i2c_dw_enable_and_wait(dev, false);
  83
  84         /* Set standard and fast speed deviders for high/low periods */
  85
  86         sda_falling_time = dev->sda_falling_time ?: 300; /* ns */
  87         scl_falling_time = dev->scl_falling_time ?: 300; /* ns */
  88
  89         /* Set SCL timing parameters for standard-mode */
  90         if (dev->ss_hcnt && dev->ss_lcnt) {
  91                 hcnt = dev->ss_hcnt;
  92                 lcnt = dev->ss_lcnt;
  93         } else {
  94                 hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev),
  95                                         4000,   /* tHD;STA = tHIGH = 4.0 us */
  96                                         sda_falling_time,
  97                                         0,      /* 0: DW default, 1: Ideal */
  98                                         0);     /* No offset */
  99                 lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev),
 100                                         4700,   /* tLOW = 4.7 us */
 101                                         scl_falling_time,
 102                                         0);     /* No offset */
 103         }
 104         dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT);
 105         dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT);
 106         dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
 107
 108         /* Set SCL timing parameters for fast-mode or fast-mode plus */
 109         if ((dev->clk_freq == 1000000) && dev->fp_hcnt && dev->fp_lcnt) {
 110                 hcnt = dev->fp_hcnt;
 111                 lcnt = dev->fp_lcnt;
 112         } else if (dev->fs_hcnt && dev->fs_lcnt) {
 113                 hcnt = dev->fs_hcnt;
 114                 lcnt = dev->fs_lcnt;
 115         } else {
 116                 hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev),
 117                                         600,    /* tHD;STA = tHIGH = 0.6 us */
 118                                         sda_falling_time,
 119                                         0,      /* 0: DW default, 1: Ideal */
 120                                         0);     /* No offset */
 121                 lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev),
 122                                         1300,   /* tLOW = 1.3 us */
 123                                         scl_falling_time,
 124                                         0);     /* No offset */
 125         }
 126         dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT);
 127         dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT);
 128         dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
 129
 130         if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) ==
 131                 DW_IC_CON_SPEED_HIGH) {
 132                 if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
 133                         != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) {
 134                         dev_err(dev->dev, "High Speed not supported!\n");
 135                         dev->master_cfg &= ~DW_IC_CON_SPEED_MASK;
 136                         dev->master_cfg |= DW_IC_CON_SPEED_FAST;
 137                 } else if (dev->hs_hcnt && dev->hs_lcnt) {
 138                         hcnt = dev->hs_hcnt;
 139                         lcnt = dev->hs_lcnt;
 140                         dw_writel(dev, hcnt, DW_IC_HS_SCL_HCNT);
 141                         dw_writel(dev, lcnt, DW_IC_HS_SCL_LCNT);
 142                         dev_dbg(dev->dev, "HighSpeed-mode HCNT:LCNT = %d:%d\n",
 143                                 hcnt, lcnt);
 144                 }
 145         }
 146
 147         /* Configure SDA Hold Time if required */
 148         reg = dw_readl(dev, DW_IC_COMP_VERSION);
 149         if (reg >= DW_IC_SDA_HOLD_MIN_VERS) {
 150                 if (!dev->sda_hold_time) {
 151                         /* Keep previous hold time setting if no one set it */
 152                         dev->sda_hold_time = dw_readl(dev, DW_IC_SDA_HOLD);
 153                 }
 154                 /*
 155                  * Workaround for avoiding TX arbitration lost in case I2C
 156                  * slave pulls SDA down "too quickly" after falling egde of
 157                  * SCL by enabling non-zero SDA RX hold. Specification says it
 158                  * extends incoming SDA low to high transition while SCL is
 159                  * high but it apprears to help also above issue.
 160                  */
 161                 if (!(dev->sda_hold_time & DW_IC_SDA_HOLD_RX_MASK))
 162                         dev->sda_hold_time |= 1 << DW_IC_SDA_HOLD_RX_SHIFT;
 163                 dw_writel(dev, dev->sda_hold_time, DW_IC_SDA_HOLD);
 164         } else {
 165                 dev_warn(dev->dev,
 166                         "Hardware too old to adjust SDA hold time.\n");
 167         }
 168
 169         i2c_dw_configure_fifo_master(dev);
 170         i2c_dw_release_lock(dev);
 171
 172         return 0;
 173 }
 174
 175 static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
 176 {
 177         struct i2c_msg *msgs = dev->msgs;
 178         u32 ic_con, ic_tar = 0;
 179
 180         /* Disable the adapter */
 181         __i2c_dw_enable_and_wait(dev, false);
 182
 183         /* If the slave address is ten bit address, enable 10BITADDR */
 184         ic_con = dw_readl(dev, DW_IC_CON);
 185         if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) {
 186                 ic_con |= DW_IC_CON_10BITADDR_MASTER;
 187                 /*
 188                  * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing
 189                  * mode has to be enabled via bit 12 of IC_TAR register.
 190                  * We set it always as I2C_DYNAMIC_TAR_UPDATE can't be
 191                  * detected from registers.
 192                  */
 193                 ic_tar = DW_IC_TAR_10BITADDR_MASTER;
 194         } else {
 195                 ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
 196         }
 197
 198         dw_writel(dev, ic_con, DW_IC_CON);
 199
 200         /*
 201          * Set the slave (target) address and enable 10-bit addressing mode
 202          * if applicable.
 203          */
 204         dw_writel(dev, msgs[dev->msg_write_idx].addr | ic_tar, DW_IC_TAR);
 205
 206         /* Enforce disabled interrupts (due to HW issues) */
 207         i2c_dw_disable_int(dev);
 208
 209         /* Enable the adapter */
 210         __i2c_dw_enable(dev, true);
 211
 212         /* Dummy read to avoid the register getting stuck on Bay Trail */
 213         dw_readl(dev, DW_IC_ENABLE_STATUS);
 214
 215         /* Clear and enable interrupts */
 216         dw_readl(dev, DW_IC_CLR_INTR);
 217         dw_writel(dev, DW_IC_INTR_MASTER_MASK, DW_IC_INTR_MASK);
 218 }
 219
 220 /*
 221  * Initiate (and continue) low level master read/write transaction.
 222  * This function is only called from i2c_dw_isr, and pumping i2c_msg
 223  * messages into the tx buffer.  Even if the size of i2c_msg data is
 224  * longer than the size of the tx buffer, it handles everything.
 225  */
 226 static void
 227 i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
 228 {
 229         struct i2c_msg *msgs = dev->msgs;
 230         u32 intr_mask;
 231         int tx_limit, rx_limit;
 232         u32 addr = msgs[dev->msg_write_idx].addr;
 233         u32 buf_len = dev->tx_buf_len;
 234         u8 *buf = dev->tx_buf;
 235         bool need_restart = false;
 236
 237         intr_mask = DW_IC_INTR_MASTER_MASK;
 238
 239         for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
 240                 u32 flags = msgs[dev->msg_write_idx].flags;
 241
 242                 /*
 243                  * If target address has changed, we need to
 244                  * reprogram the target address in the I2C
 245                  * adapter when we are done with this transfer.
 246                  */
 247                 if (msgs[dev->msg_write_idx].addr != addr) {
 248                         dev_err(dev->dev,
 249                                 "%s: invalid target address\n", __func__);
 250                         dev->msg_err = -EINVAL;
 251                         break;
 252                 }
 253
 254                 if (msgs[dev->msg_write_idx].len == 0) {
 255                         dev_err(dev->dev,
 256                                 "%s: invalid message length\n", __func__);
 257                         dev->msg_err = -EINVAL;
 258                         break;
 259                 }
 260
 261                 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
 262                         /* new i2c_msg */
 263                         buf = msgs[dev->msg_write_idx].buf;
 264                         buf_len = msgs[dev->msg_write_idx].len;
 265
 266                         /* If both IC_EMPTYFIFO_HOLD_MASTER_EN and
 267                          * IC_RESTART_EN are set, we must manually
 268                          * set restart bit between messages.
 269                          */
 270                         if ((dev->master_cfg & DW_IC_CON_RESTART_EN) &&
 271                                         (dev->msg_write_idx > 0))
 272                                 need_restart = true;
 273                 }
 274
 275                 tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);
 276                 rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR);
 277
 278                 while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
 279                         u32 cmd = 0;
 280
 281                         /*
 282                          * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must
 283                          * manually set the stop bit. However, it cannot be
 284                          * detected from the registers so we set it always
 285                          * when writing/reading the last byte.
 286                          */
 287
 288                         /*
 289                          * i2c-core always sets the buffer length of
 290                          * I2C_FUNC_SMBUS_BLOCK_DATA to 1. The length will
 291                          * be adjusted when receiving the first byte.
 292                          * Thus we can't stop the transaction here.
 293                          */
 294                         if (dev->msg_write_idx == dev->msgs_num - 1 &&
 295                             buf_len == 1 && !(flags & I2C_M_RECV_LEN))
 296                                 cmd |= BIT(9);
 297
 298                         if (need_restart) {
 299                                 cmd |= BIT(10);
 300                                 need_restart = false;
 301                         }
 302
 303                         if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
 304
 305                                 /* Avoid rx buffer overrun */
 306                                 if (dev->rx_outstanding >= dev->rx_fifo_depth)
 307                                         break;
 308
 309                                 dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD);
 310                                 rx_limit--;
 311                                 dev->rx_outstanding++;
 312                         } else
 313                                 dw_writel(dev, cmd | *buf++, DW_IC_DATA_CMD);
 314                         tx_limit--; buf_len--;
 315                 }
 316
 317                 dev->tx_buf = buf;
 318                 dev->tx_buf_len = buf_len;
 319
 320                 /*
 321                  * Because we don't know the buffer length in the
 322                  * I2C_FUNC_SMBUS_BLOCK_DATA case, we can't stop
 323                  * the transaction here.
 324                  */
 325                 if (buf_len > 0 || flags & I2C_M_RECV_LEN) {
 326                         /* more bytes to be written */
 327                         dev->status |= STATUS_WRITE_IN_PROGRESS;
 328                         break;
 329                 } else
 330                         dev->status &= ~STATUS_WRITE_IN_PROGRESS;
 331         }
 332
 333         /*
 334          * If i2c_msg index search is completed, we don't need TX_EMPTY
 335          * interrupt any more.
 336          */
 337         if (dev->msg_write_idx == dev->msgs_num)
 338                 intr_mask &= ~DW_IC_INTR_TX_EMPTY;
 339
 340         if (dev->msg_err)
 341                 intr_mask = 0;
 342
 343         dw_writel(dev, intr_mask,  DW_IC_INTR_MASK);
 344 }
 345
 346 static u8
 347 i2c_dw_recv_len(struct dw_i2c_dev *dev, u8 len)
 348 {
 349         struct i2c_msg *msgs = dev->msgs;
 350         u32 flags = msgs[dev->msg_read_idx].flags;
 351
 352         /*
 353          * Adjust the buffer length and mask the flag
 354          * after receiving the first byte.
 355          */
 356         len += (flags & I2C_CLIENT_PEC) ? 2 : 1;
 357         dev->tx_buf_len = len - min_t(u8, len, dev->rx_outstanding);
 358         msgs[dev->msg_read_idx].len = len;
 359         msgs[dev->msg_read_idx].flags &= ~I2C_M_RECV_LEN;
 360
 361         return len;
 362 }
 363
 364 static void
 365 i2c_dw_read(struct dw_i2c_dev *dev)
 366 {
 367         struct i2c_msg *msgs = dev->msgs;
 368         int rx_valid;
 369
 370         for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
 371                 u32 len;
 372                 u8 *buf;
 373
 374                 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
 375                         continue;
 376
 377                 if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
 378                         len = msgs[dev->msg_read_idx].len;
 379                         buf = msgs[dev->msg_read_idx].buf;
 380                 } else {
 381                         len = dev->rx_buf_len;
 382                         buf = dev->rx_buf;
 383                 }
 384
 385                 rx_valid = dw_readl(dev, DW_IC_RXFLR);
 386
 387                 for (; len > 0 && rx_valid > 0; len--, rx_valid--) {
 388                         u32 flags = msgs[dev->msg_read_idx].flags;
 389
 390                         *buf = dw_readl(dev, DW_IC_DATA_CMD);
 391                         /* Ensure length byte is a valid value */
 392                         if (flags & I2C_M_RECV_LEN &&
 393                                 *buf <= I2C_SMBUS_BLOCK_MAX && *buf > 0) {
 394                                 len = i2c_dw_recv_len(dev, *buf);
 395                         }
 396                         buf++;
 397                         dev->rx_outstanding--;
 398                 }
 399
 400                 if (len > 0) {
 401                         dev->status |= STATUS_READ_IN_PROGRESS;
 402                         dev->rx_buf_len = len;
 403                         dev->rx_buf = buf;
 404                         return;
 405                 } else
 406                         dev->status &= ~STATUS_READ_IN_PROGRESS;
 407         }
 408 }
 409
 410 /*
 411  * Prepare controller for a transaction and call i2c_dw_xfer_msg.
 412  */
 413 static int
 414 i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 415 {
 416         struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
 417         int ret;
 418
 419         dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
 420
 421         pm_runtime_get_sync(dev->dev);
 422
 423         reinit_completion(&dev->cmd_complete);
 424         dev->msgs = msgs;
 425         dev->msgs_num = num;
 426         dev->cmd_err = 0;
 427         dev->msg_write_idx = 0;
 428         dev->msg_read_idx = 0;
 429         dev->msg_err = 0;
 430         dev->status = STATUS_IDLE;
 431         dev->abort_source = 0;
 432         dev->rx_outstanding = 0;
 433
 434         ret = i2c_dw_acquire_lock(dev);
 435         if (ret)
 436                 goto done_nolock;
 437
 438         ret = i2c_dw_wait_bus_not_busy(dev);
 439         if (ret < 0)
 440                 goto done;
 441
 442         /* Start the transfers */
 443         i2c_dw_xfer_init(dev);
 444
 445         /* Wait for tx to complete */
 446         if (!wait_for_completion_timeout(&dev->cmd_complete, adap->timeout)) {
 447                 dev_err(dev->dev, "controller timed out\n");
 448                 /* i2c_dw_init implicitly disables the adapter */
 449                 i2c_dw_init_master(dev);
 450                 ret = -ETIMEDOUT;
 451                 goto done;
 452         }
 453
 454         /*
 455          * We must disable the adapter before returning and signaling the end
 456          * of the current transfer. Otherwise the hardware might continue
 457          * generating interrupts which in turn causes a race condition with
 458          * the following transfer.  Needs some more investigation if the
 459          * additional interrupts are a hardware bug or this driver doesn't
 460          * handle them correctly yet.
 461          */
 462         __i2c_dw_enable(dev, false);
 463
 464         if (dev->msg_err) {
 465                 ret = dev->msg_err;
 466                 goto done;
 467         }
 468
 469         /* No error */
 470         if (likely(!dev->cmd_err && !dev->status)) {
 471                 ret = num;
 472                 goto done;
 473         }
 474
 475         /* We have an error */
 476         if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
 477                 ret = i2c_dw_handle_tx_abort(dev);
 478                 goto done;
 479         }
 480
 481         if (dev->status)
 482                 dev_err(dev->dev,
 483                         "transfer terminated early - interrupt latency too high?\n");
 484
 485         ret = -EIO;
 486
 487 done:
 488         i2c_dw_release_lock(dev);
 489
 490 done_nolock:
 491         pm_runtime_mark_last_busy(dev->dev);
 492         pm_runtime_put_autosuspend(dev->dev);
 493
 494         return ret;
 495 }
 496
 497 static const struct i2c_algorithm i2c_dw_algo = {
 498         .master_xfer = i2c_dw_xfer,
 499         .functionality = i2c_dw_func,
 500 };
 501
 502 static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
 503 {
 504         u32 stat;
 505
 506         /*
 507          * The IC_INTR_STAT register just indicates "enabled" interrupts.
 508          * Ths unmasked raw version of interrupt status bits are available
 509          * in the IC_RAW_INTR_STAT register.
 510          *
 511          * That is,
 512          *   stat = dw_readl(IC_INTR_STAT);
 513          * equals to,
 514          *   stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK);
 515          *
 516          * The raw version might be useful for debugging purposes.
 517          */
 518         stat = dw_readl(dev, DW_IC_INTR_STAT);
 519
 520         /*
 521          * Do not use the IC_CLR_INTR register to clear interrupts, or
 522          * you'll miss some interrupts, triggered during the period from
 523          * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR).
 524          *
 525          * Instead, use the separately-prepared IC_CLR_* registers.
 526          */
 527         if (stat & DW_IC_INTR_RX_UNDER)
 528                 dw_readl(dev, DW_IC_CLR_RX_UNDER);
 529         if (stat & DW_IC_INTR_RX_OVER)
 530                 dw_readl(dev, DW_IC_CLR_RX_OVER);
 531         if (stat & DW_IC_INTR_TX_OVER)
 532                 dw_readl(dev, DW_IC_CLR_TX_OVER);
 533         if (stat & DW_IC_INTR_RD_REQ)
 534                 dw_readl(dev, DW_IC_CLR_RD_REQ);
 535         if (stat & DW_IC_INTR_TX_ABRT) {
 536                 /*
 537                  * The IC_TX_ABRT_SOURCE register is cleared whenever
 538                  * the IC_CLR_TX_ABRT is read.  Preserve it beforehand.
 539                  */
 540                 dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE);
 541                 dw_readl(dev, DW_IC_CLR_TX_ABRT);
 542         }
 543         if (stat & DW_IC_INTR_RX_DONE)
 544                 dw_readl(dev, DW_IC_CLR_RX_DONE);
 545         if (stat & DW_IC_INTR_ACTIVITY)
 546                 dw_readl(dev, DW_IC_CLR_ACTIVITY);
 547         if (stat & DW_IC_INTR_STOP_DET)
 548                 dw_readl(dev, DW_IC_CLR_STOP_DET);
 549         if (stat & DW_IC_INTR_START_DET)
 550                 dw_readl(dev, DW_IC_CLR_START_DET);
 551         if (stat & DW_IC_INTR_GEN_CALL)
 552                 dw_readl(dev, DW_IC_CLR_GEN_CALL);
 553
 554         return stat;
 555 }
 556
 557 /*
 558  * Interrupt service routine. This gets called whenever an I2C master interrupt
 559  * occurs.
 560  */
 561 static int i2c_dw_irq_handler_master(struct dw_i2c_dev *dev)
 562 {
 563         u32 stat;
 564
 565         stat = i2c_dw_read_clear_intrbits(dev);
 566         if (stat & DW_IC_INTR_TX_ABRT) {
 567                 dev->cmd_err |= DW_IC_ERR_TX_ABRT;
 568                 dev->status = STATUS_IDLE;
 569
 570                 /*
 571                  * Anytime TX_ABRT is set, the contents of the tx/rx
 572                  * buffers are flushed. Make sure to skip them.
 573                  */
 574                 dw_writel(dev, 0, DW_IC_INTR_MASK);
 575                 goto tx_aborted;
 576         }
 577
 578         if (stat & DW_IC_INTR_RX_FULL)
 579                 i2c_dw_read(dev);
 580
 581         if (stat & DW_IC_INTR_TX_EMPTY)
 582                 i2c_dw_xfer_msg(dev);
 583
 584         /*
 585          * No need to modify or disable the interrupt mask here.
 586          * i2c_dw_xfer_msg() will take care of it according to
 587          * the current transmit status.
 588          */
 589
 590 tx_aborted:
 591         if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err)
 592                 complete(&dev->cmd_complete);
 593         else if (unlikely(dev->flags & ACCESS_INTR_MASK)) {
 594                 /* Workaround to trigger pending interrupt */
 595                 stat = dw_readl(dev, DW_IC_INTR_MASK);
 596                 i2c_dw_disable_int(dev);
 597                 dw_writel(dev, stat, DW_IC_INTR_MASK);
 598         }
 599
 600         return 0;
 601 }
 602
 603 static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
 604 {
 605         struct dw_i2c_dev *dev = dev_id;
 606         u32 stat, enabled;
 607
 608         enabled = dw_readl(dev, DW_IC_ENABLE);
 609         stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
 610         dev_dbg(dev->dev, "enabled=%#x stat=%#x\n", enabled, stat);
 611         if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
 612                 return IRQ_NONE;
 613
 614         i2c_dw_irq_handler_master(dev);
 615
 616         return IRQ_HANDLED;
 617 }
 618
 619 int i2c_dw_probe(struct dw_i2c_dev *dev)
 620 {
 621         struct i2c_adapter *adap = &dev->adapter;
 622         unsigned long irq_flags;
 623         int ret;
 624
 625         init_completion(&dev->cmd_complete);
 626
 627         dev->init = i2c_dw_init_master;
 628         dev->disable = i2c_dw_disable;
 629         dev->disable_int = i2c_dw_disable_int;
 630
 631         ret = dev->init(dev);
 632         if (ret)
 633                 return ret;
 634
 635         snprintf(adap->name, sizeof(adap->name),
 636                  "Synopsys DesignWare I2C adapter");
 637         adap->retries = 3;
 638         adap->algo = &i2c_dw_algo;
 639         adap->dev.parent = dev->dev;
 640         i2c_set_adapdata(adap, dev);
 641
 642         if (dev->pm_disabled) {
 643                 dev_pm_syscore_device(dev->dev, true);
 644                 irq_flags = IRQF_NO_SUSPEND;
 645         } else {
 646                 irq_flags = IRQF_SHARED | IRQF_COND_SUSPEND;
 647         }
 648
 649         i2c_dw_disable_int(dev);
 650         ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, irq_flags,
 651                                dev_name(dev->dev), dev);
 652         if (ret) {
 653                 dev_err(dev->dev, "failure requesting irq %i: %d\n",
 654                         dev->irq, ret);
 655                 return ret;
 656         }
 657
 658         /*
 659          * Increment PM usage count during adapter registration in order to
 660          * avoid possible spurious runtime suspend when adapter device is
 661          * registered to the device core and immediate resume in case bus has
 662          * registered I2C slaves that do I2C transfers in their probe.
 663          */
 664         pm_runtime_get_noresume(dev->dev);
 665         ret = i2c_add_numbered_adapter(adap);
 666         if (ret)
 667                 dev_err(dev->dev, "failure adding adapter: %d\n", ret);
 668         pm_runtime_put_noidle(dev->dev);
 669
 670         return ret;
 671 }
 672 EXPORT_SYMBOL_GPL(i2c_dw_probe);
 673
 674 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus master adapter");
 675 MODULE_LICENSE("GPL");