drivers/i2c/busses/i2c-eg20t.c

   1 /*
   2  * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/delay.h>
  17 #include <linux/errno.h>
  18 #include <linux/i2c.h>
  19 #include <linux/fs.h>
  20 #include <linux/io.h>
  21 #include <linux/types.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/jiffies.h>
  24 #include <linux/pci.h>
  25 #include <linux/mutex.h>
  26 #include <linux/ktime.h>
  27 #include <linux/slab.h>
  28
  29 #define PCH_EVENT_SET   0       /* I2C Interrupt Event Set Status */
  30 #define PCH_EVENT_NONE  1       /* I2C Interrupt Event Clear Status */
  31 #define PCH_MAX_CLK             100000  /* Maximum Clock speed in MHz */
  32 #define PCH_BUFFER_MODE_ENABLE  0x0002  /* flag for Buffer mode enable */
  33 #define PCH_EEPROM_SW_RST_MODE_ENABLE   0x0008  /* EEPROM SW RST enable flag */
  34
  35 #define PCH_I2CSADR     0x00    /* I2C slave address register */
  36 #define PCH_I2CCTL      0x04    /* I2C control register */
  37 #define PCH_I2CSR       0x08    /* I2C status register */
  38 #define PCH_I2CDR       0x0C    /* I2C data register */
  39 #define PCH_I2CMON      0x10    /* I2C bus monitor register */
  40 #define PCH_I2CBC       0x14    /* I2C bus transfer rate setup counter */
  41 #define PCH_I2CMOD      0x18    /* I2C mode register */
  42 #define PCH_I2CBUFSLV   0x1C    /* I2C buffer mode slave address register */
  43 #define PCH_I2CBUFSUB   0x20    /* I2C buffer mode subaddress register */
  44 #define PCH_I2CBUFFOR   0x24    /* I2C buffer mode format register */
  45 #define PCH_I2CBUFCTL   0x28    /* I2C buffer mode control register */
  46 #define PCH_I2CBUFMSK   0x2C    /* I2C buffer mode interrupt mask register */
  47 #define PCH_I2CBUFSTA   0x30    /* I2C buffer mode status register */
  48 #define PCH_I2CBUFLEV   0x34    /* I2C buffer mode level register */
  49 #define PCH_I2CESRFOR   0x38    /* EEPROM software reset mode format register */
  50 #define PCH_I2CESRCTL   0x3C    /* EEPROM software reset mode ctrl register */
  51 #define PCH_I2CESRMSK   0x40    /* EEPROM software reset mode */
  52 #define PCH_I2CESRSTA   0x44    /* EEPROM software reset mode status register */
  53 #define PCH_I2CTMR      0x48    /* I2C timer register */
  54 #define PCH_I2CSRST     0xFC    /* I2C reset register */
  55 #define PCH_I2CNF       0xF8    /* I2C noise filter register */
  56
  57 #define BUS_IDLE_TIMEOUT        20
  58 #define PCH_I2CCTL_I2CMEN       0x0080
  59 #define TEN_BIT_ADDR_DEFAULT    0xF000
  60 #define TEN_BIT_ADDR_MASK       0xF0
  61 #define PCH_START               0x0020
  62 #define PCH_RESTART             0x0004
  63 #define PCH_ESR_START           0x0001
  64 #define PCH_BUFF_START          0x1
  65 #define PCH_REPSTART            0x0004
  66 #define PCH_ACK                 0x0008
  67 #define PCH_GETACK              0x0001
  68 #define CLR_REG                 0x0
  69 #define I2C_RD                  0x1
  70 #define I2CMCF_BIT              0x0080
  71 #define I2CMIF_BIT              0x0002
  72 #define I2CMAL_BIT              0x0010
  73 #define I2CBMFI_BIT             0x0001
  74 #define I2CBMAL_BIT             0x0002
  75 #define I2CBMNA_BIT             0x0004
  76 #define I2CBMTO_BIT             0x0008
  77 #define I2CBMIS_BIT             0x0010
  78 #define I2CESRFI_BIT            0X0001
  79 #define I2CESRTO_BIT            0x0002
  80 #define I2CESRFIIE_BIT          0x1
  81 #define I2CESRTOIE_BIT          0x2
  82 #define I2CBMDZ_BIT             0x0040
  83 #define I2CBMAG_BIT             0x0020
  84 #define I2CMBB_BIT              0x0020
  85 #define BUFFER_MODE_MASK        (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
  86                                 I2CBMTO_BIT | I2CBMIS_BIT)
  87 #define I2C_ADDR_MSK            0xFF
  88 #define I2C_MSB_2B_MSK          0x300
  89 #define FAST_MODE_CLK           400
  90 #define FAST_MODE_EN            0x0001
  91 #define SUB_ADDR_LEN_MAX        4
  92 #define BUF_LEN_MAX             32
  93 #define PCH_BUFFER_MODE         0x1
  94 #define EEPROM_SW_RST_MODE      0x0002
  95 #define NORMAL_INTR_ENBL        0x0300
  96 #define EEPROM_RST_INTR_ENBL    (I2CESRFIIE_BIT | I2CESRTOIE_BIT)
  97 #define EEPROM_RST_INTR_DISBL   0x0
  98 #define BUFFER_MODE_INTR_ENBL   0x001F
  99 #define BUFFER_MODE_INTR_DISBL  0x0
 100 #define NORMAL_MODE             0x0
 101 #define BUFFER_MODE             0x1
 102 #define EEPROM_SR_MODE          0x2
 103 #define I2C_TX_MODE             0x0010
 104 #define PCH_BUF_TX              0xFFF7
 105 #define PCH_BUF_RD              0x0008
 106 #define I2C_ERROR_MASK  (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
 107                         I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
 108 #define I2CMAL_EVENT            0x0001
 109 #define I2CMCF_EVENT            0x0002
 110 #define I2CBMFI_EVENT           0x0004
 111 #define I2CBMAL_EVENT           0x0008
 112 #define I2CBMNA_EVENT           0x0010
 113 #define I2CBMTO_EVENT           0x0020
 114 #define I2CBMIS_EVENT           0x0040
 115 #define I2CESRFI_EVENT          0x0080
 116 #define I2CESRTO_EVENT          0x0100
 117 #define PCI_DEVICE_ID_PCH_I2C   0x8817
 118
 119 #define pch_dbg(adap, fmt, arg...)  \
 120         dev_dbg(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
 121
 122 #define pch_err(adap, fmt, arg...)  \
 123         dev_err(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
 124
 125 #define pch_pci_err(pdev, fmt, arg...)  \
 126         dev_err(&pdev->dev, "%s :" fmt, __func__, ##arg)
 127
 128 #define pch_pci_dbg(pdev, fmt, arg...)  \
 129         dev_dbg(&pdev->dev, "%s :" fmt, __func__, ##arg)
 130
 131 /*
 132 Set the number of I2C instance max
 133 Intel EG20T PCH :               1ch
 134 LAPIS Semiconductor ML7213 IOH :        2ch
 135 LAPIS Semiconductor ML7831 IOH :        1ch
 136 */
 137 #define PCH_I2C_MAX_DEV                 2
 138
 139 /**
 140  * struct i2c_algo_pch_data - for I2C driver functionalities
 141  * @pch_adapter:                stores the reference to i2c_adapter structure
 142  * @p_adapter_info:             stores the reference to adapter_info structure
 143  * @pch_base_address:           specifies the remapped base address
 144  * @pch_buff_mode_en:           specifies if buffer mode is enabled
 145  * @pch_event_flag:             specifies occurrence of interrupt events
 146  * @pch_i2c_xfer_in_progress:   specifies whether the transfer is completed
 147  */
 148 struct i2c_algo_pch_data {
 149         struct i2c_adapter pch_adapter;
 150         struct adapter_info *p_adapter_info;
 151         void __iomem *pch_base_address;
 152         int pch_buff_mode_en;
 153         u32 pch_event_flag;
 154         bool pch_i2c_xfer_in_progress;
 155 };
 156
 157 /**
 158  * struct adapter_info - This structure holds the adapter information for the
 159                          PCH i2c controller
 160  * @pch_data:           stores a list of i2c_algo_pch_data
 161  * @pch_i2c_suspended:  specifies whether the system is suspended or not
 162  *                      perhaps with more lines and words.
 163  * @ch_num:             specifies the number of i2c instance
 164  *
 165  * pch_data has as many elements as maximum I2C channels
 166  */
 167 struct adapter_info {
 168         struct i2c_algo_pch_data pch_data[PCH_I2C_MAX_DEV];
 169         bool pch_i2c_suspended;
 170         int ch_num;
 171 };
 172
 173
 174 static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
 175 static int pch_clk = 50000;     /* specifies I2C clock speed in KHz */
 176 static wait_queue_head_t pch_event;
 177 static DEFINE_MUTEX(pch_mutex);
 178
 179 /* Definition for ML7213 by LAPIS Semiconductor */
 180 #define PCI_VENDOR_ID_ROHM              0x10DB
 181 #define PCI_DEVICE_ID_ML7213_I2C        0x802D
 182 #define PCI_DEVICE_ID_ML7223_I2C        0x8010
 183 #define PCI_DEVICE_ID_ML7831_I2C        0x8817
 184
 185 static const struct pci_device_id pch_pcidev_id[] = {
 186         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH_I2C),   1, },
 187         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_I2C), 2, },
 188         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_I2C), 1, },
 189         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_I2C), 1, },
 190         {0,}
 191 };
 192 MODULE_DEVICE_TABLE(pci, pch_pcidev_id);
 193
 194 static irqreturn_t pch_i2c_handler(int irq, void *pData);
 195
 196 static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
 197 {
 198         u32 val;
 199         val = ioread32(addr + offset);
 200         val |= bitmask;
 201         iowrite32(val, addr + offset);
 202 }
 203
 204 static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
 205 {
 206         u32 val;
 207         val = ioread32(addr + offset);
 208         val &= (~bitmask);
 209         iowrite32(val, addr + offset);
 210 }
 211
 212 /**
 213  * pch_i2c_init() - hardware initialization of I2C module
 214  * @adap:       Pointer to struct i2c_algo_pch_data.
 215  */
 216 static void pch_i2c_init(struct i2c_algo_pch_data *adap)
 217 {
 218         void __iomem *p = adap->pch_base_address;
 219         u32 pch_i2cbc;
 220         u32 pch_i2ctmr;
 221         u32 reg_value;
 222
 223         /* reset I2C controller */
 224         iowrite32(0x01, p + PCH_I2CSRST);
 225         msleep(20);
 226         iowrite32(0x0, p + PCH_I2CSRST);
 227
 228         /* Initialize I2C registers */
 229         iowrite32(0x21, p + PCH_I2CNF);
 230
 231         pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_I2CCTL_I2CMEN);
 232
 233         if (pch_i2c_speed != 400)
 234                 pch_i2c_speed = 100;
 235
 236         reg_value = PCH_I2CCTL_I2CMEN;
 237         if (pch_i2c_speed == FAST_MODE_CLK) {
 238                 reg_value |= FAST_MODE_EN;
 239                 pch_dbg(adap, "Fast mode enabled\n");
 240         }
 241
 242         if (pch_clk > PCH_MAX_CLK)
 243                 pch_clk = 62500;
 244
 245         pch_i2cbc = (pch_clk + (pch_i2c_speed * 4)) / (pch_i2c_speed * 8);
 246         /* Set transfer speed in I2CBC */
 247         iowrite32(pch_i2cbc, p + PCH_I2CBC);
 248
 249         pch_i2ctmr = (pch_clk) / 8;
 250         iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
 251
 252         reg_value |= NORMAL_INTR_ENBL;  /* Enable interrupts in normal mode */
 253         iowrite32(reg_value, p + PCH_I2CCTL);
 254
 255         pch_dbg(adap,
 256                 "I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
 257                 ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
 258
 259         init_waitqueue_head(&pch_event);
 260 }
 261
 262 /**
 263  * pch_i2c_wait_for_bus_idle() - check the status of bus.
 264  * @adap:       Pointer to struct i2c_algo_pch_data.
 265  * @timeout:    waiting time counter (ms).
 266  */
 267 static s32 pch_i2c_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
 268                                      s32 timeout)
 269 {
 270         void __iomem *p = adap->pch_base_address;
 271         int schedule = 0;
 272         unsigned long end = jiffies + msecs_to_jiffies(timeout);
 273
 274         while (ioread32(p + PCH_I2CSR) & I2CMBB_BIT) {
 275                 if (time_after(jiffies, end)) {
 276                         pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
 277                         pch_err(adap, "%s: Timeout Error.return%d\n",
 278                                         __func__, -ETIME);
 279                         pch_i2c_init(adap);
 280
 281                         return -ETIME;
 282                 }
 283
 284                 if (!schedule)
 285                         /* Retry after some usecs */
 286                         udelay(5);
 287                 else
 288                         /* Wait a bit more without consuming CPU */
 289                         usleep_range(20, 1000);
 290
 291                 schedule = 1;
 292         }
 293
 294         return 0;
 295 }
 296
 297 /**
 298  * pch_i2c_start() - Generate I2C start condition in normal mode.
 299  * @adap:       Pointer to struct i2c_algo_pch_data.
 300  *
 301  * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1.
 302  */
 303 static void pch_i2c_start(struct i2c_algo_pch_data *adap)
 304 {
 305         void __iomem *p = adap->pch_base_address;
 306         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 307         pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
 308 }
 309
 310 /**
 311  * pch_i2c_stop() - generate stop condition in normal mode.
 312  * @adap:       Pointer to struct i2c_algo_pch_data.
 313  */
 314 static void pch_i2c_stop(struct i2c_algo_pch_data *adap)
 315 {
 316         void __iomem *p = adap->pch_base_address;
 317         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 318         /* clear the start bit */
 319         pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
 320 }
 321
 322 static int pch_i2c_wait_for_check_xfer(struct i2c_algo_pch_data *adap)
 323 {
 324         long ret;
 325         void __iomem *p = adap->pch_base_address;
 326
 327         ret = wait_event_timeout(pch_event,
 328                         (adap->pch_event_flag != 0), msecs_to_jiffies(1000));
 329         if (!ret) {
 330                 pch_err(adap, "%s:wait-event timeout\n", __func__);
 331                 adap->pch_event_flag = 0;
 332                 pch_i2c_stop(adap);
 333                 pch_i2c_init(adap);
 334                 return -ETIMEDOUT;
 335         }
 336
 337         if (adap->pch_event_flag & I2C_ERROR_MASK) {
 338                 pch_err(adap, "Lost Arbitration\n");
 339                 adap->pch_event_flag = 0;
 340                 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMAL_BIT);
 341                 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
 342                 pch_i2c_init(adap);
 343                 return -EAGAIN;
 344         }
 345
 346         adap->pch_event_flag = 0;
 347
 348         if (ioread32(p + PCH_I2CSR) & PCH_GETACK) {
 349                 pch_dbg(adap, "Receive NACK for slave address setting\n");
 350                 return -ENXIO;
 351         }
 352
 353         return 0;
 354 }
 355
 356 /**
 357  * pch_i2c_repstart() - generate repeated start condition in normal mode
 358  * @adap:       Pointer to struct i2c_algo_pch_data.
 359  */
 360 static void pch_i2c_repstart(struct i2c_algo_pch_data *adap)
 361 {
 362         void __iomem *p = adap->pch_base_address;
 363         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 364         pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_REPSTART);
 365 }
 366
 367 /**
 368  * pch_i2c_writebytes() - write data to I2C bus in normal mode
 369  * @i2c_adap:   Pointer to the struct i2c_adapter.
 370  * @last:       specifies whether last message or not.
 371  *              In the case of compound mode it will be 1 for last message,
 372  *              otherwise 0.
 373  * @first:      specifies whether first message or not.
 374  *              1 for first message otherwise 0.
 375  */
 376 static s32 pch_i2c_writebytes(struct i2c_adapter *i2c_adap,
 377                               struct i2c_msg *msgs, u32 last, u32 first)
 378 {
 379         struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
 380         u8 *buf;
 381         u32 length;
 382         u32 addr;
 383         u32 addr_2_msb;
 384         u32 addr_8_lsb;
 385         s32 wrcount;
 386         s32 rtn;
 387         void __iomem *p = adap->pch_base_address;
 388
 389         length = msgs->len;
 390         buf = msgs->buf;
 391         addr = msgs->addr;
 392
 393         /* enable master tx */
 394         pch_setbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
 395
 396         pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL),
 397                 length);
 398
 399         if (first) {
 400                 if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
 401                         return -ETIME;
 402         }
 403
 404         if (msgs->flags & I2C_M_TEN) {
 405                 addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7) & 0x06;
 406                 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
 407                 if (first)
 408                         pch_i2c_start(adap);
 409
 410                 rtn = pch_i2c_wait_for_check_xfer(adap);
 411                 if (rtn)
 412                         return rtn;
 413
 414                 addr_8_lsb = (addr & I2C_ADDR_MSK);
 415                 iowrite32(addr_8_lsb, p + PCH_I2CDR);
 416         } else {
 417                 /* set 7 bit slave address and R/W bit as 0 */
 418                 iowrite32(addr << 1, p + PCH_I2CDR);
 419                 if (first)
 420                         pch_i2c_start(adap);
 421         }
 422
 423         rtn = pch_i2c_wait_for_check_xfer(adap);
 424         if (rtn)
 425                 return rtn;
 426
 427         for (wrcount = 0; wrcount < length; ++wrcount) {
 428                 /* write buffer value to I2C data register */
 429                 iowrite32(buf[wrcount], p + PCH_I2CDR);
 430                 pch_dbg(adap, "writing %x to Data register\n", buf[wrcount]);
 431
 432                 rtn = pch_i2c_wait_for_check_xfer(adap);
 433                 if (rtn)
 434                         return rtn;
 435
 436                 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMCF_BIT);
 437                 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
 438         }
 439
 440         /* check if this is the last message */
 441         if (last)
 442                 pch_i2c_stop(adap);
 443         else
 444                 pch_i2c_repstart(adap);
 445
 446         pch_dbg(adap, "return=%d\n", wrcount);
 447
 448         return wrcount;
 449 }
 450
 451 /**
 452  * pch_i2c_sendack() - send ACK
 453  * @adap:       Pointer to struct i2c_algo_pch_data.
 454  */
 455 static void pch_i2c_sendack(struct i2c_algo_pch_data *adap)
 456 {
 457         void __iomem *p = adap->pch_base_address;
 458         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 459         pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
 460 }
 461
 462 /**
 463  * pch_i2c_sendnack() - send NACK
 464  * @adap:       Pointer to struct i2c_algo_pch_data.
 465  */
 466 static void pch_i2c_sendnack(struct i2c_algo_pch_data *adap)
 467 {
 468         void __iomem *p = adap->pch_base_address;
 469         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 470         pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
 471 }
 472
 473 /**
 474  * pch_i2c_restart() - Generate I2C restart condition in normal mode.
 475  * @adap:       Pointer to struct i2c_algo_pch_data.
 476  *
 477  * Generate I2C restart condition in normal mode by setting I2CCTL.I2CRSTA.
 478  */
 479 static void pch_i2c_restart(struct i2c_algo_pch_data *adap)
 480 {
 481         void __iomem *p = adap->pch_base_address;
 482         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 483         pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_RESTART);
 484 }
 485
 486 /**
 487  * pch_i2c_readbytes() - read data  from I2C bus in normal mode.
 488  * @i2c_adap:   Pointer to the struct i2c_adapter.
 489  * @msgs:       Pointer to i2c_msg structure.
 490  * @last:       specifies whether last message or not.
 491  * @first:      specifies whether first message or not.
 492  */
 493 static s32 pch_i2c_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
 494                              u32 last, u32 first)
 495 {
 496         struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
 497
 498         u8 *buf;
 499         u32 count;
 500         u32 length;
 501         u32 addr;
 502         u32 addr_2_msb;
 503         u32 addr_8_lsb;
 504         void __iomem *p = adap->pch_base_address;
 505         s32 rtn;
 506
 507         length = msgs->len;
 508         buf = msgs->buf;
 509         addr = msgs->addr;
 510
 511         /* enable master reception */
 512         pch_clrbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
 513
 514         if (first) {
 515                 if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
 516                         return -ETIME;
 517         }
 518
 519         if (msgs->flags & I2C_M_TEN) {
 520                 addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
 521                 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
 522                 if (first)
 523                         pch_i2c_start(adap);
 524
 525                 rtn = pch_i2c_wait_for_check_xfer(adap);
 526                 if (rtn)
 527                         return rtn;
 528
 529                 addr_8_lsb = (addr & I2C_ADDR_MSK);
 530                 iowrite32(addr_8_lsb, p + PCH_I2CDR);
 531
 532                 pch_i2c_restart(adap);
 533
 534                 rtn = pch_i2c_wait_for_check_xfer(adap);
 535                 if (rtn)
 536                         return rtn;
 537
 538                 addr_2_msb |= I2C_RD;
 539                 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
 540         } else {
 541                 /* 7 address bits + R/W bit */
 542                 addr = (((addr) << 1) | (I2C_RD));
 543                 iowrite32(addr, p + PCH_I2CDR);
 544         }
 545
 546         /* check if it is the first message */
 547         if (first)
 548                 pch_i2c_start(adap);
 549
 550         rtn = pch_i2c_wait_for_check_xfer(adap);
 551         if (rtn)
 552                 return rtn;
 553
 554         if (length == 0) {
 555                 pch_i2c_stop(adap);
 556                 ioread32(p + PCH_I2CDR); /* Dummy read needs */
 557
 558                 count = length;
 559         } else {
 560                 int read_index;
 561                 int loop;
 562                 pch_i2c_sendack(adap);
 563
 564                 /* Dummy read */
 565                 for (loop = 1, read_index = 0; loop < length; loop++) {
 566                         buf[read_index] = ioread32(p + PCH_I2CDR);
 567
 568                         if (loop != 1)
 569                                 read_index++;
 570
 571                         rtn = pch_i2c_wait_for_check_xfer(adap);
 572                         if (rtn)
 573                                 return rtn;
 574                 }       /* end for */
 575
 576                 pch_i2c_sendnack(adap);
 577
 578                 buf[read_index] = ioread32(p + PCH_I2CDR); /* Read final - 1 */
 579
 580                 if (length != 1)
 581                         read_index++;
 582
 583                 rtn = pch_i2c_wait_for_check_xfer(adap);
 584                 if (rtn)
 585                         return rtn;
 586
 587                 if (last)
 588                         pch_i2c_stop(adap);
 589                 else
 590                         pch_i2c_repstart(adap);
 591
 592                 buf[read_index++] = ioread32(p + PCH_I2CDR); /* Read Final */
 593                 count = read_index;
 594         }
 595
 596         return count;
 597 }
 598
 599 /**
 600  * pch_i2c_cb() - Interrupt handler Call back function
 601  * @adap:       Pointer to struct i2c_algo_pch_data.
 602  */
 603 static void pch_i2c_cb(struct i2c_algo_pch_data *adap)
 604 {
 605         u32 sts;
 606         void __iomem *p = adap->pch_base_address;
 607
 608         sts = ioread32(p + PCH_I2CSR);
 609         sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
 610         if (sts & I2CMAL_BIT)
 611                 adap->pch_event_flag |= I2CMAL_EVENT;
 612
 613         if (sts & I2CMCF_BIT)
 614                 adap->pch_event_flag |= I2CMCF_EVENT;
 615
 616         /* clear the applicable bits */
 617         pch_clrbit(adap->pch_base_address, PCH_I2CSR, sts);
 618
 619         pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR));
 620
 621         wake_up(&pch_event);
 622 }
 623
 624 /**
 625  * pch_i2c_handler() - interrupt handler for the PCH I2C controller
 626  * @irq:        irq number.
 627  * @pData:      cookie passed back to the handler function.
 628  */
 629 static irqreturn_t pch_i2c_handler(int irq, void *pData)
 630 {
 631         u32 reg_val;
 632         int flag;
 633         int i;
 634         struct adapter_info *adap_info = pData;
 635         void __iomem *p;
 636         u32 mode;
 637
 638         for (i = 0, flag = 0; i < adap_info->ch_num; i++) {
 639                 p = adap_info->pch_data[i].pch_base_address;
 640                 mode = ioread32(p + PCH_I2CMOD);
 641                 mode &= BUFFER_MODE | EEPROM_SR_MODE;
 642                 if (mode != NORMAL_MODE) {
 643                         pch_err(adap_info->pch_data,
 644                                 "I2C-%d mode(%d) is not supported\n", mode, i);
 645                         continue;
 646                 }
 647                 reg_val = ioread32(p + PCH_I2CSR);
 648                 if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT)) {
 649                         pch_i2c_cb(&adap_info->pch_data[i]);
 650                         flag = 1;
 651                 }
 652         }
 653
 654         return flag ? IRQ_HANDLED : IRQ_NONE;
 655 }
 656
 657 /**
 658  * pch_i2c_xfer() - Reading adnd writing data through I2C bus
 659  * @i2c_adap:   Pointer to the struct i2c_adapter.
 660  * @msgs:       Pointer to i2c_msg structure.
 661  * @num:        number of messages.
 662  */
 663 static s32 pch_i2c_xfer(struct i2c_adapter *i2c_adap,
 664                         struct i2c_msg *msgs, s32 num)
 665 {
 666         struct i2c_msg *pmsg;
 667         u32 i = 0;
 668         u32 status;
 669         s32 ret;
 670
 671         struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
 672
 673         ret = mutex_lock_interruptible(&pch_mutex);
 674         if (ret)
 675                 return ret;
 676
 677         if (adap->p_adapter_info->pch_i2c_suspended) {
 678                 mutex_unlock(&pch_mutex);
 679                 return -EBUSY;
 680         }
 681
 682         pch_dbg(adap, "adap->p_adapter_info->pch_i2c_suspended is %d\n",
 683                 adap->p_adapter_info->pch_i2c_suspended);
 684         /* transfer not completed */
 685         adap->pch_i2c_xfer_in_progress = true;
 686
 687         for (i = 0; i < num && ret >= 0; i++) {
 688                 pmsg = &msgs[i];
 689                 pmsg->flags |= adap->pch_buff_mode_en;
 690                 status = pmsg->flags;
 691                 pch_dbg(adap,
 692                         "After invoking I2C_MODE_SEL :flag= 0x%x\n", status);
 693
 694                 if ((status & (I2C_M_RD)) != false) {
 695                         ret = pch_i2c_readbytes(i2c_adap, pmsg, (i + 1 == num),
 696                                                 (i == 0));
 697                 } else {
 698                         ret = pch_i2c_writebytes(i2c_adap, pmsg, (i + 1 == num),
 699                                                  (i == 0));
 700                 }
 701         }
 702
 703         adap->pch_i2c_xfer_in_progress = false; /* transfer completed */
 704
 705         mutex_unlock(&pch_mutex);
 706
 707         return (ret < 0) ? ret : num;
 708 }
 709
 710 /**
 711  * pch_i2c_func() - return the functionality of the I2C driver
 712  * @adap:       Pointer to struct i2c_algo_pch_data.
 713  */
 714 static u32 pch_i2c_func(struct i2c_adapter *adap)
 715 {
 716         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
 717 }
 718
 719 static struct i2c_algorithm pch_algorithm = {
 720         .master_xfer = pch_i2c_xfer,
 721         .functionality = pch_i2c_func
 722 };
 723
 724 /**
 725  * pch_i2c_disbl_int() - Disable PCH I2C interrupts
 726  * @adap:       Pointer to struct i2c_algo_pch_data.
 727  */
 728 static void pch_i2c_disbl_int(struct i2c_algo_pch_data *adap)
 729 {
 730         void __iomem *p = adap->pch_base_address;
 731
 732         pch_clrbit(adap->pch_base_address, PCH_I2CCTL, NORMAL_INTR_ENBL);
 733
 734         iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
 735
 736         iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
 737 }
 738
 739 static int pch_i2c_probe(struct pci_dev *pdev,
 740                                    const struct pci_device_id *id)
 741 {
 742         void __iomem *base_addr;
 743         int ret;
 744         int i, j;
 745         struct adapter_info *adap_info;
 746         struct i2c_adapter *pch_adap;
 747
 748         pch_pci_dbg(pdev, "Entered.\n");
 749
 750         adap_info = kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
 751         if (adap_info == NULL)
 752                 return -ENOMEM;
 753
 754         ret = pci_enable_device(pdev);
 755         if (ret) {
 756                 pch_pci_err(pdev, "pci_enable_device FAILED\n");
 757                 goto err_pci_enable;
 758         }
 759
 760         ret = pci_request_regions(pdev, KBUILD_MODNAME);
 761         if (ret) {
 762                 pch_pci_err(pdev, "pci_request_regions FAILED\n");
 763                 goto err_pci_req;
 764         }
 765
 766         base_addr = pci_iomap(pdev, 1, 0);
 767
 768         if (base_addr == NULL) {
 769                 pch_pci_err(pdev, "pci_iomap FAILED\n");
 770                 ret = -ENOMEM;
 771                 goto err_pci_iomap;
 772         }
 773
 774         /* Set the number of I2C channel instance */
 775         adap_info->ch_num = id->driver_data;
 776
 777         for (i = 0; i < adap_info->ch_num; i++) {
 778                 pch_adap = &adap_info->pch_data[i].pch_adapter;
 779                 adap_info->pch_i2c_suspended = false;
 780
 781                 adap_info->pch_data[i].p_adapter_info = adap_info;
 782
 783                 pch_adap->owner = THIS_MODULE;
 784                 pch_adap->class = I2C_CLASS_HWMON;
 785                 strlcpy(pch_adap->name, KBUILD_MODNAME, sizeof(pch_adap->name));
 786                 pch_adap->algo = &pch_algorithm;
 787                 pch_adap->algo_data = &adap_info->pch_data[i];
 788
 789                 /* base_addr + offset; */
 790                 adap_info->pch_data[i].pch_base_address = base_addr + 0x100 * i;
 791
 792                 pch_adap->dev.of_node = pdev->dev.of_node;
 793                 pch_adap->dev.parent = &pdev->dev;
 794         }
 795
 796         ret = request_irq(pdev->irq, pch_i2c_handler, IRQF_SHARED,
 797                   KBUILD_MODNAME, adap_info);
 798         if (ret) {
 799                 pch_pci_err(pdev, "request_irq FAILED\n");
 800                 goto err_request_irq;
 801         }
 802
 803         for (i = 0; i < adap_info->ch_num; i++) {
 804                 pch_adap = &adap_info->pch_data[i].pch_adapter;
 805
 806                 pch_i2c_init(&adap_info->pch_data[i]);
 807
 808                 pch_adap->nr = i;
 809                 ret = i2c_add_numbered_adapter(pch_adap);
 810                 if (ret) {
 811                         pch_pci_err(pdev, "i2c_add_adapter[ch:%d] FAILED\n", i);
 812                         goto err_add_adapter;
 813                 }
 814         }
 815
 816         pci_set_drvdata(pdev, adap_info);
 817         pch_pci_dbg(pdev, "returns %d.\n", ret);
 818         return 0;
 819
 820 err_add_adapter:
 821         for (j = 0; j < i; j++)
 822                 i2c_del_adapter(&adap_info->pch_data[j].pch_adapter);
 823         free_irq(pdev->irq, adap_info);
 824 err_request_irq:
 825         pci_iounmap(pdev, base_addr);
 826 err_pci_iomap:
 827         pci_release_regions(pdev);
 828 err_pci_req:
 829         pci_disable_device(pdev);
 830 err_pci_enable:
 831         kfree(adap_info);
 832         return ret;
 833 }
 834
 835 static void pch_i2c_remove(struct pci_dev *pdev)
 836 {
 837         int i;
 838         struct adapter_info *adap_info = pci_get_drvdata(pdev);
 839
 840         free_irq(pdev->irq, adap_info);
 841
 842         for (i = 0; i < adap_info->ch_num; i++) {
 843                 pch_i2c_disbl_int(&adap_info->pch_data[i]);
 844                 i2c_del_adapter(&adap_info->pch_data[i].pch_adapter);
 845         }
 846
 847         if (adap_info->pch_data[0].pch_base_address)
 848                 pci_iounmap(pdev, adap_info->pch_data[0].pch_base_address);
 849
 850         for (i = 0; i < adap_info->ch_num; i++)
 851                 adap_info->pch_data[i].pch_base_address = NULL;
 852
 853         pci_release_regions(pdev);
 854
 855         pci_disable_device(pdev);
 856         kfree(adap_info);
 857 }
 858
 859 #ifdef CONFIG_PM
 860 static int pch_i2c_suspend(struct pci_dev *pdev, pm_message_t state)
 861 {
 862         int ret;
 863         int i;
 864         struct adapter_info *adap_info = pci_get_drvdata(pdev);
 865         void __iomem *p = adap_info->pch_data[0].pch_base_address;
 866
 867         adap_info->pch_i2c_suspended = true;
 868
 869         for (i = 0; i < adap_info->ch_num; i++) {
 870                 while ((adap_info->pch_data[i].pch_i2c_xfer_in_progress)) {
 871                         /* Wait until all channel transfers are completed */
 872                         msleep(20);
 873                 }
 874         }
 875
 876         /* Disable the i2c interrupts */
 877         for (i = 0; i < adap_info->ch_num; i++)
 878                 pch_i2c_disbl_int(&adap_info->pch_data[i]);
 879
 880         pch_pci_dbg(pdev, "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
 881                 "invoked function pch_i2c_disbl_int successfully\n",
 882                 ioread32(p + PCH_I2CSR), ioread32(p + PCH_I2CBUFSTA),
 883                 ioread32(p + PCH_I2CESRSTA));
 884
 885         ret = pci_save_state(pdev);
 886
 887         if (ret) {
 888                 pch_pci_err(pdev, "pci_save_state\n");
 889                 return ret;
 890         }
 891
 892         pci_enable_wake(pdev, PCI_D3hot, 0);
 893         pci_disable_device(pdev);
 894         pci_set_power_state(pdev, pci_choose_state(pdev, state));
 895
 896         return 0;
 897 }
 898
 899 static int pch_i2c_resume(struct pci_dev *pdev)
 900 {
 901         int i;
 902         struct adapter_info *adap_info = pci_get_drvdata(pdev);
 903
 904         pci_set_power_state(pdev, PCI_D0);
 905         pci_restore_state(pdev);
 906
 907         if (pci_enable_device(pdev) < 0) {
 908                 pch_pci_err(pdev, "pch_i2c_resume:pci_enable_device FAILED\n");
 909                 return -EIO;
 910         }
 911
 912         pci_enable_wake(pdev, PCI_D3hot, 0);
 913
 914         for (i = 0; i < adap_info->ch_num; i++)
 915                 pch_i2c_init(&adap_info->pch_data[i]);
 916
 917         adap_info->pch_i2c_suspended = false;
 918
 919         return 0;
 920 }
 921 #else
 922 #define pch_i2c_suspend NULL
 923 #define pch_i2c_resume NULL
 924 #endif
 925
 926 static struct pci_driver pch_pcidriver = {
 927         .name = KBUILD_MODNAME,
 928         .id_table = pch_pcidev_id,
 929         .probe = pch_i2c_probe,
 930         .remove = pch_i2c_remove,
 931         .suspend = pch_i2c_suspend,
 932         .resume = pch_i2c_resume
 933 };
 934
 935 module_pci_driver(pch_pcidriver);
 936
 937 MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semico ML7213/ML7223/ML7831 IOH I2C");
 938 MODULE_LICENSE("GPL");
 939 MODULE_AUTHOR("Tomoya MORINAGA. <tomoya.rohm@gmail.com>");
 940 module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
 941 module_param(pch_clk, int, (S_IRUSR | S_IWUSR));