drivers/i2c/busses/i2c-i801.c

   1 /*
   2     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   3     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   4     <mdsxyz123@yahoo.com>
   5     Copyright (C) 2007 - 2014  Jean Delvare <jdelvare@suse.de>
   6     Copyright (C) 2010         Intel Corporation,
   7                                David Woodhouse <dwmw2@infradead.org>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18 */
  19
  20 /*
  21  * Supports the following Intel I/O Controller Hubs (ICH):
  22  *
  23  *                                      I/O                     Block   I2C
  24  *                                      region  SMBus   Block   proc.   block
  25  * Chip name                    PCI ID  size    PEC     buffer  call    read
  26  * ---------------------------------------------------------------------------
  27  * 82801AA (ICH)                0x2413  16      no      no      no      no
  28  * 82801AB (ICH0)               0x2423  16      no      no      no      no
  29  * 82801BA (ICH2)               0x2443  16      no      no      no      no
  30  * 82801CA (ICH3)               0x2483  32      soft    no      no      no
  31  * 82801DB (ICH4)               0x24c3  32      hard    yes     no      no
  32  * 82801E (ICH5)                0x24d3  32      hard    yes     yes     yes
  33  * 6300ESB                      0x25a4  32      hard    yes     yes     yes
  34  * 82801F (ICH6)                0x266a  32      hard    yes     yes     yes
  35  * 6310ESB/6320ESB              0x269b  32      hard    yes     yes     yes
  36  * 82801G (ICH7)                0x27da  32      hard    yes     yes     yes
  37  * 82801H (ICH8)                0x283e  32      hard    yes     yes     yes
  38  * 82801I (ICH9)                0x2930  32      hard    yes     yes     yes
  39  * EP80579 (Tolapai)            0x5032  32      hard    yes     yes     yes
  40  * ICH10                        0x3a30  32      hard    yes     yes     yes
  41  * ICH10                        0x3a60  32      hard    yes     yes     yes
  42  * 5/3400 Series (PCH)          0x3b30  32      hard    yes     yes     yes
  43  * 6 Series (PCH)               0x1c22  32      hard    yes     yes     yes
  44  * Patsburg (PCH)               0x1d22  32      hard    yes     yes     yes
  45  * Patsburg (PCH) IDF           0x1d70  32      hard    yes     yes     yes
  46  * Patsburg (PCH) IDF           0x1d71  32      hard    yes     yes     yes
  47  * Patsburg (PCH) IDF           0x1d72  32      hard    yes     yes     yes
  48  * DH89xxCC (PCH)               0x2330  32      hard    yes     yes     yes
  49  * Panther Point (PCH)          0x1e22  32      hard    yes     yes     yes
  50  * Lynx Point (PCH)             0x8c22  32      hard    yes     yes     yes
  51  * Lynx Point-LP (PCH)          0x9c22  32      hard    yes     yes     yes
  52  * Avoton (SOC)                 0x1f3c  32      hard    yes     yes     yes
  53  * Wellsburg (PCH)              0x8d22  32      hard    yes     yes     yes
  54  * Wellsburg (PCH) MS           0x8d7d  32      hard    yes     yes     yes
  55  * Wellsburg (PCH) MS           0x8d7e  32      hard    yes     yes     yes
  56  * Wellsburg (PCH) MS           0x8d7f  32      hard    yes     yes     yes
  57  * Coleto Creek (PCH)           0x23b0  32      hard    yes     yes     yes
  58  * Wildcat Point (PCH)          0x8ca2  32      hard    yes     yes     yes
  59  * Wildcat Point-LP (PCH)       0x9ca2  32      hard    yes     yes     yes
  60  * BayTrail (SOC)               0x0f12  32      hard    yes     yes     yes
  61  * Sunrise Point-H (PCH)        0xa123  32      hard    yes     yes     yes
  62  * Sunrise Point-LP (PCH)       0x9d23  32      hard    yes     yes     yes
  63  * DNV (SOC)                    0x19df  32      hard    yes     yes     yes
  64  * Broxton (SOC)                0x5ad4  32      hard    yes     yes     yes
  65  * Lewisburg (PCH)              0xa1a3  32      hard    yes     yes     yes
  66  * Lewisburg Supersku (PCH)     0xa223  32      hard    yes     yes     yes
  67  *
  68  * Features supported by this driver:
  69  * Software PEC                         no
  70  * Hardware PEC                         yes
  71  * Block buffer                         yes
  72  * Block process call transaction       no
  73  * I2C block read transaction           yes (doesn't use the block buffer)
  74  * Slave mode                           no
  75  * Interrupt processing                 yes
  76  *
  77  * See the file Documentation/i2c/busses/i2c-i801 for details.
  78  */
  79
  80 #include <linux/interrupt.h>
  81 #include <linux/module.h>
  82 #include <linux/pci.h>
  83 #include <linux/kernel.h>
  84 #include <linux/stddef.h>
  85 #include <linux/delay.h>
  86 #include <linux/ioport.h>
  87 #include <linux/init.h>
  88 #include <linux/i2c.h>
  89 #include <linux/acpi.h>
  90 #include <linux/io.h>
  91 #include <linux/dmi.h>
  92 #include <linux/slab.h>
  93 #include <linux/wait.h>
  94 #include <linux/err.h>
  95 #include <linux/platform_device.h>
  96 #include <linux/platform_data/itco_wdt.h>
  97
  98 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
  99                 defined CONFIG_DMI
 100 #include <linux/gpio.h>
 101 #include <linux/i2c-mux-gpio.h>
 102 #endif
 103
 104 /* I801 SMBus address offsets */
 105 #define SMBHSTSTS(p)    (0 + (p)->smba)
 106 #define SMBHSTCNT(p)    (2 + (p)->smba)
 107 #define SMBHSTCMD(p)    (3 + (p)->smba)
 108 #define SMBHSTADD(p)    (4 + (p)->smba)
 109 #define SMBHSTDAT0(p)   (5 + (p)->smba)
 110 #define SMBHSTDAT1(p)   (6 + (p)->smba)
 111 #define SMBBLKDAT(p)    (7 + (p)->smba)
 112 #define SMBPEC(p)       (8 + (p)->smba)         /* ICH3 and later */
 113 #define SMBAUXSTS(p)    (12 + (p)->smba)        /* ICH4 and later */
 114 #define SMBAUXCTL(p)    (13 + (p)->smba)        /* ICH4 and later */
 115
 116 /* PCI Address Constants */
 117 #define SMBBAR          4
 118 #define SMBPCICTL       0x004
 119 #define SMBPCISTS       0x006
 120 #define SMBHSTCFG       0x040
 121 #define TCOBASE         0x050
 122 #define TCOCTL          0x054
 123
 124 #define ACPIBASE                0x040
 125 #define ACPIBASE_SMI_OFF        0x030
 126 #define ACPICTRL                0x044
 127 #define ACPICTRL_EN             0x080
 128
 129 #define SBREG_BAR               0x10
 130 #define SBREG_SMBCTRL           0xc6000c
 131 #define SBREG_SMBCTRL_DNV       0xcf000c
 132
 133 /* Host status bits for SMBPCISTS */
 134 #define SMBPCISTS_INTS          0x08
 135
 136 /* Control bits for SMBPCICTL */
 137 #define SMBPCICTL_INTDIS        0x0400
 138
 139 /* Host configuration bits for SMBHSTCFG */
 140 #define SMBHSTCFG_HST_EN        1
 141 #define SMBHSTCFG_SMB_SMI_EN    2
 142 #define SMBHSTCFG_I2C_EN        4
 143
 144 /* TCO configuration bits for TCOCTL */
 145 #define TCOCTL_EN               0x0100
 146
 147 /* Auxiliary control register bits, ICH4+ only */
 148 #define SMBAUXCTL_CRC           1
 149 #define SMBAUXCTL_E32B          2
 150
 151 /* Other settings */
 152 #define MAX_RETRIES             400
 153
 154 /* I801 command constants */
 155 #define I801_QUICK              0x00
 156 #define I801_BYTE               0x04
 157 #define I801_BYTE_DATA          0x08
 158 #define I801_WORD_DATA          0x0C
 159 #define I801_PROC_CALL          0x10    /* unimplemented */
 160 #define I801_BLOCK_DATA         0x14
 161 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 162
 163 /* I801 Host Control register bits */
 164 #define SMBHSTCNT_INTREN        0x01
 165 #define SMBHSTCNT_KILL          0x02
 166 #define SMBHSTCNT_LAST_BYTE     0x20
 167 #define SMBHSTCNT_START         0x40
 168 #define SMBHSTCNT_PEC_EN        0x80    /* ICH3 and later */
 169
 170 /* I801 Hosts Status register bits */
 171 #define SMBHSTSTS_BYTE_DONE     0x80
 172 #define SMBHSTSTS_INUSE_STS     0x40
 173 #define SMBHSTSTS_SMBALERT_STS  0x20
 174 #define SMBHSTSTS_FAILED        0x10
 175 #define SMBHSTSTS_BUS_ERR       0x08
 176 #define SMBHSTSTS_DEV_ERR       0x04
 177 #define SMBHSTSTS_INTR          0x02
 178 #define SMBHSTSTS_HOST_BUSY     0x01
 179
 180 #define STATUS_ERROR_FLAGS      (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
 181                                  SMBHSTSTS_DEV_ERR)
 182
 183 #define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
 184                                  STATUS_ERROR_FLAGS)
 185
 186 /* Older devices have their ID defined in <linux/pci_ids.h> */
 187 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS              0x0f12
 188 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS              0x2292
 189 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS           0x1c22
 190 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS              0x1d22
 191 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
 192 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0         0x1d70
 193 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1         0x1d71
 194 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2         0x1d72
 195 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS          0x1e22
 196 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS                0x1f3c
 197 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS              0x2330
 198 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS           0x23b0
 199 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS         0x3b30
 200 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS             0x8c22
 201 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS          0x8ca2
 202 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS             0x8d22
 203 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0         0x8d7d
 204 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1         0x8d7e
 205 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2         0x8d7f
 206 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS          0x9c22
 207 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS       0x9ca2
 208 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS        0xa123
 209 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS       0x9d23
 210 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS                   0x19df
 211 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS               0x5ad4
 212 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS             0xa1a3
 213 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS        0xa223
 214
 215 struct i801_mux_config {
 216         char *gpio_chip;
 217         unsigned values[3];
 218         int n_values;
 219         unsigned classes[3];
 220         unsigned gpios[2];              /* Relative to gpio_chip->base */
 221         int n_gpios;
 222 };
 223
 224 struct i801_priv {
 225         struct i2c_adapter adapter;
 226         unsigned long smba;
 227         unsigned char original_hstcfg;
 228         struct pci_dev *pci_dev;
 229         unsigned int features;
 230
 231         /* isr processing */
 232         wait_queue_head_t waitq;
 233         u8 status;
 234
 235         /* Command state used by isr for byte-by-byte block transactions */
 236         u8 cmd;
 237         bool is_read;
 238         int count;
 239         int len;
 240         u8 *data;
 241
 242 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
 243                 defined CONFIG_DMI
 244         const struct i801_mux_config *mux_drvdata;
 245         struct platform_device *mux_pdev;
 246 #endif
 247         struct platform_device *tco_pdev;
 248
 249         /*
 250          * If set to true the host controller registers are reserved for
 251          * ACPI AML use. Protected by acpi_lock.
 252          */
 253         bool acpi_reserved;
 254         struct mutex acpi_lock;
 255 };
 256
 257 #define FEATURE_SMBUS_PEC       (1 << 0)
 258 #define FEATURE_BLOCK_BUFFER    (1 << 1)
 259 #define FEATURE_BLOCK_PROC      (1 << 2)
 260 #define FEATURE_I2C_BLOCK_READ  (1 << 3)
 261 #define FEATURE_IRQ             (1 << 4)
 262 /* Not really a feature, but it's convenient to handle it as such */
 263 #define FEATURE_IDF             (1 << 15)
 264 #define FEATURE_TCO             (1 << 16)
 265
 266 static const char *i801_feature_names[] = {
 267         "SMBus PEC",
 268         "Block buffer",
 269         "Block process call",
 270         "I2C block read",
 271         "Interrupt",
 272 };
 273
 274 static unsigned int disable_features;
 275 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
 276 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
 277         "\t\t  0x01  disable SMBus PEC\n"
 278         "\t\t  0x02  disable the block buffer\n"
 279         "\t\t  0x08  disable the I2C block read functionality\n"
 280         "\t\t  0x10  don't use interrupts ");
 281
 282 /* Make sure the SMBus host is ready to start transmitting.
 283    Return 0 if it is, -EBUSY if it is not. */
 284 static int i801_check_pre(struct i801_priv *priv)
 285 {
 286         int status;
 287
 288         status = inb_p(SMBHSTSTS(priv));
 289         if (status & SMBHSTSTS_HOST_BUSY) {
 290                 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
 291                 return -EBUSY;
 292         }
 293
 294         status &= STATUS_FLAGS;
 295         if (status) {
 296                 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
 297                         status);
 298                 outb_p(status, SMBHSTSTS(priv));
 299                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 300                 if (status) {
 301                         dev_err(&priv->pci_dev->dev,
 302                                 "Failed clearing status flags (%02x)\n",
 303                                 status);
 304                         return -EBUSY;
 305                 }
 306         }
 307
 308         return 0;
 309 }
 310
 311 /*
 312  * Convert the status register to an error code, and clear it.
 313  * Note that status only contains the bits we want to clear, not the
 314  * actual register value.
 315  */
 316 static int i801_check_post(struct i801_priv *priv, int status)
 317 {
 318         int result = 0;
 319
 320         /*
 321          * If the SMBus is still busy, we give up
 322          * Note: This timeout condition only happens when using polling
 323          * transactions.  For interrupt operation, NAK/timeout is indicated by
 324          * DEV_ERR.
 325          */
 326         if (unlikely(status < 0)) {
 327                 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
 328                 /* try to stop the current command */
 329                 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
 330                 outb_p(SMBHSTCNT_KILL, SMBHSTCNT(priv));
 331                 usleep_range(1000, 2000);
 332                 outb_p(0, SMBHSTCNT(priv));
 333
 334                 /* Check if it worked */
 335                 status = inb_p(SMBHSTSTS(priv));
 336                 if ((status & SMBHSTSTS_HOST_BUSY) ||
 337                     !(status & SMBHSTSTS_FAILED))
 338                         dev_err(&priv->pci_dev->dev,
 339                                 "Failed terminating the transaction\n");
 340                 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
 341                 return -ETIMEDOUT;
 342         }
 343
 344         if (status & SMBHSTSTS_FAILED) {
 345                 result = -EIO;
 346                 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
 347         }
 348         if (status & SMBHSTSTS_DEV_ERR) {
 349                 result = -ENXIO;
 350                 dev_dbg(&priv->pci_dev->dev, "No response\n");
 351         }
 352         if (status & SMBHSTSTS_BUS_ERR) {
 353                 result = -EAGAIN;
 354                 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
 355         }
 356
 357         /* Clear status flags except BYTE_DONE, to be cleared by caller */
 358         outb_p(status, SMBHSTSTS(priv));
 359
 360         return result;
 361 }
 362
 363 /* Wait for BUSY being cleared and either INTR or an error flag being set */
 364 static int i801_wait_intr(struct i801_priv *priv)
 365 {
 366         int timeout = 0;
 367         int status;
 368
 369         /* We will always wait for a fraction of a second! */
 370         do {
 371                 usleep_range(250, 500);
 372                 status = inb_p(SMBHSTSTS(priv));
 373         } while (((status & SMBHSTSTS_HOST_BUSY) ||
 374                   !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
 375                  (timeout++ < MAX_RETRIES));
 376
 377         if (timeout > MAX_RETRIES) {
 378                 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
 379                 return -ETIMEDOUT;
 380         }
 381         return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
 382 }
 383
 384 /* Wait for either BYTE_DONE or an error flag being set */
 385 static int i801_wait_byte_done(struct i801_priv *priv)
 386 {
 387         int timeout = 0;
 388         int status;
 389
 390         /* We will always wait for a fraction of a second! */
 391         do {
 392                 usleep_range(250, 500);
 393                 status = inb_p(SMBHSTSTS(priv));
 394         } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
 395                  (timeout++ < MAX_RETRIES));
 396
 397         if (timeout > MAX_RETRIES) {
 398                 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
 399                 return -ETIMEDOUT;
 400         }
 401         return status & STATUS_ERROR_FLAGS;
 402 }
 403
 404 static int i801_transaction(struct i801_priv *priv, int xact)
 405 {
 406         int status;
 407         int result;
 408         const struct i2c_adapter *adap = &priv->adapter;
 409
 410         result = i801_check_pre(priv);
 411         if (result < 0)
 412                 return result;
 413
 414         if (priv->features & FEATURE_IRQ) {
 415                 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
 416                        SMBHSTCNT(priv));
 417                 result = wait_event_timeout(priv->waitq,
 418                                             (status = priv->status),
 419                                             adap->timeout);
 420                 if (!result) {
 421                         status = -ETIMEDOUT;
 422                         dev_warn(&priv->pci_dev->dev,
 423                                  "Timeout waiting for interrupt!\n");
 424                 }
 425                 priv->status = 0;
 426                 return i801_check_post(priv, status);
 427         }
 428
 429         /* the current contents of SMBHSTCNT can be overwritten, since PEC,
 430          * SMBSCMD are passed in xact */
 431         outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
 432
 433         status = i801_wait_intr(priv);
 434         return i801_check_post(priv, status);
 435 }
 436
 437 static int i801_block_transaction_by_block(struct i801_priv *priv,
 438                                            union i2c_smbus_data *data,
 439                                            char read_write, int hwpec)
 440 {
 441         int i, len;
 442         int status;
 443
 444         inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
 445
 446         /* Use 32-byte buffer to process this transaction */
 447         if (read_write == I2C_SMBUS_WRITE) {
 448                 len = data->block[0];
 449                 outb_p(len, SMBHSTDAT0(priv));
 450                 for (i = 0; i < len; i++)
 451                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 452         }
 453
 454         status = i801_transaction(priv, I801_BLOCK_DATA |
 455                                   (hwpec ? SMBHSTCNT_PEC_EN : 0));
 456         if (status)
 457                 return status;
 458
 459         if (read_write == I2C_SMBUS_READ) {
 460                 len = inb_p(SMBHSTDAT0(priv));
 461                 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 462                         return -EPROTO;
 463
 464                 data->block[0] = len;
 465                 for (i = 0; i < len; i++)
 466                         data->block[i + 1] = inb_p(SMBBLKDAT(priv));
 467         }
 468         return 0;
 469 }
 470
 471 static void i801_isr_byte_done(struct i801_priv *priv)
 472 {
 473         if (priv->is_read) {
 474                 /* For SMBus block reads, length is received with first byte */
 475                 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
 476                     (priv->count == 0)) {
 477                         priv->len = inb_p(SMBHSTDAT0(priv));
 478                         if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
 479                                 dev_err(&priv->pci_dev->dev,
 480                                         "Illegal SMBus block read size %d\n",
 481                                         priv->len);
 482                                 /* FIXME: Recover */
 483                                 priv->len = I2C_SMBUS_BLOCK_MAX;
 484                         } else {
 485                                 dev_dbg(&priv->pci_dev->dev,
 486                                         "SMBus block read size is %d\n",
 487                                         priv->len);
 488                         }
 489                         priv->data[-1] = priv->len;
 490                 }
 491
 492                 /* Read next byte */
 493                 if (priv->count < priv->len)
 494                         priv->data[priv->count++] = inb(SMBBLKDAT(priv));
 495                 else
 496                         dev_dbg(&priv->pci_dev->dev,
 497                                 "Discarding extra byte on block read\n");
 498
 499                 /* Set LAST_BYTE for last byte of read transaction */
 500                 if (priv->count == priv->len - 1)
 501                         outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
 502                                SMBHSTCNT(priv));
 503         } else if (priv->count < priv->len - 1) {
 504                 /* Write next byte, except for IRQ after last byte */
 505                 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
 506         }
 507
 508         /* Clear BYTE_DONE to continue with next byte */
 509         outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 510 }
 511
 512 /*
 513  * There are two kinds of interrupts:
 514  *
 515  * 1) i801 signals transaction completion with one of these interrupts:
 516  *      INTR - Success
 517  *      DEV_ERR - Invalid command, NAK or communication timeout
 518  *      BUS_ERR - SMI# transaction collision
 519  *      FAILED - transaction was canceled due to a KILL request
 520  *    When any of these occur, update ->status and wake up the waitq.
 521  *    ->status must be cleared before kicking off the next transaction.
 522  *
 523  * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
 524  *    occurs for each byte of a byte-by-byte to prepare the next byte.
 525  */
 526 static irqreturn_t i801_isr(int irq, void *dev_id)
 527 {
 528         struct i801_priv *priv = dev_id;
 529         u16 pcists;
 530         u8 status;
 531
 532         /* Confirm this is our interrupt */
 533         pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
 534         if (!(pcists & SMBPCISTS_INTS))
 535                 return IRQ_NONE;
 536
 537         status = inb_p(SMBHSTSTS(priv));
 538         if (status & SMBHSTSTS_BYTE_DONE)
 539                 i801_isr_byte_done(priv);
 540
 541         /*
 542          * Clear irq sources and report transaction result.
 543          * ->status must be cleared before the next transaction is started.
 544          */
 545         status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
 546         if (status) {
 547                 outb_p(status, SMBHSTSTS(priv));
 548                 priv->status |= status;
 549                 wake_up(&priv->waitq);
 550         }
 551
 552         return IRQ_HANDLED;
 553 }
 554
 555 /*
 556  * For "byte-by-byte" block transactions:
 557  *   I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
 558  *   I2C read uses cmd=I801_I2C_BLOCK_DATA
 559  */
 560 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
 561                                                union i2c_smbus_data *data,
 562                                                char read_write, int command,
 563                                                int hwpec)
 564 {
 565         int i, len;
 566         int smbcmd;
 567         int status;
 568         int result;
 569         const struct i2c_adapter *adap = &priv->adapter;
 570
 571         result = i801_check_pre(priv);
 572         if (result < 0)
 573                 return result;
 574
 575         len = data->block[0];
 576
 577         if (read_write == I2C_SMBUS_WRITE) {
 578                 outb_p(len, SMBHSTDAT0(priv));
 579                 outb_p(data->block[1], SMBBLKDAT(priv));
 580         }
 581
 582         if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
 583             read_write == I2C_SMBUS_READ)
 584                 smbcmd = I801_I2C_BLOCK_DATA;
 585         else
 586                 smbcmd = I801_BLOCK_DATA;
 587
 588         if (priv->features & FEATURE_IRQ) {
 589                 priv->is_read = (read_write == I2C_SMBUS_READ);
 590                 if (len == 1 && priv->is_read)
 591                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 592                 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
 593                 priv->len = len;
 594                 priv->count = 0;
 595                 priv->data = &data->block[1];
 596
 597                 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
 598                 result = wait_event_timeout(priv->waitq,
 599                                             (status = priv->status),
 600                                             adap->timeout);
 601                 if (!result) {
 602                         status = -ETIMEDOUT;
 603                         dev_warn(&priv->pci_dev->dev,
 604                                  "Timeout waiting for interrupt!\n");
 605                 }
 606                 priv->status = 0;
 607                 return i801_check_post(priv, status);
 608         }
 609
 610         for (i = 1; i <= len; i++) {
 611                 if (i == len && read_write == I2C_SMBUS_READ)
 612                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 613                 outb_p(smbcmd, SMBHSTCNT(priv));
 614
 615                 if (i == 1)
 616                         outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
 617                                SMBHSTCNT(priv));
 618
 619                 status = i801_wait_byte_done(priv);
 620                 if (status)
 621                         goto exit;
 622
 623                 if (i == 1 && read_write == I2C_SMBUS_READ
 624                  && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 625                         len = inb_p(SMBHSTDAT0(priv));
 626                         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 627                                 dev_err(&priv->pci_dev->dev,
 628                                         "Illegal SMBus block read size %d\n",
 629                                         len);
 630                                 /* Recover */
 631                                 while (inb_p(SMBHSTSTS(priv)) &
 632                                        SMBHSTSTS_HOST_BUSY)
 633                                         outb_p(SMBHSTSTS_BYTE_DONE,
 634                                                SMBHSTSTS(priv));
 635                                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 636                                 return -EPROTO;
 637                         }
 638                         data->block[0] = len;
 639                 }
 640
 641                 /* Retrieve/store value in SMBBLKDAT */
 642                 if (read_write == I2C_SMBUS_READ)
 643                         data->block[i] = inb_p(SMBBLKDAT(priv));
 644                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 645                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 646
 647                 /* signals SMBBLKDAT ready */
 648                 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 649         }
 650
 651         status = i801_wait_intr(priv);
 652 exit:
 653         return i801_check_post(priv, status);
 654 }
 655
 656 static int i801_set_block_buffer_mode(struct i801_priv *priv)
 657 {
 658         outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
 659         if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
 660                 return -EIO;
 661         return 0;
 662 }
 663
 664 /* Block transaction function */
 665 static int i801_block_transaction(struct i801_priv *priv,
 666                                   union i2c_smbus_data *data, char read_write,
 667                                   int command, int hwpec)
 668 {
 669         int result = 0;
 670         unsigned char hostc;
 671
 672         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 673                 if (read_write == I2C_SMBUS_WRITE) {
 674                         /* set I2C_EN bit in configuration register */
 675                         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
 676                         pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
 677                                               hostc | SMBHSTCFG_I2C_EN);
 678                 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
 679                         dev_err(&priv->pci_dev->dev,
 680                                 "I2C block read is unsupported!\n");
 681                         return -EOPNOTSUPP;
 682                 }
 683         }
 684
 685         if (read_write == I2C_SMBUS_WRITE
 686          || command == I2C_SMBUS_I2C_BLOCK_DATA) {
 687                 if (data->block[0] < 1)
 688                         data->block[0] = 1;
 689                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
 690                         data->block[0] = I2C_SMBUS_BLOCK_MAX;
 691         } else {
 692                 data->block[0] = 32;    /* max for SMBus block reads */
 693         }
 694
 695         /* Experience has shown that the block buffer can only be used for
 696            SMBus (not I2C) block transactions, even though the datasheet
 697            doesn't mention this limitation. */
 698         if ((priv->features & FEATURE_BLOCK_BUFFER)
 699          && command != I2C_SMBUS_I2C_BLOCK_DATA
 700          && i801_set_block_buffer_mode(priv) == 0)
 701                 result = i801_block_transaction_by_block(priv, data,
 702                                                          read_write, hwpec);
 703         else
 704                 result = i801_block_transaction_byte_by_byte(priv, data,
 705                                                              read_write,
 706                                                              command, hwpec);
 707
 708         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 709          && read_write == I2C_SMBUS_WRITE) {
 710                 /* restore saved configuration register value */
 711                 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
 712         }
 713         return result;
 714 }
 715
 716 /* Return negative errno on error. */
 717 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
 718                        unsigned short flags, char read_write, u8 command,
 719                        int size, union i2c_smbus_data *data)
 720 {
 721         int hwpec;
 722         int block = 0;
 723         int ret = 0, xact = 0;
 724         struct i801_priv *priv = i2c_get_adapdata(adap);
 725
 726         mutex_lock(&priv->acpi_lock);
 727         if (priv->acpi_reserved) {
 728                 mutex_unlock(&priv->acpi_lock);
 729                 return -EBUSY;
 730         }
 731
 732         hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 733                 && size != I2C_SMBUS_QUICK
 734                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
 735
 736         switch (size) {
 737         case I2C_SMBUS_QUICK:
 738                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 739                        SMBHSTADD(priv));
 740                 xact = I801_QUICK;
 741                 break;
 742         case I2C_SMBUS_BYTE:
 743                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 744                        SMBHSTADD(priv));
 745                 if (read_write == I2C_SMBUS_WRITE)
 746                         outb_p(command, SMBHSTCMD(priv));
 747                 xact = I801_BYTE;
 748                 break;
 749         case I2C_SMBUS_BYTE_DATA:
 750                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 751                        SMBHSTADD(priv));
 752                 outb_p(command, SMBHSTCMD(priv));
 753                 if (read_write == I2C_SMBUS_WRITE)
 754                         outb_p(data->byte, SMBHSTDAT0(priv));
 755                 xact = I801_BYTE_DATA;
 756                 break;
 757         case I2C_SMBUS_WORD_DATA:
 758                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 759                        SMBHSTADD(priv));
 760                 outb_p(command, SMBHSTCMD(priv));
 761                 if (read_write == I2C_SMBUS_WRITE) {
 762                         outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 763                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 764                 }
 765                 xact = I801_WORD_DATA;
 766                 break;
 767         case I2C_SMBUS_BLOCK_DATA:
 768                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 769                        SMBHSTADD(priv));
 770                 outb_p(command, SMBHSTCMD(priv));
 771                 block = 1;
 772                 break;
 773         case I2C_SMBUS_I2C_BLOCK_DATA:
 774                 /* NB: page 240 of ICH5 datasheet shows that the R/#W
 775                  * bit should be cleared here, even when reading */
 776                 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
 777                 if (read_write == I2C_SMBUS_READ) {
 778                         /* NB: page 240 of ICH5 datasheet also shows
 779                          * that DATA1 is the cmd field when reading */
 780                         outb_p(command, SMBHSTDAT1(priv));
 781                 } else
 782                         outb_p(command, SMBHSTCMD(priv));
 783                 block = 1;
 784                 break;
 785         default:
 786                 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
 787                         size);
 788                 ret = -EOPNOTSUPP;
 789                 goto out;
 790         }
 791
 792         if (hwpec)      /* enable/disable hardware PEC */
 793                 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
 794         else
 795                 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
 796                        SMBAUXCTL(priv));
 797
 798         if (block)
 799                 ret = i801_block_transaction(priv, data, read_write, size,
 800                                              hwpec);
 801         else
 802                 ret = i801_transaction(priv, xact);
 803
 804         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 805            time, so we forcibly disable it after every transaction. Turn off
 806            E32B for the same reason. */
 807         if (hwpec || block)
 808                 outb_p(inb_p(SMBAUXCTL(priv)) &
 809                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 810
 811         if (block)
 812                 goto out;
 813         if (ret)
 814                 goto out;
 815         if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 816                 goto out;
 817
 818         switch (xact & 0x7f) {
 819         case I801_BYTE: /* Result put in SMBHSTDAT0 */
 820         case I801_BYTE_DATA:
 821                 data->byte = inb_p(SMBHSTDAT0(priv));
 822                 break;
 823         case I801_WORD_DATA:
 824                 data->word = inb_p(SMBHSTDAT0(priv)) +
 825                              (inb_p(SMBHSTDAT1(priv)) << 8);
 826                 break;
 827         }
 828
 829 out:
 830         mutex_unlock(&priv->acpi_lock);
 831         return ret;
 832 }
 833
 834
 835 static u32 i801_func(struct i2c_adapter *adapter)
 836 {
 837         struct i801_priv *priv = i2c_get_adapdata(adapter);
 838
 839         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 840                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 841                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 842                ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 843                ((priv->features & FEATURE_I2C_BLOCK_READ) ?
 844                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
 845 }
 846
 847 static const struct i2c_algorithm smbus_algorithm = {
 848         .smbus_xfer     = i801_access,
 849         .functionality  = i801_func,
 850 };
 851
 852 static const struct pci_device_id i801_ids[] = {
 853         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
 854         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
 855         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
 856         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
 857         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
 858         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
 859         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
 860         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
 861         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
 862         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
 863         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
 864         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
 865         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
 866         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
 867         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
 868         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
 869         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
 870         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
 871         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
 872         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
 873         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
 874         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
 875         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
 876         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
 877         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
 878         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
 879         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
 880         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
 881         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
 882         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
 883         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
 884         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
 885         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
 886         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
 887         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
 888         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
 889         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
 890         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
 891         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) },
 892         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) },
 893         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) },
 894         { 0, }
 895 };
 896
 897 MODULE_DEVICE_TABLE(pci, i801_ids);
 898
 899 #if defined CONFIG_X86 && defined CONFIG_DMI
 900 static unsigned char apanel_addr;
 901
 902 /* Scan the system ROM for the signature "FJKEYINF" */
 903 static __init const void __iomem *bios_signature(const void __iomem *bios)
 904 {
 905         ssize_t offset;
 906         const unsigned char signature[] = "FJKEYINF";
 907
 908         for (offset = 0; offset < 0x10000; offset += 0x10) {
 909                 if (check_signature(bios + offset, signature,
 910                                     sizeof(signature)-1))
 911                         return bios + offset;
 912         }
 913         return NULL;
 914 }
 915
 916 static void __init input_apanel_init(void)
 917 {
 918         void __iomem *bios;
 919         const void __iomem *p;
 920
 921         bios = ioremap(0xF0000, 0x10000); /* Can't fail */
 922         p = bios_signature(bios);
 923         if (p) {
 924                 /* just use the first address */
 925                 apanel_addr = readb(p + 8 + 3) >> 1;
 926         }
 927         iounmap(bios);
 928 }
 929
 930 struct dmi_onboard_device_info {
 931         const char *name;
 932         u8 type;
 933         unsigned short i2c_addr;
 934         const char *i2c_type;
 935 };
 936
 937 static const struct dmi_onboard_device_info dmi_devices[] = {
 938         { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
 939         { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
 940         { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
 941 };
 942
 943 static void dmi_check_onboard_device(u8 type, const char *name,
 944                                      struct i2c_adapter *adap)
 945 {
 946         int i;
 947         struct i2c_board_info info;
 948
 949         for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
 950                 /* & ~0x80, ignore enabled/disabled bit */
 951                 if ((type & ~0x80) != dmi_devices[i].type)
 952                         continue;
 953                 if (strcasecmp(name, dmi_devices[i].name))
 954                         continue;
 955
 956                 memset(&info, 0, sizeof(struct i2c_board_info));
 957                 info.addr = dmi_devices[i].i2c_addr;
 958                 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
 959                 i2c_new_device(adap, &info);
 960                 break;
 961         }
 962 }
 963
 964 /* We use our own function to check for onboard devices instead of
 965    dmi_find_device() as some buggy BIOS's have the devices we are interested
 966    in marked as disabled */
 967 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
 968 {
 969         int i, count;
 970
 971         if (dm->type != 10)
 972                 return;
 973
 974         count = (dm->length - sizeof(struct dmi_header)) / 2;
 975         for (i = 0; i < count; i++) {
 976                 const u8 *d = (char *)(dm + 1) + (i * 2);
 977                 const char *name = ((char *) dm) + dm->length;
 978                 u8 type = d[0];
 979                 u8 s = d[1];
 980
 981                 if (!s)
 982                         continue;
 983                 s--;
 984                 while (s > 0 && name[0]) {
 985                         name += strlen(name) + 1;
 986                         s--;
 987                 }
 988                 if (name[0] == 0) /* Bogus string reference */
 989                         continue;
 990
 991                 dmi_check_onboard_device(type, name, adap);
 992         }
 993 }
 994
 995 /* Register optional slaves */
 996 static void i801_probe_optional_slaves(struct i801_priv *priv)
 997 {
 998         /* Only register slaves on main SMBus channel */
 999         if (priv->features & FEATURE_IDF)
1000                 return;
1001
1002         if (apanel_addr) {
1003                 struct i2c_board_info info;
1004
1005                 memset(&info, 0, sizeof(struct i2c_board_info));
1006                 info.addr = apanel_addr;
1007                 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
1008                 i2c_new_device(&priv->adapter, &info);
1009         }
1010
1011         if (dmi_name_in_vendors("FUJITSU"))
1012                 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1013 }
1014 #else
1015 static void __init input_apanel_init(void) {}
1016 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1017 #endif  /* CONFIG_X86 && CONFIG_DMI */
1018
1019 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
1020                 defined CONFIG_DMI
1021 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1022         .gpio_chip = "gpio_ich",
1023         .values = { 0x02, 0x03 },
1024         .n_values = 2,
1025         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1026         .gpios = { 52, 53 },
1027         .n_gpios = 2,
1028 };
1029
1030 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1031         .gpio_chip = "gpio_ich",
1032         .values = { 0x02, 0x03, 0x01 },
1033         .n_values = 3,
1034         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1035         .gpios = { 52, 53 },
1036         .n_gpios = 2,
1037 };
1038
1039 static const struct dmi_system_id mux_dmi_table[] = {
1040         {
1041                 .matches = {
1042                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1043                         DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1044                 },
1045                 .driver_data = &i801_mux_config_asus_z8_d12,
1046         },
1047         {
1048                 .matches = {
1049                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1050                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1051                 },
1052                 .driver_data = &i801_mux_config_asus_z8_d12,
1053         },
1054         {
1055                 .matches = {
1056                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1057                         DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1058                 },
1059                 .driver_data = &i801_mux_config_asus_z8_d12,
1060         },
1061         {
1062                 .matches = {
1063                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1064                         DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1065                 },
1066                 .driver_data = &i801_mux_config_asus_z8_d12,
1067         },
1068         {
1069                 .matches = {
1070                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1071                         DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1072                 },
1073                 .driver_data = &i801_mux_config_asus_z8_d12,
1074         },
1075         {
1076                 .matches = {
1077                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1078                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1079                 },
1080                 .driver_data = &i801_mux_config_asus_z8_d12,
1081         },
1082         {
1083                 .matches = {
1084                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1085                         DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1086                 },
1087                 .driver_data = &i801_mux_config_asus_z8_d18,
1088         },
1089         {
1090                 .matches = {
1091                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1092                         DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1093                 },
1094                 .driver_data = &i801_mux_config_asus_z8_d18,
1095         },
1096         {
1097                 .matches = {
1098                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1099                         DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1100                 },
1101                 .driver_data = &i801_mux_config_asus_z8_d12,
1102         },
1103         { }
1104 };
1105
1106 /* Setup multiplexing if needed */
1107 static int i801_add_mux(struct i801_priv *priv)
1108 {
1109         struct device *dev = &priv->adapter.dev;
1110         const struct i801_mux_config *mux_config;
1111         struct i2c_mux_gpio_platform_data gpio_data;
1112         int err;
1113
1114         if (!priv->mux_drvdata)
1115                 return 0;
1116         mux_config = priv->mux_drvdata;
1117
1118         /* Prepare the platform data */
1119         memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1120         gpio_data.parent = priv->adapter.nr;
1121         gpio_data.values = mux_config->values;
1122         gpio_data.n_values = mux_config->n_values;
1123         gpio_data.classes = mux_config->classes;
1124         gpio_data.gpio_chip = mux_config->gpio_chip;
1125         gpio_data.gpios = mux_config->gpios;
1126         gpio_data.n_gpios = mux_config->n_gpios;
1127         gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1128
1129         /* Register the mux device */
1130         priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1131                                 PLATFORM_DEVID_AUTO, &gpio_data,
1132                                 sizeof(struct i2c_mux_gpio_platform_data));
1133         if (IS_ERR(priv->mux_pdev)) {
1134                 err = PTR_ERR(priv->mux_pdev);
1135                 priv->mux_pdev = NULL;
1136                 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1137                 return err;
1138         }
1139
1140         return 0;
1141 }
1142
1143 static void i801_del_mux(struct i801_priv *priv)
1144 {
1145         if (priv->mux_pdev)
1146                 platform_device_unregister(priv->mux_pdev);
1147 }
1148
1149 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1150 {
1151         const struct dmi_system_id *id;
1152         const struct i801_mux_config *mux_config;
1153         unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1154         int i;
1155
1156         id = dmi_first_match(mux_dmi_table);
1157         if (id) {
1158                 /* Remove branch classes from trunk */
1159                 mux_config = id->driver_data;
1160                 for (i = 0; i < mux_config->n_values; i++)
1161                         class &= ~mux_config->classes[i];
1162
1163                 /* Remember for later */
1164                 priv->mux_drvdata = mux_config;
1165         }
1166
1167         return class;
1168 }
1169 #else
1170 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1171 static inline void i801_del_mux(struct i801_priv *priv) { }
1172
1173 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1174 {
1175         return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1176 }
1177 #endif
1178
1179 static const struct itco_wdt_platform_data tco_platform_data = {
1180         .name = "Intel PCH",
1181         .version = 4,
1182 };
1183
1184 static DEFINE_SPINLOCK(p2sb_spinlock);
1185
1186 static void i801_add_tco(struct i801_priv *priv)
1187 {
1188         struct pci_dev *pci_dev = priv->pci_dev;
1189         struct resource tco_res[3], *res;
1190         struct platform_device *pdev;
1191         unsigned int devfn;
1192         u32 tco_base, tco_ctl;
1193         u32 base_addr, ctrl_val;
1194         u64 base64_addr;
1195
1196         if (!(priv->features & FEATURE_TCO))
1197                 return;
1198
1199         pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1200         pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1201         if (!(tco_ctl & TCOCTL_EN))
1202                 return;
1203
1204         memset(tco_res, 0, sizeof(tco_res));
1205
1206         res = &tco_res[ICH_RES_IO_TCO];
1207         res->start = tco_base & ~1;
1208         res->end = res->start + 32 - 1;
1209         res->flags = IORESOURCE_IO;
1210
1211         /*
1212          * Power Management registers.
1213          */
1214         devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2);
1215         pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, &base_addr);
1216
1217         res = &tco_res[ICH_RES_IO_SMI];
1218         res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF;
1219         res->end = res->start + 3;
1220         res->flags = IORESOURCE_IO;
1221
1222         /*
1223          * Enable the ACPI I/O space.
1224          */
1225         pci_bus_read_config_dword(pci_dev->bus, devfn, ACPICTRL, &ctrl_val);
1226         ctrl_val |= ACPICTRL_EN;
1227         pci_bus_write_config_dword(pci_dev->bus, devfn, ACPICTRL, ctrl_val);
1228
1229         /*
1230          * We must access the NO_REBOOT bit over the Primary to Sideband
1231          * bridge (P2SB). The BIOS prevents the P2SB device from being
1232          * enumerated by the PCI subsystem, so we need to unhide/hide it
1233          * to lookup the P2SB BAR.
1234          */
1235         spin_lock(&p2sb_spinlock);
1236
1237         devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
1238
1239         /* Unhide the P2SB device */
1240         pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
1241
1242         pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
1243         base64_addr = base_addr & 0xfffffff0;
1244
1245         pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
1246         base64_addr |= (u64)base_addr << 32;
1247
1248         /* Hide the P2SB device */
1249         pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x1);
1250         spin_unlock(&p2sb_spinlock);
1251
1252         res = &tco_res[ICH_RES_MEM_OFF];
1253         if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
1254                 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV;
1255         else
1256                 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1257
1258         res->end = res->start + 3;
1259         res->flags = IORESOURCE_MEM;
1260
1261         pdev = platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1262                                                  tco_res, 3, &tco_platform_data,
1263                                                  sizeof(tco_platform_data));
1264         if (IS_ERR(pdev)) {
1265                 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1266                 return;
1267         }
1268
1269         priv->tco_pdev = pdev;
1270 }
1271
1272 #ifdef CONFIG_ACPI
1273 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv,
1274                                       acpi_physical_address address)
1275 {
1276         return address >= priv->smba &&
1277                address <= pci_resource_end(priv->pci_dev, SMBBAR);
1278 }
1279
1280 static acpi_status
1281 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1282                      u64 *value, void *handler_context, void *region_context)
1283 {
1284         struct i801_priv *priv = handler_context;
1285         struct pci_dev *pdev = priv->pci_dev;
1286         acpi_status status;
1287
1288         /*
1289          * Once BIOS AML code touches the OpRegion we warn and inhibit any
1290          * further access from the driver itself. This device is now owned
1291          * by the system firmware.
1292          */
1293         mutex_lock(&priv->acpi_lock);
1294
1295         if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) {
1296                 priv->acpi_reserved = true;
1297
1298                 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1299                 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1300         }
1301
1302         if ((function & ACPI_IO_MASK) == ACPI_READ)
1303                 status = acpi_os_read_port(address, (u32 *)value, bits);
1304         else
1305                 status = acpi_os_write_port(address, (u32)*value, bits);
1306
1307         mutex_unlock(&priv->acpi_lock);
1308
1309         return status;
1310 }
1311
1312 static int i801_acpi_probe(struct i801_priv *priv)
1313 {
1314         struct acpi_device *adev;
1315         acpi_status status;
1316
1317         adev = ACPI_COMPANION(&priv->pci_dev->dev);
1318         if (adev) {
1319                 status = acpi_install_address_space_handler(adev->handle,
1320                                 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler,
1321                                 NULL, priv);
1322                 if (ACPI_SUCCESS(status))
1323                         return 0;
1324         }
1325
1326         return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1327 }
1328
1329 static void i801_acpi_remove(struct i801_priv *priv)
1330 {
1331         struct acpi_device *adev;
1332
1333         adev = ACPI_COMPANION(&priv->pci_dev->dev);
1334         if (!adev)
1335                 return;
1336
1337         acpi_remove_address_space_handler(adev->handle,
1338                 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1339 }
1340 #else
1341 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
1342 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1343 #endif
1344
1345 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1346 {
1347         unsigned char temp;
1348         int err, i;
1349         struct i801_priv *priv;
1350
1351         priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1352         if (!priv)
1353                 return -ENOMEM;
1354
1355         i2c_set_adapdata(&priv->adapter, priv);
1356         priv->adapter.owner = THIS_MODULE;
1357         priv->adapter.class = i801_get_adapter_class(priv);
1358         priv->adapter.algo = &smbus_algorithm;
1359         priv->adapter.dev.parent = &dev->dev;
1360         ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1361         priv->adapter.retries = 3;
1362         mutex_init(&priv->acpi_lock);
1363
1364         priv->pci_dev = dev;
1365         switch (dev->device) {
1366         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS:
1367         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS:
1368         case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS:
1369         case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS:
1370         case PCI_DEVICE_ID_INTEL_DNV_SMBUS:
1371                 priv->features |= FEATURE_I2C_BLOCK_READ;
1372                 priv->features |= FEATURE_IRQ;
1373                 priv->features |= FEATURE_SMBUS_PEC;
1374                 priv->features |= FEATURE_BLOCK_BUFFER;
1375                 priv->features |= FEATURE_TCO;
1376                 break;
1377
1378         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1379         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1380         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1381         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1382         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1383         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1384                 priv->features |= FEATURE_IDF;
1385                 /* fall through */
1386         default:
1387                 priv->features |= FEATURE_I2C_BLOCK_READ;
1388                 priv->features |= FEATURE_IRQ;
1389                 /* fall through */
1390         case PCI_DEVICE_ID_INTEL_82801DB_3:
1391                 priv->features |= FEATURE_SMBUS_PEC;
1392                 priv->features |= FEATURE_BLOCK_BUFFER;
1393                 /* fall through */
1394         case PCI_DEVICE_ID_INTEL_82801CA_3:
1395         case PCI_DEVICE_ID_INTEL_82801BA_2:
1396         case PCI_DEVICE_ID_INTEL_82801AB_3:
1397         case PCI_DEVICE_ID_INTEL_82801AA_3:
1398                 break;
1399         }
1400
1401         /* Disable features on user request */
1402         for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1403                 if (priv->features & disable_features & (1 << i))
1404                         dev_notice(&dev->dev, "%s disabled by user\n",
1405                                    i801_feature_names[i]);
1406         }
1407         priv->features &= ~disable_features;
1408
1409         err = pcim_enable_device(dev);
1410         if (err) {
1411                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1412                         err);
1413                 return err;
1414         }
1415         pcim_pin_device(dev);
1416
1417         /* Determine the address of the SMBus area */
1418         priv->smba = pci_resource_start(dev, SMBBAR);
1419         if (!priv->smba) {
1420                 dev_err(&dev->dev,
1421                         "SMBus base address uninitialized, upgrade BIOS\n");
1422                 return -ENODEV;
1423         }
1424
1425         if (i801_acpi_probe(priv))
1426                 return -ENODEV;
1427
1428         err = pcim_iomap_regions(dev, 1 << SMBBAR,
1429                                  dev_driver_string(&dev->dev));
1430         if (err) {
1431                 dev_err(&dev->dev,
1432                         "Failed to request SMBus region 0x%lx-0x%Lx\n",
1433                         priv->smba,
1434                         (unsigned long long)pci_resource_end(dev, SMBBAR));
1435                 i801_acpi_remove(priv);
1436                 return err;
1437         }
1438
1439         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1440         priv->original_hstcfg = temp;
1441         temp &= ~SMBHSTCFG_I2C_EN;      /* SMBus timing */
1442         if (!(temp & SMBHSTCFG_HST_EN)) {
1443                 dev_info(&dev->dev, "Enabling SMBus device\n");
1444                 temp |= SMBHSTCFG_HST_EN;
1445         }
1446         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
1447
1448         if (temp & SMBHSTCFG_SMB_SMI_EN) {
1449                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1450                 /* Disable SMBus interrupt feature if SMBus using SMI# */
1451                 priv->features &= ~FEATURE_IRQ;
1452         }
1453
1454         /* Clear special mode bits */
1455         if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1456                 outb_p(inb_p(SMBAUXCTL(priv)) &
1457                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1458
1459         /* Default timeout in interrupt mode: 200 ms */
1460         priv->adapter.timeout = HZ / 5;
1461
1462         if (priv->features & FEATURE_IRQ) {
1463                 u16 pcictl, pcists;
1464
1465                 /* Complain if an interrupt is already pending */
1466                 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
1467                 if (pcists & SMBPCISTS_INTS)
1468                         dev_warn(&dev->dev, "An interrupt is pending!\n");
1469
1470                 /* Check if interrupts have been disabled */
1471                 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl);
1472                 if (pcictl & SMBPCICTL_INTDIS) {
1473                         dev_info(&dev->dev, "Interrupts are disabled\n");
1474                         priv->features &= ~FEATURE_IRQ;
1475                 }
1476         }
1477
1478         if (priv->features & FEATURE_IRQ) {
1479                 init_waitqueue_head(&priv->waitq);
1480
1481                 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1482                                        IRQF_SHARED,
1483                                        dev_driver_string(&dev->dev), priv);
1484                 if (err) {
1485                         dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1486                                 dev->irq, err);
1487                         priv->features &= ~FEATURE_IRQ;
1488                 }
1489         }
1490         dev_info(&dev->dev, "SMBus using %s\n",
1491                  priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1492
1493         i801_add_tco(priv);
1494
1495         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1496                 "SMBus I801 adapter at %04lx", priv->smba);
1497         err = i2c_add_adapter(&priv->adapter);
1498         if (err) {
1499                 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
1500                 i801_acpi_remove(priv);
1501                 return err;
1502         }
1503
1504         i801_probe_optional_slaves(priv);
1505         /* We ignore errors - multiplexing is optional */
1506         i801_add_mux(priv);
1507
1508         pci_set_drvdata(dev, priv);
1509
1510         return 0;
1511 }
1512
1513 static void i801_remove(struct pci_dev *dev)
1514 {
1515         struct i801_priv *priv = pci_get_drvdata(dev);
1516
1517         i801_del_mux(priv);
1518         i2c_del_adapter(&priv->adapter);
1519         i801_acpi_remove(priv);
1520         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1521
1522         platform_device_unregister(priv->tco_pdev);
1523
1524         /*
1525          * do not call pci_disable_device(dev) since it can cause hard hangs on
1526          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1527          */
1528 }
1529
1530 #ifdef CONFIG_PM
1531 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
1532 {
1533         struct i801_priv *priv = pci_get_drvdata(dev);
1534
1535         pci_save_state(dev);
1536         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1537         pci_set_power_state(dev, pci_choose_state(dev, mesg));
1538         return 0;
1539 }
1540
1541 static int i801_resume(struct pci_dev *dev)
1542 {
1543         pci_set_power_state(dev, PCI_D0);
1544         pci_restore_state(dev);
1545         return 0;
1546 }
1547 #else
1548 #define i801_suspend NULL
1549 #define i801_resume NULL
1550 #endif
1551
1552 static struct pci_driver i801_driver = {
1553         .name           = "i801_smbus",
1554         .id_table       = i801_ids,
1555         .probe          = i801_probe,
1556         .remove         = i801_remove,
1557         .suspend        = i801_suspend,
1558         .resume         = i801_resume,
1559 };
1560
1561 static int __init i2c_i801_init(void)
1562 {
1563         if (dmi_name_in_vendors("FUJITSU"))
1564                 input_apanel_init();
1565         return pci_register_driver(&i801_driver);
1566 }
1567
1568 static void __exit i2c_i801_exit(void)
1569 {
1570         pci_unregister_driver(&i801_driver);
1571 }
1572
1573 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>");
1574 MODULE_DESCRIPTION("I801 SMBus driver");
1575 MODULE_LICENSE("GPL");
1576
1577 module_init(i2c_i801_init);
1578 module_exit(i2c_i801_exit);