drivers/i2c/busses/i2c-i801.c

   1 /*
   2     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   3     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   4     <mdsxyz123@yahoo.com>
   5     Copyright (C) 2007 - 2014  Jean Delvare <jdelvare@suse.de>
   6     Copyright (C) 2010         Intel Corporation,
   7                                David Woodhouse <dwmw2@infradead.org>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18 */
  19
  20 /*
  21  * Supports the following Intel I/O Controller Hubs (ICH):
  22  *
  23  *                                      I/O                     Block   I2C
  24  *                                      region  SMBus   Block   proc.   block
  25  * Chip name                    PCI ID  size    PEC     buffer  call    read
  26  * ---------------------------------------------------------------------------
  27  * 82801AA (ICH)                0x2413  16      no      no      no      no
  28  * 82801AB (ICH0)               0x2423  16      no      no      no      no
  29  * 82801BA (ICH2)               0x2443  16      no      no      no      no
  30  * 82801CA (ICH3)               0x2483  32      soft    no      no      no
  31  * 82801DB (ICH4)               0x24c3  32      hard    yes     no      no
  32  * 82801E (ICH5)                0x24d3  32      hard    yes     yes     yes
  33  * 6300ESB                      0x25a4  32      hard    yes     yes     yes
  34  * 82801F (ICH6)                0x266a  32      hard    yes     yes     yes
  35  * 6310ESB/6320ESB              0x269b  32      hard    yes     yes     yes
  36  * 82801G (ICH7)                0x27da  32      hard    yes     yes     yes
  37  * 82801H (ICH8)                0x283e  32      hard    yes     yes     yes
  38  * 82801I (ICH9)                0x2930  32      hard    yes     yes     yes
  39  * EP80579 (Tolapai)            0x5032  32      hard    yes     yes     yes
  40  * ICH10                        0x3a30  32      hard    yes     yes     yes
  41  * ICH10                        0x3a60  32      hard    yes     yes     yes
  42  * 5/3400 Series (PCH)          0x3b30  32      hard    yes     yes     yes
  43  * 6 Series (PCH)               0x1c22  32      hard    yes     yes     yes
  44  * Patsburg (PCH)               0x1d22  32      hard    yes     yes     yes
  45  * Patsburg (PCH) IDF           0x1d70  32      hard    yes     yes     yes
  46  * Patsburg (PCH) IDF           0x1d71  32      hard    yes     yes     yes
  47  * Patsburg (PCH) IDF           0x1d72  32      hard    yes     yes     yes
  48  * DH89xxCC (PCH)               0x2330  32      hard    yes     yes     yes
  49  * Panther Point (PCH)          0x1e22  32      hard    yes     yes     yes
  50  * Lynx Point (PCH)             0x8c22  32      hard    yes     yes     yes
  51  * Lynx Point-LP (PCH)          0x9c22  32      hard    yes     yes     yes
  52  * Avoton (SOC)                 0x1f3c  32      hard    yes     yes     yes
  53  * Wellsburg (PCH)              0x8d22  32      hard    yes     yes     yes
  54  * Wellsburg (PCH) MS           0x8d7d  32      hard    yes     yes     yes
  55  * Wellsburg (PCH) MS           0x8d7e  32      hard    yes     yes     yes
  56  * Wellsburg (PCH) MS           0x8d7f  32      hard    yes     yes     yes
  57  * Coleto Creek (PCH)           0x23b0  32      hard    yes     yes     yes
  58  * Wildcat Point (PCH)          0x8ca2  32      hard    yes     yes     yes
  59  * Wildcat Point-LP (PCH)       0x9ca2  32      hard    yes     yes     yes
  60  * BayTrail (SOC)               0x0f12  32      hard    yes     yes     yes
  61  * Braswell (SOC)               0x2292  32      hard    yes     yes     yes
  62  * Sunrise Point-H (PCH)        0xa123  32      hard    yes     yes     yes
  63  * Sunrise Point-LP (PCH)       0x9d23  32      hard    yes     yes     yes
  64  * DNV (SOC)                    0x19df  32      hard    yes     yes     yes
  65  * Broxton (SOC)                0x5ad4  32      hard    yes     yes     yes
  66  * Lewisburg (PCH)              0xa1a3  32      hard    yes     yes     yes
  67  * Lewisburg Supersku (PCH)     0xa223  32      hard    yes     yes     yes
  68  * Kaby Lake PCH-H (PCH)        0xa2a3  32      hard    yes     yes     yes
  69  * Gemini Lake (SOC)            0x31d4  32      hard    yes     yes     yes
  70  * Cannon Lake-H (PCH)          0xa323  32      hard    yes     yes     yes
  71  * Cannon Lake-LP (PCH)         0x9da3  32      hard    yes     yes     yes
  72  * Cedar Fork (PCH)             0x18df  32      hard    yes     yes     yes
  73  * Ice Lake-LP (PCH)            0x34a3  32      hard    yes     yes     yes
  74  * Comet Lake (PCH)             0x02a3  32      hard    yes     yes     yes
  75  *
  76  * Features supported by this driver:
  77  * Software PEC                         no
  78  * Hardware PEC                         yes
  79  * Block buffer                         yes
  80  * Block process call transaction       no
  81  * I2C block read transaction           yes (doesn't use the block buffer)
  82  * Slave mode                           no
  83  * SMBus Host Notify                    yes
  84  * Interrupt processing                 yes
  85  *
  86  * See the file Documentation/i2c/busses/i2c-i801 for details.
  87  */
  88
  89 #include <linux/interrupt.h>
  90 #include <linux/module.h>
  91 #include <linux/pci.h>
  92 #include <linux/kernel.h>
  93 #include <linux/stddef.h>
  94 #include <linux/delay.h>
  95 #include <linux/ioport.h>
  96 #include <linux/init.h>
  97 #include <linux/i2c.h>
  98 #include <linux/i2c-smbus.h>
  99 #include <linux/acpi.h>
 100 #include <linux/io.h>
 101 #include <linux/dmi.h>
 102 #include <linux/slab.h>
 103 #include <linux/wait.h>
 104 #include <linux/err.h>
 105 #include <linux/platform_device.h>
 106 #include <linux/platform_data/itco_wdt.h>
 107 #include <linux/pm_runtime.h>
 108
 109 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
 110 #include <linux/gpio.h>
 111 #include <linux/platform_data/i2c-mux-gpio.h>
 112 #endif
 113
 114 /* I801 SMBus address offsets */
 115 #define SMBHSTSTS(p)    (0 + (p)->smba)
 116 #define SMBHSTCNT(p)    (2 + (p)->smba)
 117 #define SMBHSTCMD(p)    (3 + (p)->smba)
 118 #define SMBHSTADD(p)    (4 + (p)->smba)
 119 #define SMBHSTDAT0(p)   (5 + (p)->smba)
 120 #define SMBHSTDAT1(p)   (6 + (p)->smba)
 121 #define SMBBLKDAT(p)    (7 + (p)->smba)
 122 #define SMBPEC(p)       (8 + (p)->smba)         /* ICH3 and later */
 123 #define SMBAUXSTS(p)    (12 + (p)->smba)        /* ICH4 and later */
 124 #define SMBAUXCTL(p)    (13 + (p)->smba)        /* ICH4 and later */
 125 #define SMBSLVSTS(p)    (16 + (p)->smba)        /* ICH3 and later */
 126 #define SMBSLVCMD(p)    (17 + (p)->smba)        /* ICH3 and later */
 127 #define SMBNTFDADD(p)   (20 + (p)->smba)        /* ICH3 and later */
 128
 129 /* PCI Address Constants */
 130 #define SMBBAR          4
 131 #define SMBPCICTL       0x004
 132 #define SMBPCISTS       0x006
 133 #define SMBHSTCFG       0x040
 134 #define TCOBASE         0x050
 135 #define TCOCTL          0x054
 136
 137 #define ACPIBASE                0x040
 138 #define ACPIBASE_SMI_OFF        0x030
 139 #define ACPICTRL                0x044
 140 #define ACPICTRL_EN             0x080
 141
 142 #define SBREG_BAR               0x10
 143 #define SBREG_SMBCTRL           0xc6000c
 144 #define SBREG_SMBCTRL_DNV       0xcf000c
 145
 146 /* Host status bits for SMBPCISTS */
 147 #define SMBPCISTS_INTS          BIT(3)
 148
 149 /* Control bits for SMBPCICTL */
 150 #define SMBPCICTL_INTDIS        BIT(10)
 151
 152 /* Host configuration bits for SMBHSTCFG */
 153 #define SMBHSTCFG_HST_EN        BIT(0)
 154 #define SMBHSTCFG_SMB_SMI_EN    BIT(1)
 155 #define SMBHSTCFG_I2C_EN        BIT(2)
 156 #define SMBHSTCFG_SPD_WD        BIT(4)
 157
 158 /* TCO configuration bits for TCOCTL */
 159 #define TCOCTL_EN               BIT(8)
 160
 161 /* Auxiliary status register bits, ICH4+ only */
 162 #define SMBAUXSTS_CRCE          BIT(0)
 163 #define SMBAUXSTS_STCO          BIT(1)
 164
 165 /* Auxiliary control register bits, ICH4+ only */
 166 #define SMBAUXCTL_CRC           BIT(0)
 167 #define SMBAUXCTL_E32B          BIT(1)
 168
 169 /* Other settings */
 170 #define MAX_RETRIES             400
 171
 172 /* I801 command constants */
 173 #define I801_QUICK              0x00
 174 #define I801_BYTE               0x04
 175 #define I801_BYTE_DATA          0x08
 176 #define I801_WORD_DATA          0x0C
 177 #define I801_PROC_CALL          0x10    /* unimplemented */
 178 #define I801_BLOCK_DATA         0x14
 179 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 180
 181 /* I801 Host Control register bits */
 182 #define SMBHSTCNT_INTREN        BIT(0)
 183 #define SMBHSTCNT_KILL          BIT(1)
 184 #define SMBHSTCNT_LAST_BYTE     BIT(5)
 185 #define SMBHSTCNT_START         BIT(6)
 186 #define SMBHSTCNT_PEC_EN        BIT(7)  /* ICH3 and later */
 187
 188 /* I801 Hosts Status register bits */
 189 #define SMBHSTSTS_BYTE_DONE     BIT(7)
 190 #define SMBHSTSTS_INUSE_STS     BIT(6)
 191 #define SMBHSTSTS_SMBALERT_STS  BIT(5)
 192 #define SMBHSTSTS_FAILED        BIT(4)
 193 #define SMBHSTSTS_BUS_ERR       BIT(3)
 194 #define SMBHSTSTS_DEV_ERR       BIT(2)
 195 #define SMBHSTSTS_INTR          BIT(1)
 196 #define SMBHSTSTS_HOST_BUSY     BIT(0)
 197
 198 /* Host Notify Status register bits */
 199 #define SMBSLVSTS_HST_NTFY_STS  BIT(0)
 200
 201 /* Host Notify Command register bits */
 202 #define SMBSLVCMD_HST_NTFY_INTREN       BIT(0)
 203
 204 #define STATUS_ERROR_FLAGS      (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
 205                                  SMBHSTSTS_DEV_ERR)
 206
 207 #define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
 208                                  STATUS_ERROR_FLAGS)
 209
 210 /* Older devices have their ID defined in <linux/pci_ids.h> */
 211 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS              0x0f12
 212 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS                   0x18df
 213 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS                   0x19df
 214 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS           0x1c22
 215 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS              0x1d22
 216 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
 217 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0         0x1d70
 218 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1         0x1d71
 219 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2         0x1d72
 220 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS          0x1e22
 221 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS                0x1f3c
 222 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS              0x2292
 223 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS              0x2330
 224 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS           0x23b0
 225 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS            0x31d4
 226 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS            0x34a3
 227 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS         0x3b30
 228 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS               0x5ad4
 229 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS             0x8c22
 230 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS          0x8ca2
 231 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS             0x8d22
 232 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0         0x8d7d
 233 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1         0x8d7e
 234 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2         0x8d7f
 235 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS          0x9c22
 236 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS       0x9ca2
 237 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS       0x9d23
 238 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS         0x9da3
 239 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS        0xa123
 240 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS             0xa1a3
 241 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS        0xa223
 242 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS        0xa2a3
 243 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS          0xa323
 244 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS             0x02a3
 245
 246 struct i801_mux_config {
 247         char *gpio_chip;
 248         unsigned values[3];
 249         int n_values;
 250         unsigned classes[3];
 251         unsigned gpios[2];              /* Relative to gpio_chip->base */
 252         int n_gpios;
 253 };
 254
 255 struct i801_priv {
 256         struct i2c_adapter adapter;
 257         unsigned long smba;
 258         unsigned char original_hstcfg;
 259         unsigned char original_slvcmd;
 260         struct pci_dev *pci_dev;
 261         unsigned int features;
 262
 263         /* isr processing */
 264         wait_queue_head_t waitq;
 265         u8 status;
 266
 267         /* Command state used by isr for byte-by-byte block transactions */
 268         u8 cmd;
 269         bool is_read;
 270         int count;
 271         int len;
 272         u8 *data;
 273
 274 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
 275         const struct i801_mux_config *mux_drvdata;
 276         struct platform_device *mux_pdev;
 277 #endif
 278         struct platform_device *tco_pdev;
 279
 280         /*
 281          * If set to true the host controller registers are reserved for
 282          * ACPI AML use. Protected by acpi_lock.
 283          */
 284         bool acpi_reserved;
 285         struct mutex acpi_lock;
 286 };
 287
 288 #define FEATURE_SMBUS_PEC       BIT(0)
 289 #define FEATURE_BLOCK_BUFFER    BIT(1)
 290 #define FEATURE_BLOCK_PROC      BIT(2)
 291 #define FEATURE_I2C_BLOCK_READ  BIT(3)
 292 #define FEATURE_IRQ             BIT(4)
 293 #define FEATURE_HOST_NOTIFY     BIT(5)
 294 /* Not really a feature, but it's convenient to handle it as such */
 295 #define FEATURE_IDF             BIT(15)
 296 #define FEATURE_TCO             BIT(16)
 297
 298 static const char *i801_feature_names[] = {
 299         "SMBus PEC",
 300         "Block buffer",
 301         "Block process call",
 302         "I2C block read",
 303         "Interrupt",
 304         "SMBus Host Notify",
 305 };
 306
 307 static unsigned int disable_features;
 308 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
 309 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
 310         "\t\t  0x01  disable SMBus PEC\n"
 311         "\t\t  0x02  disable the block buffer\n"
 312         "\t\t  0x08  disable the I2C block read functionality\n"
 313         "\t\t  0x10  don't use interrupts\n"
 314         "\t\t  0x20  disable SMBus Host Notify ");
 315
 316 /* Make sure the SMBus host is ready to start transmitting.
 317    Return 0 if it is, -EBUSY if it is not. */
 318 static int i801_check_pre(struct i801_priv *priv)
 319 {
 320         int status;
 321
 322         status = inb_p(SMBHSTSTS(priv));
 323         if (status & SMBHSTSTS_HOST_BUSY) {
 324                 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
 325                 return -EBUSY;
 326         }
 327
 328         status &= STATUS_FLAGS;
 329         if (status) {
 330                 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
 331                         status);
 332                 outb_p(status, SMBHSTSTS(priv));
 333                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 334                 if (status) {
 335                         dev_err(&priv->pci_dev->dev,
 336                                 "Failed clearing status flags (%02x)\n",
 337                                 status);
 338                         return -EBUSY;
 339                 }
 340         }
 341
 342         /*
 343          * Clear CRC status if needed.
 344          * During normal operation, i801_check_post() takes care
 345          * of it after every operation.  We do it here only in case
 346          * the hardware was already in this state when the driver
 347          * started.
 348          */
 349         if (priv->features & FEATURE_SMBUS_PEC) {
 350                 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
 351                 if (status) {
 352                         dev_dbg(&priv->pci_dev->dev,
 353                                 "Clearing aux status flags (%02x)\n", status);
 354                         outb_p(status, SMBAUXSTS(priv));
 355                         status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
 356                         if (status) {
 357                                 dev_err(&priv->pci_dev->dev,
 358                                         "Failed clearing aux status flags (%02x)\n",
 359                                         status);
 360                                 return -EBUSY;
 361                         }
 362                 }
 363         }
 364
 365         return 0;
 366 }
 367
 368 /*
 369  * Convert the status register to an error code, and clear it.
 370  * Note that status only contains the bits we want to clear, not the
 371  * actual register value.
 372  */
 373 static int i801_check_post(struct i801_priv *priv, int status)
 374 {
 375         int result = 0;
 376
 377         /*
 378          * If the SMBus is still busy, we give up
 379          * Note: This timeout condition only happens when using polling
 380          * transactions.  For interrupt operation, NAK/timeout is indicated by
 381          * DEV_ERR.
 382          */
 383         if (unlikely(status < 0)) {
 384                 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
 385                 /* try to stop the current command */
 386                 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
 387                 outb_p(SMBHSTCNT_KILL, SMBHSTCNT(priv));
 388                 usleep_range(1000, 2000);
 389                 outb_p(0, SMBHSTCNT(priv));
 390
 391                 /* Check if it worked */
 392                 status = inb_p(SMBHSTSTS(priv));
 393                 if ((status & SMBHSTSTS_HOST_BUSY) ||
 394                     !(status & SMBHSTSTS_FAILED))
 395                         dev_err(&priv->pci_dev->dev,
 396                                 "Failed terminating the transaction\n");
 397                 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
 398                 return -ETIMEDOUT;
 399         }
 400
 401         if (status & SMBHSTSTS_FAILED) {
 402                 result = -EIO;
 403                 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
 404         }
 405         if (status & SMBHSTSTS_DEV_ERR) {
 406                 /*
 407                  * This may be a PEC error, check and clear it.
 408                  *
 409                  * AUXSTS is handled differently from HSTSTS.
 410                  * For HSTSTS, i801_isr() or i801_wait_intr()
 411                  * has already cleared the error bits in hardware,
 412                  * and we are passed a copy of the original value
 413                  * in "status".
 414                  * For AUXSTS, the hardware register is left
 415                  * for us to handle here.
 416                  * This is asymmetric, slightly iffy, but safe,
 417                  * since all this code is serialized and the CRCE
 418                  * bit is harmless as long as it's cleared before
 419                  * the next operation.
 420                  */
 421                 if ((priv->features & FEATURE_SMBUS_PEC) &&
 422                     (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) {
 423                         outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv));
 424                         result = -EBADMSG;
 425                         dev_dbg(&priv->pci_dev->dev, "PEC error\n");
 426                 } else {
 427                         result = -ENXIO;
 428                         dev_dbg(&priv->pci_dev->dev, "No response\n");
 429                 }
 430         }
 431         if (status & SMBHSTSTS_BUS_ERR) {
 432                 result = -EAGAIN;
 433                 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
 434         }
 435
 436         /* Clear status flags except BYTE_DONE, to be cleared by caller */
 437         outb_p(status, SMBHSTSTS(priv));
 438
 439         return result;
 440 }
 441
 442 /* Wait for BUSY being cleared and either INTR or an error flag being set */
 443 static int i801_wait_intr(struct i801_priv *priv)
 444 {
 445         int timeout = 0;
 446         int status;
 447
 448         /* We will always wait for a fraction of a second! */
 449         do {
 450                 usleep_range(250, 500);
 451                 status = inb_p(SMBHSTSTS(priv));
 452         } while (((status & SMBHSTSTS_HOST_BUSY) ||
 453                   !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
 454                  (timeout++ < MAX_RETRIES));
 455
 456         if (timeout > MAX_RETRIES) {
 457                 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
 458                 return -ETIMEDOUT;
 459         }
 460         return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
 461 }
 462
 463 /* Wait for either BYTE_DONE or an error flag being set */
 464 static int i801_wait_byte_done(struct i801_priv *priv)
 465 {
 466         int timeout = 0;
 467         int status;
 468
 469         /* We will always wait for a fraction of a second! */
 470         do {
 471                 usleep_range(250, 500);
 472                 status = inb_p(SMBHSTSTS(priv));
 473         } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
 474                  (timeout++ < MAX_RETRIES));
 475
 476         if (timeout > MAX_RETRIES) {
 477                 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
 478                 return -ETIMEDOUT;
 479         }
 480         return status & STATUS_ERROR_FLAGS;
 481 }
 482
 483 static int i801_transaction(struct i801_priv *priv, int xact)
 484 {
 485         int status;
 486         int result;
 487         const struct i2c_adapter *adap = &priv->adapter;
 488
 489         result = i801_check_pre(priv);
 490         if (result < 0)
 491                 return result;
 492
 493         if (priv->features & FEATURE_IRQ) {
 494                 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
 495                        SMBHSTCNT(priv));
 496                 result = wait_event_timeout(priv->waitq,
 497                                             (status = priv->status),
 498                                             adap->timeout);
 499                 if (!result) {
 500                         status = -ETIMEDOUT;
 501                         dev_warn(&priv->pci_dev->dev,
 502                                  "Timeout waiting for interrupt!\n");
 503                 }
 504                 priv->status = 0;
 505                 return i801_check_post(priv, status);
 506         }
 507
 508         /* the current contents of SMBHSTCNT can be overwritten, since PEC,
 509          * SMBSCMD are passed in xact */
 510         outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
 511
 512         status = i801_wait_intr(priv);
 513         return i801_check_post(priv, status);
 514 }
 515
 516 static int i801_block_transaction_by_block(struct i801_priv *priv,
 517                                            union i2c_smbus_data *data,
 518                                            char read_write, int hwpec)
 519 {
 520         int i, len;
 521         int status;
 522
 523         inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
 524
 525         /* Use 32-byte buffer to process this transaction */
 526         if (read_write == I2C_SMBUS_WRITE) {
 527                 len = data->block[0];
 528                 outb_p(len, SMBHSTDAT0(priv));
 529                 for (i = 0; i < len; i++)
 530                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 531         }
 532
 533         status = i801_transaction(priv, I801_BLOCK_DATA |
 534                                   (hwpec ? SMBHSTCNT_PEC_EN : 0));
 535         if (status)
 536                 return status;
 537
 538         if (read_write == I2C_SMBUS_READ) {
 539                 len = inb_p(SMBHSTDAT0(priv));
 540                 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 541                         return -EPROTO;
 542
 543                 data->block[0] = len;
 544                 for (i = 0; i < len; i++)
 545                         data->block[i + 1] = inb_p(SMBBLKDAT(priv));
 546         }
 547         return 0;
 548 }
 549
 550 static void i801_isr_byte_done(struct i801_priv *priv)
 551 {
 552         if (priv->is_read) {
 553                 /* For SMBus block reads, length is received with first byte */
 554                 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
 555                     (priv->count == 0)) {
 556                         priv->len = inb_p(SMBHSTDAT0(priv));
 557                         if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
 558                                 dev_err(&priv->pci_dev->dev,
 559                                         "Illegal SMBus block read size %d\n",
 560                                         priv->len);
 561                                 /* FIXME: Recover */
 562                                 priv->len = I2C_SMBUS_BLOCK_MAX;
 563                         } else {
 564                                 dev_dbg(&priv->pci_dev->dev,
 565                                         "SMBus block read size is %d\n",
 566                                         priv->len);
 567                         }
 568                         priv->data[-1] = priv->len;
 569                 }
 570
 571                 /* Read next byte */
 572                 if (priv->count < priv->len)
 573                         priv->data[priv->count++] = inb(SMBBLKDAT(priv));
 574                 else
 575                         dev_dbg(&priv->pci_dev->dev,
 576                                 "Discarding extra byte on block read\n");
 577
 578                 /* Set LAST_BYTE for last byte of read transaction */
 579                 if (priv->count == priv->len - 1)
 580                         outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
 581                                SMBHSTCNT(priv));
 582         } else if (priv->count < priv->len - 1) {
 583                 /* Write next byte, except for IRQ after last byte */
 584                 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
 585         }
 586
 587         /* Clear BYTE_DONE to continue with next byte */
 588         outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 589 }
 590
 591 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
 592 {
 593         unsigned short addr;
 594
 595         addr = inb_p(SMBNTFDADD(priv)) >> 1;
 596
 597         /*
 598          * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba)
 599          * always returns 0. Our current implementation doesn't provide
 600          * data, so we just ignore it.
 601          */
 602         i2c_handle_smbus_host_notify(&priv->adapter, addr);
 603
 604         /* clear Host Notify bit and return */
 605         outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
 606         return IRQ_HANDLED;
 607 }
 608
 609 /*
 610  * There are three kinds of interrupts:
 611  *
 612  * 1) i801 signals transaction completion with one of these interrupts:
 613  *      INTR - Success
 614  *      DEV_ERR - Invalid command, NAK or communication timeout
 615  *      BUS_ERR - SMI# transaction collision
 616  *      FAILED - transaction was canceled due to a KILL request
 617  *    When any of these occur, update ->status and wake up the waitq.
 618  *    ->status must be cleared before kicking off the next transaction.
 619  *
 620  * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
 621  *    occurs for each byte of a byte-by-byte to prepare the next byte.
 622  *
 623  * 3) Host Notify interrupts
 624  */
 625 static irqreturn_t i801_isr(int irq, void *dev_id)
 626 {
 627         struct i801_priv *priv = dev_id;
 628         u16 pcists;
 629         u8 status;
 630
 631         /* Confirm this is our interrupt */
 632         pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
 633         if (!(pcists & SMBPCISTS_INTS))
 634                 return IRQ_NONE;
 635
 636         if (priv->features & FEATURE_HOST_NOTIFY) {
 637                 status = inb_p(SMBSLVSTS(priv));
 638                 if (status & SMBSLVSTS_HST_NTFY_STS)
 639                         return i801_host_notify_isr(priv);
 640         }
 641
 642         status = inb_p(SMBHSTSTS(priv));
 643         if (status & SMBHSTSTS_BYTE_DONE)
 644                 i801_isr_byte_done(priv);
 645
 646         /*
 647          * Clear irq sources and report transaction result.
 648          * ->status must be cleared before the next transaction is started.
 649          */
 650         status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
 651         if (status) {
 652                 outb_p(status, SMBHSTSTS(priv));
 653                 priv->status = status;
 654                 wake_up(&priv->waitq);
 655         }
 656
 657         return IRQ_HANDLED;
 658 }
 659
 660 /*
 661  * For "byte-by-byte" block transactions:
 662  *   I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
 663  *   I2C read uses cmd=I801_I2C_BLOCK_DATA
 664  */
 665 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
 666                                                union i2c_smbus_data *data,
 667                                                char read_write, int command,
 668                                                int hwpec)
 669 {
 670         int i, len;
 671         int smbcmd;
 672         int status;
 673         int result;
 674         const struct i2c_adapter *adap = &priv->adapter;
 675
 676         result = i801_check_pre(priv);
 677         if (result < 0)
 678                 return result;
 679
 680         len = data->block[0];
 681
 682         if (read_write == I2C_SMBUS_WRITE) {
 683                 outb_p(len, SMBHSTDAT0(priv));
 684                 outb_p(data->block[1], SMBBLKDAT(priv));
 685         }
 686
 687         if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
 688             read_write == I2C_SMBUS_READ)
 689                 smbcmd = I801_I2C_BLOCK_DATA;
 690         else
 691                 smbcmd = I801_BLOCK_DATA;
 692
 693         if (priv->features & FEATURE_IRQ) {
 694                 priv->is_read = (read_write == I2C_SMBUS_READ);
 695                 if (len == 1 && priv->is_read)
 696                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 697                 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
 698                 priv->len = len;
 699                 priv->count = 0;
 700                 priv->data = &data->block[1];
 701
 702                 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
 703                 result = wait_event_timeout(priv->waitq,
 704                                             (status = priv->status),
 705                                             adap->timeout);
 706                 if (!result) {
 707                         status = -ETIMEDOUT;
 708                         dev_warn(&priv->pci_dev->dev,
 709                                  "Timeout waiting for interrupt!\n");
 710                 }
 711                 priv->status = 0;
 712                 return i801_check_post(priv, status);
 713         }
 714
 715         for (i = 1; i <= len; i++) {
 716                 if (i == len && read_write == I2C_SMBUS_READ)
 717                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 718                 outb_p(smbcmd, SMBHSTCNT(priv));
 719
 720                 if (i == 1)
 721                         outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
 722                                SMBHSTCNT(priv));
 723
 724                 status = i801_wait_byte_done(priv);
 725                 if (status)
 726                         goto exit;
 727
 728                 if (i == 1 && read_write == I2C_SMBUS_READ
 729                  && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 730                         len = inb_p(SMBHSTDAT0(priv));
 731                         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 732                                 dev_err(&priv->pci_dev->dev,
 733                                         "Illegal SMBus block read size %d\n",
 734                                         len);
 735                                 /* Recover */
 736                                 while (inb_p(SMBHSTSTS(priv)) &
 737                                        SMBHSTSTS_HOST_BUSY)
 738                                         outb_p(SMBHSTSTS_BYTE_DONE,
 739                                                SMBHSTSTS(priv));
 740                                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 741                                 return -EPROTO;
 742                         }
 743                         data->block[0] = len;
 744                 }
 745
 746                 /* Retrieve/store value in SMBBLKDAT */
 747                 if (read_write == I2C_SMBUS_READ)
 748                         data->block[i] = inb_p(SMBBLKDAT(priv));
 749                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 750                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 751
 752                 /* signals SMBBLKDAT ready */
 753                 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 754         }
 755
 756         status = i801_wait_intr(priv);
 757 exit:
 758         return i801_check_post(priv, status);
 759 }
 760
 761 static int i801_set_block_buffer_mode(struct i801_priv *priv)
 762 {
 763         outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
 764         if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
 765                 return -EIO;
 766         return 0;
 767 }
 768
 769 /* Block transaction function */
 770 static int i801_block_transaction(struct i801_priv *priv,
 771                                   union i2c_smbus_data *data, char read_write,
 772                                   int command, int hwpec)
 773 {
 774         int result = 0;
 775         unsigned char hostc;
 776
 777         if (read_write == I2C_SMBUS_READ && command == I2C_SMBUS_BLOCK_DATA)
 778                 data->block[0] = I2C_SMBUS_BLOCK_MAX;
 779         else if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
 780                 return -EPROTO;
 781
 782         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 783                 if (read_write == I2C_SMBUS_WRITE) {
 784                         /* set I2C_EN bit in configuration register */
 785                         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
 786                         pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
 787                                               hostc | SMBHSTCFG_I2C_EN);
 788                 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
 789                         dev_err(&priv->pci_dev->dev,
 790                                 "I2C block read is unsupported!\n");
 791                         return -EOPNOTSUPP;
 792                 }
 793         }
 794
 795         /* Experience has shown that the block buffer can only be used for
 796            SMBus (not I2C) block transactions, even though the datasheet
 797            doesn't mention this limitation. */
 798         if ((priv->features & FEATURE_BLOCK_BUFFER)
 799          && command != I2C_SMBUS_I2C_BLOCK_DATA
 800          && i801_set_block_buffer_mode(priv) == 0)
 801                 result = i801_block_transaction_by_block(priv, data,
 802                                                          read_write, hwpec);
 803         else
 804                 result = i801_block_transaction_byte_by_byte(priv, data,
 805                                                              read_write,
 806                                                              command, hwpec);
 807
 808         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 809          && read_write == I2C_SMBUS_WRITE) {
 810                 /* restore saved configuration register value */
 811                 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
 812         }
 813         return result;
 814 }
 815
 816 /* Return negative errno on error. */
 817 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
 818                        unsigned short flags, char read_write, u8 command,
 819                        int size, union i2c_smbus_data *data)
 820 {
 821         int hwpec;
 822         int block = 0;
 823         int ret = 0, xact = 0;
 824         struct i801_priv *priv = i2c_get_adapdata(adap);
 825
 826         mutex_lock(&priv->acpi_lock);
 827         if (priv->acpi_reserved) {
 828                 mutex_unlock(&priv->acpi_lock);
 829                 return -EBUSY;
 830         }
 831
 832         pm_runtime_get_sync(&priv->pci_dev->dev);
 833
 834         hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 835                 && size != I2C_SMBUS_QUICK
 836                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
 837
 838         switch (size) {
 839         case I2C_SMBUS_QUICK:
 840                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 841                        SMBHSTADD(priv));
 842                 xact = I801_QUICK;
 843                 break;
 844         case I2C_SMBUS_BYTE:
 845                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 846                        SMBHSTADD(priv));
 847                 if (read_write == I2C_SMBUS_WRITE)
 848                         outb_p(command, SMBHSTCMD(priv));
 849                 xact = I801_BYTE;
 850                 break;
 851         case I2C_SMBUS_BYTE_DATA:
 852                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 853                        SMBHSTADD(priv));
 854                 outb_p(command, SMBHSTCMD(priv));
 855                 if (read_write == I2C_SMBUS_WRITE)
 856                         outb_p(data->byte, SMBHSTDAT0(priv));
 857                 xact = I801_BYTE_DATA;
 858                 break;
 859         case I2C_SMBUS_WORD_DATA:
 860                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 861                        SMBHSTADD(priv));
 862                 outb_p(command, SMBHSTCMD(priv));
 863                 if (read_write == I2C_SMBUS_WRITE) {
 864                         outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 865                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 866                 }
 867                 xact = I801_WORD_DATA;
 868                 break;
 869         case I2C_SMBUS_BLOCK_DATA:
 870                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 871                        SMBHSTADD(priv));
 872                 outb_p(command, SMBHSTCMD(priv));
 873                 block = 1;
 874                 break;
 875         case I2C_SMBUS_I2C_BLOCK_DATA:
 876                 /*
 877                  * NB: page 240 of ICH5 datasheet shows that the R/#W
 878                  * bit should be cleared here, even when reading.
 879                  * However if SPD Write Disable is set (Lynx Point and later),
 880                  * the read will fail if we don't set the R/#W bit.
 881                  */
 882                 outb_p(((addr & 0x7f) << 1) |
 883                        ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ?
 884                         (read_write & 0x01) : 0),
 885                        SMBHSTADD(priv));
 886                 if (read_write == I2C_SMBUS_READ) {
 887                         /* NB: page 240 of ICH5 datasheet also shows
 888                          * that DATA1 is the cmd field when reading */
 889                         outb_p(command, SMBHSTDAT1(priv));
 890                 } else
 891                         outb_p(command, SMBHSTCMD(priv));
 892                 block = 1;
 893                 break;
 894         default:
 895                 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
 896                         size);
 897                 ret = -EOPNOTSUPP;
 898                 goto out;
 899         }
 900
 901         if (hwpec)      /* enable/disable hardware PEC */
 902                 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
 903         else
 904                 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
 905                        SMBAUXCTL(priv));
 906
 907         if (block)
 908                 ret = i801_block_transaction(priv, data, read_write, size,
 909                                              hwpec);
 910         else
 911                 ret = i801_transaction(priv, xact);
 912
 913         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 914            time, so we forcibly disable it after every transaction. Turn off
 915            E32B for the same reason. */
 916         if (hwpec || block)
 917                 outb_p(inb_p(SMBAUXCTL(priv)) &
 918                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 919
 920         if (block)
 921                 goto out;
 922         if (ret)
 923                 goto out;
 924         if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 925                 goto out;
 926
 927         switch (xact & 0x7f) {
 928         case I801_BYTE: /* Result put in SMBHSTDAT0 */
 929         case I801_BYTE_DATA:
 930                 data->byte = inb_p(SMBHSTDAT0(priv));
 931                 break;
 932         case I801_WORD_DATA:
 933                 data->word = inb_p(SMBHSTDAT0(priv)) +
 934                              (inb_p(SMBHSTDAT1(priv)) << 8);
 935                 break;
 936         }
 937
 938 out:
 939         pm_runtime_mark_last_busy(&priv->pci_dev->dev);
 940         pm_runtime_put_autosuspend(&priv->pci_dev->dev);
 941         mutex_unlock(&priv->acpi_lock);
 942         return ret;
 943 }
 944
 945
 946 static u32 i801_func(struct i2c_adapter *adapter)
 947 {
 948         struct i801_priv *priv = i2c_get_adapdata(adapter);
 949
 950         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 951                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 952                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 953                ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 954                ((priv->features & FEATURE_I2C_BLOCK_READ) ?
 955                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
 956                ((priv->features & FEATURE_HOST_NOTIFY) ?
 957                 I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
 958 }
 959
 960 static void i801_enable_host_notify(struct i2c_adapter *adapter)
 961 {
 962         struct i801_priv *priv = i2c_get_adapdata(adapter);
 963
 964         if (!(priv->features & FEATURE_HOST_NOTIFY))
 965                 return;
 966
 967         if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd))
 968                 outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd,
 969                        SMBSLVCMD(priv));
 970
 971         /* clear Host Notify bit to allow a new notification */
 972         outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
 973 }
 974
 975 static void i801_disable_host_notify(struct i801_priv *priv)
 976 {
 977         if (!(priv->features & FEATURE_HOST_NOTIFY))
 978                 return;
 979
 980         outb_p(priv->original_slvcmd, SMBSLVCMD(priv));
 981 }
 982
 983 static const struct i2c_algorithm smbus_algorithm = {
 984         .smbus_xfer     = i801_access,
 985         .functionality  = i801_func,
 986 };
 987
 988 static const struct pci_device_id i801_ids[] = {
 989         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
 990         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
 991         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
 992         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
 993         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
 994         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
 995         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
 996         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
 997         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
 998         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
 999         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
1000         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
1001         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
1002         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
1003         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
1004         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
1005         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
1006         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
1007         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
1008         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
1009         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
1010         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
1011         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
1012         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
1013         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
1014         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
1015         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
1016         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
1017         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
1018         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
1019         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
1020         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS) },
1021         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
1022         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
1023         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
1024         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
1025         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
1026         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
1027         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMBUS) },
1028         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
1029         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) },
1030         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) },
1031         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) },
1032         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) },
1033         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS) },
1034         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS) },
1035         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS) },
1036         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS) },
1037         { 0, }
1038 };
1039
1040 MODULE_DEVICE_TABLE(pci, i801_ids);
1041
1042 #if defined CONFIG_X86 && defined CONFIG_DMI
1043 static unsigned char apanel_addr;
1044
1045 /* Scan the system ROM for the signature "FJKEYINF" */
1046 static __init const void __iomem *bios_signature(const void __iomem *bios)
1047 {
1048         ssize_t offset;
1049         const unsigned char signature[] = "FJKEYINF";
1050
1051         for (offset = 0; offset < 0x10000; offset += 0x10) {
1052                 if (check_signature(bios + offset, signature,
1053                                     sizeof(signature)-1))
1054                         return bios + offset;
1055         }
1056         return NULL;
1057 }
1058
1059 static void __init input_apanel_init(void)
1060 {
1061         void __iomem *bios;
1062         const void __iomem *p;
1063
1064         bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1065         p = bios_signature(bios);
1066         if (p) {
1067                 /* just use the first address */
1068                 apanel_addr = readb(p + 8 + 3) >> 1;
1069         }
1070         iounmap(bios);
1071 }
1072
1073 struct dmi_onboard_device_info {
1074         const char *name;
1075         u8 type;
1076         unsigned short i2c_addr;
1077         const char *i2c_type;
1078 };
1079
1080 static const struct dmi_onboard_device_info dmi_devices[] = {
1081         { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1082         { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1083         { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1084 };
1085
1086 static void dmi_check_onboard_device(u8 type, const char *name,
1087                                      struct i2c_adapter *adap)
1088 {
1089         int i;
1090         struct i2c_board_info info;
1091
1092         for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1093                 /* & ~0x80, ignore enabled/disabled bit */
1094                 if ((type & ~0x80) != dmi_devices[i].type)
1095                         continue;
1096                 if (strcasecmp(name, dmi_devices[i].name))
1097                         continue;
1098
1099                 memset(&info, 0, sizeof(struct i2c_board_info));
1100                 info.addr = dmi_devices[i].i2c_addr;
1101                 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
1102                 i2c_new_device(adap, &info);
1103                 break;
1104         }
1105 }
1106
1107 /* We use our own function to check for onboard devices instead of
1108    dmi_find_device() as some buggy BIOS's have the devices we are interested
1109    in marked as disabled */
1110 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
1111 {
1112         int i, count;
1113
1114         if (dm->type != 10)
1115                 return;
1116
1117         count = (dm->length - sizeof(struct dmi_header)) / 2;
1118         for (i = 0; i < count; i++) {
1119                 const u8 *d = (char *)(dm + 1) + (i * 2);
1120                 const char *name = ((char *) dm) + dm->length;
1121                 u8 type = d[0];
1122                 u8 s = d[1];
1123
1124                 if (!s)
1125                         continue;
1126                 s--;
1127                 while (s > 0 && name[0]) {
1128                         name += strlen(name) + 1;
1129                         s--;
1130                 }
1131                 if (name[0] == 0) /* Bogus string reference */
1132                         continue;
1133
1134                 dmi_check_onboard_device(type, name, adap);
1135         }
1136 }
1137
1138 /* Register optional slaves */
1139 static void i801_probe_optional_slaves(struct i801_priv *priv)
1140 {
1141         /* Only register slaves on main SMBus channel */
1142         if (priv->features & FEATURE_IDF)
1143                 return;
1144
1145         if (apanel_addr) {
1146                 struct i2c_board_info info;
1147
1148                 memset(&info, 0, sizeof(struct i2c_board_info));
1149                 info.addr = apanel_addr;
1150                 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
1151                 i2c_new_device(&priv->adapter, &info);
1152         }
1153
1154         if (dmi_name_in_vendors("FUJITSU"))
1155                 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1156 }
1157 #else
1158 static void __init input_apanel_init(void) {}
1159 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1160 #endif  /* CONFIG_X86 && CONFIG_DMI */
1161
1162 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
1163 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1164         .gpio_chip = "gpio_ich",
1165         .values = { 0x02, 0x03 },
1166         .n_values = 2,
1167         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1168         .gpios = { 52, 53 },
1169         .n_gpios = 2,
1170 };
1171
1172 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1173         .gpio_chip = "gpio_ich",
1174         .values = { 0x02, 0x03, 0x01 },
1175         .n_values = 3,
1176         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1177         .gpios = { 52, 53 },
1178         .n_gpios = 2,
1179 };
1180
1181 static const struct dmi_system_id mux_dmi_table[] = {
1182         {
1183                 .matches = {
1184                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1185                         DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1186                 },
1187                 .driver_data = &i801_mux_config_asus_z8_d12,
1188         },
1189         {
1190                 .matches = {
1191                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1192                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1193                 },
1194                 .driver_data = &i801_mux_config_asus_z8_d12,
1195         },
1196         {
1197                 .matches = {
1198                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1199                         DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1200                 },
1201                 .driver_data = &i801_mux_config_asus_z8_d12,
1202         },
1203         {
1204                 .matches = {
1205                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1206                         DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1207                 },
1208                 .driver_data = &i801_mux_config_asus_z8_d12,
1209         },
1210         {
1211                 .matches = {
1212                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1213                         DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1214                 },
1215                 .driver_data = &i801_mux_config_asus_z8_d12,
1216         },
1217         {
1218                 .matches = {
1219                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1220                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1221                 },
1222                 .driver_data = &i801_mux_config_asus_z8_d12,
1223         },
1224         {
1225                 .matches = {
1226                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1227                         DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1228                 },
1229                 .driver_data = &i801_mux_config_asus_z8_d18,
1230         },
1231         {
1232                 .matches = {
1233                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1234                         DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1235                 },
1236                 .driver_data = &i801_mux_config_asus_z8_d18,
1237         },
1238         {
1239                 .matches = {
1240                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1241                         DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1242                 },
1243                 .driver_data = &i801_mux_config_asus_z8_d12,
1244         },
1245         { }
1246 };
1247
1248 /* Setup multiplexing if needed */
1249 static int i801_add_mux(struct i801_priv *priv)
1250 {
1251         struct device *dev = &priv->adapter.dev;
1252         const struct i801_mux_config *mux_config;
1253         struct i2c_mux_gpio_platform_data gpio_data;
1254         int err;
1255
1256         if (!priv->mux_drvdata)
1257                 return 0;
1258         mux_config = priv->mux_drvdata;
1259
1260         /* Prepare the platform data */
1261         memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1262         gpio_data.parent = priv->adapter.nr;
1263         gpio_data.values = mux_config->values;
1264         gpio_data.n_values = mux_config->n_values;
1265         gpio_data.classes = mux_config->classes;
1266         gpio_data.gpio_chip = mux_config->gpio_chip;
1267         gpio_data.gpios = mux_config->gpios;
1268         gpio_data.n_gpios = mux_config->n_gpios;
1269         gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1270
1271         /* Register the mux device */
1272         priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1273                                 PLATFORM_DEVID_AUTO, &gpio_data,
1274                                 sizeof(struct i2c_mux_gpio_platform_data));
1275         if (IS_ERR(priv->mux_pdev)) {
1276                 err = PTR_ERR(priv->mux_pdev);
1277                 priv->mux_pdev = NULL;
1278                 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1279                 return err;
1280         }
1281
1282         return 0;
1283 }
1284
1285 static void i801_del_mux(struct i801_priv *priv)
1286 {
1287         if (priv->mux_pdev)
1288                 platform_device_unregister(priv->mux_pdev);
1289 }
1290
1291 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1292 {
1293         const struct dmi_system_id *id;
1294         const struct i801_mux_config *mux_config;
1295         unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1296         int i;
1297
1298         id = dmi_first_match(mux_dmi_table);
1299         if (id) {
1300                 /* Remove branch classes from trunk */
1301                 mux_config = id->driver_data;
1302                 for (i = 0; i < mux_config->n_values; i++)
1303                         class &= ~mux_config->classes[i];
1304
1305                 /* Remember for later */
1306                 priv->mux_drvdata = mux_config;
1307         }
1308
1309         return class;
1310 }
1311 #else
1312 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1313 static inline void i801_del_mux(struct i801_priv *priv) { }
1314
1315 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1316 {
1317         return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1318 }
1319 #endif
1320
1321 static const struct itco_wdt_platform_data tco_platform_data = {
1322         .name = "Intel PCH",
1323         .version = 4,
1324 };
1325
1326 static DEFINE_SPINLOCK(p2sb_spinlock);
1327
1328 static void i801_add_tco(struct i801_priv *priv)
1329 {
1330         struct pci_dev *pci_dev = priv->pci_dev;
1331         struct resource tco_res[3], *res;
1332         struct platform_device *pdev;
1333         unsigned int devfn;
1334         u32 tco_base, tco_ctl;
1335         u32 base_addr, ctrl_val;
1336         u64 base64_addr;
1337         u8 hidden;
1338
1339         if (!(priv->features & FEATURE_TCO))
1340                 return;
1341
1342         pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1343         pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1344         if (!(tco_ctl & TCOCTL_EN))
1345                 return;
1346
1347         memset(tco_res, 0, sizeof(tco_res));
1348
1349         res = &tco_res[ICH_RES_IO_TCO];
1350         res->start = tco_base & ~1;
1351         res->end = res->start + 32 - 1;
1352         res->flags = IORESOURCE_IO;
1353
1354         /*
1355          * Power Management registers.
1356          */
1357         devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2);
1358         pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, &base_addr);
1359
1360         res = &tco_res[ICH_RES_IO_SMI];
1361         res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF;
1362         res->end = res->start + 3;
1363         res->flags = IORESOURCE_IO;
1364
1365         /*
1366          * Enable the ACPI I/O space.
1367          */
1368         pci_bus_read_config_dword(pci_dev->bus, devfn, ACPICTRL, &ctrl_val);
1369         ctrl_val |= ACPICTRL_EN;
1370         pci_bus_write_config_dword(pci_dev->bus, devfn, ACPICTRL, ctrl_val);
1371
1372         /*
1373          * We must access the NO_REBOOT bit over the Primary to Sideband
1374          * bridge (P2SB). The BIOS prevents the P2SB device from being
1375          * enumerated by the PCI subsystem, so we need to unhide/hide it
1376          * to lookup the P2SB BAR.
1377          */
1378         spin_lock(&p2sb_spinlock);
1379
1380         devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
1381
1382         /* Unhide the P2SB device, if it is hidden */
1383         pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden);
1384         if (hidden)
1385                 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
1386
1387         pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
1388         base64_addr = base_addr & 0xfffffff0;
1389
1390         pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
1391         base64_addr |= (u64)base_addr << 32;
1392
1393         /* Hide the P2SB device, if it was hidden before */
1394         if (hidden)
1395                 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden);
1396         spin_unlock(&p2sb_spinlock);
1397
1398         res = &tco_res[ICH_RES_MEM_OFF];
1399         if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
1400                 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV;
1401         else
1402                 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1403
1404         res->end = res->start + 3;
1405         res->flags = IORESOURCE_MEM;
1406
1407         pdev = platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1408                                                  tco_res, 3, &tco_platform_data,
1409                                                  sizeof(tco_platform_data));
1410         if (IS_ERR(pdev)) {
1411                 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1412                 return;
1413         }
1414
1415         priv->tco_pdev = pdev;
1416 }
1417
1418 #ifdef CONFIG_ACPI
1419 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv,
1420                                       acpi_physical_address address)
1421 {
1422         return address >= priv->smba &&
1423                address <= pci_resource_end(priv->pci_dev, SMBBAR);
1424 }
1425
1426 static acpi_status
1427 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1428                      u64 *value, void *handler_context, void *region_context)
1429 {
1430         struct i801_priv *priv = handler_context;
1431         struct pci_dev *pdev = priv->pci_dev;
1432         acpi_status status;
1433
1434         /*
1435          * Once BIOS AML code touches the OpRegion we warn and inhibit any
1436          * further access from the driver itself. This device is now owned
1437          * by the system firmware.
1438          */
1439         mutex_lock(&priv->acpi_lock);
1440
1441         if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) {
1442                 priv->acpi_reserved = true;
1443
1444                 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1445                 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1446
1447                 /*
1448                  * BIOS is accessing the host controller so prevent it from
1449                  * suspending automatically from now on.
1450                  */
1451                 pm_runtime_get_sync(&pdev->dev);
1452         }
1453
1454         if ((function & ACPI_IO_MASK) == ACPI_READ)
1455                 status = acpi_os_read_port(address, (u32 *)value, bits);
1456         else
1457                 status = acpi_os_write_port(address, (u32)*value, bits);
1458
1459         mutex_unlock(&priv->acpi_lock);
1460
1461         return status;
1462 }
1463
1464 static int i801_acpi_probe(struct i801_priv *priv)
1465 {
1466         struct acpi_device *adev;
1467         acpi_status status;
1468
1469         adev = ACPI_COMPANION(&priv->pci_dev->dev);
1470         if (adev) {
1471                 status = acpi_install_address_space_handler(adev->handle,
1472                                 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler,
1473                                 NULL, priv);
1474                 if (ACPI_SUCCESS(status))
1475                         return 0;
1476         }
1477
1478         return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1479 }
1480
1481 static void i801_acpi_remove(struct i801_priv *priv)
1482 {
1483         struct acpi_device *adev;
1484
1485         adev = ACPI_COMPANION(&priv->pci_dev->dev);
1486         if (!adev)
1487                 return;
1488
1489         acpi_remove_address_space_handler(adev->handle,
1490                 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1491
1492         mutex_lock(&priv->acpi_lock);
1493         if (priv->acpi_reserved)
1494                 pm_runtime_put(&priv->pci_dev->dev);
1495         mutex_unlock(&priv->acpi_lock);
1496 }
1497 #else
1498 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
1499 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1500 #endif
1501
1502 static unsigned char i801_setup_hstcfg(struct i801_priv *priv)
1503 {
1504         unsigned char hstcfg = priv->original_hstcfg;
1505
1506         hstcfg &= ~SMBHSTCFG_I2C_EN;    /* SMBus timing */
1507         hstcfg |= SMBHSTCFG_HST_EN;
1508         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg);
1509         return hstcfg;
1510 }
1511
1512 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1513 {
1514         unsigned char temp;
1515         int err, i;
1516         struct i801_priv *priv;
1517
1518         priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1519         if (!priv)
1520                 return -ENOMEM;
1521
1522         i2c_set_adapdata(&priv->adapter, priv);
1523         priv->adapter.owner = THIS_MODULE;
1524         priv->adapter.class = i801_get_adapter_class(priv);
1525         priv->adapter.algo = &smbus_algorithm;
1526         priv->adapter.dev.parent = &dev->dev;
1527         ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1528         priv->adapter.retries = 3;
1529         mutex_init(&priv->acpi_lock);
1530
1531         priv->pci_dev = dev;
1532         switch (dev->device) {
1533         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS:
1534         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS:
1535         case PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS:
1536         case PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS:
1537         case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS:
1538         case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS:
1539         case PCI_DEVICE_ID_INTEL_CDF_SMBUS:
1540         case PCI_DEVICE_ID_INTEL_DNV_SMBUS:
1541         case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS:
1542         case PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS:
1543         case PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS:
1544                 priv->features |= FEATURE_I2C_BLOCK_READ;
1545                 priv->features |= FEATURE_IRQ;
1546                 priv->features |= FEATURE_SMBUS_PEC;
1547                 priv->features |= FEATURE_BLOCK_BUFFER;
1548                 /* If we have ACPI based watchdog use that instead */
1549                 if (!acpi_has_watchdog())
1550                         priv->features |= FEATURE_TCO;
1551                 priv->features |= FEATURE_HOST_NOTIFY;
1552                 break;
1553
1554         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1555         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1556         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1557         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1558         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1559         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1560                 priv->features |= FEATURE_IDF;
1561                 /* fall through */
1562         default:
1563                 priv->features |= FEATURE_I2C_BLOCK_READ;
1564                 priv->features |= FEATURE_IRQ;
1565                 /* fall through */
1566         case PCI_DEVICE_ID_INTEL_82801DB_3:
1567                 priv->features |= FEATURE_SMBUS_PEC;
1568                 priv->features |= FEATURE_BLOCK_BUFFER;
1569                 /* fall through */
1570         case PCI_DEVICE_ID_INTEL_82801CA_3:
1571                 priv->features |= FEATURE_HOST_NOTIFY;
1572                 /* fall through */
1573         case PCI_DEVICE_ID_INTEL_82801BA_2:
1574         case PCI_DEVICE_ID_INTEL_82801AB_3:
1575         case PCI_DEVICE_ID_INTEL_82801AA_3:
1576                 break;
1577         }
1578
1579         /* Disable features on user request */
1580         for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1581                 if (priv->features & disable_features & (1 << i))
1582                         dev_notice(&dev->dev, "%s disabled by user\n",
1583                                    i801_feature_names[i]);
1584         }
1585         priv->features &= ~disable_features;
1586
1587         err = pcim_enable_device(dev);
1588         if (err) {
1589                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1590                         err);
1591                 return err;
1592         }
1593         pcim_pin_device(dev);
1594
1595         /* Determine the address of the SMBus area */
1596         priv->smba = pci_resource_start(dev, SMBBAR);
1597         if (!priv->smba) {
1598                 dev_err(&dev->dev,
1599                         "SMBus base address uninitialized, upgrade BIOS\n");
1600                 return -ENODEV;
1601         }
1602
1603         if (i801_acpi_probe(priv))
1604                 return -ENODEV;
1605
1606         err = pcim_iomap_regions(dev, 1 << SMBBAR,
1607                                  dev_driver_string(&dev->dev));
1608         if (err) {
1609                 dev_err(&dev->dev,
1610                         "Failed to request SMBus region 0x%lx-0x%Lx\n",
1611                         priv->smba,
1612                         (unsigned long long)pci_resource_end(dev, SMBBAR));
1613                 i801_acpi_remove(priv);
1614                 return err;
1615         }
1616
1617         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &priv->original_hstcfg);
1618         temp = i801_setup_hstcfg(priv);
1619         if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN))
1620                 dev_info(&dev->dev, "Enabling SMBus device\n");
1621
1622         if (temp & SMBHSTCFG_SMB_SMI_EN) {
1623                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1624                 /* Disable SMBus interrupt feature if SMBus using SMI# */
1625                 priv->features &= ~FEATURE_IRQ;
1626         }
1627         if (temp & SMBHSTCFG_SPD_WD)
1628                 dev_info(&dev->dev, "SPD Write Disable is set\n");
1629
1630         /* Clear special mode bits */
1631         if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1632                 outb_p(inb_p(SMBAUXCTL(priv)) &
1633                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1634
1635         /* Remember original Host Notify setting */
1636         if (priv->features & FEATURE_HOST_NOTIFY)
1637                 priv->original_slvcmd = inb_p(SMBSLVCMD(priv));
1638
1639         /* Default timeout in interrupt mode: 200 ms */
1640         priv->adapter.timeout = HZ / 5;
1641
1642         if (dev->irq == IRQ_NOTCONNECTED)
1643                 priv->features &= ~FEATURE_IRQ;
1644
1645         if (priv->features & FEATURE_IRQ) {
1646                 u16 pcictl, pcists;
1647
1648                 /* Complain if an interrupt is already pending */
1649                 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
1650                 if (pcists & SMBPCISTS_INTS)
1651                         dev_warn(&dev->dev, "An interrupt is pending!\n");
1652
1653                 /* Check if interrupts have been disabled */
1654                 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl);
1655                 if (pcictl & SMBPCICTL_INTDIS) {
1656                         dev_info(&dev->dev, "Interrupts are disabled\n");
1657                         priv->features &= ~FEATURE_IRQ;
1658                 }
1659         }
1660
1661         if (priv->features & FEATURE_IRQ) {
1662                 init_waitqueue_head(&priv->waitq);
1663
1664                 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1665                                        IRQF_SHARED,
1666                                        dev_driver_string(&dev->dev), priv);
1667                 if (err) {
1668                         dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1669                                 dev->irq, err);
1670                         priv->features &= ~FEATURE_IRQ;
1671                 }
1672         }
1673         dev_info(&dev->dev, "SMBus using %s\n",
1674                  priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1675
1676         i801_add_tco(priv);
1677
1678         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1679                 "SMBus I801 adapter at %04lx", priv->smba);
1680         err = i2c_add_adapter(&priv->adapter);
1681         if (err) {
1682                 i801_acpi_remove(priv);
1683                 return err;
1684         }
1685
1686         i801_enable_host_notify(&priv->adapter);
1687
1688         i801_probe_optional_slaves(priv);
1689         /* We ignore errors - multiplexing is optional */
1690         i801_add_mux(priv);
1691
1692         pci_set_drvdata(dev, priv);
1693
1694         dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NEVER_SKIP);
1695         pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1696         pm_runtime_use_autosuspend(&dev->dev);
1697         pm_runtime_put_autosuspend(&dev->dev);
1698         pm_runtime_allow(&dev->dev);
1699
1700         return 0;
1701 }
1702
1703 static void i801_remove(struct pci_dev *dev)
1704 {
1705         struct i801_priv *priv = pci_get_drvdata(dev);
1706
1707         pm_runtime_forbid(&dev->dev);
1708         pm_runtime_get_noresume(&dev->dev);
1709
1710         i801_disable_host_notify(priv);
1711         i801_del_mux(priv);
1712         i2c_del_adapter(&priv->adapter);
1713         i801_acpi_remove(priv);
1714         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1715
1716         platform_device_unregister(priv->tco_pdev);
1717
1718         /*
1719          * do not call pci_disable_device(dev) since it can cause hard hangs on
1720          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1721          */
1722 }
1723
1724 static void i801_shutdown(struct pci_dev *dev)
1725 {
1726         struct i801_priv *priv = pci_get_drvdata(dev);
1727
1728         /* Restore config registers to avoid hard hang on some systems */
1729         i801_disable_host_notify(priv);
1730         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1731 }
1732
1733 #ifdef CONFIG_PM_SLEEP
1734 static int i801_suspend(struct device *dev)
1735 {
1736         struct pci_dev *pci_dev = to_pci_dev(dev);
1737         struct i801_priv *priv = pci_get_drvdata(pci_dev);
1738
1739         pci_write_config_byte(pci_dev, SMBHSTCFG, priv->original_hstcfg);
1740         return 0;
1741 }
1742
1743 static int i801_resume(struct device *dev)
1744 {
1745         struct pci_dev *pci_dev = to_pci_dev(dev);
1746         struct i801_priv *priv = pci_get_drvdata(pci_dev);
1747
1748         i801_setup_hstcfg(priv);
1749         i801_enable_host_notify(&priv->adapter);
1750
1751         return 0;
1752 }
1753 #endif
1754
1755 static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume);
1756
1757 static struct pci_driver i801_driver = {
1758         .name           = "i801_smbus",
1759         .id_table       = i801_ids,
1760         .probe          = i801_probe,
1761         .remove         = i801_remove,
1762         .shutdown       = i801_shutdown,
1763         .driver         = {
1764                 .pm     = &i801_pm_ops,
1765         },
1766 };
1767
1768 static int __init i2c_i801_init(void)
1769 {
1770         if (dmi_name_in_vendors("FUJITSU"))
1771                 input_apanel_init();
1772         return pci_register_driver(&i801_driver);
1773 }
1774
1775 static void __exit i2c_i801_exit(void)
1776 {
1777         pci_unregister_driver(&i801_driver);
1778 }
1779
1780 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>");
1781 MODULE_DESCRIPTION("I801 SMBus driver");
1782 MODULE_LICENSE("GPL");
1783
1784 module_init(i2c_i801_init);
1785 module_exit(i2c_i801_exit);