drivers/i2c/busses/i2c-imx.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *      Copyright (C) 2002 Motorola GSG-China
   4  *
   5  * Author:
   6  *      Darius Augulis, Teltonika Inc.
   7  *
   8  * Desc.:
   9  *      Implementation of I2C Adapter/Algorithm Driver
  10  *      for I2C Bus integrated in Freescale i.MX/MXC processors
  11  *
  12  *      Derived from Motorola GSG China I2C example driver
  13  *
  14  *      Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
  15  *      Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
  16  *      Copyright (C) 2007 RightHand Technologies, Inc.
  17  *      Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
  18  *
  19  *      Copyright 2013 Freescale Semiconductor, Inc.
  20  *
  21  */
  22
  23 #include <linux/clk.h>
  24 #include <linux/completion.h>
  25 #include <linux/delay.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/dmaengine.h>
  28 #include <linux/dmapool.h>
  29 #include <linux/err.h>
  30 #include <linux/errno.h>
  31 #include <linux/gpio/consumer.h>
  32 #include <linux/i2c.h>
  33 #include <linux/init.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/io.h>
  36 #include <linux/kernel.h>
  37 #include <linux/module.h>
  38 #include <linux/of.h>
  39 #include <linux/of_device.h>
  40 #include <linux/of_dma.h>
  41 #include <linux/pinctrl/consumer.h>
  42 #include <linux/platform_data/i2c-imx.h>
  43 #include <linux/platform_device.h>
  44 #include <linux/pm_runtime.h>
  45 #include <linux/sched.h>
  46 #include <linux/slab.h>
  47
  48 /* This will be the driver name the kernel reports */
  49 #define DRIVER_NAME "imx-i2c"
  50
  51 /* Default value */
  52 #define IMX_I2C_BIT_RATE        100000  /* 100kHz */
  53
  54 /*
  55  * Enable DMA if transfer byte size is bigger than this threshold.
  56  * As the hardware request, it must bigger than 4 bytes.\
  57  * I have set '16' here, maybe it's not the best but I think it's
  58  * the appropriate.
  59  */
  60 #define DMA_THRESHOLD   16
  61 #define DMA_TIMEOUT     1000
  62
  63 /* IMX I2C registers:
  64  * the I2C register offset is different between SoCs,
  65  * to provid support for all these chips, split the
  66  * register offset into a fixed base address and a
  67  * variable shift value, then the full register offset
  68  * will be calculated by
  69  * reg_off = ( reg_base_addr << reg_shift)
  70  */
  71 #define IMX_I2C_IADR    0x00    /* i2c slave address */
  72 #define IMX_I2C_IFDR    0x01    /* i2c frequency divider */
  73 #define IMX_I2C_I2CR    0x02    /* i2c control */
  74 #define IMX_I2C_I2SR    0x03    /* i2c status */
  75 #define IMX_I2C_I2DR    0x04    /* i2c transfer data */
  76
  77 #define IMX_I2C_REGSHIFT        2
  78 #define VF610_I2C_REGSHIFT      0
  79
  80 /* Bits of IMX I2C registers */
  81 #define I2SR_RXAK       0x01
  82 #define I2SR_IIF        0x02
  83 #define I2SR_SRW        0x04
  84 #define I2SR_IAL        0x10
  85 #define I2SR_IBB        0x20
  86 #define I2SR_IAAS       0x40
  87 #define I2SR_ICF        0x80
  88 #define I2CR_DMAEN      0x02
  89 #define I2CR_RSTA       0x04
  90 #define I2CR_TXAK       0x08
  91 #define I2CR_MTX        0x10
  92 #define I2CR_MSTA       0x20
  93 #define I2CR_IIEN       0x40
  94 #define I2CR_IEN        0x80
  95
  96 /* register bits different operating codes definition:
  97  * 1) I2SR: Interrupt flags clear operation differ between SoCs:
  98  * - write zero to clear(w0c) INT flag on i.MX,
  99  * - but write one to clear(w1c) INT flag on Vybrid.
 100  * 2) I2CR: I2C module enable operation also differ between SoCs:
 101  * - set I2CR_IEN bit enable the module on i.MX,
 102  * - but clear I2CR_IEN bit enable the module on Vybrid.
 103  */
 104 #define I2SR_CLR_OPCODE_W0C     0x0
 105 #define I2SR_CLR_OPCODE_W1C     (I2SR_IAL | I2SR_IIF)
 106 #define I2CR_IEN_OPCODE_0       0x0
 107 #define I2CR_IEN_OPCODE_1       I2CR_IEN
 108
 109 #define I2C_PM_TIMEOUT          10 /* ms */
 110
 111 /*
 112  * sorted list of clock divider, register value pairs
 113  * taken from table 26-5, p.26-9, Freescale i.MX
 114  * Integrated Portable System Processor Reference Manual
 115  * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
 116  *
 117  * Duplicated divider values removed from list
 118  */
 119 struct imx_i2c_clk_pair {
 120         u16     div;
 121         u16     val;
 122 };
 123
 124 static struct imx_i2c_clk_pair imx_i2c_clk_div[] = {
 125         { 22,   0x20 }, { 24,   0x21 }, { 26,   0x22 }, { 28,   0x23 },
 126         { 30,   0x00 }, { 32,   0x24 }, { 36,   0x25 }, { 40,   0x26 },
 127         { 42,   0x03 }, { 44,   0x27 }, { 48,   0x28 }, { 52,   0x05 },
 128         { 56,   0x29 }, { 60,   0x06 }, { 64,   0x2A }, { 72,   0x2B },
 129         { 80,   0x2C }, { 88,   0x09 }, { 96,   0x2D }, { 104,  0x0A },
 130         { 112,  0x2E }, { 128,  0x2F }, { 144,  0x0C }, { 160,  0x30 },
 131         { 192,  0x31 }, { 224,  0x32 }, { 240,  0x0F }, { 256,  0x33 },
 132         { 288,  0x10 }, { 320,  0x34 }, { 384,  0x35 }, { 448,  0x36 },
 133         { 480,  0x13 }, { 512,  0x37 }, { 576,  0x14 }, { 640,  0x38 },
 134         { 768,  0x39 }, { 896,  0x3A }, { 960,  0x17 }, { 1024, 0x3B },
 135         { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
 136         { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
 137         { 3072, 0x1E }, { 3840, 0x1F }
 138 };
 139
 140 /* Vybrid VF610 clock divider, register value pairs */
 141 static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = {
 142         { 20,   0x00 }, { 22,   0x01 }, { 24,   0x02 }, { 26,   0x03 },
 143         { 28,   0x04 }, { 30,   0x05 }, { 32,   0x09 }, { 34,   0x06 },
 144         { 36,   0x0A }, { 40,   0x07 }, { 44,   0x0C }, { 48,   0x0D },
 145         { 52,   0x43 }, { 56,   0x0E }, { 60,   0x45 }, { 64,   0x12 },
 146         { 68,   0x0F }, { 72,   0x13 }, { 80,   0x14 }, { 88,   0x15 },
 147         { 96,   0x19 }, { 104,  0x16 }, { 112,  0x1A }, { 128,  0x17 },
 148         { 136,  0x4F }, { 144,  0x1C }, { 160,  0x1D }, { 176,  0x55 },
 149         { 192,  0x1E }, { 208,  0x56 }, { 224,  0x22 }, { 228,  0x24 },
 150         { 240,  0x1F }, { 256,  0x23 }, { 288,  0x5C }, { 320,  0x25 },
 151         { 384,  0x26 }, { 448,  0x2A }, { 480,  0x27 }, { 512,  0x2B },
 152         { 576,  0x2C }, { 640,  0x2D }, { 768,  0x31 }, { 896,  0x32 },
 153         { 960,  0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
 154         { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
 155         { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
 156         { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
 157 };
 158
 159 enum imx_i2c_type {
 160         IMX1_I2C,
 161         IMX21_I2C,
 162         VF610_I2C,
 163 };
 164
 165 struct imx_i2c_hwdata {
 166         enum imx_i2c_type       devtype;
 167         unsigned                regshift;
 168         struct imx_i2c_clk_pair *clk_div;
 169         unsigned                ndivs;
 170         unsigned                i2sr_clr_opcode;
 171         unsigned                i2cr_ien_opcode;
 172 };
 173
 174 struct imx_i2c_dma {
 175         struct dma_chan         *chan_tx;
 176         struct dma_chan         *chan_rx;
 177         struct dma_chan         *chan_using;
 178         struct completion       cmd_complete;
 179         dma_addr_t              dma_buf;
 180         unsigned int            dma_len;
 181         enum dma_transfer_direction dma_transfer_dir;
 182         enum dma_data_direction dma_data_dir;
 183 };
 184
 185 struct imx_i2c_struct {
 186         struct i2c_adapter      adapter;
 187         struct clk              *clk;
 188         struct notifier_block   clk_change_nb;
 189         void __iomem            *base;
 190         wait_queue_head_t       queue;
 191         unsigned long           i2csr;
 192         unsigned int            disable_delay;
 193         int                     stopped;
 194         unsigned int            ifdr; /* IMX_I2C_IFDR */
 195         unsigned int            cur_clk;
 196         unsigned int            bitrate;
 197         const struct imx_i2c_hwdata     *hwdata;
 198         struct i2c_bus_recovery_info rinfo;
 199
 200         struct pinctrl *pinctrl;
 201         struct pinctrl_state *pinctrl_pins_default;
 202         struct pinctrl_state *pinctrl_pins_gpio;
 203
 204         struct imx_i2c_dma      *dma;
 205 };
 206
 207 static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
 208         .devtype                = IMX1_I2C,
 209         .regshift               = IMX_I2C_REGSHIFT,
 210         .clk_div                = imx_i2c_clk_div,
 211         .ndivs                  = ARRAY_SIZE(imx_i2c_clk_div),
 212         .i2sr_clr_opcode        = I2SR_CLR_OPCODE_W0C,
 213         .i2cr_ien_opcode        = I2CR_IEN_OPCODE_1,
 214
 215 };
 216
 217 static const struct imx_i2c_hwdata imx21_i2c_hwdata = {
 218         .devtype                = IMX21_I2C,
 219         .regshift               = IMX_I2C_REGSHIFT,
 220         .clk_div                = imx_i2c_clk_div,
 221         .ndivs                  = ARRAY_SIZE(imx_i2c_clk_div),
 222         .i2sr_clr_opcode        = I2SR_CLR_OPCODE_W0C,
 223         .i2cr_ien_opcode        = I2CR_IEN_OPCODE_1,
 224
 225 };
 226
 227 static struct imx_i2c_hwdata vf610_i2c_hwdata = {
 228         .devtype                = VF610_I2C,
 229         .regshift               = VF610_I2C_REGSHIFT,
 230         .clk_div                = vf610_i2c_clk_div,
 231         .ndivs                  = ARRAY_SIZE(vf610_i2c_clk_div),
 232         .i2sr_clr_opcode        = I2SR_CLR_OPCODE_W1C,
 233         .i2cr_ien_opcode        = I2CR_IEN_OPCODE_0,
 234
 235 };
 236
 237 static const struct platform_device_id imx_i2c_devtype[] = {
 238         {
 239                 .name = "imx1-i2c",
 240                 .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata,
 241         }, {
 242                 .name = "imx21-i2c",
 243                 .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata,
 244         }, {
 245                 /* sentinel */
 246         }
 247 };
 248 MODULE_DEVICE_TABLE(platform, imx_i2c_devtype);
 249
 250 static const struct of_device_id i2c_imx_dt_ids[] = {
 251         { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, },
 252         { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, },
 253         { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, },
 254         { /* sentinel */ }
 255 };
 256 MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids);
 257
 258 static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx)
 259 {
 260         return i2c_imx->hwdata->devtype == IMX1_I2C;
 261 }
 262
 263 static inline void imx_i2c_write_reg(unsigned int val,
 264                 struct imx_i2c_struct *i2c_imx, unsigned int reg)
 265 {
 266         writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
 267 }
 268
 269 static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx,
 270                 unsigned int reg)
 271 {
 272         return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
 273 }
 274
 275 /* Functions for DMA support */
 276 static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
 277                                                 dma_addr_t phy_addr)
 278 {
 279         struct imx_i2c_dma *dma;
 280         struct dma_slave_config dma_sconfig;
 281         struct device *dev = &i2c_imx->adapter.dev;
 282         int ret;
 283
 284         dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
 285         if (!dma)
 286                 return;
 287
 288         dma->chan_tx = dma_request_slave_channel(dev, "tx");
 289         if (!dma->chan_tx) {
 290                 dev_dbg(dev, "can't request DMA tx channel\n");
 291                 goto fail_al;
 292         }
 293
 294         dma_sconfig.dst_addr = phy_addr +
 295                                 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
 296         dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 297         dma_sconfig.dst_maxburst = 1;
 298         dma_sconfig.direction = DMA_MEM_TO_DEV;
 299         ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig);
 300         if (ret < 0) {
 301                 dev_dbg(dev, "can't configure tx channel\n");
 302                 goto fail_tx;
 303         }
 304
 305         dma->chan_rx = dma_request_slave_channel(dev, "rx");
 306         if (!dma->chan_rx) {
 307                 dev_dbg(dev, "can't request DMA rx channel\n");
 308                 goto fail_tx;
 309         }
 310
 311         dma_sconfig.src_addr = phy_addr +
 312                                 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
 313         dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 314         dma_sconfig.src_maxburst = 1;
 315         dma_sconfig.direction = DMA_DEV_TO_MEM;
 316         ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig);
 317         if (ret < 0) {
 318                 dev_dbg(dev, "can't configure rx channel\n");
 319                 goto fail_rx;
 320         }
 321
 322         i2c_imx->dma = dma;
 323         init_completion(&dma->cmd_complete);
 324         dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n",
 325                 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
 326
 327         return;
 328
 329 fail_rx:
 330         dma_release_channel(dma->chan_rx);
 331 fail_tx:
 332         dma_release_channel(dma->chan_tx);
 333 fail_al:
 334         devm_kfree(dev, dma);
 335         dev_info(dev, "can't use DMA, using PIO instead.\n");
 336 }
 337
 338 static void i2c_imx_dma_callback(void *arg)
 339 {
 340         struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg;
 341         struct imx_i2c_dma *dma = i2c_imx->dma;
 342
 343         dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf,
 344                         dma->dma_len, dma->dma_data_dir);
 345         complete(&dma->cmd_complete);
 346 }
 347
 348 static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx,
 349                                         struct i2c_msg *msgs)
 350 {
 351         struct imx_i2c_dma *dma = i2c_imx->dma;
 352         struct dma_async_tx_descriptor *txdesc;
 353         struct device *dev = &i2c_imx->adapter.dev;
 354         struct device *chan_dev = dma->chan_using->device->dev;
 355
 356         dma->dma_buf = dma_map_single(chan_dev, msgs->buf,
 357                                         dma->dma_len, dma->dma_data_dir);
 358         if (dma_mapping_error(chan_dev, dma->dma_buf)) {
 359                 dev_err(dev, "DMA mapping failed\n");
 360                 goto err_map;
 361         }
 362
 363         txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf,
 364                                         dma->dma_len, dma->dma_transfer_dir,
 365                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 366         if (!txdesc) {
 367                 dev_err(dev, "Not able to get desc for DMA xfer\n");
 368                 goto err_desc;
 369         }
 370
 371         reinit_completion(&dma->cmd_complete);
 372         txdesc->callback = i2c_imx_dma_callback;
 373         txdesc->callback_param = i2c_imx;
 374         if (dma_submit_error(dmaengine_submit(txdesc))) {
 375                 dev_err(dev, "DMA submit failed\n");
 376                 goto err_submit;
 377         }
 378
 379         dma_async_issue_pending(dma->chan_using);
 380         return 0;
 381
 382 err_submit:
 383         dmaengine_terminate_all(dma->chan_using);
 384 err_desc:
 385         dma_unmap_single(chan_dev, dma->dma_buf,
 386                         dma->dma_len, dma->dma_data_dir);
 387 err_map:
 388         return -EINVAL;
 389 }
 390
 391 static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx)
 392 {
 393         struct imx_i2c_dma *dma = i2c_imx->dma;
 394
 395         dma->dma_buf = 0;
 396         dma->dma_len = 0;
 397
 398         dma_release_channel(dma->chan_tx);
 399         dma->chan_tx = NULL;
 400
 401         dma_release_channel(dma->chan_rx);
 402         dma->chan_rx = NULL;
 403
 404         dma->chan_using = NULL;
 405 }
 406
 407 static void i2c_imx_clear_irq(struct imx_i2c_struct *i2c_imx, unsigned int bits)
 408 {
 409         unsigned int temp;
 410
 411         /*
 412          * i2sr_clr_opcode is the value to clear all interrupts. Here we want to
 413          * clear only <bits>, so we write ~i2sr_clr_opcode with just <bits>
 414          * toggled. This is required because i.MX needs W0C and Vybrid uses W1C.
 415          */
 416         temp = ~i2c_imx->hwdata->i2sr_clr_opcode ^ bits;
 417         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
 418 }
 419
 420 static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy)
 421 {
 422         unsigned long orig_jiffies = jiffies;
 423         unsigned int temp;
 424
 425         dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
 426
 427         while (1) {
 428                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 429
 430                 /* check for arbitration lost */
 431                 if (temp & I2SR_IAL) {
 432                         i2c_imx_clear_irq(i2c_imx, I2SR_IAL);
 433                         return -EAGAIN;
 434                 }
 435
 436                 if (for_busy && (temp & I2SR_IBB)) {
 437                         i2c_imx->stopped = 0;
 438                         break;
 439                 }
 440                 if (!for_busy && !(temp & I2SR_IBB)) {
 441                         i2c_imx->stopped = 1;
 442                         break;
 443                 }
 444                 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
 445                         dev_dbg(&i2c_imx->adapter.dev,
 446                                 "<%s> I2C bus is busy\n", __func__);
 447                         return -ETIMEDOUT;
 448                 }
 449                 schedule();
 450         }
 451
 452         return 0;
 453 }
 454
 455 static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx)
 456 {
 457         wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);
 458
 459         if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
 460                 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
 461                 return -ETIMEDOUT;
 462         }
 463
 464         /* check for arbitration lost */
 465         if (i2c_imx->i2csr & I2SR_IAL) {
 466                 dev_dbg(&i2c_imx->adapter.dev, "<%s> Arbitration lost\n", __func__);
 467                 i2c_imx_clear_irq(i2c_imx, I2SR_IAL);
 468
 469                 i2c_imx->i2csr = 0;
 470                 return -EAGAIN;
 471         }
 472
 473         dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
 474         i2c_imx->i2csr = 0;
 475         return 0;
 476 }
 477
 478 static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
 479 {
 480         if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) {
 481                 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
 482                 return -ENXIO;  /* No ACK */
 483         }
 484
 485         dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
 486         return 0;
 487 }
 488
 489 static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
 490                             unsigned int i2c_clk_rate)
 491 {
 492         struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div;
 493         unsigned int div;
 494         int i;
 495
 496         /* Divider value calculation */
 497         if (i2c_imx->cur_clk == i2c_clk_rate)
 498                 return;
 499
 500         i2c_imx->cur_clk = i2c_clk_rate;
 501
 502         div = (i2c_clk_rate + i2c_imx->bitrate - 1) / i2c_imx->bitrate;
 503         if (div < i2c_clk_div[0].div)
 504                 i = 0;
 505         else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div)
 506                 i = i2c_imx->hwdata->ndivs - 1;
 507         else
 508                 for (i = 0; i2c_clk_div[i].div < div; i++)
 509                         ;
 510
 511         /* Store divider value */
 512         i2c_imx->ifdr = i2c_clk_div[i].val;
 513
 514         /*
 515          * There dummy delay is calculated.
 516          * It should be about one I2C clock period long.
 517          * This delay is used in I2C bus disable function
 518          * to fix chip hardware bug.
 519          */
 520         i2c_imx->disable_delay = (500000U * i2c_clk_div[i].div
 521                 + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);
 522
 523 #ifdef CONFIG_I2C_DEBUG_BUS
 524         dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n",
 525                 i2c_clk_rate, div);
 526         dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n",
 527                 i2c_clk_div[i].val, i2c_clk_div[i].div);
 528 #endif
 529 }
 530
 531 static int i2c_imx_clk_notifier_call(struct notifier_block *nb,
 532                                      unsigned long action, void *data)
 533 {
 534         struct clk_notifier_data *ndata = data;
 535         struct imx_i2c_struct *i2c_imx = container_of(nb,
 536                                                       struct imx_i2c_struct,
 537                                                       clk_change_nb);
 538
 539         if (action & POST_RATE_CHANGE)
 540                 i2c_imx_set_clk(i2c_imx, ndata->new_rate);
 541
 542         return NOTIFY_OK;
 543 }
 544
 545 static int i2c_imx_start(struct imx_i2c_struct *i2c_imx)
 546 {
 547         unsigned int temp = 0;
 548         int result;
 549
 550         dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
 551
 552         imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR);
 553         /* Enable I2C controller */
 554         imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
 555         imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR);
 556
 557         /* Wait controller to be stable */
 558         usleep_range(50, 150);
 559
 560         /* Start I2C transaction */
 561         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 562         temp |= I2CR_MSTA;
 563         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 564         result = i2c_imx_bus_busy(i2c_imx, 1);
 565         if (result)
 566                 return result;
 567
 568         temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
 569         temp &= ~I2CR_DMAEN;
 570         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 571         return result;
 572 }
 573
 574 static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
 575 {
 576         unsigned int temp = 0;
 577
 578         if (!i2c_imx->stopped) {
 579                 /* Stop I2C transaction */
 580                 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
 581                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 582                 if (!(temp & I2CR_MSTA))
 583                         i2c_imx->stopped = 1;
 584                 temp &= ~(I2CR_MSTA | I2CR_MTX);
 585                 if (i2c_imx->dma)
 586                         temp &= ~I2CR_DMAEN;
 587                 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 588         }
 589         if (is_imx1_i2c(i2c_imx)) {
 590                 /*
 591                  * This delay caused by an i.MXL hardware bug.
 592                  * If no (or too short) delay, no "STOP" bit will be generated.
 593                  */
 594                 udelay(i2c_imx->disable_delay);
 595         }
 596
 597         if (!i2c_imx->stopped)
 598                 i2c_imx_bus_busy(i2c_imx, 0);
 599
 600         /* Disable I2C controller */
 601         temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
 602         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 603 }
 604
 605 static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
 606 {
 607         struct imx_i2c_struct *i2c_imx = dev_id;
 608         unsigned int temp;
 609
 610         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 611         if (temp & I2SR_IIF) {
 612                 /* save status register */
 613                 i2c_imx->i2csr = temp;
 614                 i2c_imx_clear_irq(i2c_imx, I2SR_IIF);
 615                 wake_up(&i2c_imx->queue);
 616                 return IRQ_HANDLED;
 617         }
 618
 619         return IRQ_NONE;
 620 }
 621
 622 static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx,
 623                                         struct i2c_msg *msgs)
 624 {
 625         int result;
 626         unsigned long time_left;
 627         unsigned int temp = 0;
 628         unsigned long orig_jiffies = jiffies;
 629         struct imx_i2c_dma *dma = i2c_imx->dma;
 630         struct device *dev = &i2c_imx->adapter.dev;
 631
 632         dma->chan_using = dma->chan_tx;
 633         dma->dma_transfer_dir = DMA_MEM_TO_DEV;
 634         dma->dma_data_dir = DMA_TO_DEVICE;
 635         dma->dma_len = msgs->len - 1;
 636         result = i2c_imx_dma_xfer(i2c_imx, msgs);
 637         if (result)
 638                 return result;
 639
 640         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 641         temp |= I2CR_DMAEN;
 642         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 643
 644         /*
 645          * Write slave address.
 646          * The first byte must be transmitted by the CPU.
 647          */
 648         imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
 649         time_left = wait_for_completion_timeout(
 650                                 &i2c_imx->dma->cmd_complete,
 651                                 msecs_to_jiffies(DMA_TIMEOUT));
 652         if (time_left == 0) {
 653                 dmaengine_terminate_all(dma->chan_using);
 654                 return -ETIMEDOUT;
 655         }
 656
 657         /* Waiting for transfer complete. */
 658         while (1) {
 659                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 660                 if (temp & I2SR_ICF)
 661                         break;
 662                 if (time_after(jiffies, orig_jiffies +
 663                                 msecs_to_jiffies(DMA_TIMEOUT))) {
 664                         dev_dbg(dev, "<%s> Timeout\n", __func__);
 665                         return -ETIMEDOUT;
 666                 }
 667                 schedule();
 668         }
 669
 670         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 671         temp &= ~I2CR_DMAEN;
 672         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 673
 674         /* The last data byte must be transferred by the CPU. */
 675         imx_i2c_write_reg(msgs->buf[msgs->len-1],
 676                                 i2c_imx, IMX_I2C_I2DR);
 677         result = i2c_imx_trx_complete(i2c_imx);
 678         if (result)
 679                 return result;
 680
 681         return i2c_imx_acked(i2c_imx);
 682 }
 683
 684 static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx,
 685                         struct i2c_msg *msgs, bool is_lastmsg)
 686 {
 687         int result;
 688         unsigned long time_left;
 689         unsigned int temp;
 690         unsigned long orig_jiffies = jiffies;
 691         struct imx_i2c_dma *dma = i2c_imx->dma;
 692         struct device *dev = &i2c_imx->adapter.dev;
 693
 694
 695         dma->chan_using = dma->chan_rx;
 696         dma->dma_transfer_dir = DMA_DEV_TO_MEM;
 697         dma->dma_data_dir = DMA_FROM_DEVICE;
 698         /* The last two data bytes must be transferred by the CPU. */
 699         dma->dma_len = msgs->len - 2;
 700         result = i2c_imx_dma_xfer(i2c_imx, msgs);
 701         if (result)
 702                 return result;
 703
 704         time_left = wait_for_completion_timeout(
 705                                 &i2c_imx->dma->cmd_complete,
 706                                 msecs_to_jiffies(DMA_TIMEOUT));
 707         if (time_left == 0) {
 708                 dmaengine_terminate_all(dma->chan_using);
 709                 return -ETIMEDOUT;
 710         }
 711
 712         /* waiting for transfer complete. */
 713         while (1) {
 714                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 715                 if (temp & I2SR_ICF)
 716                         break;
 717                 if (time_after(jiffies, orig_jiffies +
 718                                 msecs_to_jiffies(DMA_TIMEOUT))) {
 719                         dev_dbg(dev, "<%s> Timeout\n", __func__);
 720                         return -ETIMEDOUT;
 721                 }
 722                 schedule();
 723         }
 724
 725         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 726         temp &= ~I2CR_DMAEN;
 727         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 728
 729         /* read n-1 byte data */
 730         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 731         temp |= I2CR_TXAK;
 732         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 733
 734         msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
 735         /* read n byte data */
 736         result = i2c_imx_trx_complete(i2c_imx);
 737         if (result)
 738                 return result;
 739
 740         if (is_lastmsg) {
 741                 /*
 742                  * It must generate STOP before read I2DR to prevent
 743                  * controller from generating another clock cycle
 744                  */
 745                 dev_dbg(dev, "<%s> clear MSTA\n", __func__);
 746                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 747                 if (!(temp & I2CR_MSTA))
 748                         i2c_imx->stopped = 1;
 749                 temp &= ~(I2CR_MSTA | I2CR_MTX);
 750                 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 751                 if (!i2c_imx->stopped)
 752                         i2c_imx_bus_busy(i2c_imx, 0);
 753         } else {
 754                 /*
 755                  * For i2c master receiver repeat restart operation like:
 756                  * read -> repeat MSTA -> read/write
 757                  * The controller must set MTX before read the last byte in
 758                  * the first read operation, otherwise the first read cost
 759                  * one extra clock cycle.
 760                  */
 761                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 762                 temp |= I2CR_MTX;
 763                 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 764         }
 765         msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
 766
 767         return 0;
 768 }
 769
 770 static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
 771 {
 772         int i, result;
 773
 774         dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
 775                 __func__, i2c_8bit_addr_from_msg(msgs));
 776
 777         /* write slave address */
 778         imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
 779         result = i2c_imx_trx_complete(i2c_imx);
 780         if (result)
 781                 return result;
 782         result = i2c_imx_acked(i2c_imx);
 783         if (result)
 784                 return result;
 785         dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
 786
 787         /* write data */
 788         for (i = 0; i < msgs->len; i++) {
 789                 dev_dbg(&i2c_imx->adapter.dev,
 790                         "<%s> write byte: B%d=0x%X\n",
 791                         __func__, i, msgs->buf[i]);
 792                 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR);
 793                 result = i2c_imx_trx_complete(i2c_imx);
 794                 if (result)
 795                         return result;
 796                 result = i2c_imx_acked(i2c_imx);
 797                 if (result)
 798                         return result;
 799         }
 800         return 0;
 801 }
 802
 803 static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, bool is_lastmsg)
 804 {
 805         int i, result;
 806         unsigned int temp;
 807         int block_data = msgs->flags & I2C_M_RECV_LEN;
 808         int use_dma = i2c_imx->dma && msgs->len >= DMA_THRESHOLD && !block_data;
 809
 810         dev_dbg(&i2c_imx->adapter.dev,
 811                 "<%s> write slave address: addr=0x%x\n",
 812                 __func__, i2c_8bit_addr_from_msg(msgs));
 813
 814         /* write slave address */
 815         imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
 816         result = i2c_imx_trx_complete(i2c_imx);
 817         if (result)
 818                 return result;
 819         result = i2c_imx_acked(i2c_imx);
 820         if (result)
 821                 return result;
 822
 823         dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
 824
 825         /* setup bus to read data */
 826         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 827         temp &= ~I2CR_MTX;
 828
 829         /*
 830          * Reset the I2CR_TXAK flag initially for SMBus block read since the
 831          * length is unknown
 832          */
 833         if ((msgs->len - 1) || block_data)
 834                 temp &= ~I2CR_TXAK;
 835         if (use_dma)
 836                 temp |= I2CR_DMAEN;
 837         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 838         imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */
 839
 840         dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
 841
 842         if (use_dma)
 843                 return i2c_imx_dma_read(i2c_imx, msgs, is_lastmsg);
 844
 845         /* read data */
 846         for (i = 0; i < msgs->len; i++) {
 847                 u8 len = 0;
 848
 849                 result = i2c_imx_trx_complete(i2c_imx);
 850                 if (result)
 851                         return result;
 852                 /*
 853                  * First byte is the length of remaining packet
 854                  * in the SMBus block data read. Add it to
 855                  * msgs->len.
 856                  */
 857                 if ((!i) && block_data) {
 858                         len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
 859                         if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX))
 860                                 return -EPROTO;
 861                         dev_dbg(&i2c_imx->adapter.dev,
 862                                 "<%s> read length: 0x%X\n",
 863                                 __func__, len);
 864                         msgs->len += len;
 865                 }
 866                 if (i == (msgs->len - 1)) {
 867                         if (is_lastmsg) {
 868                                 /*
 869                                  * It must generate STOP before read I2DR to prevent
 870                                  * controller from generating another clock cycle
 871                                  */
 872                                 dev_dbg(&i2c_imx->adapter.dev,
 873                                         "<%s> clear MSTA\n", __func__);
 874                                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 875                                 if (!(temp & I2CR_MSTA))
 876                                         i2c_imx->stopped =  1;
 877                                 temp &= ~(I2CR_MSTA | I2CR_MTX);
 878                                 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 879                                 if (!i2c_imx->stopped)
 880                                         i2c_imx_bus_busy(i2c_imx, 0);
 881                         } else {
 882                                 /*
 883                                  * For i2c master receiver repeat restart operation like:
 884                                  * read -> repeat MSTA -> read/write
 885                                  * The controller must set MTX before read the last byte in
 886                                  * the first read operation, otherwise the first read cost
 887                                  * one extra clock cycle.
 888                                  */
 889                                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 890                                 temp |= I2CR_MTX;
 891                                 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 892                         }
 893                 } else if (i == (msgs->len - 2)) {
 894                         dev_dbg(&i2c_imx->adapter.dev,
 895                                 "<%s> set TXAK\n", __func__);
 896                         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 897                         temp |= I2CR_TXAK;
 898                         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 899                 }
 900                 if ((!i) && block_data)
 901                         msgs->buf[0] = len;
 902                 else
 903                         msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
 904                 dev_dbg(&i2c_imx->adapter.dev,
 905                         "<%s> read byte: B%d=0x%X\n",
 906                         __func__, i, msgs->buf[i]);
 907         }
 908         return 0;
 909 }
 910
 911 static int i2c_imx_xfer(struct i2c_adapter *adapter,
 912                                                 struct i2c_msg *msgs, int num)
 913 {
 914         unsigned int i, temp;
 915         int result;
 916         bool is_lastmsg = false;
 917         struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
 918
 919         dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
 920
 921         result = pm_runtime_get_sync(i2c_imx->adapter.dev.parent);
 922         if (result < 0)
 923                 goto out;
 924
 925         /* Start I2C transfer */
 926         result = i2c_imx_start(i2c_imx);
 927         if (result) {
 928                 if (i2c_imx->adapter.bus_recovery_info) {
 929                         i2c_recover_bus(&i2c_imx->adapter);
 930                         result = i2c_imx_start(i2c_imx);
 931                 }
 932         }
 933
 934         if (result)
 935                 goto fail0;
 936
 937         /* read/write data */
 938         for (i = 0; i < num; i++) {
 939                 if (i == num - 1)
 940                         is_lastmsg = true;
 941
 942                 if (i) {
 943                         dev_dbg(&i2c_imx->adapter.dev,
 944                                 "<%s> repeated start\n", __func__);
 945                         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 946                         temp |= I2CR_RSTA;
 947                         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 948                         result = i2c_imx_bus_busy(i2c_imx, 1);
 949                         if (result)
 950                                 goto fail0;
 951                 }
 952                 dev_dbg(&i2c_imx->adapter.dev,
 953                         "<%s> transfer message: %d\n", __func__, i);
 954                 /* write/read data */
 955 #ifdef CONFIG_I2C_DEBUG_BUS
 956                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 957                 dev_dbg(&i2c_imx->adapter.dev,
 958                         "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n",
 959                         __func__,
 960                         (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
 961                         (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
 962                         (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
 963                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 964                 dev_dbg(&i2c_imx->adapter.dev,
 965                         "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n",
 966                         __func__,
 967                         (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
 968                         (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
 969                         (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
 970                         (temp & I2SR_RXAK ? 1 : 0));
 971 #endif
 972                 if (msgs[i].flags & I2C_M_RD)
 973                         result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg);
 974                 else {
 975                         if (i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD)
 976                                 result = i2c_imx_dma_write(i2c_imx, &msgs[i]);
 977                         else
 978                                 result = i2c_imx_write(i2c_imx, &msgs[i]);
 979                 }
 980                 if (result)
 981                         goto fail0;
 982         }
 983
 984 fail0:
 985         /* Stop I2C transfer */
 986         i2c_imx_stop(i2c_imx);
 987
 988         pm_runtime_mark_last_busy(i2c_imx->adapter.dev.parent);
 989         pm_runtime_put_autosuspend(i2c_imx->adapter.dev.parent);
 990
 991 out:
 992         dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
 993                 (result < 0) ? "error" : "success msg",
 994                         (result < 0) ? result : num);
 995         return (result < 0) ? result : num;
 996 }
 997
 998 static void i2c_imx_prepare_recovery(struct i2c_adapter *adap)
 999 {
1000         struct imx_i2c_struct *i2c_imx;
1001
1002         i2c_imx = container_of(adap, struct imx_i2c_struct, adapter);
1003
1004         pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_gpio);
1005 }
1006
1007 static void i2c_imx_unprepare_recovery(struct i2c_adapter *adap)
1008 {
1009         struct imx_i2c_struct *i2c_imx;
1010
1011         i2c_imx = container_of(adap, struct imx_i2c_struct, adapter);
1012
1013         pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_default);
1014 }
1015
1016 /*
1017  * We switch SCL and SDA to their GPIO function and do some bitbanging
1018  * for bus recovery. These alternative pinmux settings can be
1019  * described in the device tree by a separate pinctrl state "gpio". If
1020  * this is missing this is not a big problem, the only implication is
1021  * that we can't do bus recovery.
1022  */
1023 static int i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx,
1024                 struct platform_device *pdev)
1025 {
1026         struct i2c_bus_recovery_info *rinfo = &i2c_imx->rinfo;
1027
1028         i2c_imx->pinctrl = devm_pinctrl_get(&pdev->dev);
1029         if (!i2c_imx->pinctrl || IS_ERR(i2c_imx->pinctrl)) {
1030                 dev_info(&pdev->dev, "can't get pinctrl, bus recovery not supported\n");
1031                 return PTR_ERR(i2c_imx->pinctrl);
1032         }
1033
1034         i2c_imx->pinctrl_pins_default = pinctrl_lookup_state(i2c_imx->pinctrl,
1035                         PINCTRL_STATE_DEFAULT);
1036         i2c_imx->pinctrl_pins_gpio = pinctrl_lookup_state(i2c_imx->pinctrl,
1037                         "gpio");
1038         rinfo->sda_gpiod = devm_gpiod_get(&pdev->dev, "sda", GPIOD_IN);
1039         rinfo->scl_gpiod = devm_gpiod_get(&pdev->dev, "scl", GPIOD_OUT_HIGH_OPEN_DRAIN);
1040
1041         if (PTR_ERR(rinfo->sda_gpiod) == -EPROBE_DEFER ||
1042             PTR_ERR(rinfo->scl_gpiod) == -EPROBE_DEFER) {
1043                 return -EPROBE_DEFER;
1044         } else if (IS_ERR(rinfo->sda_gpiod) ||
1045                    IS_ERR(rinfo->scl_gpiod) ||
1046                    IS_ERR(i2c_imx->pinctrl_pins_default) ||
1047                    IS_ERR(i2c_imx->pinctrl_pins_gpio)) {
1048                 dev_dbg(&pdev->dev, "recovery information incomplete\n");
1049                 return 0;
1050         }
1051
1052         dev_dbg(&pdev->dev, "using scl%s for recovery\n",
1053                 rinfo->sda_gpiod ? ",sda" : "");
1054
1055         rinfo->prepare_recovery = i2c_imx_prepare_recovery;
1056         rinfo->unprepare_recovery = i2c_imx_unprepare_recovery;
1057         rinfo->recover_bus = i2c_generic_scl_recovery;
1058         i2c_imx->adapter.bus_recovery_info = rinfo;
1059
1060         return 0;
1061 }
1062
1063 static u32 i2c_imx_func(struct i2c_adapter *adapter)
1064 {
1065         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
1066                 | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
1067 }
1068
1069 static const struct i2c_algorithm i2c_imx_algo = {
1070         .master_xfer    = i2c_imx_xfer,
1071         .functionality  = i2c_imx_func,
1072 };
1073
1074 static int i2c_imx_probe(struct platform_device *pdev)
1075 {
1076         const struct of_device_id *of_id = of_match_device(i2c_imx_dt_ids,
1077                                                            &pdev->dev);
1078         struct imx_i2c_struct *i2c_imx;
1079         struct resource *res;
1080         struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev);
1081         void __iomem *base;
1082         int irq, ret;
1083         dma_addr_t phy_addr;
1084
1085         dev_dbg(&pdev->dev, "<%s>\n", __func__);
1086
1087         irq = platform_get_irq(pdev, 0);
1088         if (irq < 0) {
1089                 dev_err(&pdev->dev, "can't get irq number\n");
1090                 return irq;
1091         }
1092
1093         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1094         base = devm_ioremap_resource(&pdev->dev, res);
1095         if (IS_ERR(base))
1096                 return PTR_ERR(base);
1097
1098         phy_addr = (dma_addr_t)res->start;
1099         i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL);
1100         if (!i2c_imx)
1101                 return -ENOMEM;
1102
1103         if (of_id)
1104                 i2c_imx->hwdata = of_id->data;
1105         else
1106                 i2c_imx->hwdata = (struct imx_i2c_hwdata *)
1107                                 platform_get_device_id(pdev)->driver_data;
1108
1109         /* Setup i2c_imx driver structure */
1110         strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name));
1111         i2c_imx->adapter.owner          = THIS_MODULE;
1112         i2c_imx->adapter.algo           = &i2c_imx_algo;
1113         i2c_imx->adapter.dev.parent     = &pdev->dev;
1114         i2c_imx->adapter.nr             = pdev->id;
1115         i2c_imx->adapter.dev.of_node    = pdev->dev.of_node;
1116         i2c_imx->base                   = base;
1117
1118         /* Get I2C clock */
1119         i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
1120         if (IS_ERR(i2c_imx->clk)) {
1121                 if (PTR_ERR(i2c_imx->clk) != -EPROBE_DEFER)
1122                         dev_err(&pdev->dev, "can't get I2C clock\n");
1123                 return PTR_ERR(i2c_imx->clk);
1124         }
1125
1126         ret = clk_prepare_enable(i2c_imx->clk);
1127         if (ret) {
1128                 dev_err(&pdev->dev, "can't enable I2C clock, ret=%d\n", ret);
1129                 return ret;
1130         }
1131
1132         /* Init queue */
1133         init_waitqueue_head(&i2c_imx->queue);
1134
1135         /* Set up adapter data */
1136         i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
1137
1138         /* Set up platform driver data */
1139         platform_set_drvdata(pdev, i2c_imx);
1140
1141         pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT);
1142         pm_runtime_use_autosuspend(&pdev->dev);
1143         pm_runtime_set_active(&pdev->dev);
1144         pm_runtime_enable(&pdev->dev);
1145
1146         ret = pm_runtime_get_sync(&pdev->dev);
1147         if (ret < 0)
1148                 goto rpm_disable;
1149
1150         /* Request IRQ */
1151         ret = request_threaded_irq(irq, i2c_imx_isr, NULL, IRQF_SHARED,
1152                                    pdev->name, i2c_imx);
1153         if (ret) {
1154                 dev_err(&pdev->dev, "can't claim irq %d\n", irq);
1155                 goto rpm_disable;
1156         }
1157
1158         /* Set up clock divider */
1159         i2c_imx->bitrate = IMX_I2C_BIT_RATE;
1160         ret = of_property_read_u32(pdev->dev.of_node,
1161                                    "clock-frequency", &i2c_imx->bitrate);
1162         if (ret < 0 && pdata && pdata->bitrate)
1163                 i2c_imx->bitrate = pdata->bitrate;
1164         i2c_imx->clk_change_nb.notifier_call = i2c_imx_clk_notifier_call;
1165         clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb);
1166         i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk));
1167
1168         /* Set up chip registers to defaults */
1169         imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
1170                         i2c_imx, IMX_I2C_I2CR);
1171         imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
1172
1173         /* Init optional bus recovery function */
1174         ret = i2c_imx_init_recovery_info(i2c_imx, pdev);
1175         /* Give it another chance if pinctrl used is not ready yet */
1176         if (ret == -EPROBE_DEFER)
1177                 goto clk_notifier_unregister;
1178
1179         /* Add I2C adapter */
1180         ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
1181         if (ret < 0)
1182                 goto clk_notifier_unregister;
1183
1184         pm_runtime_mark_last_busy(&pdev->dev);
1185         pm_runtime_put_autosuspend(&pdev->dev);
1186
1187         dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);
1188         dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res);
1189         dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
1190                 i2c_imx->adapter.name);
1191         dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
1192
1193         /* Init DMA config if supported */
1194         i2c_imx_dma_request(i2c_imx, phy_addr);
1195
1196         return 0;   /* Return OK */
1197
1198 clk_notifier_unregister:
1199         clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb);
1200         free_irq(irq, i2c_imx);
1201 rpm_disable:
1202         pm_runtime_put_noidle(&pdev->dev);
1203         pm_runtime_disable(&pdev->dev);
1204         pm_runtime_set_suspended(&pdev->dev);
1205         pm_runtime_dont_use_autosuspend(&pdev->dev);
1206         clk_disable_unprepare(i2c_imx->clk);
1207         return ret;
1208 }
1209
1210 static int i2c_imx_remove(struct platform_device *pdev)
1211 {
1212         struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
1213         int irq, ret;
1214
1215         ret = pm_runtime_get_sync(&pdev->dev);
1216         if (ret < 0)
1217                 return ret;
1218
1219         /* remove adapter */
1220         dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
1221         i2c_del_adapter(&i2c_imx->adapter);
1222
1223         if (i2c_imx->dma)
1224                 i2c_imx_dma_free(i2c_imx);
1225
1226         /* setup chip registers to defaults */
1227         imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
1228         imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR);
1229         imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR);
1230         imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR);
1231
1232         clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb);
1233         irq = platform_get_irq(pdev, 0);
1234         if (irq >= 0)
1235                 free_irq(irq, i2c_imx);
1236         clk_disable_unprepare(i2c_imx->clk);
1237
1238         pm_runtime_put_noidle(&pdev->dev);
1239         pm_runtime_disable(&pdev->dev);
1240
1241         return 0;
1242 }
1243
1244 #ifdef CONFIG_PM
1245 static int i2c_imx_runtime_suspend(struct device *dev)
1246 {
1247         struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);
1248
1249         clk_disable(i2c_imx->clk);
1250
1251         return 0;
1252 }
1253
1254 static int i2c_imx_runtime_resume(struct device *dev)
1255 {
1256         struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);
1257         int ret;
1258
1259         ret = clk_enable(i2c_imx->clk);
1260         if (ret)
1261                 dev_err(dev, "can't enable I2C clock, ret=%d\n", ret);
1262
1263         return ret;
1264 }
1265
1266 static const struct dev_pm_ops i2c_imx_pm_ops = {
1267         SET_RUNTIME_PM_OPS(i2c_imx_runtime_suspend,
1268                            i2c_imx_runtime_resume, NULL)
1269 };
1270 #define I2C_IMX_PM_OPS (&i2c_imx_pm_ops)
1271 #else
1272 #define I2C_IMX_PM_OPS NULL
1273 #endif /* CONFIG_PM */
1274
1275 static struct platform_driver i2c_imx_driver = {
1276         .probe = i2c_imx_probe,
1277         .remove = i2c_imx_remove,
1278         .driver = {
1279                 .name = DRIVER_NAME,
1280                 .pm = I2C_IMX_PM_OPS,
1281                 .of_match_table = i2c_imx_dt_ids,
1282         },
1283         .id_table = imx_i2c_devtype,
1284 };
1285
1286 static int __init i2c_adap_imx_init(void)
1287 {
1288         return platform_driver_register(&i2c_imx_driver);
1289 }
1290 subsys_initcall(i2c_adap_imx_init);
1291
1292 static void __exit i2c_adap_imx_exit(void)
1293 {
1294         platform_driver_unregister(&i2c_imx_driver);
1295 }
1296 module_exit(i2c_adap_imx_exit);
1297
1298 MODULE_LICENSE("GPL");
1299 MODULE_AUTHOR("Darius Augulis");
1300 MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
1301 MODULE_ALIAS("platform:" DRIVER_NAME);