drivers/i2c/busses/i2c-ismt.c

   1 /*
   2  * This file is provided under a dual BSD/GPLv2 license.  When using or
   3  * redistributing this file, you may do so under either license.
   4  *
   5  * Copyright(c) 2012 Intel Corporation. All rights reserved.
   6  *
   7  * GPL LICENSE SUMMARY
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of version 2 of the GNU General Public License as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  * The full GNU General Public License is included in this distribution
  18  * in the file called LICENSE.GPL.
  19  *
  20  * BSD LICENSE
  21  *
  22  * Redistribution and use in source and binary forms, with or without
  23  * modification, are permitted provided that the following conditions
  24  * are met:
  25  *
  26  *   * Redistributions of source code must retain the above copyright
  27  *     notice, this list of conditions and the following disclaimer.
  28  *   * Redistributions in binary form must reproduce the above copyright
  29  *     notice, this list of conditions and the following disclaimer in
  30  *     the documentation and/or other materials provided with the
  31  *     distribution.
  32  *   * Neither the name of Intel Corporation nor the names of its
  33  *     contributors may be used to endorse or promote products derived
  34  *     from this software without specific prior written permission.
  35  *
  36  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  37  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  38  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  39  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  40  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  41  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  42  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  43  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  44  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  45  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  46  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  47  */
  48
  49 /*
  50  *  Supports the SMBus Message Transport (SMT) in the Intel Atom Processor
  51  *  S12xx Product Family.
  52  *
  53  *  Features supported by this driver:
  54  *  Hardware PEC                     yes
  55  *  Block buffer                     yes
  56  *  Block process call transaction   no
  57  *  Slave mode                       no
  58  */
  59
  60 #include <linux/module.h>
  61 #include <linux/pci.h>
  62 #include <linux/kernel.h>
  63 #include <linux/stddef.h>
  64 #include <linux/completion.h>
  65 #include <linux/dma-mapping.h>
  66 #include <linux/i2c.h>
  67 #include <linux/acpi.h>
  68 #include <linux/interrupt.h>
  69
  70 #include <linux/io-64-nonatomic-lo-hi.h>
  71
  72 /* PCI Address Constants */
  73 #define SMBBAR          0
  74
  75 /* PCI DIDs for the Intel SMBus Message Transport (SMT) Devices */
  76 #define PCI_DEVICE_ID_INTEL_S1200_SMT0  0x0c59
  77 #define PCI_DEVICE_ID_INTEL_S1200_SMT1  0x0c5a
  78 #define PCI_DEVICE_ID_INTEL_DNV_SMT     0x19ac
  79 #define PCI_DEVICE_ID_INTEL_AVOTON_SMT  0x1f15
  80
  81 #define ISMT_DESC_ENTRIES       2       /* number of descriptor entries */
  82 #define ISMT_MAX_RETRIES        3       /* number of SMBus retries to attempt */
  83 #define ISMT_LOG_ENTRIES        3       /* number of interrupt cause log entries */
  84
  85 /* Hardware Descriptor Constants - Control Field */
  86 #define ISMT_DESC_CWRL  0x01    /* Command/Write Length */
  87 #define ISMT_DESC_BLK   0X04    /* Perform Block Transaction */
  88 #define ISMT_DESC_FAIR  0x08    /* Set fairness flag upon successful arbit. */
  89 #define ISMT_DESC_PEC   0x10    /* Packet Error Code */
  90 #define ISMT_DESC_I2C   0x20    /* I2C Enable */
  91 #define ISMT_DESC_INT   0x40    /* Interrupt */
  92 #define ISMT_DESC_SOE   0x80    /* Stop On Error */
  93
  94 /* Hardware Descriptor Constants - Status Field */
  95 #define ISMT_DESC_SCS   0x01    /* Success */
  96 #define ISMT_DESC_DLTO  0x04    /* Data Low Time Out */
  97 #define ISMT_DESC_NAK   0x08    /* NAK Received */
  98 #define ISMT_DESC_CRC   0x10    /* CRC Error */
  99 #define ISMT_DESC_CLTO  0x20    /* Clock Low Time Out */
 100 #define ISMT_DESC_COL   0x40    /* Collisions */
 101 #define ISMT_DESC_LPR   0x80    /* Large Packet Received */
 102
 103 /* Macros */
 104 #define ISMT_DESC_ADDR_RW(addr, rw) (((addr) << 1) | (rw))
 105
 106 /* iSMT General Register address offsets (SMBBAR + <addr>) */
 107 #define ISMT_GR_GCTRL           0x000   /* General Control */
 108 #define ISMT_GR_SMTICL          0x008   /* SMT Interrupt Cause Location */
 109 #define ISMT_GR_ERRINTMSK       0x010   /* Error Interrupt Mask */
 110 #define ISMT_GR_ERRAERMSK       0x014   /* Error AER Mask */
 111 #define ISMT_GR_ERRSTS          0x018   /* Error Status */
 112 #define ISMT_GR_ERRINFO         0x01c   /* Error Information */
 113
 114 /* iSMT Master Registers */
 115 #define ISMT_MSTR_MDBA          0x100   /* Master Descriptor Base Address */
 116 #define ISMT_MSTR_MCTRL         0x108   /* Master Control */
 117 #define ISMT_MSTR_MSTS          0x10c   /* Master Status */
 118 #define ISMT_MSTR_MDS           0x110   /* Master Descriptor Size */
 119 #define ISMT_MSTR_RPOLICY       0x114   /* Retry Policy */
 120
 121 /* iSMT Miscellaneous Registers */
 122 #define ISMT_SPGT       0x300   /* SMBus PHY Global Timing */
 123
 124 /* General Control Register (GCTRL) bit definitions */
 125 #define ISMT_GCTRL_TRST 0x04    /* Target Reset */
 126 #define ISMT_GCTRL_KILL 0x08    /* Kill */
 127 #define ISMT_GCTRL_SRST 0x40    /* Soft Reset */
 128
 129 /* Master Control Register (MCTRL) bit definitions */
 130 #define ISMT_MCTRL_SS   0x01            /* Start/Stop */
 131 #define ISMT_MCTRL_MEIE 0x10            /* Master Error Interrupt Enable */
 132 #define ISMT_MCTRL_FMHP 0x00ff0000      /* Firmware Master Head Ptr (FMHP) */
 133
 134 /* Master Status Register (MSTS) bit definitions */
 135 #define ISMT_MSTS_HMTP  0xff0000        /* HW Master Tail Pointer (HMTP) */
 136 #define ISMT_MSTS_MIS   0x20            /* Master Interrupt Status (MIS) */
 137 #define ISMT_MSTS_MEIS  0x10            /* Master Error Int Status (MEIS) */
 138 #define ISMT_MSTS_IP    0x01            /* In Progress */
 139
 140 /* Master Descriptor Size (MDS) bit definitions */
 141 #define ISMT_MDS_MASK   0xff    /* Master Descriptor Size mask (MDS) */
 142
 143 /* SMBus PHY Global Timing Register (SPGT) bit definitions */
 144 #define ISMT_SPGT_SPD_MASK      0xc0000000      /* SMBus Speed mask */
 145 #define ISMT_SPGT_SPD_80K       0x00            /* 80 kHz */
 146 #define ISMT_SPGT_SPD_100K      (0x1 << 30)     /* 100 kHz */
 147 #define ISMT_SPGT_SPD_400K      (0x2 << 30)     /* 400 kHz */
 148 #define ISMT_SPGT_SPD_1M        (0x3 << 30)     /* 1 MHz */
 149
 150
 151 /* MSI Control Register (MSICTL) bit definitions */
 152 #define ISMT_MSICTL_MSIE        0x01    /* MSI Enable */
 153
 154 /* iSMT Hardware Descriptor */
 155 struct ismt_desc {
 156         u8 tgtaddr_rw;  /* target address & r/w bit */
 157         u8 wr_len_cmd;  /* write length in bytes or a command */
 158         u8 rd_len;      /* read length */
 159         u8 control;     /* control bits */
 160         u8 status;      /* status bits */
 161         u8 retry;       /* collision retry and retry count */
 162         u8 rxbytes;     /* received bytes */
 163         u8 txbytes;     /* transmitted bytes */
 164         u32 dptr_low;   /* lower 32 bit of the data pointer */
 165         u32 dptr_high;  /* upper 32 bit of the data pointer */
 166 } __packed;
 167
 168 struct ismt_priv {
 169         struct i2c_adapter adapter;
 170         void __iomem *smba;                     /* PCI BAR */
 171         struct pci_dev *pci_dev;
 172         struct ismt_desc *hw;                   /* descriptor virt base addr */
 173         dma_addr_t io_rng_dma;                  /* descriptor HW base addr */
 174         u8 head;                                /* ring buffer head pointer */
 175         struct completion cmp;                  /* interrupt completion */
 176         u8 buffer[I2C_SMBUS_BLOCK_MAX + 16];    /* temp R/W data buffer */
 177         dma_addr_t log_dma;
 178         u32 *log;
 179 };
 180
 181 /**
 182  * ismt_ids - PCI device IDs supported by this driver
 183  */
 184 static const struct pci_device_id ismt_ids[] = {
 185         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT0) },
 186         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT1) },
 187         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMT) },
 188         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMT) },
 189         { 0, }
 190 };
 191
 192 MODULE_DEVICE_TABLE(pci, ismt_ids);
 193
 194 /* Bus speed control bits for slow debuggers - refer to the docs for usage */
 195 static unsigned int bus_speed;
 196 module_param(bus_speed, uint, S_IRUGO);
 197 MODULE_PARM_DESC(bus_speed, "Bus Speed in kHz (0 = BIOS default)");
 198
 199 /**
 200  * __ismt_desc_dump() - dump the contents of a specific descriptor
 201  */
 202 static void __ismt_desc_dump(struct device *dev, const struct ismt_desc *desc)
 203 {
 204
 205         dev_dbg(dev, "Descriptor struct:  %p\n", desc);
 206         dev_dbg(dev, "\ttgtaddr_rw=0x%02X\n", desc->tgtaddr_rw);
 207         dev_dbg(dev, "\twr_len_cmd=0x%02X\n", desc->wr_len_cmd);
 208         dev_dbg(dev, "\trd_len=    0x%02X\n", desc->rd_len);
 209         dev_dbg(dev, "\tcontrol=   0x%02X\n", desc->control);
 210         dev_dbg(dev, "\tstatus=    0x%02X\n", desc->status);
 211         dev_dbg(dev, "\tretry=     0x%02X\n", desc->retry);
 212         dev_dbg(dev, "\trxbytes=   0x%02X\n", desc->rxbytes);
 213         dev_dbg(dev, "\ttxbytes=   0x%02X\n", desc->txbytes);
 214         dev_dbg(dev, "\tdptr_low=  0x%08X\n", desc->dptr_low);
 215         dev_dbg(dev, "\tdptr_high= 0x%08X\n", desc->dptr_high);
 216 }
 217 /**
 218  * ismt_desc_dump() - dump the contents of a descriptor for debug purposes
 219  * @priv: iSMT private data
 220  */
 221 static void ismt_desc_dump(struct ismt_priv *priv)
 222 {
 223         struct device *dev = &priv->pci_dev->dev;
 224         struct ismt_desc *desc = &priv->hw[priv->head];
 225
 226         dev_dbg(dev, "Dump of the descriptor struct:  0x%X\n", priv->head);
 227         __ismt_desc_dump(dev, desc);
 228 }
 229
 230 /**
 231  * ismt_gen_reg_dump() - dump the iSMT General Registers
 232  * @priv: iSMT private data
 233  */
 234 static void ismt_gen_reg_dump(struct ismt_priv *priv)
 235 {
 236         struct device *dev = &priv->pci_dev->dev;
 237
 238         dev_dbg(dev, "Dump of the iSMT General Registers\n");
 239         dev_dbg(dev, "  GCTRL.... : (0x%p)=0x%X\n",
 240                 priv->smba + ISMT_GR_GCTRL,
 241                 readl(priv->smba + ISMT_GR_GCTRL));
 242         dev_dbg(dev, "  SMTICL... : (0x%p)=0x%016llX\n",
 243                 priv->smba + ISMT_GR_SMTICL,
 244                 (long long unsigned int)readq(priv->smba + ISMT_GR_SMTICL));
 245         dev_dbg(dev, "  ERRINTMSK : (0x%p)=0x%X\n",
 246                 priv->smba + ISMT_GR_ERRINTMSK,
 247                 readl(priv->smba + ISMT_GR_ERRINTMSK));
 248         dev_dbg(dev, "  ERRAERMSK : (0x%p)=0x%X\n",
 249                 priv->smba + ISMT_GR_ERRAERMSK,
 250                 readl(priv->smba + ISMT_GR_ERRAERMSK));
 251         dev_dbg(dev, "  ERRSTS... : (0x%p)=0x%X\n",
 252                 priv->smba + ISMT_GR_ERRSTS,
 253                 readl(priv->smba + ISMT_GR_ERRSTS));
 254         dev_dbg(dev, "  ERRINFO.. : (0x%p)=0x%X\n",
 255                 priv->smba + ISMT_GR_ERRINFO,
 256                 readl(priv->smba + ISMT_GR_ERRINFO));
 257 }
 258
 259 /**
 260  * ismt_mstr_reg_dump() - dump the iSMT Master Registers
 261  * @priv: iSMT private data
 262  */
 263 static void ismt_mstr_reg_dump(struct ismt_priv *priv)
 264 {
 265         struct device *dev = &priv->pci_dev->dev;
 266
 267         dev_dbg(dev, "Dump of the iSMT Master Registers\n");
 268         dev_dbg(dev, "  MDBA..... : (0x%p)=0x%016llX\n",
 269                 priv->smba + ISMT_MSTR_MDBA,
 270                 (long long unsigned int)readq(priv->smba + ISMT_MSTR_MDBA));
 271         dev_dbg(dev, "  MCTRL.... : (0x%p)=0x%X\n",
 272                 priv->smba + ISMT_MSTR_MCTRL,
 273                 readl(priv->smba + ISMT_MSTR_MCTRL));
 274         dev_dbg(dev, "  MSTS..... : (0x%p)=0x%X\n",
 275                 priv->smba + ISMT_MSTR_MSTS,
 276                 readl(priv->smba + ISMT_MSTR_MSTS));
 277         dev_dbg(dev, "  MDS...... : (0x%p)=0x%X\n",
 278                 priv->smba + ISMT_MSTR_MDS,
 279                 readl(priv->smba + ISMT_MSTR_MDS));
 280         dev_dbg(dev, "  RPOLICY.. : (0x%p)=0x%X\n",
 281                 priv->smba + ISMT_MSTR_RPOLICY,
 282                 readl(priv->smba + ISMT_MSTR_RPOLICY));
 283         dev_dbg(dev, "  SPGT..... : (0x%p)=0x%X\n",
 284                 priv->smba + ISMT_SPGT,
 285                 readl(priv->smba + ISMT_SPGT));
 286 }
 287
 288 /**
 289  * ismt_submit_desc() - add a descriptor to the ring
 290  * @priv: iSMT private data
 291  */
 292 static void ismt_submit_desc(struct ismt_priv *priv)
 293 {
 294         uint fmhp;
 295         uint val;
 296
 297         ismt_desc_dump(priv);
 298         ismt_gen_reg_dump(priv);
 299         ismt_mstr_reg_dump(priv);
 300
 301         /* Set the FMHP (Firmware Master Head Pointer)*/
 302         fmhp = ((priv->head + 1) % ISMT_DESC_ENTRIES) << 16;
 303         val = readl(priv->smba + ISMT_MSTR_MCTRL);
 304         writel((val & ~ISMT_MCTRL_FMHP) | fmhp,
 305                priv->smba + ISMT_MSTR_MCTRL);
 306
 307         /* Set the start bit */
 308         val = readl(priv->smba + ISMT_MSTR_MCTRL);
 309         writel(val | ISMT_MCTRL_SS,
 310                priv->smba + ISMT_MSTR_MCTRL);
 311 }
 312
 313 /**
 314  * ismt_process_desc() - handle the completion of the descriptor
 315  * @desc: the iSMT hardware descriptor
 316  * @data: data buffer from the upper layer
 317  * @priv: ismt_priv struct holding our dma buffer
 318  * @size: SMBus transaction type
 319  * @read_write: flag to indicate if this is a read or write
 320  */
 321 static int ismt_process_desc(const struct ismt_desc *desc,
 322                              union i2c_smbus_data *data,
 323                              struct ismt_priv *priv, int size,
 324                              char read_write)
 325 {
 326         u8 *dma_buffer = PTR_ALIGN(&priv->buffer[0], 16);
 327
 328         dev_dbg(&priv->pci_dev->dev, "Processing completed descriptor\n");
 329         __ismt_desc_dump(&priv->pci_dev->dev, desc);
 330         ismt_gen_reg_dump(priv);
 331         ismt_mstr_reg_dump(priv);
 332
 333         if (desc->status & ISMT_DESC_SCS) {
 334                 if (read_write == I2C_SMBUS_WRITE &&
 335                     size != I2C_SMBUS_PROC_CALL)
 336                         return 0;
 337
 338                 switch (size) {
 339                 case I2C_SMBUS_BYTE:
 340                 case I2C_SMBUS_BYTE_DATA:
 341                         data->byte = dma_buffer[0];
 342                         break;
 343                 case I2C_SMBUS_WORD_DATA:
 344                 case I2C_SMBUS_PROC_CALL:
 345                         data->word = dma_buffer[0] | (dma_buffer[1] << 8);
 346                         break;
 347                 case I2C_SMBUS_BLOCK_DATA:
 348                         if (desc->rxbytes != dma_buffer[0] + 1)
 349                                 return -EMSGSIZE;
 350
 351                         memcpy(data->block, dma_buffer, desc->rxbytes);
 352                         break;
 353                 case I2C_SMBUS_I2C_BLOCK_DATA:
 354                         memcpy(&data->block[1], dma_buffer, desc->rxbytes);
 355                         data->block[0] = desc->rxbytes;
 356                         break;
 357                 }
 358                 return 0;
 359         }
 360
 361         if (likely(desc->status & ISMT_DESC_NAK))
 362                 return -ENXIO;
 363
 364         if (desc->status & ISMT_DESC_CRC)
 365                 return -EBADMSG;
 366
 367         if (desc->status & ISMT_DESC_COL)
 368                 return -EAGAIN;
 369
 370         if (desc->status & ISMT_DESC_LPR)
 371                 return -EPROTO;
 372
 373         if (desc->status & (ISMT_DESC_DLTO | ISMT_DESC_CLTO))
 374                 return -ETIMEDOUT;
 375
 376         return -EIO;
 377 }
 378
 379 /**
 380  * ismt_access() - process an SMBus command
 381  * @adap: the i2c host adapter
 382  * @addr: address of the i2c/SMBus target
 383  * @flags: command options
 384  * @read_write: read from or write to device
 385  * @command: the i2c/SMBus command to issue
 386  * @size: SMBus transaction type
 387  * @data: read/write data buffer
 388  */
 389 static int ismt_access(struct i2c_adapter *adap, u16 addr,
 390                        unsigned short flags, char read_write, u8 command,
 391                        int size, union i2c_smbus_data *data)
 392 {
 393         int ret;
 394         unsigned long time_left;
 395         dma_addr_t dma_addr = 0; /* address of the data buffer */
 396         u8 dma_size = 0;
 397         enum dma_data_direction dma_direction = 0;
 398         struct ismt_desc *desc;
 399         struct ismt_priv *priv = i2c_get_adapdata(adap);
 400         struct device *dev = &priv->pci_dev->dev;
 401         u8 *dma_buffer = PTR_ALIGN(&priv->buffer[0], 16);
 402
 403         desc = &priv->hw[priv->head];
 404
 405         /* Initialize the DMA buffer */
 406         memset(priv->buffer, 0, sizeof(priv->buffer));
 407
 408         /* Initialize the descriptor */
 409         memset(desc, 0, sizeof(struct ismt_desc));
 410         desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, read_write);
 411
 412         /* Always clear the log entries */
 413         memset(priv->log, 0, ISMT_LOG_ENTRIES * sizeof(u32));
 414
 415         /* Initialize common control bits */
 416         if (likely(pci_dev_msi_enabled(priv->pci_dev)))
 417                 desc->control = ISMT_DESC_INT | ISMT_DESC_FAIR;
 418         else
 419                 desc->control = ISMT_DESC_FAIR;
 420
 421         if ((flags & I2C_CLIENT_PEC) && (size != I2C_SMBUS_QUICK)
 422             && (size != I2C_SMBUS_I2C_BLOCK_DATA))
 423                 desc->control |= ISMT_DESC_PEC;
 424
 425         switch (size) {
 426         case I2C_SMBUS_QUICK:
 427                 dev_dbg(dev, "I2C_SMBUS_QUICK\n");
 428                 break;
 429
 430         case I2C_SMBUS_BYTE:
 431                 if (read_write == I2C_SMBUS_WRITE) {
 432                         /*
 433                          * Send Byte
 434                          * The command field contains the write data
 435                          */
 436                         dev_dbg(dev, "I2C_SMBUS_BYTE:  WRITE\n");
 437                         desc->control |= ISMT_DESC_CWRL;
 438                         desc->wr_len_cmd = command;
 439                 } else {
 440                         /* Receive Byte */
 441                         dev_dbg(dev, "I2C_SMBUS_BYTE:  READ\n");
 442                         dma_size = 1;
 443                         dma_direction = DMA_FROM_DEVICE;
 444                         desc->rd_len = 1;
 445                 }
 446                 break;
 447
 448         case I2C_SMBUS_BYTE_DATA:
 449                 if (read_write == I2C_SMBUS_WRITE) {
 450                         /*
 451                          * Write Byte
 452                          * Command plus 1 data byte
 453                          */
 454                         dev_dbg(dev, "I2C_SMBUS_BYTE_DATA:  WRITE\n");
 455                         desc->wr_len_cmd = 2;
 456                         dma_size = 2;
 457                         dma_direction = DMA_TO_DEVICE;
 458                         dma_buffer[0] = command;
 459                         dma_buffer[1] = data->byte;
 460                 } else {
 461                         /* Read Byte */
 462                         dev_dbg(dev, "I2C_SMBUS_BYTE_DATA:  READ\n");
 463                         desc->control |= ISMT_DESC_CWRL;
 464                         desc->wr_len_cmd = command;
 465                         desc->rd_len = 1;
 466                         dma_size = 1;
 467                         dma_direction = DMA_FROM_DEVICE;
 468                 }
 469                 break;
 470
 471         case I2C_SMBUS_WORD_DATA:
 472                 if (read_write == I2C_SMBUS_WRITE) {
 473                         /* Write Word */
 474                         dev_dbg(dev, "I2C_SMBUS_WORD_DATA:  WRITE\n");
 475                         desc->wr_len_cmd = 3;
 476                         dma_size = 3;
 477                         dma_direction = DMA_TO_DEVICE;
 478                         dma_buffer[0] = command;
 479                         dma_buffer[1] = data->word & 0xff;
 480                         dma_buffer[2] = data->word >> 8;
 481                 } else {
 482                         /* Read Word */
 483                         dev_dbg(dev, "I2C_SMBUS_WORD_DATA:  READ\n");
 484                         desc->wr_len_cmd = command;
 485                         desc->control |= ISMT_DESC_CWRL;
 486                         desc->rd_len = 2;
 487                         dma_size = 2;
 488                         dma_direction = DMA_FROM_DEVICE;
 489                 }
 490                 break;
 491
 492         case I2C_SMBUS_PROC_CALL:
 493                 dev_dbg(dev, "I2C_SMBUS_PROC_CALL\n");
 494                 desc->wr_len_cmd = 3;
 495                 desc->rd_len = 2;
 496                 dma_size = 3;
 497                 dma_direction = DMA_BIDIRECTIONAL;
 498                 dma_buffer[0] = command;
 499                 dma_buffer[1] = data->word & 0xff;
 500                 dma_buffer[2] = data->word >> 8;
 501                 break;
 502
 503         case I2C_SMBUS_BLOCK_DATA:
 504                 if (read_write == I2C_SMBUS_WRITE) {
 505                         /* Block Write */
 506                         dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA:  WRITE\n");
 507                         if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
 508                                 return -EINVAL;
 509
 510                         dma_size = data->block[0] + 1;
 511                         dma_direction = DMA_TO_DEVICE;
 512                         desc->wr_len_cmd = dma_size;
 513                         desc->control |= ISMT_DESC_BLK;
 514                         dma_buffer[0] = command;
 515                         memcpy(&dma_buffer[1], &data->block[1], dma_size - 1);
 516                 } else {
 517                         /* Block Read */
 518                         dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA:  READ\n");
 519                         dma_size = I2C_SMBUS_BLOCK_MAX;
 520                         dma_direction = DMA_FROM_DEVICE;
 521                         desc->rd_len = dma_size;
 522                         desc->wr_len_cmd = command;
 523                         desc->control |= (ISMT_DESC_BLK | ISMT_DESC_CWRL);
 524                 }
 525                 break;
 526
 527         case I2C_SMBUS_I2C_BLOCK_DATA:
 528                 /* Make sure the length is valid */
 529                 if (data->block[0] < 1)
 530                         data->block[0] = 1;
 531
 532                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
 533                         data->block[0] = I2C_SMBUS_BLOCK_MAX;
 534
 535                 if (read_write == I2C_SMBUS_WRITE) {
 536                         /* i2c Block Write */
 537                         dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA:  WRITE\n");
 538                         dma_size = data->block[0] + 1;
 539                         dma_direction = DMA_TO_DEVICE;
 540                         desc->wr_len_cmd = dma_size;
 541                         desc->control |= ISMT_DESC_I2C;
 542                         dma_buffer[0] = command;
 543                         memcpy(&dma_buffer[1], &data->block[1], dma_size - 1);
 544                 } else {
 545                         /* i2c Block Read */
 546                         dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA:  READ\n");
 547                         dma_size = data->block[0];
 548                         dma_direction = DMA_FROM_DEVICE;
 549                         desc->rd_len = dma_size;
 550                         desc->wr_len_cmd = command;
 551                         desc->control |= (ISMT_DESC_I2C | ISMT_DESC_CWRL);
 552                         /*
 553                          * Per the "Table 15-15. I2C Commands",
 554                          * in the External Design Specification (EDS),
 555                          * (Document Number: 508084, Revision: 2.0),
 556                          * the _rw bit must be 0
 557                          */
 558                         desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, 0);
 559                 }
 560                 break;
 561
 562         default:
 563                 dev_err(dev, "Unsupported transaction %d\n",
 564                         size);
 565                 return -EOPNOTSUPP;
 566         }
 567
 568         /* map the data buffer */
 569         if (dma_size != 0) {
 570                 dev_dbg(dev, " dev=%p\n", dev);
 571                 dev_dbg(dev, " data=%p\n", data);
 572                 dev_dbg(dev, " dma_buffer=%p\n", dma_buffer);
 573                 dev_dbg(dev, " dma_size=%d\n", dma_size);
 574                 dev_dbg(dev, " dma_direction=%d\n", dma_direction);
 575
 576                 dma_addr = dma_map_single(dev,
 577                                       dma_buffer,
 578                                       dma_size,
 579                                       dma_direction);
 580
 581                 if (dma_mapping_error(dev, dma_addr)) {
 582                         dev_err(dev, "Error in mapping dma buffer %p\n",
 583                                 dma_buffer);
 584                         return -EIO;
 585                 }
 586
 587                 dev_dbg(dev, " dma_addr = %pad\n", &dma_addr);
 588
 589                 desc->dptr_low = lower_32_bits(dma_addr);
 590                 desc->dptr_high = upper_32_bits(dma_addr);
 591         }
 592
 593         reinit_completion(&priv->cmp);
 594
 595         /* Add the descriptor */
 596         ismt_submit_desc(priv);
 597
 598         /* Now we wait for interrupt completion, 1s */
 599         time_left = wait_for_completion_timeout(&priv->cmp, HZ*1);
 600
 601         /* unmap the data buffer */
 602         if (dma_size != 0)
 603                 dma_unmap_single(dev, dma_addr, dma_size, dma_direction);
 604
 605         if (unlikely(!time_left)) {
 606                 dev_err(dev, "completion wait timed out\n");
 607                 ret = -ETIMEDOUT;
 608                 goto out;
 609         }
 610
 611         /* do any post processing of the descriptor here */
 612         ret = ismt_process_desc(desc, data, priv, size, read_write);
 613
 614 out:
 615         /* Update the ring pointer */
 616         priv->head++;
 617         priv->head %= ISMT_DESC_ENTRIES;
 618
 619         return ret;
 620 }
 621
 622 /**
 623  * ismt_func() - report which i2c commands are supported by this adapter
 624  * @adap: the i2c host adapter
 625  */
 626 static u32 ismt_func(struct i2c_adapter *adap)
 627 {
 628         return I2C_FUNC_SMBUS_QUICK             |
 629                I2C_FUNC_SMBUS_BYTE              |
 630                I2C_FUNC_SMBUS_BYTE_DATA         |
 631                I2C_FUNC_SMBUS_WORD_DATA         |
 632                I2C_FUNC_SMBUS_PROC_CALL         |
 633                I2C_FUNC_SMBUS_BLOCK_DATA        |
 634                I2C_FUNC_SMBUS_I2C_BLOCK         |
 635                I2C_FUNC_SMBUS_PEC;
 636 }
 637
 638 /**
 639  * smbus_algorithm - the adapter algorithm and supported functionality
 640  * @smbus_xfer: the adapter algorithm
 641  * @functionality: functionality supported by the adapter
 642  */
 643 static const struct i2c_algorithm smbus_algorithm = {
 644         .smbus_xfer     = ismt_access,
 645         .functionality  = ismt_func,
 646 };
 647
 648 /**
 649  * ismt_handle_isr() - interrupt handler bottom half
 650  * @priv: iSMT private data
 651  */
 652 static irqreturn_t ismt_handle_isr(struct ismt_priv *priv)
 653 {
 654         complete(&priv->cmp);
 655
 656         return IRQ_HANDLED;
 657 }
 658
 659
 660 /**
 661  * ismt_do_interrupt() - IRQ interrupt handler
 662  * @vec: interrupt vector
 663  * @data: iSMT private data
 664  */
 665 static irqreturn_t ismt_do_interrupt(int vec, void *data)
 666 {
 667         u32 val;
 668         struct ismt_priv *priv = data;
 669
 670         /*
 671          * check to see it's our interrupt, return IRQ_NONE if not ours
 672          * since we are sharing interrupt
 673          */
 674         val = readl(priv->smba + ISMT_MSTR_MSTS);
 675
 676         if (!(val & (ISMT_MSTS_MIS | ISMT_MSTS_MEIS)))
 677                 return IRQ_NONE;
 678         else
 679                 writel(val | ISMT_MSTS_MIS | ISMT_MSTS_MEIS,
 680                        priv->smba + ISMT_MSTR_MSTS);
 681
 682         return ismt_handle_isr(priv);
 683 }
 684
 685 /**
 686  * ismt_do_msi_interrupt() - MSI interrupt handler
 687  * @vec: interrupt vector
 688  * @data: iSMT private data
 689  */
 690 static irqreturn_t ismt_do_msi_interrupt(int vec, void *data)
 691 {
 692         return ismt_handle_isr(data);
 693 }
 694
 695 /**
 696  * ismt_hw_init() - initialize the iSMT hardware
 697  * @priv: iSMT private data
 698  */
 699 static void ismt_hw_init(struct ismt_priv *priv)
 700 {
 701         u32 val;
 702         struct device *dev = &priv->pci_dev->dev;
 703
 704         /* initialize the Master Descriptor Base Address (MDBA) */
 705         writeq(priv->io_rng_dma, priv->smba + ISMT_MSTR_MDBA);
 706
 707         writeq(priv->log_dma, priv->smba + ISMT_GR_SMTICL);
 708
 709         /* initialize the Master Control Register (MCTRL) */
 710         writel(ISMT_MCTRL_MEIE, priv->smba + ISMT_MSTR_MCTRL);
 711
 712         /* initialize the Master Status Register (MSTS) */
 713         writel(0, priv->smba + ISMT_MSTR_MSTS);
 714
 715         /* initialize the Master Descriptor Size (MDS) */
 716         val = readl(priv->smba + ISMT_MSTR_MDS);
 717         writel((val & ~ISMT_MDS_MASK) | (ISMT_DESC_ENTRIES - 1),
 718                 priv->smba + ISMT_MSTR_MDS);
 719
 720         /*
 721          * Set the SMBus speed (could use this for slow HW debuggers)
 722          */
 723
 724         val = readl(priv->smba + ISMT_SPGT);
 725
 726         switch (bus_speed) {
 727         case 0:
 728                 break;
 729
 730         case 80:
 731                 dev_dbg(dev, "Setting SMBus clock to 80 kHz\n");
 732                 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_80K),
 733                         priv->smba + ISMT_SPGT);
 734                 break;
 735
 736         case 100:
 737                 dev_dbg(dev, "Setting SMBus clock to 100 kHz\n");
 738                 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_100K),
 739                         priv->smba + ISMT_SPGT);
 740                 break;
 741
 742         case 400:
 743                 dev_dbg(dev, "Setting SMBus clock to 400 kHz\n");
 744                 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_400K),
 745                         priv->smba + ISMT_SPGT);
 746                 break;
 747
 748         case 1000:
 749                 dev_dbg(dev, "Setting SMBus clock to 1000 kHz\n");
 750                 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_1M),
 751                         priv->smba + ISMT_SPGT);
 752                 break;
 753
 754         default:
 755                 dev_warn(dev, "Invalid SMBus clock speed, only 0, 80, 100, 400, and 1000 are valid\n");
 756                 break;
 757         }
 758
 759         val = readl(priv->smba + ISMT_SPGT);
 760
 761         switch (val & ISMT_SPGT_SPD_MASK) {
 762         case ISMT_SPGT_SPD_80K:
 763                 bus_speed = 80;
 764                 break;
 765         case ISMT_SPGT_SPD_100K:
 766                 bus_speed = 100;
 767                 break;
 768         case ISMT_SPGT_SPD_400K:
 769                 bus_speed = 400;
 770                 break;
 771         case ISMT_SPGT_SPD_1M:
 772                 bus_speed = 1000;
 773                 break;
 774         }
 775         dev_dbg(dev, "SMBus clock is running at %d kHz\n", bus_speed);
 776 }
 777
 778 /**
 779  * ismt_dev_init() - initialize the iSMT data structures
 780  * @priv: iSMT private data
 781  */
 782 static int ismt_dev_init(struct ismt_priv *priv)
 783 {
 784         /* allocate memory for the descriptor */
 785         priv->hw = dmam_alloc_coherent(&priv->pci_dev->dev,
 786                                        (ISMT_DESC_ENTRIES
 787                                                * sizeof(struct ismt_desc)),
 788                                        &priv->io_rng_dma,
 789                                        GFP_KERNEL);
 790         if (!priv->hw)
 791                 return -ENOMEM;
 792
 793         memset(priv->hw, 0, (ISMT_DESC_ENTRIES * sizeof(struct ismt_desc)));
 794
 795         priv->head = 0;
 796         init_completion(&priv->cmp);
 797
 798         priv->log = dmam_alloc_coherent(&priv->pci_dev->dev,
 799                                         ISMT_LOG_ENTRIES * sizeof(u32),
 800                                         &priv->log_dma, GFP_KERNEL);
 801         if (!priv->log)
 802                 return -ENOMEM;
 803
 804         return 0;
 805 }
 806
 807 /**
 808  * ismt_int_init() - initialize interrupts
 809  * @priv: iSMT private data
 810  */
 811 static int ismt_int_init(struct ismt_priv *priv)
 812 {
 813         int err;
 814
 815         /* Try using MSI interrupts */
 816         err = pci_enable_msi(priv->pci_dev);
 817         if (err)
 818                 goto intx;
 819
 820         err = devm_request_irq(&priv->pci_dev->dev,
 821                                priv->pci_dev->irq,
 822                                ismt_do_msi_interrupt,
 823                                0,
 824                                "ismt-msi",
 825                                priv);
 826         if (err) {
 827                 pci_disable_msi(priv->pci_dev);
 828                 goto intx;
 829         }
 830
 831         return 0;
 832
 833         /* Try using legacy interrupts */
 834 intx:
 835         dev_warn(&priv->pci_dev->dev,
 836                  "Unable to use MSI interrupts, falling back to legacy\n");
 837
 838         err = devm_request_irq(&priv->pci_dev->dev,
 839                                priv->pci_dev->irq,
 840                                ismt_do_interrupt,
 841                                IRQF_SHARED,
 842                                "ismt-intx",
 843                                priv);
 844         if (err) {
 845                 dev_err(&priv->pci_dev->dev, "no usable interrupts\n");
 846                 return err;
 847         }
 848
 849         return 0;
 850 }
 851
 852 static struct pci_driver ismt_driver;
 853
 854 /**
 855  * ismt_probe() - probe for iSMT devices
 856  * @pdev: PCI-Express device
 857  * @id: PCI-Express device ID
 858  */
 859 static int
 860 ismt_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 861 {
 862         int err;
 863         struct ismt_priv *priv;
 864         unsigned long start, len;
 865
 866         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 867         if (!priv)
 868                 return -ENOMEM;
 869
 870         pci_set_drvdata(pdev, priv);
 871
 872         i2c_set_adapdata(&priv->adapter, priv);
 873         priv->adapter.owner = THIS_MODULE;
 874         priv->adapter.class = I2C_CLASS_HWMON;
 875         priv->adapter.algo = &smbus_algorithm;
 876         priv->adapter.dev.parent = &pdev->dev;
 877         ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&pdev->dev));
 878         priv->adapter.retries = ISMT_MAX_RETRIES;
 879
 880         priv->pci_dev = pdev;
 881
 882         err = pcim_enable_device(pdev);
 883         if (err) {
 884                 dev_err(&pdev->dev, "Failed to enable SMBus PCI device (%d)\n",
 885                         err);
 886                 return err;
 887         }
 888
 889         /* enable bus mastering */
 890         pci_set_master(pdev);
 891
 892         /* Determine the address of the SMBus area */
 893         start = pci_resource_start(pdev, SMBBAR);
 894         len = pci_resource_len(pdev, SMBBAR);
 895         if (!start || !len) {
 896                 dev_err(&pdev->dev,
 897                         "SMBus base address uninitialized, upgrade BIOS\n");
 898                 return -ENODEV;
 899         }
 900
 901         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
 902                  "SMBus iSMT adapter at %lx", start);
 903
 904         dev_dbg(&priv->pci_dev->dev, " start=0x%lX\n", start);
 905         dev_dbg(&priv->pci_dev->dev, " len=0x%lX\n", len);
 906
 907         err = acpi_check_resource_conflict(&pdev->resource[SMBBAR]);
 908         if (err) {
 909                 dev_err(&pdev->dev, "ACPI resource conflict!\n");
 910                 return err;
 911         }
 912
 913         err = pci_request_region(pdev, SMBBAR, ismt_driver.name);
 914         if (err) {
 915                 dev_err(&pdev->dev,
 916                         "Failed to request SMBus region 0x%lx-0x%lx\n",
 917                         start, start + len);
 918                 return err;
 919         }
 920
 921         priv->smba = pcim_iomap(pdev, SMBBAR, len);
 922         if (!priv->smba) {
 923                 dev_err(&pdev->dev, "Unable to ioremap SMBus BAR\n");
 924                 return -ENODEV;
 925         }
 926
 927         if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) ||
 928             (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) {
 929                 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
 930                     (pci_set_consistent_dma_mask(pdev,
 931                                                  DMA_BIT_MASK(32)) != 0)) {
 932                         dev_err(&pdev->dev, "pci_set_dma_mask fail %p\n",
 933                                 pdev);
 934                         return -ENODEV;
 935                 }
 936         }
 937
 938         err = ismt_dev_init(priv);
 939         if (err)
 940                 return err;
 941
 942         ismt_hw_init(priv);
 943
 944         err = ismt_int_init(priv);
 945         if (err)
 946                 return err;
 947
 948         err = i2c_add_adapter(&priv->adapter);
 949         if (err)
 950                 return -ENODEV;
 951         return 0;
 952 }
 953
 954 /**
 955  * ismt_remove() - release driver resources
 956  * @pdev: PCI-Express device
 957  */
 958 static void ismt_remove(struct pci_dev *pdev)
 959 {
 960         struct ismt_priv *priv = pci_get_drvdata(pdev);
 961
 962         i2c_del_adapter(&priv->adapter);
 963 }
 964
 965 static struct pci_driver ismt_driver = {
 966         .name = "ismt_smbus",
 967         .id_table = ismt_ids,
 968         .probe = ismt_probe,
 969         .remove = ismt_remove,
 970 };
 971
 972 module_pci_driver(ismt_driver);
 973
 974 MODULE_LICENSE("Dual BSD/GPL");
 975 MODULE_AUTHOR("Bill E. Brown <bill.e.brown@intel.com>");
 976 MODULE_DESCRIPTION("Intel SMBus Message Transport (iSMT) driver");