drivers/i2c/busses/i2c-ismt.c

   1 /*
   2  * This file is provided under a dual BSD/GPLv2 license.  When using or
   3  * redistributing this file, you may do so under either license.
   4  *
   5  * Copyright(c) 2012 Intel Corporation. All rights reserved.
   6  *
   7  * GPL LICENSE SUMMARY
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of version 2 of the GNU General Public License as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  * The full GNU General Public License is included in this distribution
  18  * in the file called LICENSE.GPL.
  19  *
  20  * BSD LICENSE
  21  *
  22  * Redistribution and use in source and binary forms, with or without
  23  * modification, are permitted provided that the following conditions
  24  * are met:
  25  *
  26  *   * Redistributions of source code must retain the above copyright
  27  *     notice, this list of conditions and the following disclaimer.
  28  *   * Redistributions in binary form must reproduce the above copyright
  29  *     notice, this list of conditions and the following disclaimer in
  30  *     the documentation and/or other materials provided with the
  31  *     distribution.
  32  *   * Neither the name of Intel Corporation nor the names of its
  33  *     contributors may be used to endorse or promote products derived
  34  *     from this software without specific prior written permission.
  35  *
  36  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  37  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  38  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  39  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  40  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  41  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  42  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  43  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  44  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  45  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  46  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  47  */
  48
  49 /*
  50  *  Supports the SMBus Message Transport (SMT) in the Intel Atom Processor
  51  *  S12xx Product Family.
  52  *
  53  *  Features supported by this driver:
  54  *  Hardware PEC                     yes
  55  *  Block buffer                     yes
  56  *  Block process call transaction   no
  57  *  Slave mode                       no
  58  */
  59
  60 #include <linux/module.h>
  61 #include <linux/pci.h>
  62 #include <linux/kernel.h>
  63 #include <linux/stddef.h>
  64 #include <linux/completion.h>
  65 #include <linux/dma-mapping.h>
  66 #include <linux/i2c.h>
  67 #include <linux/acpi.h>
  68 #include <linux/interrupt.h>
  69
  70 #include <linux/io-64-nonatomic-lo-hi.h>
  71
  72 /* PCI Address Constants */
  73 #define SMBBAR          0
  74
  75 /* PCI DIDs for the Intel SMBus Message Transport (SMT) Devices */
  76 #define PCI_DEVICE_ID_INTEL_S1200_SMT0  0x0c59
  77 #define PCI_DEVICE_ID_INTEL_S1200_SMT1  0x0c5a
  78 #define PCI_DEVICE_ID_INTEL_DNV_SMT     0x19ac
  79 #define PCI_DEVICE_ID_INTEL_AVOTON_SMT  0x1f15
  80
  81 #define ISMT_DESC_ENTRIES       2       /* number of descriptor entries */
  82 #define ISMT_MAX_RETRIES        3       /* number of SMBus retries to attempt */
  83
  84 /* Hardware Descriptor Constants - Control Field */
  85 #define ISMT_DESC_CWRL  0x01    /* Command/Write Length */
  86 #define ISMT_DESC_BLK   0X04    /* Perform Block Transaction */
  87 #define ISMT_DESC_FAIR  0x08    /* Set fairness flag upon successful arbit. */
  88 #define ISMT_DESC_PEC   0x10    /* Packet Error Code */
  89 #define ISMT_DESC_I2C   0x20    /* I2C Enable */
  90 #define ISMT_DESC_INT   0x40    /* Interrupt */
  91 #define ISMT_DESC_SOE   0x80    /* Stop On Error */
  92
  93 /* Hardware Descriptor Constants - Status Field */
  94 #define ISMT_DESC_SCS   0x01    /* Success */
  95 #define ISMT_DESC_DLTO  0x04    /* Data Low Time Out */
  96 #define ISMT_DESC_NAK   0x08    /* NAK Received */
  97 #define ISMT_DESC_CRC   0x10    /* CRC Error */
  98 #define ISMT_DESC_CLTO  0x20    /* Clock Low Time Out */
  99 #define ISMT_DESC_COL   0x40    /* Collisions */
 100 #define ISMT_DESC_LPR   0x80    /* Large Packet Received */
 101
 102 /* Macros */
 103 #define ISMT_DESC_ADDR_RW(addr, rw) (((addr) << 1) | (rw))
 104
 105 /* iSMT General Register address offsets (SMBBAR + <addr>) */
 106 #define ISMT_GR_GCTRL           0x000   /* General Control */
 107 #define ISMT_GR_SMTICL          0x008   /* SMT Interrupt Cause Location */
 108 #define ISMT_GR_ERRINTMSK       0x010   /* Error Interrupt Mask */
 109 #define ISMT_GR_ERRAERMSK       0x014   /* Error AER Mask */
 110 #define ISMT_GR_ERRSTS          0x018   /* Error Status */
 111 #define ISMT_GR_ERRINFO         0x01c   /* Error Information */
 112
 113 /* iSMT Master Registers */
 114 #define ISMT_MSTR_MDBA          0x100   /* Master Descriptor Base Address */
 115 #define ISMT_MSTR_MCTRL         0x108   /* Master Control */
 116 #define ISMT_MSTR_MSTS          0x10c   /* Master Status */
 117 #define ISMT_MSTR_MDS           0x110   /* Master Descriptor Size */
 118 #define ISMT_MSTR_RPOLICY       0x114   /* Retry Policy */
 119
 120 /* iSMT Miscellaneous Registers */
 121 #define ISMT_SPGT       0x300   /* SMBus PHY Global Timing */
 122
 123 /* General Control Register (GCTRL) bit definitions */
 124 #define ISMT_GCTRL_TRST 0x04    /* Target Reset */
 125 #define ISMT_GCTRL_KILL 0x08    /* Kill */
 126 #define ISMT_GCTRL_SRST 0x40    /* Soft Reset */
 127
 128 /* Master Control Register (MCTRL) bit definitions */
 129 #define ISMT_MCTRL_SS   0x01            /* Start/Stop */
 130 #define ISMT_MCTRL_MEIE 0x10            /* Master Error Interrupt Enable */
 131 #define ISMT_MCTRL_FMHP 0x00ff0000      /* Firmware Master Head Ptr (FMHP) */
 132
 133 /* Master Status Register (MSTS) bit definitions */
 134 #define ISMT_MSTS_HMTP  0xff0000        /* HW Master Tail Pointer (HMTP) */
 135 #define ISMT_MSTS_MIS   0x20            /* Master Interrupt Status (MIS) */
 136 #define ISMT_MSTS_MEIS  0x10            /* Master Error Int Status (MEIS) */
 137 #define ISMT_MSTS_IP    0x01            /* In Progress */
 138
 139 /* Master Descriptor Size (MDS) bit definitions */
 140 #define ISMT_MDS_MASK   0xff    /* Master Descriptor Size mask (MDS) */
 141
 142 /* SMBus PHY Global Timing Register (SPGT) bit definitions */
 143 #define ISMT_SPGT_SPD_MASK      0xc0000000      /* SMBus Speed mask */
 144 #define ISMT_SPGT_SPD_80K       0x00            /* 80 kHz */
 145 #define ISMT_SPGT_SPD_100K      (0x1 << 30)     /* 100 kHz */
 146 #define ISMT_SPGT_SPD_400K      (0x2 << 30)     /* 400 kHz */
 147 #define ISMT_SPGT_SPD_1M        (0x3 << 30)     /* 1 MHz */
 148
 149
 150 /* MSI Control Register (MSICTL) bit definitions */
 151 #define ISMT_MSICTL_MSIE        0x01    /* MSI Enable */
 152
 153 /* iSMT Hardware Descriptor */
 154 struct ismt_desc {
 155         u8 tgtaddr_rw;  /* target address & r/w bit */
 156         u8 wr_len_cmd;  /* write length in bytes or a command */
 157         u8 rd_len;      /* read length */
 158         u8 control;     /* control bits */
 159         u8 status;      /* status bits */
 160         u8 retry;       /* collision retry and retry count */
 161         u8 rxbytes;     /* received bytes */
 162         u8 txbytes;     /* transmitted bytes */
 163         u32 dptr_low;   /* lower 32 bit of the data pointer */
 164         u32 dptr_high;  /* upper 32 bit of the data pointer */
 165 } __packed;
 166
 167 struct ismt_priv {
 168         struct i2c_adapter adapter;
 169         void __iomem *smba;                     /* PCI BAR */
 170         struct pci_dev *pci_dev;
 171         struct ismt_desc *hw;                   /* descriptor virt base addr */
 172         dma_addr_t io_rng_dma;                  /* descriptor HW base addr */
 173         u8 head;                                /* ring buffer head pointer */
 174         struct completion cmp;                  /* interrupt completion */
 175         u8 dma_buffer[I2C_SMBUS_BLOCK_MAX + 1]; /* temp R/W data buffer */
 176 };
 177
 178 /**
 179  * ismt_ids - PCI device IDs supported by this driver
 180  */
 181 static const struct pci_device_id ismt_ids[] = {
 182         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT0) },
 183         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT1) },
 184         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMT) },
 185         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMT) },
 186         { 0, }
 187 };
 188
 189 MODULE_DEVICE_TABLE(pci, ismt_ids);
 190
 191 /* Bus speed control bits for slow debuggers - refer to the docs for usage */
 192 static unsigned int bus_speed;
 193 module_param(bus_speed, uint, S_IRUGO);
 194 MODULE_PARM_DESC(bus_speed, "Bus Speed in kHz (0 = BIOS default)");
 195
 196 /**
 197  * __ismt_desc_dump() - dump the contents of a specific descriptor
 198  */
 199 static void __ismt_desc_dump(struct device *dev, const struct ismt_desc *desc)
 200 {
 201
 202         dev_dbg(dev, "Descriptor struct:  %p\n", desc);
 203         dev_dbg(dev, "\ttgtaddr_rw=0x%02X\n", desc->tgtaddr_rw);
 204         dev_dbg(dev, "\twr_len_cmd=0x%02X\n", desc->wr_len_cmd);
 205         dev_dbg(dev, "\trd_len=    0x%02X\n", desc->rd_len);
 206         dev_dbg(dev, "\tcontrol=   0x%02X\n", desc->control);
 207         dev_dbg(dev, "\tstatus=    0x%02X\n", desc->status);
 208         dev_dbg(dev, "\tretry=     0x%02X\n", desc->retry);
 209         dev_dbg(dev, "\trxbytes=   0x%02X\n", desc->rxbytes);
 210         dev_dbg(dev, "\ttxbytes=   0x%02X\n", desc->txbytes);
 211         dev_dbg(dev, "\tdptr_low=  0x%08X\n", desc->dptr_low);
 212         dev_dbg(dev, "\tdptr_high= 0x%08X\n", desc->dptr_high);
 213 }
 214 /**
 215  * ismt_desc_dump() - dump the contents of a descriptor for debug purposes
 216  * @priv: iSMT private data
 217  */
 218 static void ismt_desc_dump(struct ismt_priv *priv)
 219 {
 220         struct device *dev = &priv->pci_dev->dev;
 221         struct ismt_desc *desc = &priv->hw[priv->head];
 222
 223         dev_dbg(dev, "Dump of the descriptor struct:  0x%X\n", priv->head);
 224         __ismt_desc_dump(dev, desc);
 225 }
 226
 227 /**
 228  * ismt_gen_reg_dump() - dump the iSMT General Registers
 229  * @priv: iSMT private data
 230  */
 231 static void ismt_gen_reg_dump(struct ismt_priv *priv)
 232 {
 233         struct device *dev = &priv->pci_dev->dev;
 234
 235         dev_dbg(dev, "Dump of the iSMT General Registers\n");
 236         dev_dbg(dev, "  GCTRL.... : (0x%p)=0x%X\n",
 237                 priv->smba + ISMT_GR_GCTRL,
 238                 readl(priv->smba + ISMT_GR_GCTRL));
 239         dev_dbg(dev, "  SMTICL... : (0x%p)=0x%016llX\n",
 240                 priv->smba + ISMT_GR_SMTICL,
 241                 (long long unsigned int)readq(priv->smba + ISMT_GR_SMTICL));
 242         dev_dbg(dev, "  ERRINTMSK : (0x%p)=0x%X\n",
 243                 priv->smba + ISMT_GR_ERRINTMSK,
 244                 readl(priv->smba + ISMT_GR_ERRINTMSK));
 245         dev_dbg(dev, "  ERRAERMSK : (0x%p)=0x%X\n",
 246                 priv->smba + ISMT_GR_ERRAERMSK,
 247                 readl(priv->smba + ISMT_GR_ERRAERMSK));
 248         dev_dbg(dev, "  ERRSTS... : (0x%p)=0x%X\n",
 249                 priv->smba + ISMT_GR_ERRSTS,
 250                 readl(priv->smba + ISMT_GR_ERRSTS));
 251         dev_dbg(dev, "  ERRINFO.. : (0x%p)=0x%X\n",
 252                 priv->smba + ISMT_GR_ERRINFO,
 253                 readl(priv->smba + ISMT_GR_ERRINFO));
 254 }
 255
 256 /**
 257  * ismt_mstr_reg_dump() - dump the iSMT Master Registers
 258  * @priv: iSMT private data
 259  */
 260 static void ismt_mstr_reg_dump(struct ismt_priv *priv)
 261 {
 262         struct device *dev = &priv->pci_dev->dev;
 263
 264         dev_dbg(dev, "Dump of the iSMT Master Registers\n");
 265         dev_dbg(dev, "  MDBA..... : (0x%p)=0x%016llX\n",
 266                 priv->smba + ISMT_MSTR_MDBA,
 267                 (long long unsigned int)readq(priv->smba + ISMT_MSTR_MDBA));
 268         dev_dbg(dev, "  MCTRL.... : (0x%p)=0x%X\n",
 269                 priv->smba + ISMT_MSTR_MCTRL,
 270                 readl(priv->smba + ISMT_MSTR_MCTRL));
 271         dev_dbg(dev, "  MSTS..... : (0x%p)=0x%X\n",
 272                 priv->smba + ISMT_MSTR_MSTS,
 273                 readl(priv->smba + ISMT_MSTR_MSTS));
 274         dev_dbg(dev, "  MDS...... : (0x%p)=0x%X\n",
 275                 priv->smba + ISMT_MSTR_MDS,
 276                 readl(priv->smba + ISMT_MSTR_MDS));
 277         dev_dbg(dev, "  RPOLICY.. : (0x%p)=0x%X\n",
 278                 priv->smba + ISMT_MSTR_RPOLICY,
 279                 readl(priv->smba + ISMT_MSTR_RPOLICY));
 280         dev_dbg(dev, "  SPGT..... : (0x%p)=0x%X\n",
 281                 priv->smba + ISMT_SPGT,
 282                 readl(priv->smba + ISMT_SPGT));
 283 }
 284
 285 /**
 286  * ismt_submit_desc() - add a descriptor to the ring
 287  * @priv: iSMT private data
 288  */
 289 static void ismt_submit_desc(struct ismt_priv *priv)
 290 {
 291         uint fmhp;
 292         uint val;
 293
 294         ismt_desc_dump(priv);
 295         ismt_gen_reg_dump(priv);
 296         ismt_mstr_reg_dump(priv);
 297
 298         /* Set the FMHP (Firmware Master Head Pointer)*/
 299         fmhp = ((priv->head + 1) % ISMT_DESC_ENTRIES) << 16;
 300         val = readl(priv->smba + ISMT_MSTR_MCTRL);
 301         writel((val & ~ISMT_MCTRL_FMHP) | fmhp,
 302                priv->smba + ISMT_MSTR_MCTRL);
 303
 304         /* Set the start bit */
 305         val = readl(priv->smba + ISMT_MSTR_MCTRL);
 306         writel(val | ISMT_MCTRL_SS,
 307                priv->smba + ISMT_MSTR_MCTRL);
 308 }
 309
 310 /**
 311  * ismt_process_desc() - handle the completion of the descriptor
 312  * @desc: the iSMT hardware descriptor
 313  * @data: data buffer from the upper layer
 314  * @priv: ismt_priv struct holding our dma buffer
 315  * @size: SMBus transaction type
 316  * @read_write: flag to indicate if this is a read or write
 317  */
 318 static int ismt_process_desc(const struct ismt_desc *desc,
 319                              union i2c_smbus_data *data,
 320                              struct ismt_priv *priv, int size,
 321                              char read_write)
 322 {
 323         u8 *dma_buffer = priv->dma_buffer;
 324
 325         dev_dbg(&priv->pci_dev->dev, "Processing completed descriptor\n");
 326         __ismt_desc_dump(&priv->pci_dev->dev, desc);
 327
 328         if (desc->status & ISMT_DESC_SCS) {
 329                 if (read_write == I2C_SMBUS_WRITE &&
 330                     size != I2C_SMBUS_PROC_CALL)
 331                         return 0;
 332
 333                 switch (size) {
 334                 case I2C_SMBUS_BYTE:
 335                 case I2C_SMBUS_BYTE_DATA:
 336                         data->byte = dma_buffer[0];
 337                         break;
 338                 case I2C_SMBUS_WORD_DATA:
 339                 case I2C_SMBUS_PROC_CALL:
 340                         data->word = dma_buffer[0] | (dma_buffer[1] << 8);
 341                         break;
 342                 case I2C_SMBUS_BLOCK_DATA:
 343                         if (desc->rxbytes != dma_buffer[0] + 1)
 344                                 return -EMSGSIZE;
 345
 346                         memcpy(data->block, dma_buffer, desc->rxbytes);
 347                         break;
 348                 case I2C_SMBUS_I2C_BLOCK_DATA:
 349                         memcpy(&data->block[1], dma_buffer, desc->rxbytes);
 350                         data->block[0] = desc->rxbytes;
 351                         break;
 352                 }
 353                 return 0;
 354         }
 355
 356         if (likely(desc->status & ISMT_DESC_NAK))
 357                 return -ENXIO;
 358
 359         if (desc->status & ISMT_DESC_CRC)
 360                 return -EBADMSG;
 361
 362         if (desc->status & ISMT_DESC_COL)
 363                 return -EAGAIN;
 364
 365         if (desc->status & ISMT_DESC_LPR)
 366                 return -EPROTO;
 367
 368         if (desc->status & (ISMT_DESC_DLTO | ISMT_DESC_CLTO))
 369                 return -ETIMEDOUT;
 370
 371         return -EIO;
 372 }
 373
 374 /**
 375  * ismt_access() - process an SMBus command
 376  * @adap: the i2c host adapter
 377  * @addr: address of the i2c/SMBus target
 378  * @flags: command options
 379  * @read_write: read from or write to device
 380  * @command: the i2c/SMBus command to issue
 381  * @size: SMBus transaction type
 382  * @data: read/write data buffer
 383  */
 384 static int ismt_access(struct i2c_adapter *adap, u16 addr,
 385                        unsigned short flags, char read_write, u8 command,
 386                        int size, union i2c_smbus_data *data)
 387 {
 388         int ret;
 389         unsigned long time_left;
 390         dma_addr_t dma_addr = 0; /* address of the data buffer */
 391         u8 dma_size = 0;
 392         enum dma_data_direction dma_direction = 0;
 393         struct ismt_desc *desc;
 394         struct ismt_priv *priv = i2c_get_adapdata(adap);
 395         struct device *dev = &priv->pci_dev->dev;
 396
 397         desc = &priv->hw[priv->head];
 398
 399         /* Initialize the DMA buffer */
 400         memset(priv->dma_buffer, 0, sizeof(priv->dma_buffer));
 401
 402         /* Initialize the descriptor */
 403         memset(desc, 0, sizeof(struct ismt_desc));
 404         desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, read_write);
 405
 406         /* Initialize common control bits */
 407         if (likely(pci_dev_msi_enabled(priv->pci_dev)))
 408                 desc->control = ISMT_DESC_INT | ISMT_DESC_FAIR;
 409         else
 410                 desc->control = ISMT_DESC_FAIR;
 411
 412         if ((flags & I2C_CLIENT_PEC) && (size != I2C_SMBUS_QUICK)
 413             && (size != I2C_SMBUS_I2C_BLOCK_DATA))
 414                 desc->control |= ISMT_DESC_PEC;
 415
 416         switch (size) {
 417         case I2C_SMBUS_QUICK:
 418                 dev_dbg(dev, "I2C_SMBUS_QUICK\n");
 419                 break;
 420
 421         case I2C_SMBUS_BYTE:
 422                 if (read_write == I2C_SMBUS_WRITE) {
 423                         /*
 424                          * Send Byte
 425                          * The command field contains the write data
 426                          */
 427                         dev_dbg(dev, "I2C_SMBUS_BYTE:  WRITE\n");
 428                         desc->control |= ISMT_DESC_CWRL;
 429                         desc->wr_len_cmd = command;
 430                 } else {
 431                         /* Receive Byte */
 432                         dev_dbg(dev, "I2C_SMBUS_BYTE:  READ\n");
 433                         dma_size = 1;
 434                         dma_direction = DMA_FROM_DEVICE;
 435                         desc->rd_len = 1;
 436                 }
 437                 break;
 438
 439         case I2C_SMBUS_BYTE_DATA:
 440                 if (read_write == I2C_SMBUS_WRITE) {
 441                         /*
 442                          * Write Byte
 443                          * Command plus 1 data byte
 444                          */
 445                         dev_dbg(dev, "I2C_SMBUS_BYTE_DATA:  WRITE\n");
 446                         desc->wr_len_cmd = 2;
 447                         dma_size = 2;
 448                         dma_direction = DMA_TO_DEVICE;
 449                         priv->dma_buffer[0] = command;
 450                         priv->dma_buffer[1] = data->byte;
 451                 } else {
 452                         /* Read Byte */
 453                         dev_dbg(dev, "I2C_SMBUS_BYTE_DATA:  READ\n");
 454                         desc->control |= ISMT_DESC_CWRL;
 455                         desc->wr_len_cmd = command;
 456                         desc->rd_len = 1;
 457                         dma_size = 1;
 458                         dma_direction = DMA_FROM_DEVICE;
 459                 }
 460                 break;
 461
 462         case I2C_SMBUS_WORD_DATA:
 463                 if (read_write == I2C_SMBUS_WRITE) {
 464                         /* Write Word */
 465                         dev_dbg(dev, "I2C_SMBUS_WORD_DATA:  WRITE\n");
 466                         desc->wr_len_cmd = 3;
 467                         dma_size = 3;
 468                         dma_direction = DMA_TO_DEVICE;
 469                         priv->dma_buffer[0] = command;
 470                         priv->dma_buffer[1] = data->word & 0xff;
 471                         priv->dma_buffer[2] = data->word >> 8;
 472                 } else {
 473                         /* Read Word */
 474                         dev_dbg(dev, "I2C_SMBUS_WORD_DATA:  READ\n");
 475                         desc->wr_len_cmd = command;
 476                         desc->control |= ISMT_DESC_CWRL;
 477                         desc->rd_len = 2;
 478                         dma_size = 2;
 479                         dma_direction = DMA_FROM_DEVICE;
 480                 }
 481                 break;
 482
 483         case I2C_SMBUS_PROC_CALL:
 484                 dev_dbg(dev, "I2C_SMBUS_PROC_CALL\n");
 485                 desc->wr_len_cmd = 3;
 486                 desc->rd_len = 2;
 487                 dma_size = 3;
 488                 dma_direction = DMA_BIDIRECTIONAL;
 489                 priv->dma_buffer[0] = command;
 490                 priv->dma_buffer[1] = data->word & 0xff;
 491                 priv->dma_buffer[2] = data->word >> 8;
 492                 break;
 493
 494         case I2C_SMBUS_BLOCK_DATA:
 495                 if (read_write == I2C_SMBUS_WRITE) {
 496                         /* Block Write */
 497                         dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA:  WRITE\n");
 498                         dma_size = data->block[0] + 1;
 499                         dma_direction = DMA_TO_DEVICE;
 500                         desc->wr_len_cmd = dma_size;
 501                         desc->control |= ISMT_DESC_BLK;
 502                         priv->dma_buffer[0] = command;
 503                         memcpy(&priv->dma_buffer[1], &data->block[1], dma_size - 1);
 504                 } else {
 505                         /* Block Read */
 506                         dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA:  READ\n");
 507                         dma_size = I2C_SMBUS_BLOCK_MAX;
 508                         dma_direction = DMA_FROM_DEVICE;
 509                         desc->rd_len = dma_size;
 510                         desc->wr_len_cmd = command;
 511                         desc->control |= (ISMT_DESC_BLK | ISMT_DESC_CWRL);
 512                 }
 513                 break;
 514
 515         case I2C_SMBUS_I2C_BLOCK_DATA:
 516                 /* Make sure the length is valid */
 517                 if (data->block[0] < 1)
 518                         data->block[0] = 1;
 519
 520                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
 521                         data->block[0] = I2C_SMBUS_BLOCK_MAX;
 522
 523                 if (read_write == I2C_SMBUS_WRITE) {
 524                         /* i2c Block Write */
 525                         dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA:  WRITE\n");
 526                         dma_size = data->block[0] + 1;
 527                         dma_direction = DMA_TO_DEVICE;
 528                         desc->wr_len_cmd = dma_size;
 529                         desc->control |= ISMT_DESC_I2C;
 530                         priv->dma_buffer[0] = command;
 531                         memcpy(&priv->dma_buffer[1], &data->block[1], dma_size - 1);
 532                 } else {
 533                         /* i2c Block Read */
 534                         dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA:  READ\n");
 535                         dma_size = data->block[0];
 536                         dma_direction = DMA_FROM_DEVICE;
 537                         desc->rd_len = dma_size;
 538                         desc->wr_len_cmd = command;
 539                         desc->control |= (ISMT_DESC_I2C | ISMT_DESC_CWRL);
 540                         /*
 541                          * Per the "Table 15-15. I2C Commands",
 542                          * in the External Design Specification (EDS),
 543                          * (Document Number: 508084, Revision: 2.0),
 544                          * the _rw bit must be 0
 545                          */
 546                         desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, 0);
 547                 }
 548                 break;
 549
 550         default:
 551                 dev_err(dev, "Unsupported transaction %d\n",
 552                         size);
 553                 return -EOPNOTSUPP;
 554         }
 555
 556         /* map the data buffer */
 557         if (dma_size != 0) {
 558                 dev_dbg(dev, " dev=%p\n", dev);
 559                 dev_dbg(dev, " data=%p\n", data);
 560                 dev_dbg(dev, " dma_buffer=%p\n", priv->dma_buffer);
 561                 dev_dbg(dev, " dma_size=%d\n", dma_size);
 562                 dev_dbg(dev, " dma_direction=%d\n", dma_direction);
 563
 564                 dma_addr = dma_map_single(dev,
 565                                       priv->dma_buffer,
 566                                       dma_size,
 567                                       dma_direction);
 568
 569                 if (dma_mapping_error(dev, dma_addr)) {
 570                         dev_err(dev, "Error in mapping dma buffer %p\n",
 571                                 priv->dma_buffer);
 572                         return -EIO;
 573                 }
 574
 575                 dev_dbg(dev, " dma_addr = 0x%016llX\n",
 576                         (unsigned long long)dma_addr);
 577
 578                 desc->dptr_low = lower_32_bits(dma_addr);
 579                 desc->dptr_high = upper_32_bits(dma_addr);
 580         }
 581
 582         reinit_completion(&priv->cmp);
 583
 584         /* Add the descriptor */
 585         ismt_submit_desc(priv);
 586
 587         /* Now we wait for interrupt completion, 1s */
 588         time_left = wait_for_completion_timeout(&priv->cmp, HZ*1);
 589
 590         /* unmap the data buffer */
 591         if (dma_size != 0)
 592                 dma_unmap_single(dev, dma_addr, dma_size, dma_direction);
 593
 594         if (unlikely(!time_left)) {
 595                 dev_err(dev, "completion wait timed out\n");
 596                 ret = -ETIMEDOUT;
 597                 goto out;
 598         }
 599
 600         /* do any post processing of the descriptor here */
 601         ret = ismt_process_desc(desc, data, priv, size, read_write);
 602
 603 out:
 604         /* Update the ring pointer */
 605         priv->head++;
 606         priv->head %= ISMT_DESC_ENTRIES;
 607
 608         return ret;
 609 }
 610
 611 /**
 612  * ismt_func() - report which i2c commands are supported by this adapter
 613  * @adap: the i2c host adapter
 614  */
 615 static u32 ismt_func(struct i2c_adapter *adap)
 616 {
 617         return I2C_FUNC_SMBUS_QUICK             |
 618                I2C_FUNC_SMBUS_BYTE              |
 619                I2C_FUNC_SMBUS_BYTE_DATA         |
 620                I2C_FUNC_SMBUS_WORD_DATA         |
 621                I2C_FUNC_SMBUS_PROC_CALL         |
 622                I2C_FUNC_SMBUS_BLOCK_DATA        |
 623                I2C_FUNC_SMBUS_I2C_BLOCK         |
 624                I2C_FUNC_SMBUS_PEC;
 625 }
 626
 627 /**
 628  * smbus_algorithm - the adapter algorithm and supported functionality
 629  * @smbus_xfer: the adapter algorithm
 630  * @functionality: functionality supported by the adapter
 631  */
 632 static const struct i2c_algorithm smbus_algorithm = {
 633         .smbus_xfer     = ismt_access,
 634         .functionality  = ismt_func,
 635 };
 636
 637 /**
 638  * ismt_handle_isr() - interrupt handler bottom half
 639  * @priv: iSMT private data
 640  */
 641 static irqreturn_t ismt_handle_isr(struct ismt_priv *priv)
 642 {
 643         complete(&priv->cmp);
 644
 645         return IRQ_HANDLED;
 646 }
 647
 648
 649 /**
 650  * ismt_do_interrupt() - IRQ interrupt handler
 651  * @vec: interrupt vector
 652  * @data: iSMT private data
 653  */
 654 static irqreturn_t ismt_do_interrupt(int vec, void *data)
 655 {
 656         u32 val;
 657         struct ismt_priv *priv = data;
 658
 659         /*
 660          * check to see it's our interrupt, return IRQ_NONE if not ours
 661          * since we are sharing interrupt
 662          */
 663         val = readl(priv->smba + ISMT_MSTR_MSTS);
 664
 665         if (!(val & (ISMT_MSTS_MIS | ISMT_MSTS_MEIS)))
 666                 return IRQ_NONE;
 667         else
 668                 writel(val | ISMT_MSTS_MIS | ISMT_MSTS_MEIS,
 669                        priv->smba + ISMT_MSTR_MSTS);
 670
 671         return ismt_handle_isr(priv);
 672 }
 673
 674 /**
 675  * ismt_do_msi_interrupt() - MSI interrupt handler
 676  * @vec: interrupt vector
 677  * @data: iSMT private data
 678  */
 679 static irqreturn_t ismt_do_msi_interrupt(int vec, void *data)
 680 {
 681         return ismt_handle_isr(data);
 682 }
 683
 684 /**
 685  * ismt_hw_init() - initialize the iSMT hardware
 686  * @priv: iSMT private data
 687  */
 688 static void ismt_hw_init(struct ismt_priv *priv)
 689 {
 690         u32 val;
 691         struct device *dev = &priv->pci_dev->dev;
 692
 693         /* initialize the Master Descriptor Base Address (MDBA) */
 694         writeq(priv->io_rng_dma, priv->smba + ISMT_MSTR_MDBA);
 695
 696         /* initialize the Master Control Register (MCTRL) */
 697         writel(ISMT_MCTRL_MEIE, priv->smba + ISMT_MSTR_MCTRL);
 698
 699         /* initialize the Master Status Register (MSTS) */
 700         writel(0, priv->smba + ISMT_MSTR_MSTS);
 701
 702         /* initialize the Master Descriptor Size (MDS) */
 703         val = readl(priv->smba + ISMT_MSTR_MDS);
 704         writel((val & ~ISMT_MDS_MASK) | (ISMT_DESC_ENTRIES - 1),
 705                 priv->smba + ISMT_MSTR_MDS);
 706
 707         /*
 708          * Set the SMBus speed (could use this for slow HW debuggers)
 709          */
 710
 711         val = readl(priv->smba + ISMT_SPGT);
 712
 713         switch (bus_speed) {
 714         case 0:
 715                 break;
 716
 717         case 80:
 718                 dev_dbg(dev, "Setting SMBus clock to 80 kHz\n");
 719                 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_80K),
 720                         priv->smba + ISMT_SPGT);
 721                 break;
 722
 723         case 100:
 724                 dev_dbg(dev, "Setting SMBus clock to 100 kHz\n");
 725                 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_100K),
 726                         priv->smba + ISMT_SPGT);
 727                 break;
 728
 729         case 400:
 730                 dev_dbg(dev, "Setting SMBus clock to 400 kHz\n");
 731                 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_400K),
 732                         priv->smba + ISMT_SPGT);
 733                 break;
 734
 735         case 1000:
 736                 dev_dbg(dev, "Setting SMBus clock to 1000 kHz\n");
 737                 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_1M),
 738                         priv->smba + ISMT_SPGT);
 739                 break;
 740
 741         default:
 742                 dev_warn(dev, "Invalid SMBus clock speed, only 0, 80, 100, 400, and 1000 are valid\n");
 743                 break;
 744         }
 745
 746         val = readl(priv->smba + ISMT_SPGT);
 747
 748         switch (val & ISMT_SPGT_SPD_MASK) {
 749         case ISMT_SPGT_SPD_80K:
 750                 bus_speed = 80;
 751                 break;
 752         case ISMT_SPGT_SPD_100K:
 753                 bus_speed = 100;
 754                 break;
 755         case ISMT_SPGT_SPD_400K:
 756                 bus_speed = 400;
 757                 break;
 758         case ISMT_SPGT_SPD_1M:
 759                 bus_speed = 1000;
 760                 break;
 761         }
 762         dev_dbg(dev, "SMBus clock is running at %d kHz\n", bus_speed);
 763 }
 764
 765 /**
 766  * ismt_dev_init() - initialize the iSMT data structures
 767  * @priv: iSMT private data
 768  */
 769 static int ismt_dev_init(struct ismt_priv *priv)
 770 {
 771         /* allocate memory for the descriptor */
 772         priv->hw = dmam_alloc_coherent(&priv->pci_dev->dev,
 773                                        (ISMT_DESC_ENTRIES
 774                                                * sizeof(struct ismt_desc)),
 775                                        &priv->io_rng_dma,
 776                                        GFP_KERNEL);
 777         if (!priv->hw)
 778                 return -ENOMEM;
 779
 780         memset(priv->hw, 0, (ISMT_DESC_ENTRIES * sizeof(struct ismt_desc)));
 781
 782         priv->head = 0;
 783         init_completion(&priv->cmp);
 784
 785         return 0;
 786 }
 787
 788 /**
 789  * ismt_int_init() - initialize interrupts
 790  * @priv: iSMT private data
 791  */
 792 static int ismt_int_init(struct ismt_priv *priv)
 793 {
 794         int err;
 795
 796         /* Try using MSI interrupts */
 797         err = pci_enable_msi(priv->pci_dev);
 798         if (err)
 799                 goto intx;
 800
 801         err = devm_request_irq(&priv->pci_dev->dev,
 802                                priv->pci_dev->irq,
 803                                ismt_do_msi_interrupt,
 804                                0,
 805                                "ismt-msi",
 806                                priv);
 807         if (err) {
 808                 pci_disable_msi(priv->pci_dev);
 809                 goto intx;
 810         }
 811
 812         return 0;
 813
 814         /* Try using legacy interrupts */
 815 intx:
 816         dev_warn(&priv->pci_dev->dev,
 817                  "Unable to use MSI interrupts, falling back to legacy\n");
 818
 819         err = devm_request_irq(&priv->pci_dev->dev,
 820                                priv->pci_dev->irq,
 821                                ismt_do_interrupt,
 822                                IRQF_SHARED,
 823                                "ismt-intx",
 824                                priv);
 825         if (err) {
 826                 dev_err(&priv->pci_dev->dev, "no usable interrupts\n");
 827                 return err;
 828         }
 829
 830         return 0;
 831 }
 832
 833 static struct pci_driver ismt_driver;
 834
 835 /**
 836  * ismt_probe() - probe for iSMT devices
 837  * @pdev: PCI-Express device
 838  * @id: PCI-Express device ID
 839  */
 840 static int
 841 ismt_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 842 {
 843         int err;
 844         struct ismt_priv *priv;
 845         unsigned long start, len;
 846
 847         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 848         if (!priv)
 849                 return -ENOMEM;
 850
 851         pci_set_drvdata(pdev, priv);
 852
 853         i2c_set_adapdata(&priv->adapter, priv);
 854         priv->adapter.owner = THIS_MODULE;
 855         priv->adapter.class = I2C_CLASS_HWMON;
 856         priv->adapter.algo = &smbus_algorithm;
 857         priv->adapter.dev.parent = &pdev->dev;
 858         ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&pdev->dev));
 859         priv->adapter.retries = ISMT_MAX_RETRIES;
 860
 861         priv->pci_dev = pdev;
 862
 863         err = pcim_enable_device(pdev);
 864         if (err) {
 865                 dev_err(&pdev->dev, "Failed to enable SMBus PCI device (%d)\n",
 866                         err);
 867                 return err;
 868         }
 869
 870         /* enable bus mastering */
 871         pci_set_master(pdev);
 872
 873         /* Determine the address of the SMBus area */
 874         start = pci_resource_start(pdev, SMBBAR);
 875         len = pci_resource_len(pdev, SMBBAR);
 876         if (!start || !len) {
 877                 dev_err(&pdev->dev,
 878                         "SMBus base address uninitialized, upgrade BIOS\n");
 879                 return -ENODEV;
 880         }
 881
 882         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
 883                  "SMBus iSMT adapter at %lx", start);
 884
 885         dev_dbg(&priv->pci_dev->dev, " start=0x%lX\n", start);
 886         dev_dbg(&priv->pci_dev->dev, " len=0x%lX\n", len);
 887
 888         err = acpi_check_resource_conflict(&pdev->resource[SMBBAR]);
 889         if (err) {
 890                 dev_err(&pdev->dev, "ACPI resource conflict!\n");
 891                 return err;
 892         }
 893
 894         err = pci_request_region(pdev, SMBBAR, ismt_driver.name);
 895         if (err) {
 896                 dev_err(&pdev->dev,
 897                         "Failed to request SMBus region 0x%lx-0x%lx\n",
 898                         start, start + len);
 899                 return err;
 900         }
 901
 902         priv->smba = pcim_iomap(pdev, SMBBAR, len);
 903         if (!priv->smba) {
 904                 dev_err(&pdev->dev, "Unable to ioremap SMBus BAR\n");
 905                 return -ENODEV;
 906         }
 907
 908         if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) ||
 909             (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) {
 910                 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
 911                     (pci_set_consistent_dma_mask(pdev,
 912                                                  DMA_BIT_MASK(32)) != 0)) {
 913                         dev_err(&pdev->dev, "pci_set_dma_mask fail %p\n",
 914                                 pdev);
 915                         return -ENODEV;
 916                 }
 917         }
 918
 919         err = ismt_dev_init(priv);
 920         if (err)
 921                 return err;
 922
 923         ismt_hw_init(priv);
 924
 925         err = ismt_int_init(priv);
 926         if (err)
 927                 return err;
 928
 929         err = i2c_add_adapter(&priv->adapter);
 930         if (err)
 931                 return -ENODEV;
 932         return 0;
 933 }
 934
 935 /**
 936  * ismt_remove() - release driver resources
 937  * @pdev: PCI-Express device
 938  */
 939 static void ismt_remove(struct pci_dev *pdev)
 940 {
 941         struct ismt_priv *priv = pci_get_drvdata(pdev);
 942
 943         i2c_del_adapter(&priv->adapter);
 944 }
 945
 946 static struct pci_driver ismt_driver = {
 947         .name = "ismt_smbus",
 948         .id_table = ismt_ids,
 949         .probe = ismt_probe,
 950         .remove = ismt_remove,
 951 };
 952
 953 module_pci_driver(ismt_driver);
 954
 955 MODULE_LICENSE("Dual BSD/GPL");
 956 MODULE_AUTHOR("Bill E. Brown <bill.e.brown@intel.com>");
 957 MODULE_DESCRIPTION("Intel SMBus Message Transport (iSMT) driver");