drivers/i2c/busses/i2c-owl.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Actions Semiconductor Owl SoC's I2C driver
   4  *
   5  * Copyright (c) 2014 Actions Semi Inc.
   6  * Author: David Liu <liuwei@actions-semi.com>
   7  *
   8  * Copyright (c) 2018 Linaro Ltd.
   9  * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/delay.h>
  14 #include <linux/i2c.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/io.h>
  17 #include <linux/module.h>
  18 #include <linux/of_device.h>
  19
  20 /* I2C registers */
  21 #define OWL_I2C_REG_CTL         0x0000
  22 #define OWL_I2C_REG_CLKDIV      0x0004
  23 #define OWL_I2C_REG_STAT        0x0008
  24 #define OWL_I2C_REG_ADDR        0x000C
  25 #define OWL_I2C_REG_TXDAT       0x0010
  26 #define OWL_I2C_REG_RXDAT       0x0014
  27 #define OWL_I2C_REG_CMD         0x0018
  28 #define OWL_I2C_REG_FIFOCTL     0x001C
  29 #define OWL_I2C_REG_FIFOSTAT    0x0020
  30 #define OWL_I2C_REG_DATCNT      0x0024
  31 #define OWL_I2C_REG_RCNT        0x0028
  32
  33 /* I2Cx_CTL Bit Mask */
  34 #define OWL_I2C_CTL_RB          BIT(1)
  35 #define OWL_I2C_CTL_GBCC(x)     (((x) & 0x3) << 2)
  36 #define OWL_I2C_CTL_GBCC_NONE   OWL_I2C_CTL_GBCC(0)
  37 #define OWL_I2C_CTL_GBCC_START  OWL_I2C_CTL_GBCC(1)
  38 #define OWL_I2C_CTL_GBCC_STOP   OWL_I2C_CTL_GBCC(2)
  39 #define OWL_I2C_CTL_GBCC_RSTART OWL_I2C_CTL_GBCC(3)
  40 #define OWL_I2C_CTL_IRQE        BIT(5)
  41 #define OWL_I2C_CTL_EN          BIT(7)
  42 #define OWL_I2C_CTL_AE          BIT(8)
  43 #define OWL_I2C_CTL_SHSM        BIT(10)
  44
  45 #define OWL_I2C_DIV_FACTOR(x)   ((x) & 0xff)
  46
  47 /* I2Cx_STAT Bit Mask */
  48 #define OWL_I2C_STAT_RACK       BIT(0)
  49 #define OWL_I2C_STAT_BEB        BIT(1)
  50 #define OWL_I2C_STAT_IRQP       BIT(2)
  51 #define OWL_I2C_STAT_LAB        BIT(3)
  52 #define OWL_I2C_STAT_STPD       BIT(4)
  53 #define OWL_I2C_STAT_STAD       BIT(5)
  54 #define OWL_I2C_STAT_BBB        BIT(6)
  55 #define OWL_I2C_STAT_TCB        BIT(7)
  56 #define OWL_I2C_STAT_LBST       BIT(8)
  57 #define OWL_I2C_STAT_SAMB       BIT(9)
  58 #define OWL_I2C_STAT_SRGC       BIT(10)
  59
  60 /* I2Cx_CMD Bit Mask */
  61 #define OWL_I2C_CMD_SBE         BIT(0)
  62 #define OWL_I2C_CMD_RBE         BIT(4)
  63 #define OWL_I2C_CMD_DE          BIT(8)
  64 #define OWL_I2C_CMD_NS          BIT(9)
  65 #define OWL_I2C_CMD_SE          BIT(10)
  66 #define OWL_I2C_CMD_MSS         BIT(11)
  67 #define OWL_I2C_CMD_WRS         BIT(12)
  68 #define OWL_I2C_CMD_SECL        BIT(15)
  69
  70 #define OWL_I2C_CMD_AS(x)       (((x) & 0x7) << 1)
  71 #define OWL_I2C_CMD_SAS(x)      (((x) & 0x7) << 5)
  72
  73 /* I2Cx_FIFOCTL Bit Mask */
  74 #define OWL_I2C_FIFOCTL_NIB     BIT(0)
  75 #define OWL_I2C_FIFOCTL_RFR     BIT(1)
  76 #define OWL_I2C_FIFOCTL_TFR     BIT(2)
  77
  78 /* I2Cc_FIFOSTAT Bit Mask */
  79 #define OWL_I2C_FIFOSTAT_RNB    BIT(1)
  80 #define OWL_I2C_FIFOSTAT_RFE    BIT(2)
  81 #define OWL_I2C_FIFOSTAT_TFF    BIT(5)
  82 #define OWL_I2C_FIFOSTAT_TFD    GENMASK(23, 16)
  83 #define OWL_I2C_FIFOSTAT_RFD    GENMASK(15, 8)
  84
  85 /* I2C bus timeout */
  86 #define OWL_I2C_TIMEOUT         msecs_to_jiffies(4 * 1000)
  87
  88 #define OWL_I2C_MAX_RETRIES     50
  89
  90 #define OWL_I2C_DEF_SPEED_HZ    100000
  91 #define OWL_I2C_MAX_SPEED_HZ    400000
  92
  93 struct owl_i2c_dev {
  94         struct i2c_adapter      adap;
  95         struct i2c_msg          *msg;
  96         struct completion       msg_complete;
  97         struct clk              *clk;
  98         spinlock_t              lock;
  99         void __iomem            *base;
 100         unsigned long           clk_rate;
 101         u32                     bus_freq;
 102         u32                     msg_ptr;
 103         int                     err;
 104 };
 105
 106 static void owl_i2c_update_reg(void __iomem *reg, unsigned int val, bool state)
 107 {
 108         unsigned int regval;
 109
 110         regval = readl(reg);
 111
 112         if (state)
 113                 regval |= val;
 114         else
 115                 regval &= ~val;
 116
 117         writel(regval, reg);
 118 }
 119
 120 static void owl_i2c_reset(struct owl_i2c_dev *i2c_dev)
 121 {
 122         owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
 123                            OWL_I2C_CTL_EN, false);
 124         mdelay(1);
 125         owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
 126                            OWL_I2C_CTL_EN, true);
 127
 128         /* Clear status registers */
 129         writel(0, i2c_dev->base + OWL_I2C_REG_STAT);
 130 }
 131
 132 static int owl_i2c_reset_fifo(struct owl_i2c_dev *i2c_dev)
 133 {
 134         unsigned int val, timeout = 0;
 135
 136         /* Reset FIFO */
 137         owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL,
 138                            OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR,
 139                            true);
 140
 141         /* Wait 50ms for FIFO reset complete */
 142         do {
 143                 val = readl(i2c_dev->base + OWL_I2C_REG_FIFOCTL);
 144                 if (!(val & (OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR)))
 145                         break;
 146                 usleep_range(500, 1000);
 147         } while (timeout++ < OWL_I2C_MAX_RETRIES);
 148
 149         if (timeout > OWL_I2C_MAX_RETRIES) {
 150                 dev_err(&i2c_dev->adap.dev, "FIFO reset timeout\n");
 151                 return -ETIMEDOUT;
 152         }
 153
 154         return 0;
 155 }
 156
 157 static void owl_i2c_set_freq(struct owl_i2c_dev *i2c_dev)
 158 {
 159         unsigned int val;
 160
 161         val = DIV_ROUND_UP(i2c_dev->clk_rate, i2c_dev->bus_freq * 16);
 162
 163         /* Set clock divider factor */
 164         writel(OWL_I2C_DIV_FACTOR(val), i2c_dev->base + OWL_I2C_REG_CLKDIV);
 165 }
 166
 167 static irqreturn_t owl_i2c_interrupt(int irq, void *_dev)
 168 {
 169         struct owl_i2c_dev *i2c_dev = _dev;
 170         struct i2c_msg *msg = i2c_dev->msg;
 171         unsigned long flags;
 172         unsigned int stat, fifostat;
 173
 174         spin_lock_irqsave(&i2c_dev->lock, flags);
 175
 176         i2c_dev->err = 0;
 177
 178         /* Handle NACK from slave */
 179         fifostat = readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT);
 180         if (fifostat & OWL_I2C_FIFOSTAT_RNB) {
 181                 i2c_dev->err = -ENXIO;
 182                 /* Clear NACK error bit by writing "1" */
 183                 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOSTAT,
 184                                    OWL_I2C_FIFOSTAT_RNB, true);
 185                 goto stop;
 186         }
 187
 188         /* Handle bus error */
 189         stat = readl(i2c_dev->base + OWL_I2C_REG_STAT);
 190         if (stat & OWL_I2C_STAT_BEB) {
 191                 i2c_dev->err = -EIO;
 192                 /* Clear BUS error bit by writing "1" */
 193                 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_STAT,
 194                                    OWL_I2C_STAT_BEB, true);
 195                 goto stop;
 196         }
 197
 198         /* Handle FIFO read */
 199         if (msg->flags & I2C_M_RD) {
 200                 while ((readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) &
 201                         OWL_I2C_FIFOSTAT_RFE) && i2c_dev->msg_ptr < msg->len) {
 202                         msg->buf[i2c_dev->msg_ptr++] = readl(i2c_dev->base +
 203                                                              OWL_I2C_REG_RXDAT);
 204                 }
 205         } else {
 206                 /* Handle the remaining bytes which were not sent */
 207                 while (!(readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) &
 208                          OWL_I2C_FIFOSTAT_TFF) && i2c_dev->msg_ptr < msg->len) {
 209                         writel(msg->buf[i2c_dev->msg_ptr++],
 210                                i2c_dev->base + OWL_I2C_REG_TXDAT);
 211                 }
 212         }
 213
 214 stop:
 215         /* Clear pending interrupts */
 216         owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_STAT,
 217                            OWL_I2C_STAT_IRQP, true);
 218
 219         complete_all(&i2c_dev->msg_complete);
 220         spin_unlock_irqrestore(&i2c_dev->lock, flags);
 221
 222         return IRQ_HANDLED;
 223 }
 224
 225 static u32 owl_i2c_func(struct i2c_adapter *adap)
 226 {
 227         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 228 }
 229
 230 static int owl_i2c_check_bus_busy(struct i2c_adapter *adap)
 231 {
 232         struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
 233         unsigned long timeout;
 234
 235         /* Check for Bus busy */
 236         timeout = jiffies + OWL_I2C_TIMEOUT;
 237         while (readl(i2c_dev->base + OWL_I2C_REG_STAT) & OWL_I2C_STAT_BBB) {
 238                 if (time_after(jiffies, timeout)) {
 239                         dev_err(&adap->dev, "Bus busy timeout\n");
 240                         return -ETIMEDOUT;
 241                 }
 242         }
 243
 244         return 0;
 245 }
 246
 247 static int owl_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
 248                                int num)
 249 {
 250         struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
 251         struct i2c_msg *msg;
 252         unsigned long time_left, flags;
 253         unsigned int i2c_cmd, val;
 254         unsigned int addr;
 255         int ret, idx;
 256
 257         spin_lock_irqsave(&i2c_dev->lock, flags);
 258
 259         /* Reset I2C controller */
 260         owl_i2c_reset(i2c_dev);
 261
 262         /* Set bus frequency */
 263         owl_i2c_set_freq(i2c_dev);
 264
 265         /*
 266          * Spinlock should be released before calling reset FIFO and
 267          * bus busy check since those functions may sleep
 268          */
 269         spin_unlock_irqrestore(&i2c_dev->lock, flags);
 270
 271         /* Reset FIFO */
 272         ret = owl_i2c_reset_fifo(i2c_dev);
 273         if (ret)
 274                 goto unlocked_err_exit;
 275
 276         /* Check for bus busy */
 277         ret = owl_i2c_check_bus_busy(adap);
 278         if (ret)
 279                 goto unlocked_err_exit;
 280
 281         spin_lock_irqsave(&i2c_dev->lock, flags);
 282
 283         /* Check for Arbitration lost */
 284         val = readl(i2c_dev->base + OWL_I2C_REG_STAT);
 285         if (val & OWL_I2C_STAT_LAB) {
 286                 val &= ~OWL_I2C_STAT_LAB;
 287                 writel(val, i2c_dev->base + OWL_I2C_REG_STAT);
 288                 ret = -EAGAIN;
 289                 goto err_exit;
 290         }
 291
 292         reinit_completion(&i2c_dev->msg_complete);
 293
 294         /* Enable I2C controller interrupt */
 295         owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
 296                            OWL_I2C_CTL_IRQE, true);
 297
 298         /*
 299          * Select: FIFO enable, Master mode, Stop enable, Data count enable,
 300          * Send start bit
 301          */
 302         i2c_cmd = OWL_I2C_CMD_SECL | OWL_I2C_CMD_MSS | OWL_I2C_CMD_SE |
 303                   OWL_I2C_CMD_NS | OWL_I2C_CMD_DE | OWL_I2C_CMD_SBE;
 304
 305         /* Handle repeated start condition */
 306         if (num > 1) {
 307                 /* Set internal address length and enable repeated start */
 308                 i2c_cmd |= OWL_I2C_CMD_AS(msgs[0].len + 1) |
 309                            OWL_I2C_CMD_SAS(1) | OWL_I2C_CMD_RBE;
 310
 311                 /* Write slave address */
 312                 addr = i2c_8bit_addr_from_msg(&msgs[0]);
 313                 writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT);
 314
 315                 /* Write internal register address */
 316                 for (idx = 0; idx < msgs[0].len; idx++)
 317                         writel(msgs[0].buf[idx],
 318                                i2c_dev->base + OWL_I2C_REG_TXDAT);
 319
 320                 msg = &msgs[1];
 321         } else {
 322                 /* Set address length */
 323                 i2c_cmd |= OWL_I2C_CMD_AS(1);
 324                 msg = &msgs[0];
 325         }
 326
 327         i2c_dev->msg = msg;
 328         i2c_dev->msg_ptr = 0;
 329
 330         /* Set data count for the message */
 331         writel(msg->len, i2c_dev->base + OWL_I2C_REG_DATCNT);
 332
 333         addr = i2c_8bit_addr_from_msg(msg);
 334         writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT);
 335
 336         if (!(msg->flags & I2C_M_RD)) {
 337                 /* Write data to FIFO */
 338                 for (idx = 0; idx < msg->len; idx++) {
 339                         /* Check for FIFO full */
 340                         if (readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) &
 341                             OWL_I2C_FIFOSTAT_TFF)
 342                                 break;
 343
 344                         writel(msg->buf[idx],
 345                                i2c_dev->base + OWL_I2C_REG_TXDAT);
 346                 }
 347
 348                 i2c_dev->msg_ptr = idx;
 349         }
 350
 351         /* Ignore the NACK if needed */
 352         if (msg->flags & I2C_M_IGNORE_NAK)
 353                 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL,
 354                                    OWL_I2C_FIFOCTL_NIB, true);
 355         else
 356                 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL,
 357                                    OWL_I2C_FIFOCTL_NIB, false);
 358
 359         /* Start the transfer */
 360         writel(i2c_cmd, i2c_dev->base + OWL_I2C_REG_CMD);
 361
 362         spin_unlock_irqrestore(&i2c_dev->lock, flags);
 363
 364         time_left = wait_for_completion_timeout(&i2c_dev->msg_complete,
 365                                                 adap->timeout);
 366
 367         spin_lock_irqsave(&i2c_dev->lock, flags);
 368         if (time_left == 0) {
 369                 dev_err(&adap->dev, "Transaction timed out\n");
 370                 /* Send stop condition and release the bus */
 371                 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
 372                                    OWL_I2C_CTL_GBCC_STOP | OWL_I2C_CTL_RB,
 373                                    true);
 374                 ret = -ETIMEDOUT;
 375                 goto err_exit;
 376         }
 377
 378         ret = i2c_dev->err < 0 ? i2c_dev->err : num;
 379
 380 err_exit:
 381         spin_unlock_irqrestore(&i2c_dev->lock, flags);
 382
 383 unlocked_err_exit:
 384         /* Disable I2C controller */
 385         owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
 386                            OWL_I2C_CTL_EN, false);
 387
 388         return ret;
 389 }
 390
 391 static const struct i2c_algorithm owl_i2c_algorithm = {
 392         .master_xfer    = owl_i2c_master_xfer,
 393         .functionality  = owl_i2c_func,
 394 };
 395
 396 static const struct i2c_adapter_quirks owl_i2c_quirks = {
 397         .flags          = I2C_AQ_COMB | I2C_AQ_COMB_WRITE_FIRST,
 398         .max_read_len   = 240,
 399         .max_write_len  = 240,
 400         .max_comb_1st_msg_len = 6,
 401         .max_comb_2nd_msg_len = 240,
 402 };
 403
 404 static int owl_i2c_probe(struct platform_device *pdev)
 405 {
 406         struct device *dev = &pdev->dev;
 407         struct owl_i2c_dev *i2c_dev;
 408         struct resource *res;
 409         int ret, irq;
 410
 411         i2c_dev = devm_kzalloc(dev, sizeof(*i2c_dev), GFP_KERNEL);
 412         if (!i2c_dev)
 413                 return -ENOMEM;
 414
 415         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 416         i2c_dev->base = devm_ioremap_resource(dev, res);
 417         if (IS_ERR(i2c_dev->base))
 418                 return PTR_ERR(i2c_dev->base);
 419
 420         irq = platform_get_irq(pdev, 0);
 421         if (irq < 0) {
 422                 dev_err(dev, "failed to get IRQ number\n");
 423                 return irq;
 424         }
 425
 426         if (of_property_read_u32(dev->of_node, "clock-frequency",
 427                                  &i2c_dev->bus_freq))
 428                 i2c_dev->bus_freq = OWL_I2C_DEF_SPEED_HZ;
 429
 430         /* We support only frequencies of 100k and 400k for now */
 431         if (i2c_dev->bus_freq != OWL_I2C_DEF_SPEED_HZ &&
 432             i2c_dev->bus_freq != OWL_I2C_MAX_SPEED_HZ) {
 433                 dev_err(dev, "invalid clock-frequency %d\n", i2c_dev->bus_freq);
 434                 return -EINVAL;
 435         }
 436
 437         i2c_dev->clk = devm_clk_get(dev, NULL);
 438         if (IS_ERR(i2c_dev->clk)) {
 439                 dev_err(dev, "failed to get clock\n");
 440                 return PTR_ERR(i2c_dev->clk);
 441         }
 442
 443         ret = clk_prepare_enable(i2c_dev->clk);
 444         if (ret)
 445                 return ret;
 446
 447         i2c_dev->clk_rate = clk_get_rate(i2c_dev->clk);
 448         if (!i2c_dev->clk_rate) {
 449                 dev_err(dev, "input clock rate should not be zero\n");
 450                 ret = -EINVAL;
 451                 goto disable_clk;
 452         }
 453
 454         init_completion(&i2c_dev->msg_complete);
 455         spin_lock_init(&i2c_dev->lock);
 456         i2c_dev->adap.owner = THIS_MODULE;
 457         i2c_dev->adap.algo = &owl_i2c_algorithm;
 458         i2c_dev->adap.timeout = OWL_I2C_TIMEOUT;
 459         i2c_dev->adap.quirks = &owl_i2c_quirks;
 460         i2c_dev->adap.dev.parent = dev;
 461         i2c_dev->adap.dev.of_node = dev->of_node;
 462         snprintf(i2c_dev->adap.name, sizeof(i2c_dev->adap.name),
 463                  "%s", "OWL I2C adapter");
 464         i2c_set_adapdata(&i2c_dev->adap, i2c_dev);
 465
 466         platform_set_drvdata(pdev, i2c_dev);
 467
 468         ret = devm_request_irq(dev, irq, owl_i2c_interrupt, 0, pdev->name,
 469                                i2c_dev);
 470         if (ret) {
 471                 dev_err(dev, "failed to request irq %d\n", irq);
 472                 goto disable_clk;
 473         }
 474
 475         return i2c_add_adapter(&i2c_dev->adap);
 476
 477 disable_clk:
 478         clk_disable_unprepare(i2c_dev->clk);
 479
 480         return ret;
 481 }
 482
 483 static const struct of_device_id owl_i2c_of_match[] = {
 484         { .compatible = "actions,s900-i2c" },
 485         { /* sentinel */ }
 486 };
 487 MODULE_DEVICE_TABLE(of, owl_i2c_of_match);
 488
 489 static struct platform_driver owl_i2c_driver = {
 490         .probe          = owl_i2c_probe,
 491         .driver         = {
 492                 .name   = "owl-i2c",
 493                 .of_match_table = of_match_ptr(owl_i2c_of_match),
 494         },
 495 };
 496 module_platform_driver(owl_i2c_driver);
 497
 498 MODULE_AUTHOR("David Liu <liuwei@actions-semi.com>");
 499 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
 500 MODULE_DESCRIPTION("Actions Semiconductor Owl SoC's I2C driver");
 501 MODULE_LICENSE("GPL");