drivers/i2c/busses/i2c-qup.c

   1 /*
   2  * Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
   3  * Copyright (c) 2014, Sony Mobile Communications AB.
   4  *
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 and
   8  * only version 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/atomic.h>
  18 #include <linux/clk.h>
  19 #include <linux/delay.h>
  20 #include <linux/dmaengine.h>
  21 #include <linux/dmapool.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/err.h>
  24 #include <linux/i2c.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/module.h>
  28 #include <linux/of.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/scatterlist.h>
  32
  33 /* QUP Registers */
  34 #define QUP_CONFIG              0x000
  35 #define QUP_STATE               0x004
  36 #define QUP_IO_MODE             0x008
  37 #define QUP_SW_RESET            0x00c
  38 #define QUP_OPERATIONAL         0x018
  39 #define QUP_ERROR_FLAGS         0x01c
  40 #define QUP_ERROR_FLAGS_EN      0x020
  41 #define QUP_OPERATIONAL_MASK    0x028
  42 #define QUP_HW_VERSION          0x030
  43 #define QUP_MX_OUTPUT_CNT       0x100
  44 #define QUP_OUT_FIFO_BASE       0x110
  45 #define QUP_MX_WRITE_CNT        0x150
  46 #define QUP_MX_INPUT_CNT        0x200
  47 #define QUP_MX_READ_CNT         0x208
  48 #define QUP_IN_FIFO_BASE        0x218
  49 #define QUP_I2C_CLK_CTL         0x400
  50 #define QUP_I2C_STATUS          0x404
  51 #define QUP_I2C_MASTER_GEN      0x408
  52
  53 /* QUP States and reset values */
  54 #define QUP_RESET_STATE         0
  55 #define QUP_RUN_STATE           1
  56 #define QUP_PAUSE_STATE         3
  57 #define QUP_STATE_MASK          3
  58
  59 #define QUP_STATE_VALID         BIT(2)
  60 #define QUP_I2C_MAST_GEN        BIT(4)
  61 #define QUP_I2C_FLUSH           BIT(6)
  62
  63 #define QUP_OPERATIONAL_RESET   0x000ff0
  64 #define QUP_I2C_STATUS_RESET    0xfffffc
  65
  66 /* QUP OPERATIONAL FLAGS */
  67 #define QUP_I2C_NACK_FLAG       BIT(3)
  68 #define QUP_OUT_NOT_EMPTY       BIT(4)
  69 #define QUP_IN_NOT_EMPTY        BIT(5)
  70 #define QUP_OUT_FULL            BIT(6)
  71 #define QUP_OUT_SVC_FLAG        BIT(8)
  72 #define QUP_IN_SVC_FLAG         BIT(9)
  73 #define QUP_MX_OUTPUT_DONE      BIT(10)
  74 #define QUP_MX_INPUT_DONE       BIT(11)
  75
  76 /* I2C mini core related values */
  77 #define QUP_CLOCK_AUTO_GATE     BIT(13)
  78 #define I2C_MINI_CORE           (2 << 8)
  79 #define I2C_N_VAL               15
  80 #define I2C_N_VAL_V2            7
  81
  82 /* Most significant word offset in FIFO port */
  83 #define QUP_MSW_SHIFT           (I2C_N_VAL + 1)
  84
  85 /* Packing/Unpacking words in FIFOs, and IO modes */
  86 #define QUP_OUTPUT_BLK_MODE     (1 << 10)
  87 #define QUP_OUTPUT_BAM_MODE     (3 << 10)
  88 #define QUP_INPUT_BLK_MODE      (1 << 12)
  89 #define QUP_INPUT_BAM_MODE      (3 << 12)
  90 #define QUP_BAM_MODE            (QUP_OUTPUT_BAM_MODE | QUP_INPUT_BAM_MODE)
  91 #define QUP_UNPACK_EN           BIT(14)
  92 #define QUP_PACK_EN             BIT(15)
  93
  94 #define QUP_REPACK_EN           (QUP_UNPACK_EN | QUP_PACK_EN)
  95 #define QUP_V2_TAGS_EN          1
  96
  97 #define QUP_OUTPUT_BLOCK_SIZE(x)(((x) >> 0) & 0x03)
  98 #define QUP_OUTPUT_FIFO_SIZE(x) (((x) >> 2) & 0x07)
  99 #define QUP_INPUT_BLOCK_SIZE(x) (((x) >> 5) & 0x03)
 100 #define QUP_INPUT_FIFO_SIZE(x)  (((x) >> 7) & 0x07)
 101
 102 /* QUP tags */
 103 #define QUP_TAG_START           (1 << 8)
 104 #define QUP_TAG_DATA            (2 << 8)
 105 #define QUP_TAG_STOP            (3 << 8)
 106 #define QUP_TAG_REC             (4 << 8)
 107 #define QUP_BAM_INPUT_EOT               0x93
 108 #define QUP_BAM_FLUSH_STOP              0x96
 109
 110 /* QUP v2 tags */
 111 #define QUP_TAG_V2_START               0x81
 112 #define QUP_TAG_V2_DATAWR              0x82
 113 #define QUP_TAG_V2_DATAWR_STOP         0x83
 114 #define QUP_TAG_V2_DATARD              0x85
 115 #define QUP_TAG_V2_DATARD_STOP         0x87
 116
 117 /* Status, Error flags */
 118 #define I2C_STATUS_WR_BUFFER_FULL       BIT(0)
 119 #define I2C_STATUS_BUS_ACTIVE           BIT(8)
 120 #define I2C_STATUS_ERROR_MASK           0x38000fc
 121 #define QUP_STATUS_ERROR_FLAGS          0x7c
 122
 123 #define QUP_READ_LIMIT                  256
 124 #define SET_BIT                         0x1
 125 #define RESET_BIT                       0x0
 126 #define ONE_BYTE                        0x1
 127 #define QUP_I2C_MX_CONFIG_DURING_RUN   BIT(31)
 128
 129 #define MX_TX_RX_LEN                    SZ_64K
 130 #define MX_BLOCKS                       (MX_TX_RX_LEN / QUP_READ_LIMIT)
 131
 132 /* Max timeout in ms for 32k bytes */
 133 #define TOUT_MAX                        300
 134
 135 struct qup_i2c_block {
 136         int     count;
 137         int     pos;
 138         int     tx_tag_len;
 139         int     rx_tag_len;
 140         int     data_len;
 141         u8      tags[6];
 142 };
 143
 144 struct qup_i2c_tag {
 145         u8 *start;
 146         dma_addr_t addr;
 147 };
 148
 149 struct qup_i2c_bam {
 150         struct  qup_i2c_tag tag;
 151         struct  dma_chan *dma;
 152         struct  scatterlist *sg;
 153 };
 154
 155 struct qup_i2c_dev {
 156         struct device           *dev;
 157         void __iomem            *base;
 158         int                     irq;
 159         struct clk              *clk;
 160         struct clk              *pclk;
 161         struct i2c_adapter      adap;
 162
 163         int                     clk_ctl;
 164         int                     out_fifo_sz;
 165         int                     in_fifo_sz;
 166         int                     out_blk_sz;
 167         int                     in_blk_sz;
 168
 169         unsigned long           one_byte_t;
 170         struct qup_i2c_block    blk;
 171
 172         struct i2c_msg          *msg;
 173         /* Current posion in user message buffer */
 174         int                     pos;
 175         /* I2C protocol errors */
 176         u32                     bus_err;
 177         /* QUP core errors */
 178         u32                     qup_err;
 179
 180         /* To check if this is the last msg */
 181         bool                    is_last;
 182
 183         /* To configure when bus is in run state */
 184         int                     config_run;
 185
 186         /* dma parameters */
 187         bool                    is_dma;
 188         struct                  dma_pool *dpool;
 189         struct                  qup_i2c_tag start_tag;
 190         struct                  qup_i2c_bam brx;
 191         struct                  qup_i2c_bam btx;
 192
 193         struct completion       xfer;
 194 };
 195
 196 static irqreturn_t qup_i2c_interrupt(int irq, void *dev)
 197 {
 198         struct qup_i2c_dev *qup = dev;
 199         u32 bus_err;
 200         u32 qup_err;
 201         u32 opflags;
 202
 203         bus_err = readl(qup->base + QUP_I2C_STATUS);
 204         qup_err = readl(qup->base + QUP_ERROR_FLAGS);
 205         opflags = readl(qup->base + QUP_OPERATIONAL);
 206
 207         if (!qup->msg) {
 208                 /* Clear Error interrupt */
 209                 writel(QUP_RESET_STATE, qup->base + QUP_STATE);
 210                 return IRQ_HANDLED;
 211         }
 212
 213         bus_err &= I2C_STATUS_ERROR_MASK;
 214         qup_err &= QUP_STATUS_ERROR_FLAGS;
 215
 216         /* Clear the error bits in QUP_ERROR_FLAGS */
 217         if (qup_err)
 218                 writel(qup_err, qup->base + QUP_ERROR_FLAGS);
 219
 220         /* Clear the error bits in QUP_I2C_STATUS */
 221         if (bus_err)
 222                 writel(bus_err, qup->base + QUP_I2C_STATUS);
 223
 224         /* Reset the QUP State in case of error */
 225         if (qup_err || bus_err) {
 226                 writel(QUP_RESET_STATE, qup->base + QUP_STATE);
 227                 goto done;
 228         }
 229
 230         if (opflags & QUP_IN_SVC_FLAG)
 231                 writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL);
 232
 233         if (opflags & QUP_OUT_SVC_FLAG)
 234                 writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL);
 235
 236 done:
 237         qup->qup_err = qup_err;
 238         qup->bus_err = bus_err;
 239         complete(&qup->xfer);
 240         return IRQ_HANDLED;
 241 }
 242
 243 static int qup_i2c_poll_state_mask(struct qup_i2c_dev *qup,
 244                                    u32 req_state, u32 req_mask)
 245 {
 246         int retries = 1;
 247         u32 state;
 248
 249         /*
 250          * State transition takes 3 AHB clocks cycles + 3 I2C master clock
 251          * cycles. So retry once after a 1uS delay.
 252          */
 253         do {
 254                 state = readl(qup->base + QUP_STATE);
 255
 256                 if (state & QUP_STATE_VALID &&
 257                     (state & req_mask) == req_state)
 258                         return 0;
 259
 260                 udelay(1);
 261         } while (retries--);
 262
 263         return -ETIMEDOUT;
 264 }
 265
 266 static int qup_i2c_poll_state(struct qup_i2c_dev *qup, u32 req_state)
 267 {
 268         return qup_i2c_poll_state_mask(qup, req_state, QUP_STATE_MASK);
 269 }
 270
 271 static void qup_i2c_flush(struct qup_i2c_dev *qup)
 272 {
 273         u32 val = readl(qup->base + QUP_STATE);
 274
 275         val |= QUP_I2C_FLUSH;
 276         writel(val, qup->base + QUP_STATE);
 277 }
 278
 279 static int qup_i2c_poll_state_valid(struct qup_i2c_dev *qup)
 280 {
 281         return qup_i2c_poll_state_mask(qup, 0, 0);
 282 }
 283
 284 static int qup_i2c_poll_state_i2c_master(struct qup_i2c_dev *qup)
 285 {
 286         return qup_i2c_poll_state_mask(qup, QUP_I2C_MAST_GEN, QUP_I2C_MAST_GEN);
 287 }
 288
 289 static int qup_i2c_change_state(struct qup_i2c_dev *qup, u32 state)
 290 {
 291         if (qup_i2c_poll_state_valid(qup) != 0)
 292                 return -EIO;
 293
 294         writel(state, qup->base + QUP_STATE);
 295
 296         if (qup_i2c_poll_state(qup, state) != 0)
 297                 return -EIO;
 298         return 0;
 299 }
 300
 301 /**
 302  * qup_i2c_wait_ready - wait for a give number of bytes in tx/rx path
 303  * @qup: The qup_i2c_dev device
 304  * @op: The bit/event to wait on
 305  * @val: value of the bit to wait on, 0 or 1
 306  * @len: The length the bytes to be transferred
 307  */
 308 static int qup_i2c_wait_ready(struct qup_i2c_dev *qup, int op, bool val,
 309                               int len)
 310 {
 311         unsigned long timeout;
 312         u32 opflags;
 313         u32 status;
 314         u32 shift = __ffs(op);
 315         int ret = 0;
 316
 317         len *= qup->one_byte_t;
 318         /* timeout after a wait of twice the max time */
 319         timeout = jiffies + len * 4;
 320
 321         for (;;) {
 322                 opflags = readl(qup->base + QUP_OPERATIONAL);
 323                 status = readl(qup->base + QUP_I2C_STATUS);
 324
 325                 if (((opflags & op) >> shift) == val) {
 326                         if ((op == QUP_OUT_NOT_EMPTY) && qup->is_last) {
 327                                 if (!(status & I2C_STATUS_BUS_ACTIVE)) {
 328                                         ret = 0;
 329                                         goto done;
 330                                 }
 331                         } else {
 332                                 ret = 0;
 333                                 goto done;
 334                         }
 335                 }
 336
 337                 if (time_after(jiffies, timeout)) {
 338                         ret = -ETIMEDOUT;
 339                         goto done;
 340                 }
 341                 usleep_range(len, len * 2);
 342         }
 343
 344 done:
 345         if (qup->bus_err || qup->qup_err)
 346                 ret =  (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO;
 347
 348         return ret;
 349 }
 350
 351 static void qup_i2c_set_write_mode_v2(struct qup_i2c_dev *qup,
 352                                       struct i2c_msg *msg)
 353 {
 354         /* Number of entries to shift out, including the tags */
 355         int total = msg->len + qup->blk.tx_tag_len;
 356
 357         total |= qup->config_run;
 358
 359         if (total < qup->out_fifo_sz) {
 360                 /* FIFO mode */
 361                 writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
 362                 writel(total, qup->base + QUP_MX_WRITE_CNT);
 363         } else {
 364                 /* BLOCK mode (transfer data on chunks) */
 365                 writel(QUP_OUTPUT_BLK_MODE | QUP_REPACK_EN,
 366                        qup->base + QUP_IO_MODE);
 367                 writel(total, qup->base + QUP_MX_OUTPUT_CNT);
 368         }
 369 }
 370
 371 static void qup_i2c_set_write_mode(struct qup_i2c_dev *qup, struct i2c_msg *msg)
 372 {
 373         /* Number of entries to shift out, including the start */
 374         int total = msg->len + 1;
 375
 376         if (total < qup->out_fifo_sz) {
 377                 /* FIFO mode */
 378                 writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
 379                 writel(total, qup->base + QUP_MX_WRITE_CNT);
 380         } else {
 381                 /* BLOCK mode (transfer data on chunks) */
 382                 writel(QUP_OUTPUT_BLK_MODE | QUP_REPACK_EN,
 383                        qup->base + QUP_IO_MODE);
 384                 writel(total, qup->base + QUP_MX_OUTPUT_CNT);
 385         }
 386 }
 387
 388 static int check_for_fifo_space(struct qup_i2c_dev *qup)
 389 {
 390         int ret;
 391
 392         ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
 393         if (ret)
 394                 goto out;
 395
 396         ret = qup_i2c_wait_ready(qup, QUP_OUT_FULL,
 397                                  RESET_BIT, 4 * ONE_BYTE);
 398         if (ret) {
 399                 /* Fifo is full. Drain out the fifo */
 400                 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
 401                 if (ret)
 402                         goto out;
 403
 404                 ret = qup_i2c_wait_ready(qup, QUP_OUT_NOT_EMPTY,
 405                                          RESET_BIT, 256 * ONE_BYTE);
 406                 if (ret) {
 407                         dev_err(qup->dev, "timeout for fifo out full");
 408                         goto out;
 409                 }
 410
 411                 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
 412                 if (ret)
 413                         goto out;
 414         }
 415
 416 out:
 417         return ret;
 418 }
 419
 420 static int qup_i2c_issue_write(struct qup_i2c_dev *qup, struct i2c_msg *msg)
 421 {
 422         u32 addr = msg->addr << 1;
 423         u32 qup_tag;
 424         int idx;
 425         u32 val;
 426         int ret = 0;
 427
 428         if (qup->pos == 0) {
 429                 val = QUP_TAG_START | addr;
 430                 idx = 1;
 431         } else {
 432                 val = 0;
 433                 idx = 0;
 434         }
 435
 436         while (qup->pos < msg->len) {
 437                 /* Check that there's space in the FIFO for our pair */
 438                 ret = check_for_fifo_space(qup);
 439                 if (ret)
 440                         return ret;
 441
 442                 if (qup->pos == msg->len - 1)
 443                         qup_tag = QUP_TAG_STOP;
 444                 else
 445                         qup_tag = QUP_TAG_DATA;
 446
 447                 if (idx & 1)
 448                         val |= (qup_tag | msg->buf[qup->pos]) << QUP_MSW_SHIFT;
 449                 else
 450                         val = qup_tag | msg->buf[qup->pos];
 451
 452                 /* Write out the pair and the last odd value */
 453                 if (idx & 1 || qup->pos == msg->len - 1)
 454                         writel(val, qup->base + QUP_OUT_FIFO_BASE);
 455
 456                 qup->pos++;
 457                 idx++;
 458         }
 459
 460         ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
 461
 462         return ret;
 463 }
 464
 465 static void qup_i2c_set_blk_data(struct qup_i2c_dev *qup,
 466                                  struct i2c_msg *msg)
 467 {
 468         memset(&qup->blk, 0, sizeof(qup->blk));
 469
 470         qup->blk.data_len = msg->len;
 471         qup->blk.count = (msg->len + QUP_READ_LIMIT - 1) / QUP_READ_LIMIT;
 472
 473         /* 4 bytes for first block and 2 writes for rest */
 474         qup->blk.tx_tag_len = 4 + (qup->blk.count - 1) * 2;
 475
 476         /* There are 2 tag bytes that are read in to fifo for every block */
 477         if (msg->flags & I2C_M_RD)
 478                 qup->blk.rx_tag_len = qup->blk.count * 2;
 479 }
 480
 481 static int qup_i2c_send_data(struct qup_i2c_dev *qup, int tlen, u8 *tbuf,
 482                              int dlen, u8 *dbuf)
 483 {
 484         u32 val = 0, idx = 0, pos = 0, i = 0, t;
 485         int  len = tlen + dlen;
 486         u8 *buf = tbuf;
 487         int ret = 0;
 488
 489         while (len > 0) {
 490                 ret = check_for_fifo_space(qup);
 491                 if (ret)
 492                         return ret;
 493
 494                 t = (len >= 4) ? 4 : len;
 495
 496                 while (idx < t) {
 497                         if (!i && (pos >= tlen)) {
 498                                 buf = dbuf;
 499                                 pos = 0;
 500                                 i = 1;
 501                         }
 502                         val |= buf[pos++] << (idx++ * 8);
 503                 }
 504
 505                 writel(val, qup->base + QUP_OUT_FIFO_BASE);
 506                 idx  = 0;
 507                 val = 0;
 508                 len -= 4;
 509         }
 510
 511         ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
 512
 513         return ret;
 514 }
 515
 516 static int qup_i2c_get_data_len(struct qup_i2c_dev *qup)
 517 {
 518         int data_len;
 519
 520         if (qup->blk.data_len > QUP_READ_LIMIT)
 521                 data_len = QUP_READ_LIMIT;
 522         else
 523                 data_len = qup->blk.data_len;
 524
 525         return data_len;
 526 }
 527
 528 static int qup_i2c_set_tags(u8 *tags, struct qup_i2c_dev *qup,
 529                             struct i2c_msg *msg,  int is_dma)
 530 {
 531         u16 addr = i2c_8bit_addr_from_msg(msg);
 532         int len = 0;
 533         int data_len;
 534
 535         int last = (qup->blk.pos == (qup->blk.count - 1)) && (qup->is_last);
 536
 537         if (qup->blk.pos == 0) {
 538                 tags[len++] = QUP_TAG_V2_START;
 539                 tags[len++] = addr & 0xff;
 540
 541                 if (msg->flags & I2C_M_TEN)
 542                         tags[len++] = addr >> 8;
 543         }
 544
 545         /* Send _STOP commands for the last block */
 546         if (last) {
 547                 if (msg->flags & I2C_M_RD)
 548                         tags[len++] = QUP_TAG_V2_DATARD_STOP;
 549                 else
 550                         tags[len++] = QUP_TAG_V2_DATAWR_STOP;
 551         } else {
 552                 if (msg->flags & I2C_M_RD)
 553                         tags[len++] = QUP_TAG_V2_DATARD;
 554                 else
 555                         tags[len++] = QUP_TAG_V2_DATAWR;
 556         }
 557
 558         data_len = qup_i2c_get_data_len(qup);
 559
 560         /* 0 implies 256 bytes */
 561         if (data_len == QUP_READ_LIMIT)
 562                 tags[len++] = 0;
 563         else
 564                 tags[len++] = data_len;
 565
 566         if ((msg->flags & I2C_M_RD) && last && is_dma) {
 567                 tags[len++] = QUP_BAM_INPUT_EOT;
 568                 tags[len++] = QUP_BAM_FLUSH_STOP;
 569         }
 570
 571         return len;
 572 }
 573
 574 static int qup_i2c_issue_xfer_v2(struct qup_i2c_dev *qup, struct i2c_msg *msg)
 575 {
 576         int data_len = 0, tag_len, index;
 577         int ret;
 578
 579         tag_len = qup_i2c_set_tags(qup->blk.tags, qup, msg, 0);
 580         index = msg->len - qup->blk.data_len;
 581
 582         /* only tags are written for read */
 583         if (!(msg->flags & I2C_M_RD))
 584                 data_len = qup_i2c_get_data_len(qup);
 585
 586         ret = qup_i2c_send_data(qup, tag_len, qup->blk.tags,
 587                                 data_len, &msg->buf[index]);
 588         qup->blk.data_len -= data_len;
 589
 590         return ret;
 591 }
 592
 593 static void qup_i2c_bam_cb(void *data)
 594 {
 595         struct qup_i2c_dev *qup = data;
 596
 597         complete(&qup->xfer);
 598 }
 599
 600 static int qup_sg_set_buf(struct scatterlist *sg, void *buf,
 601                           unsigned int buflen, struct qup_i2c_dev *qup,
 602                           int dir)
 603 {
 604         int ret;
 605
 606         sg_set_buf(sg, buf, buflen);
 607         ret = dma_map_sg(qup->dev, sg, 1, dir);
 608         if (!ret)
 609                 return -EINVAL;
 610
 611         return 0;
 612 }
 613
 614 static void qup_i2c_rel_dma(struct qup_i2c_dev *qup)
 615 {
 616         if (qup->btx.dma)
 617                 dma_release_channel(qup->btx.dma);
 618         if (qup->brx.dma)
 619                 dma_release_channel(qup->brx.dma);
 620         qup->btx.dma = NULL;
 621         qup->brx.dma = NULL;
 622 }
 623
 624 static int qup_i2c_req_dma(struct qup_i2c_dev *qup)
 625 {
 626         int err;
 627
 628         if (!qup->btx.dma) {
 629                 qup->btx.dma = dma_request_slave_channel_reason(qup->dev, "tx");
 630                 if (IS_ERR(qup->btx.dma)) {
 631                         err = PTR_ERR(qup->btx.dma);
 632                         qup->btx.dma = NULL;
 633                         dev_err(qup->dev, "\n tx channel not available");
 634                         return err;
 635                 }
 636         }
 637
 638         if (!qup->brx.dma) {
 639                 qup->brx.dma = dma_request_slave_channel_reason(qup->dev, "rx");
 640                 if (IS_ERR(qup->brx.dma)) {
 641                         dev_err(qup->dev, "\n rx channel not available");
 642                         err = PTR_ERR(qup->brx.dma);
 643                         qup->brx.dma = NULL;
 644                         qup_i2c_rel_dma(qup);
 645                         return err;
 646                 }
 647         }
 648         return 0;
 649 }
 650
 651 static int qup_i2c_bam_do_xfer(struct qup_i2c_dev *qup, struct i2c_msg *msg,
 652                                int num)
 653 {
 654         struct dma_async_tx_descriptor *txd, *rxd = NULL;
 655         int ret = 0, idx = 0, limit = QUP_READ_LIMIT;
 656         dma_cookie_t cookie_rx, cookie_tx;
 657         u32 rx_nents = 0, tx_nents = 0, len, blocks, rem;
 658         u32 i, tlen, tx_len, tx_buf = 0, rx_buf = 0, off = 0;
 659         u8 *tags;
 660
 661         while (idx < num) {
 662                 tx_len = 0, len = 0, i = 0;
 663
 664                 qup->is_last = (idx == (num - 1));
 665
 666                 qup_i2c_set_blk_data(qup, msg);
 667
 668                 blocks = qup->blk.count;
 669                 rem = msg->len - (blocks - 1) * limit;
 670
 671                 if (msg->flags & I2C_M_RD) {
 672                         rx_nents += (blocks * 2) + 1;
 673                         tx_nents += 1;
 674
 675                         while (qup->blk.pos < blocks) {
 676                                 tlen = (i == (blocks - 1)) ? rem : limit;
 677                                 tags = &qup->start_tag.start[off + len];
 678                                 len += qup_i2c_set_tags(tags, qup, msg, 1);
 679                                 qup->blk.data_len -= tlen;
 680
 681                                 /* scratch buf to read the start and len tags */
 682                                 ret = qup_sg_set_buf(&qup->brx.sg[rx_buf++],
 683                                                      &qup->brx.tag.start[0],
 684                                                      2, qup, DMA_FROM_DEVICE);
 685
 686                                 if (ret)
 687                                         return ret;
 688
 689                                 ret = qup_sg_set_buf(&qup->brx.sg[rx_buf++],
 690                                                      &msg->buf[limit * i],
 691                                                      tlen, qup,
 692                                                      DMA_FROM_DEVICE);
 693                                 if (ret)
 694                                         return ret;
 695
 696                                 i++;
 697                                 qup->blk.pos = i;
 698                         }
 699                         ret = qup_sg_set_buf(&qup->btx.sg[tx_buf++],
 700                                              &qup->start_tag.start[off],
 701                                              len, qup, DMA_TO_DEVICE);
 702                         if (ret)
 703                                 return ret;
 704
 705                         off += len;
 706                         /* scratch buf to read the BAM EOT and FLUSH tags */
 707                         ret = qup_sg_set_buf(&qup->brx.sg[rx_buf++],
 708                                              &qup->brx.tag.start[0],
 709                                              2, qup, DMA_FROM_DEVICE);
 710                         if (ret)
 711                                 return ret;
 712                 } else {
 713                         tx_nents += (blocks * 2);
 714
 715                         while (qup->blk.pos < blocks) {
 716                                 tlen = (i == (blocks - 1)) ? rem : limit;
 717                                 tags = &qup->start_tag.start[off + tx_len];
 718                                 len = qup_i2c_set_tags(tags, qup, msg, 1);
 719                                 qup->blk.data_len -= tlen;
 720
 721                                 ret = qup_sg_set_buf(&qup->btx.sg[tx_buf++],
 722                                                      tags, len,
 723                                                      qup, DMA_TO_DEVICE);
 724                                 if (ret)
 725                                         return ret;
 726
 727                                 tx_len += len;
 728                                 ret = qup_sg_set_buf(&qup->btx.sg[tx_buf++],
 729                                                      &msg->buf[limit * i],
 730                                                      tlen, qup, DMA_TO_DEVICE);
 731                                 if (ret)
 732                                         return ret;
 733                                 i++;
 734                                 qup->blk.pos = i;
 735                         }
 736                         off += tx_len;
 737
 738                         if (idx == (num - 1)) {
 739                                 len = 1;
 740                                 if (rx_nents) {
 741                                         qup->btx.tag.start[0] =
 742                                                         QUP_BAM_INPUT_EOT;
 743                                         len++;
 744                                 }
 745                                 qup->btx.tag.start[len - 1] =
 746                                                         QUP_BAM_FLUSH_STOP;
 747                                 ret = qup_sg_set_buf(&qup->btx.sg[tx_buf++],
 748                                                      &qup->btx.tag.start[0],
 749                                                      len, qup, DMA_TO_DEVICE);
 750                                 if (ret)
 751                                         return ret;
 752                                 tx_nents += 1;
 753                         }
 754                 }
 755                 idx++;
 756                 msg++;
 757         }
 758
 759         txd = dmaengine_prep_slave_sg(qup->btx.dma, qup->btx.sg, tx_nents,
 760                                       DMA_MEM_TO_DEV,
 761                                       DMA_PREP_INTERRUPT | DMA_PREP_FENCE);
 762         if (!txd) {
 763                 dev_err(qup->dev, "failed to get tx desc\n");
 764                 ret = -EINVAL;
 765                 goto desc_err;
 766         }
 767
 768         if (!rx_nents) {
 769                 txd->callback = qup_i2c_bam_cb;
 770                 txd->callback_param = qup;
 771         }
 772
 773         cookie_tx = dmaengine_submit(txd);
 774         if (dma_submit_error(cookie_tx)) {
 775                 ret = -EINVAL;
 776                 goto desc_err;
 777         }
 778
 779         dma_async_issue_pending(qup->btx.dma);
 780
 781         if (rx_nents) {
 782                 rxd = dmaengine_prep_slave_sg(qup->brx.dma, qup->brx.sg,
 783                                               rx_nents, DMA_DEV_TO_MEM,
 784                                               DMA_PREP_INTERRUPT);
 785                 if (!rxd) {
 786                         dev_err(qup->dev, "failed to get rx desc\n");
 787                         ret = -EINVAL;
 788
 789                         /* abort TX descriptors */
 790                         dmaengine_terminate_all(qup->btx.dma);
 791                         goto desc_err;
 792                 }
 793
 794                 rxd->callback = qup_i2c_bam_cb;
 795                 rxd->callback_param = qup;
 796                 cookie_rx = dmaengine_submit(rxd);
 797                 if (dma_submit_error(cookie_rx)) {
 798                         ret = -EINVAL;
 799                         goto desc_err;
 800                 }
 801
 802                 dma_async_issue_pending(qup->brx.dma);
 803         }
 804
 805         if (!wait_for_completion_timeout(&qup->xfer, TOUT_MAX * HZ)) {
 806                 dev_err(qup->dev, "normal trans timed out\n");
 807                 ret = -ETIMEDOUT;
 808         }
 809
 810         if (ret || qup->bus_err || qup->qup_err) {
 811                 reinit_completion(&qup->xfer);
 812
 813                 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
 814                 if (ret) {
 815                         dev_err(qup->dev, "change to run state timed out");
 816                         goto desc_err;
 817                 }
 818
 819                 if (rx_nents)
 820                         writel(QUP_BAM_INPUT_EOT,
 821                                qup->base + QUP_OUT_FIFO_BASE);
 822
 823                 writel(QUP_BAM_FLUSH_STOP, qup->base + QUP_OUT_FIFO_BASE);
 824
 825                 qup_i2c_flush(qup);
 826
 827                 /* wait for remaining interrupts to occur */
 828                 if (!wait_for_completion_timeout(&qup->xfer, HZ))
 829                         dev_err(qup->dev, "flush timed out\n");
 830
 831                 qup_i2c_rel_dma(qup);
 832
 833                 ret =  (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO;
 834         }
 835
 836 desc_err:
 837         dma_unmap_sg(qup->dev, qup->btx.sg, tx_nents, DMA_TO_DEVICE);
 838
 839         if (rx_nents)
 840                 dma_unmap_sg(qup->dev, qup->brx.sg, rx_nents,
 841                              DMA_FROM_DEVICE);
 842
 843         return ret;
 844 }
 845
 846 static int qup_i2c_bam_xfer(struct i2c_adapter *adap, struct i2c_msg *msg,
 847                             int num)
 848 {
 849         struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
 850         int ret = 0;
 851
 852         enable_irq(qup->irq);
 853         ret = qup_i2c_req_dma(qup);
 854
 855         if (ret)
 856                 goto out;
 857
 858         writel(0, qup->base + QUP_MX_INPUT_CNT);
 859         writel(0, qup->base + QUP_MX_OUTPUT_CNT);
 860
 861         /* set BAM mode */
 862         writel(QUP_REPACK_EN | QUP_BAM_MODE, qup->base + QUP_IO_MODE);
 863
 864         /* mask fifo irqs */
 865         writel((0x3 << 8), qup->base + QUP_OPERATIONAL_MASK);
 866
 867         /* set RUN STATE */
 868         ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
 869         if (ret)
 870                 goto out;
 871
 872         writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
 873
 874         qup->msg = msg;
 875         ret = qup_i2c_bam_do_xfer(qup, qup->msg, num);
 876 out:
 877         disable_irq(qup->irq);
 878
 879         qup->msg = NULL;
 880         return ret;
 881 }
 882
 883 static int qup_i2c_wait_for_complete(struct qup_i2c_dev *qup,
 884                                      struct i2c_msg *msg)
 885 {
 886         unsigned long left;
 887         int ret = 0;
 888
 889         left = wait_for_completion_timeout(&qup->xfer, HZ);
 890         if (!left) {
 891                 writel(1, qup->base + QUP_SW_RESET);
 892                 ret = -ETIMEDOUT;
 893         }
 894
 895         if (qup->bus_err || qup->qup_err)
 896                 ret =  (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO;
 897
 898         return ret;
 899 }
 900
 901 static int qup_i2c_write_one_v2(struct qup_i2c_dev *qup, struct i2c_msg *msg)
 902 {
 903         int ret = 0;
 904
 905         qup->msg = msg;
 906         qup->pos = 0;
 907         enable_irq(qup->irq);
 908         qup_i2c_set_blk_data(qup, msg);
 909         qup_i2c_set_write_mode_v2(qup, msg);
 910
 911         ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
 912         if (ret)
 913                 goto err;
 914
 915         writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
 916
 917         do {
 918                 ret = qup_i2c_issue_xfer_v2(qup, msg);
 919                 if (ret)
 920                         goto err;
 921
 922                 ret = qup_i2c_wait_for_complete(qup, msg);
 923                 if (ret)
 924                         goto err;
 925
 926                 qup->blk.pos++;
 927         } while (qup->blk.pos < qup->blk.count);
 928
 929         ret = qup_i2c_wait_ready(qup, QUP_OUT_NOT_EMPTY, RESET_BIT, ONE_BYTE);
 930
 931 err:
 932         disable_irq(qup->irq);
 933         qup->msg = NULL;
 934
 935         return ret;
 936 }
 937
 938 static int qup_i2c_write_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)
 939 {
 940         int ret;
 941
 942         qup->msg = msg;
 943         qup->pos = 0;
 944
 945         enable_irq(qup->irq);
 946
 947         qup_i2c_set_write_mode(qup, msg);
 948
 949         ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
 950         if (ret)
 951                 goto err;
 952
 953         writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
 954
 955         do {
 956                 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
 957                 if (ret)
 958                         goto err;
 959
 960                 ret = qup_i2c_issue_write(qup, msg);
 961                 if (ret)
 962                         goto err;
 963
 964                 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
 965                 if (ret)
 966                         goto err;
 967
 968                 ret = qup_i2c_wait_for_complete(qup, msg);
 969                 if (ret)
 970                         goto err;
 971         } while (qup->pos < msg->len);
 972
 973         /* Wait for the outstanding data in the fifo to drain */
 974         ret = qup_i2c_wait_ready(qup, QUP_OUT_NOT_EMPTY, RESET_BIT, ONE_BYTE);
 975 err:
 976         disable_irq(qup->irq);
 977         qup->msg = NULL;
 978
 979         return ret;
 980 }
 981
 982 static void qup_i2c_set_read_mode(struct qup_i2c_dev *qup, int len)
 983 {
 984         if (len < qup->in_fifo_sz) {
 985                 /* FIFO mode */
 986                 writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
 987                 writel(len, qup->base + QUP_MX_READ_CNT);
 988         } else {
 989                 /* BLOCK mode (transfer data on chunks) */
 990                 writel(QUP_INPUT_BLK_MODE | QUP_REPACK_EN,
 991                        qup->base + QUP_IO_MODE);
 992                 writel(len, qup->base + QUP_MX_INPUT_CNT);
 993         }
 994 }
 995
 996 static void qup_i2c_set_read_mode_v2(struct qup_i2c_dev *qup, int len)
 997 {
 998         int tx_len = qup->blk.tx_tag_len;
 999
1000         len += qup->blk.rx_tag_len;
1001         len |= qup->config_run;
1002         tx_len |= qup->config_run;
1003
1004         if (len < qup->in_fifo_sz) {
1005                 /* FIFO mode */
1006                 writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
1007                 writel(tx_len, qup->base + QUP_MX_WRITE_CNT);
1008                 writel(len, qup->base + QUP_MX_READ_CNT);
1009         } else {
1010                 /* BLOCK mode (transfer data on chunks) */
1011                 writel(QUP_INPUT_BLK_MODE | QUP_REPACK_EN,
1012                        qup->base + QUP_IO_MODE);
1013                 writel(tx_len, qup->base + QUP_MX_OUTPUT_CNT);
1014                 writel(len, qup->base + QUP_MX_INPUT_CNT);
1015         }
1016 }
1017
1018 static void qup_i2c_issue_read(struct qup_i2c_dev *qup, struct i2c_msg *msg)
1019 {
1020         u32 addr, len, val;
1021
1022         addr = i2c_8bit_addr_from_msg(msg);
1023
1024         /* 0 is used to specify a length 256 (QUP_READ_LIMIT) */
1025         len = (msg->len == QUP_READ_LIMIT) ? 0 : msg->len;
1026
1027         val = ((QUP_TAG_REC | len) << QUP_MSW_SHIFT) | QUP_TAG_START | addr;
1028         writel(val, qup->base + QUP_OUT_FIFO_BASE);
1029 }
1030
1031
1032 static int qup_i2c_read_fifo(struct qup_i2c_dev *qup, struct i2c_msg *msg)
1033 {
1034         u32 val = 0;
1035         int idx;
1036         int ret = 0;
1037
1038         for (idx = 0; qup->pos < msg->len; idx++) {
1039                 if ((idx & 1) == 0) {
1040                         /* Check that FIFO have data */
1041                         ret = qup_i2c_wait_ready(qup, QUP_IN_NOT_EMPTY,
1042                                                  SET_BIT, 4 * ONE_BYTE);
1043                         if (ret)
1044                                 return ret;
1045
1046                         /* Reading 2 words at time */
1047                         val = readl(qup->base + QUP_IN_FIFO_BASE);
1048
1049                         msg->buf[qup->pos++] = val & 0xFF;
1050                 } else {
1051                         msg->buf[qup->pos++] = val >> QUP_MSW_SHIFT;
1052                 }
1053         }
1054
1055         return ret;
1056 }
1057
1058 static int qup_i2c_read_fifo_v2(struct qup_i2c_dev *qup,
1059                                 struct i2c_msg *msg)
1060 {
1061         u32 val;
1062         int idx, pos = 0, ret = 0, total;
1063
1064         total = qup_i2c_get_data_len(qup);
1065
1066         /* 2 extra bytes for read tags */
1067         while (pos < (total + 2)) {
1068                 /* Check that FIFO have data */
1069                 ret = qup_i2c_wait_ready(qup, QUP_IN_NOT_EMPTY,
1070                                          SET_BIT, 4 * ONE_BYTE);
1071                 if (ret) {
1072                         dev_err(qup->dev, "timeout for fifo not empty");
1073                         return ret;
1074                 }
1075                 val = readl(qup->base + QUP_IN_FIFO_BASE);
1076
1077                 for (idx = 0; idx < 4; idx++, val >>= 8, pos++) {
1078                         /* first 2 bytes are tag bytes */
1079                         if (pos < 2)
1080                                 continue;
1081
1082                         if (pos >= (total + 2))
1083                                 goto out;
1084
1085                         msg->buf[qup->pos++] = val & 0xff;
1086                 }
1087         }
1088
1089 out:
1090         qup->blk.data_len -= total;
1091
1092         return ret;
1093 }
1094
1095 static int qup_i2c_read_one_v2(struct qup_i2c_dev *qup, struct i2c_msg *msg)
1096 {
1097         int ret = 0;
1098
1099         qup->msg = msg;
1100         qup->pos  = 0;
1101         enable_irq(qup->irq);
1102         qup_i2c_set_blk_data(qup, msg);
1103         qup_i2c_set_read_mode_v2(qup, msg->len);
1104
1105         ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1106         if (ret)
1107                 goto err;
1108
1109         writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
1110
1111         do {
1112                 ret = qup_i2c_issue_xfer_v2(qup, msg);
1113                 if (ret)
1114                         goto err;
1115
1116                 ret = qup_i2c_wait_for_complete(qup, msg);
1117                 if (ret)
1118                         goto err;
1119
1120                 ret = qup_i2c_read_fifo_v2(qup, msg);
1121                 if (ret)
1122                         goto err;
1123
1124                 qup->blk.pos++;
1125         } while (qup->blk.pos < qup->blk.count);
1126
1127 err:
1128         disable_irq(qup->irq);
1129         qup->msg = NULL;
1130
1131         return ret;
1132 }
1133
1134 static int qup_i2c_read_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)
1135 {
1136         int ret;
1137
1138         qup->msg = msg;
1139         qup->pos  = 0;
1140
1141         enable_irq(qup->irq);
1142         qup_i2c_set_read_mode(qup, msg->len);
1143
1144         ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1145         if (ret)
1146                 goto err;
1147
1148         writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
1149
1150         ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
1151         if (ret)
1152                 goto err;
1153
1154         qup_i2c_issue_read(qup, msg);
1155
1156         ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1157         if (ret)
1158                 goto err;
1159
1160         do {
1161                 ret = qup_i2c_wait_for_complete(qup, msg);
1162                 if (ret)
1163                         goto err;
1164
1165                 ret = qup_i2c_read_fifo(qup, msg);
1166                 if (ret)
1167                         goto err;
1168         } while (qup->pos < msg->len);
1169
1170 err:
1171         disable_irq(qup->irq);
1172         qup->msg = NULL;
1173
1174         return ret;
1175 }
1176
1177 static int qup_i2c_xfer(struct i2c_adapter *adap,
1178                         struct i2c_msg msgs[],
1179                         int num)
1180 {
1181         struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
1182         int ret, idx;
1183
1184         ret = pm_runtime_get_sync(qup->dev);
1185         if (ret < 0)
1186                 goto out;
1187
1188         qup->bus_err = 0;
1189         qup->qup_err = 0;
1190
1191         writel(1, qup->base + QUP_SW_RESET);
1192         ret = qup_i2c_poll_state(qup, QUP_RESET_STATE);
1193         if (ret)
1194                 goto out;
1195
1196         /* Configure QUP as I2C mini core */
1197         writel(I2C_MINI_CORE | I2C_N_VAL, qup->base + QUP_CONFIG);
1198
1199         for (idx = 0; idx < num; idx++) {
1200                 if (msgs[idx].len == 0) {
1201                         ret = -EINVAL;
1202                         goto out;
1203                 }
1204
1205                 if (qup_i2c_poll_state_i2c_master(qup)) {
1206                         ret = -EIO;
1207                         goto out;
1208                 }
1209
1210                 if (msgs[idx].flags & I2C_M_RD)
1211                         ret = qup_i2c_read_one(qup, &msgs[idx]);
1212                 else
1213                         ret = qup_i2c_write_one(qup, &msgs[idx]);
1214
1215                 if (ret)
1216                         break;
1217
1218                 ret = qup_i2c_change_state(qup, QUP_RESET_STATE);
1219                 if (ret)
1220                         break;
1221         }
1222
1223         if (ret == 0)
1224                 ret = num;
1225 out:
1226
1227         pm_runtime_mark_last_busy(qup->dev);
1228         pm_runtime_put_autosuspend(qup->dev);
1229
1230         return ret;
1231 }
1232
1233 static int qup_i2c_xfer_v2(struct i2c_adapter *adap,
1234                            struct i2c_msg msgs[],
1235                            int num)
1236 {
1237         struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
1238         int ret, len, idx = 0, use_dma = 0;
1239
1240         qup->bus_err = 0;
1241         qup->qup_err = 0;
1242
1243         ret = pm_runtime_get_sync(qup->dev);
1244         if (ret < 0)
1245                 goto out;
1246
1247         writel(1, qup->base + QUP_SW_RESET);
1248         ret = qup_i2c_poll_state(qup, QUP_RESET_STATE);
1249         if (ret)
1250                 goto out;
1251
1252         /* Configure QUP as I2C mini core */
1253         writel(I2C_MINI_CORE | I2C_N_VAL_V2, qup->base + QUP_CONFIG);
1254         writel(QUP_V2_TAGS_EN, qup->base + QUP_I2C_MASTER_GEN);
1255
1256         if ((qup->is_dma)) {
1257                 /* All i2c_msgs should be transferred using either dma or cpu */
1258                 for (idx = 0; idx < num; idx++) {
1259                         if (msgs[idx].len == 0) {
1260                                 ret = -EINVAL;
1261                                 goto out;
1262                         }
1263
1264                         len = (msgs[idx].len > qup->out_fifo_sz) ||
1265                               (msgs[idx].len > qup->in_fifo_sz);
1266
1267                         if ((!is_vmalloc_addr(msgs[idx].buf)) && len) {
1268                                 use_dma = 1;
1269                          } else {
1270                                 use_dma = 0;
1271                                 break;
1272                         }
1273                 }
1274         }
1275
1276         idx = 0;
1277
1278         do {
1279                 if (msgs[idx].len == 0) {
1280                         ret = -EINVAL;
1281                         goto out;
1282                 }
1283
1284                 if (qup_i2c_poll_state_i2c_master(qup)) {
1285                         ret = -EIO;
1286                         goto out;
1287                 }
1288
1289                 qup->is_last = (idx == (num - 1));
1290                 if (idx)
1291                         qup->config_run = QUP_I2C_MX_CONFIG_DURING_RUN;
1292                 else
1293                         qup->config_run = 0;
1294
1295                 reinit_completion(&qup->xfer);
1296
1297                 if (use_dma) {
1298                         ret = qup_i2c_bam_xfer(adap, &msgs[idx], num);
1299                 } else {
1300                         if (msgs[idx].flags & I2C_M_RD)
1301                                 ret = qup_i2c_read_one_v2(qup, &msgs[idx]);
1302                         else
1303                                 ret = qup_i2c_write_one_v2(qup, &msgs[idx]);
1304                 }
1305         } while ((idx++ < (num - 1)) && !use_dma && !ret);
1306
1307         if (!ret)
1308                 ret = qup_i2c_change_state(qup, QUP_RESET_STATE);
1309
1310         if (ret == 0)
1311                 ret = num;
1312 out:
1313         pm_runtime_mark_last_busy(qup->dev);
1314         pm_runtime_put_autosuspend(qup->dev);
1315
1316         return ret;
1317 }
1318
1319 static u32 qup_i2c_func(struct i2c_adapter *adap)
1320 {
1321         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
1322 }
1323
1324 static const struct i2c_algorithm qup_i2c_algo = {
1325         .master_xfer    = qup_i2c_xfer,
1326         .functionality  = qup_i2c_func,
1327 };
1328
1329 static const struct i2c_algorithm qup_i2c_algo_v2 = {
1330         .master_xfer    = qup_i2c_xfer_v2,
1331         .functionality  = qup_i2c_func,
1332 };
1333
1334 /*
1335  * The QUP block will issue a NACK and STOP on the bus when reaching
1336  * the end of the read, the length of the read is specified as one byte
1337  * which limits the possible read to 256 (QUP_READ_LIMIT) bytes.
1338  */
1339 static struct i2c_adapter_quirks qup_i2c_quirks = {
1340         .max_read_len = QUP_READ_LIMIT,
1341 };
1342
1343 static void qup_i2c_enable_clocks(struct qup_i2c_dev *qup)
1344 {
1345         clk_prepare_enable(qup->clk);
1346         clk_prepare_enable(qup->pclk);
1347 }
1348
1349 static void qup_i2c_disable_clocks(struct qup_i2c_dev *qup)
1350 {
1351         u32 config;
1352
1353         qup_i2c_change_state(qup, QUP_RESET_STATE);
1354         clk_disable_unprepare(qup->clk);
1355         config = readl(qup->base + QUP_CONFIG);
1356         config |= QUP_CLOCK_AUTO_GATE;
1357         writel(config, qup->base + QUP_CONFIG);
1358         clk_disable_unprepare(qup->pclk);
1359 }
1360
1361 static int qup_i2c_probe(struct platform_device *pdev)
1362 {
1363         static const int blk_sizes[] = {4, 16, 32};
1364         struct device_node *node = pdev->dev.of_node;
1365         struct qup_i2c_dev *qup;
1366         unsigned long one_bit_t;
1367         struct resource *res;
1368         u32 io_mode, hw_ver, size;
1369         int ret, fs_div, hs_div;
1370         int src_clk_freq;
1371         u32 clk_freq = 100000;
1372         int blocks;
1373
1374         qup = devm_kzalloc(&pdev->dev, sizeof(*qup), GFP_KERNEL);
1375         if (!qup)
1376                 return -ENOMEM;
1377
1378         qup->dev = &pdev->dev;
1379         init_completion(&qup->xfer);
1380         platform_set_drvdata(pdev, qup);
1381
1382         of_property_read_u32(node, "clock-frequency", &clk_freq);
1383
1384         if (of_device_is_compatible(pdev->dev.of_node, "qcom,i2c-qup-v1.1.1")) {
1385                 qup->adap.algo = &qup_i2c_algo;
1386                 qup->adap.quirks = &qup_i2c_quirks;
1387         } else {
1388                 qup->adap.algo = &qup_i2c_algo_v2;
1389                 ret = qup_i2c_req_dma(qup);
1390
1391                 if (ret == -EPROBE_DEFER)
1392                         goto fail_dma;
1393                 else if (ret != 0)
1394                         goto nodma;
1395
1396                 blocks = (MX_BLOCKS << 1) + 1;
1397                 qup->btx.sg = devm_kzalloc(&pdev->dev,
1398                                            sizeof(*qup->btx.sg) * blocks,
1399                                            GFP_KERNEL);
1400                 if (!qup->btx.sg) {
1401                         ret = -ENOMEM;
1402                         goto fail_dma;
1403                 }
1404                 sg_init_table(qup->btx.sg, blocks);
1405
1406                 qup->brx.sg = devm_kzalloc(&pdev->dev,
1407                                            sizeof(*qup->brx.sg) * blocks,
1408                                            GFP_KERNEL);
1409                 if (!qup->brx.sg) {
1410                         ret = -ENOMEM;
1411                         goto fail_dma;
1412                 }
1413                 sg_init_table(qup->brx.sg, blocks);
1414
1415                 /* 2 tag bytes for each block + 5 for start, stop tags */
1416                 size = blocks * 2 + 5;
1417
1418                 qup->start_tag.start = devm_kzalloc(&pdev->dev,
1419                                                     size, GFP_KERNEL);
1420                 if (!qup->start_tag.start) {
1421                         ret = -ENOMEM;
1422                         goto fail_dma;
1423                 }
1424
1425                 qup->brx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL);
1426                 if (!qup->brx.tag.start) {
1427                         ret = -ENOMEM;
1428                         goto fail_dma;
1429                 }
1430
1431                 qup->btx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL);
1432                 if (!qup->btx.tag.start) {
1433                         ret = -ENOMEM;
1434                         goto fail_dma;
1435                 }
1436                 qup->is_dma = true;
1437         }
1438
1439 nodma:
1440         /* We support frequencies up to FAST Mode (400KHz) */
1441         if (!clk_freq || clk_freq > 400000) {
1442                 dev_err(qup->dev, "clock frequency not supported %d\n",
1443                         clk_freq);
1444                 return -EINVAL;
1445         }
1446
1447         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1448         qup->base = devm_ioremap_resource(qup->dev, res);
1449         if (IS_ERR(qup->base))
1450                 return PTR_ERR(qup->base);
1451
1452         qup->irq = platform_get_irq(pdev, 0);
1453         if (qup->irq < 0) {
1454                 dev_err(qup->dev, "No IRQ defined\n");
1455                 return qup->irq;
1456         }
1457
1458         qup->clk = devm_clk_get(qup->dev, "core");
1459         if (IS_ERR(qup->clk)) {
1460                 dev_err(qup->dev, "Could not get core clock\n");
1461                 return PTR_ERR(qup->clk);
1462         }
1463
1464         qup->pclk = devm_clk_get(qup->dev, "iface");
1465         if (IS_ERR(qup->pclk)) {
1466                 dev_err(qup->dev, "Could not get iface clock\n");
1467                 return PTR_ERR(qup->pclk);
1468         }
1469
1470         qup_i2c_enable_clocks(qup);
1471
1472         /*
1473          * Bootloaders might leave a pending interrupt on certain QUP's,
1474          * so we reset the core before registering for interrupts.
1475          */
1476         writel(1, qup->base + QUP_SW_RESET);
1477         ret = qup_i2c_poll_state_valid(qup);
1478         if (ret)
1479                 goto fail;
1480
1481         ret = devm_request_irq(qup->dev, qup->irq, qup_i2c_interrupt,
1482                                IRQF_TRIGGER_HIGH, "i2c_qup", qup);
1483         if (ret) {
1484                 dev_err(qup->dev, "Request %d IRQ failed\n", qup->irq);
1485                 goto fail;
1486         }
1487         disable_irq(qup->irq);
1488
1489         hw_ver = readl(qup->base + QUP_HW_VERSION);
1490         dev_dbg(qup->dev, "Revision %x\n", hw_ver);
1491
1492         io_mode = readl(qup->base + QUP_IO_MODE);
1493
1494         /*
1495          * The block/fifo size w.r.t. 'actual data' is 1/2 due to 'tag'
1496          * associated with each byte written/received
1497          */
1498         size = QUP_OUTPUT_BLOCK_SIZE(io_mode);
1499         if (size >= ARRAY_SIZE(blk_sizes)) {
1500                 ret = -EIO;
1501                 goto fail;
1502         }
1503         qup->out_blk_sz = blk_sizes[size] / 2;
1504
1505         size = QUP_INPUT_BLOCK_SIZE(io_mode);
1506         if (size >= ARRAY_SIZE(blk_sizes)) {
1507                 ret = -EIO;
1508                 goto fail;
1509         }
1510         qup->in_blk_sz = blk_sizes[size] / 2;
1511
1512         size = QUP_OUTPUT_FIFO_SIZE(io_mode);
1513         qup->out_fifo_sz = qup->out_blk_sz * (2 << size);
1514
1515         size = QUP_INPUT_FIFO_SIZE(io_mode);
1516         qup->in_fifo_sz = qup->in_blk_sz * (2 << size);
1517
1518         src_clk_freq = clk_get_rate(qup->clk);
1519         fs_div = ((src_clk_freq / clk_freq) / 2) - 3;
1520         hs_div = 3;
1521         qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff);
1522
1523         /*
1524          * Time it takes for a byte to be clocked out on the bus.
1525          * Each byte takes 9 clock cycles (8 bits + 1 ack).
1526          */
1527         one_bit_t = (USEC_PER_SEC / clk_freq) + 1;
1528         qup->one_byte_t = one_bit_t * 9;
1529
1530         dev_dbg(qup->dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",
1531                 qup->in_blk_sz, qup->in_fifo_sz,
1532                 qup->out_blk_sz, qup->out_fifo_sz);
1533
1534         i2c_set_adapdata(&qup->adap, qup);
1535         qup->adap.dev.parent = qup->dev;
1536         qup->adap.dev.of_node = pdev->dev.of_node;
1537         qup->is_last = true;
1538
1539         strlcpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name));
1540
1541         pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC);
1542         pm_runtime_use_autosuspend(qup->dev);
1543         pm_runtime_set_active(qup->dev);
1544         pm_runtime_enable(qup->dev);
1545
1546         ret = i2c_add_adapter(&qup->adap);
1547         if (ret)
1548                 goto fail_runtime;
1549
1550         return 0;
1551
1552 fail_runtime:
1553         pm_runtime_disable(qup->dev);
1554         pm_runtime_set_suspended(qup->dev);
1555 fail:
1556         qup_i2c_disable_clocks(qup);
1557 fail_dma:
1558         if (qup->btx.dma)
1559                 dma_release_channel(qup->btx.dma);
1560         if (qup->brx.dma)
1561                 dma_release_channel(qup->brx.dma);
1562         return ret;
1563 }
1564
1565 static int qup_i2c_remove(struct platform_device *pdev)
1566 {
1567         struct qup_i2c_dev *qup = platform_get_drvdata(pdev);
1568
1569         if (qup->is_dma) {
1570                 dma_release_channel(qup->btx.dma);
1571                 dma_release_channel(qup->brx.dma);
1572         }
1573
1574         disable_irq(qup->irq);
1575         qup_i2c_disable_clocks(qup);
1576         i2c_del_adapter(&qup->adap);
1577         pm_runtime_disable(qup->dev);
1578         pm_runtime_set_suspended(qup->dev);
1579         return 0;
1580 }
1581
1582 #ifdef CONFIG_PM
1583 static int qup_i2c_pm_suspend_runtime(struct device *device)
1584 {
1585         struct qup_i2c_dev *qup = dev_get_drvdata(device);
1586
1587         dev_dbg(device, "pm_runtime: suspending...\n");
1588         qup_i2c_disable_clocks(qup);
1589         return 0;
1590 }
1591
1592 static int qup_i2c_pm_resume_runtime(struct device *device)
1593 {
1594         struct qup_i2c_dev *qup = dev_get_drvdata(device);
1595
1596         dev_dbg(device, "pm_runtime: resuming...\n");
1597         qup_i2c_enable_clocks(qup);
1598         return 0;
1599 }
1600 #endif
1601
1602 #ifdef CONFIG_PM_SLEEP
1603 static int qup_i2c_suspend(struct device *device)
1604 {
1605         if (!pm_runtime_suspended(device))
1606                 return qup_i2c_pm_suspend_runtime(device);
1607         return 0;
1608 }
1609
1610 static int qup_i2c_resume(struct device *device)
1611 {
1612         qup_i2c_pm_resume_runtime(device);
1613         pm_runtime_mark_last_busy(device);
1614         pm_request_autosuspend(device);
1615         return 0;
1616 }
1617 #endif
1618
1619 static const struct dev_pm_ops qup_i2c_qup_pm_ops = {
1620         SET_SYSTEM_SLEEP_PM_OPS(
1621                 qup_i2c_suspend,
1622                 qup_i2c_resume)
1623         SET_RUNTIME_PM_OPS(
1624                 qup_i2c_pm_suspend_runtime,
1625                 qup_i2c_pm_resume_runtime,
1626                 NULL)
1627 };
1628
1629 static const struct of_device_id qup_i2c_dt_match[] = {
1630         { .compatible = "qcom,i2c-qup-v1.1.1" },
1631         { .compatible = "qcom,i2c-qup-v2.1.1" },
1632         { .compatible = "qcom,i2c-qup-v2.2.1" },
1633         {}
1634 };
1635 MODULE_DEVICE_TABLE(of, qup_i2c_dt_match);
1636
1637 static struct platform_driver qup_i2c_driver = {
1638         .probe  = qup_i2c_probe,
1639         .remove = qup_i2c_remove,
1640         .driver = {
1641                 .name = "i2c_qup",
1642                 .pm = &qup_i2c_qup_pm_ops,
1643                 .of_match_table = qup_i2c_dt_match,
1644         },
1645 };
1646
1647 module_platform_driver(qup_i2c_driver);
1648
1649 MODULE_LICENSE("GPL v2");
1650 MODULE_ALIAS("platform:i2c_qup");