drivers/i2c/busses/i2c-s3c2410.c

   1 /* linux/drivers/i2c/busses/i2c-s3c2410.c
   2  *
   3  * Copyright (C) 2004,2005,2009 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * S3C2410 I2C Controller
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17 */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21
  22 #include <linux/i2c.h>
  23 #include <linux/init.h>
  24 #include <linux/time.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/delay.h>
  27 #include <linux/errno.h>
  28 #include <linux/err.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/clk.h>
  32 #include <linux/cpufreq.h>
  33 #include <linux/slab.h>
  34 #include <linux/io.h>
  35 #include <linux/of.h>
  36 #include <linux/of_gpio.h>
  37 #include <linux/pinctrl/consumer.h>
  38 #include <linux/mfd/syscon.h>
  39 #include <linux/regmap.h>
  40
  41 #include <asm/irq.h>
  42
  43 #include <linux/platform_data/i2c-s3c2410.h>
  44
  45 /* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
  46
  47 #define S3C2410_IICCON                  0x00
  48 #define S3C2410_IICSTAT                 0x04
  49 #define S3C2410_IICADD                  0x08
  50 #define S3C2410_IICDS                   0x0C
  51 #define S3C2440_IICLC                   0x10
  52
  53 #define S3C2410_IICCON_ACKEN            (1 << 7)
  54 #define S3C2410_IICCON_TXDIV_16         (0 << 6)
  55 #define S3C2410_IICCON_TXDIV_512        (1 << 6)
  56 #define S3C2410_IICCON_IRQEN            (1 << 5)
  57 #define S3C2410_IICCON_IRQPEND          (1 << 4)
  58 #define S3C2410_IICCON_SCALE(x)         ((x) & 0xf)
  59 #define S3C2410_IICCON_SCALEMASK        (0xf)
  60
  61 #define S3C2410_IICSTAT_MASTER_RX       (2 << 6)
  62 #define S3C2410_IICSTAT_MASTER_TX       (3 << 6)
  63 #define S3C2410_IICSTAT_SLAVE_RX        (0 << 6)
  64 #define S3C2410_IICSTAT_SLAVE_TX        (1 << 6)
  65 #define S3C2410_IICSTAT_MODEMASK        (3 << 6)
  66
  67 #define S3C2410_IICSTAT_START           (1 << 5)
  68 #define S3C2410_IICSTAT_BUSBUSY         (1 << 5)
  69 #define S3C2410_IICSTAT_TXRXEN          (1 << 4)
  70 #define S3C2410_IICSTAT_ARBITR          (1 << 3)
  71 #define S3C2410_IICSTAT_ASSLAVE         (1 << 2)
  72 #define S3C2410_IICSTAT_ADDR0           (1 << 1)
  73 #define S3C2410_IICSTAT_LASTBIT         (1 << 0)
  74
  75 #define S3C2410_IICLC_SDA_DELAY0        (0 << 0)
  76 #define S3C2410_IICLC_SDA_DELAY5        (1 << 0)
  77 #define S3C2410_IICLC_SDA_DELAY10       (2 << 0)
  78 #define S3C2410_IICLC_SDA_DELAY15       (3 << 0)
  79 #define S3C2410_IICLC_SDA_DELAY_MASK    (3 << 0)
  80
  81 #define S3C2410_IICLC_FILTER_ON         (1 << 2)
  82
  83 /* Treat S3C2410 as baseline hardware, anything else is supported via quirks */
  84 #define QUIRK_S3C2440           (1 << 0)
  85 #define QUIRK_HDMIPHY           (1 << 1)
  86 #define QUIRK_NO_GPIO           (1 << 2)
  87 #define QUIRK_POLL              (1 << 3)
  88
  89 /* Max time to wait for bus to become idle after a xfer (in us) */
  90 #define S3C2410_IDLE_TIMEOUT    5000
  91
  92 /* Exynos5 Sysreg offset */
  93 #define EXYNOS5_SYS_I2C_CFG     0x0234
  94
  95 /* i2c controller state */
  96 enum s3c24xx_i2c_state {
  97         STATE_IDLE,
  98         STATE_START,
  99         STATE_READ,
 100         STATE_WRITE,
 101         STATE_STOP
 102 };
 103
 104 struct s3c24xx_i2c {
 105         wait_queue_head_t       wait;
 106         kernel_ulong_t          quirks;
 107         unsigned int            suspended:1;
 108
 109         struct i2c_msg          *msg;
 110         unsigned int            msg_num;
 111         unsigned int            msg_idx;
 112         unsigned int            msg_ptr;
 113
 114         unsigned int            tx_setup;
 115         unsigned int            irq;
 116
 117         enum s3c24xx_i2c_state  state;
 118         unsigned long           clkrate;
 119
 120         void __iomem            *regs;
 121         struct clk              *clk;
 122         struct device           *dev;
 123         struct i2c_adapter      adap;
 124
 125         struct s3c2410_platform_i2c     *pdata;
 126         int                     gpios[2];
 127         struct pinctrl          *pctrl;
 128 #if defined(CONFIG_ARM_S3C24XX_CPUFREQ)
 129         struct notifier_block   freq_transition;
 130 #endif
 131         struct regmap           *sysreg;
 132         unsigned int            sys_i2c_cfg;
 133 };
 134
 135 static const struct platform_device_id s3c24xx_driver_ids[] = {
 136         {
 137                 .name           = "s3c2410-i2c",
 138                 .driver_data    = 0,
 139         }, {
 140                 .name           = "s3c2440-i2c",
 141                 .driver_data    = QUIRK_S3C2440,
 142         }, {
 143                 .name           = "s3c2440-hdmiphy-i2c",
 144                 .driver_data    = QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO,
 145         }, { },
 146 };
 147 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
 148
 149 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat);
 150
 151 #ifdef CONFIG_OF
 152 static const struct of_device_id s3c24xx_i2c_match[] = {
 153         { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 },
 154         { .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 },
 155         { .compatible = "samsung,s3c2440-hdmiphy-i2c",
 156           .data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) },
 157         { .compatible = "samsung,exynos5440-i2c",
 158           .data = (void *)(QUIRK_S3C2440 | QUIRK_NO_GPIO) },
 159         { .compatible = "samsung,exynos5-sata-phy-i2c",
 160           .data = (void *)(QUIRK_S3C2440 | QUIRK_POLL | QUIRK_NO_GPIO) },
 161         {},
 162 };
 163 MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match);
 164 #endif
 165
 166 /*
 167  * Get controller type either from device tree or platform device variant.
 168  */
 169 static inline kernel_ulong_t s3c24xx_get_device_quirks(struct platform_device *pdev)
 170 {
 171         if (pdev->dev.of_node) {
 172                 const struct of_device_id *match;
 173
 174                 match = of_match_node(s3c24xx_i2c_match, pdev->dev.of_node);
 175                 return (kernel_ulong_t)match->data;
 176         }
 177
 178         return platform_get_device_id(pdev)->driver_data;
 179 }
 180
 181 /*
 182  * Complete the message and wake up the caller, using the given return code,
 183  * or zero to mean ok.
 184  */
 185 static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
 186 {
 187         dev_dbg(i2c->dev, "master_complete %d\n", ret);
 188
 189         i2c->msg_ptr = 0;
 190         i2c->msg = NULL;
 191         i2c->msg_idx++;
 192         i2c->msg_num = 0;
 193         if (ret)
 194                 i2c->msg_idx = ret;
 195
 196         if (!(i2c->quirks & QUIRK_POLL))
 197                 wake_up(&i2c->wait);
 198 }
 199
 200 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
 201 {
 202         unsigned long tmp;
 203
 204         tmp = readl(i2c->regs + S3C2410_IICCON);
 205         writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
 206 }
 207
 208 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
 209 {
 210         unsigned long tmp;
 211
 212         tmp = readl(i2c->regs + S3C2410_IICCON);
 213         writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
 214 }
 215
 216 /* irq enable/disable functions */
 217 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
 218 {
 219         unsigned long tmp;
 220
 221         tmp = readl(i2c->regs + S3C2410_IICCON);
 222         writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
 223 }
 224
 225 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
 226 {
 227         unsigned long tmp;
 228
 229         tmp = readl(i2c->regs + S3C2410_IICCON);
 230         writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
 231 }
 232
 233 static bool is_ack(struct s3c24xx_i2c *i2c)
 234 {
 235         int tries;
 236
 237         for (tries = 50; tries; --tries) {
 238                 if (readl(i2c->regs + S3C2410_IICCON)
 239                         & S3C2410_IICCON_IRQPEND) {
 240                         if (!(readl(i2c->regs + S3C2410_IICSTAT)
 241                                 & S3C2410_IICSTAT_LASTBIT))
 242                                 return true;
 243                 }
 244                 usleep_range(1000, 2000);
 245         }
 246         dev_err(i2c->dev, "ack was not received\n");
 247         return false;
 248 }
 249
 250 /*
 251  * put the start of a message onto the bus
 252  */
 253 static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
 254                                       struct i2c_msg *msg)
 255 {
 256         unsigned int addr = (msg->addr & 0x7f) << 1;
 257         unsigned long stat;
 258         unsigned long iiccon;
 259
 260         stat = 0;
 261         stat |=  S3C2410_IICSTAT_TXRXEN;
 262
 263         if (msg->flags & I2C_M_RD) {
 264                 stat |= S3C2410_IICSTAT_MASTER_RX;
 265                 addr |= 1;
 266         } else
 267                 stat |= S3C2410_IICSTAT_MASTER_TX;
 268
 269         if (msg->flags & I2C_M_REV_DIR_ADDR)
 270                 addr ^= 1;
 271
 272         /* todo - check for whether ack wanted or not */
 273         s3c24xx_i2c_enable_ack(i2c);
 274
 275         iiccon = readl(i2c->regs + S3C2410_IICCON);
 276         writel(stat, i2c->regs + S3C2410_IICSTAT);
 277
 278         dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
 279         writeb(addr, i2c->regs + S3C2410_IICDS);
 280
 281         /*
 282          * delay here to ensure the data byte has gotten onto the bus
 283          * before the transaction is started
 284          */
 285         ndelay(i2c->tx_setup);
 286
 287         dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
 288         writel(iiccon, i2c->regs + S3C2410_IICCON);
 289
 290         stat |= S3C2410_IICSTAT_START;
 291         writel(stat, i2c->regs + S3C2410_IICSTAT);
 292
 293         if (i2c->quirks & QUIRK_POLL) {
 294                 while ((i2c->msg_num != 0) && is_ack(i2c)) {
 295                         i2c_s3c_irq_nextbyte(i2c, stat);
 296                         stat = readl(i2c->regs + S3C2410_IICSTAT);
 297
 298                         if (stat & S3C2410_IICSTAT_ARBITR)
 299                                 dev_err(i2c->dev, "deal with arbitration loss\n");
 300                 }
 301         }
 302 }
 303
 304 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
 305 {
 306         unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 307
 308         dev_dbg(i2c->dev, "STOP\n");
 309
 310         /*
 311          * The datasheet says that the STOP sequence should be:
 312          *  1) I2CSTAT.5 = 0    - Clear BUSY (or 'generate STOP')
 313          *  2) I2CCON.4 = 0     - Clear IRQPEND
 314          *  3) Wait until the stop condition takes effect.
 315          *  4*) I2CSTAT.4 = 0   - Clear TXRXEN
 316          *
 317          * Where, step "4*" is only for buses with the "HDMIPHY" quirk.
 318          *
 319          * However, after much experimentation, it appears that:
 320          * a) normal buses automatically clear BUSY and transition from
 321          *    Master->Slave when they complete generating a STOP condition.
 322          *    Therefore, step (3) can be done in doxfer() by polling I2CCON.4
 323          *    after starting the STOP generation here.
 324          * b) HDMIPHY bus does neither, so there is no way to do step 3.
 325          *    There is no indication when this bus has finished generating
 326          *    STOP.
 327          *
 328          * In fact, we have found that as soon as the IRQPEND bit is cleared in
 329          * step 2, the HDMIPHY bus generates the STOP condition, and then
 330          * immediately starts transferring another data byte, even though the
 331          * bus is supposedly stopped.  This is presumably because the bus is
 332          * still in "Master" mode, and its BUSY bit is still set.
 333          *
 334          * To avoid these extra post-STOP transactions on HDMI phy devices, we
 335          * just disable Serial Output on the bus (I2CSTAT.4 = 0) directly,
 336          * instead of first generating a proper STOP condition.  This should
 337          * float SDA & SCK terminating the transfer.  Subsequent transfers
 338          *  start with a proper START condition, and proceed normally.
 339          *
 340          * The HDMIPHY bus is an internal bus that always has exactly two
 341          * devices, the host as Master and the HDMIPHY device as the slave.
 342          * Skipping the STOP condition has been tested on this bus and works.
 343          */
 344         if (i2c->quirks & QUIRK_HDMIPHY) {
 345                 /* Stop driving the I2C pins */
 346                 iicstat &= ~S3C2410_IICSTAT_TXRXEN;
 347         } else {
 348                 /* stop the transfer */
 349                 iicstat &= ~S3C2410_IICSTAT_START;
 350         }
 351         writel(iicstat, i2c->regs + S3C2410_IICSTAT);
 352
 353         i2c->state = STATE_STOP;
 354
 355         s3c24xx_i2c_master_complete(i2c, ret);
 356         s3c24xx_i2c_disable_irq(i2c);
 357 }
 358
 359 /*
 360  * helper functions to determine the current state in the set of
 361  * messages we are sending
 362  */
 363
 364 /*
 365  * returns TRUE if the current message is the last in the set
 366  */
 367 static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
 368 {
 369         return i2c->msg_idx >= (i2c->msg_num - 1);
 370 }
 371
 372 /*
 373  * returns TRUE if we this is the last byte in the current message
 374  */
 375 static inline int is_msglast(struct s3c24xx_i2c *i2c)
 376 {
 377         /*
 378          * msg->len is always 1 for the first byte of smbus block read.
 379          * Actual length will be read from slave. More bytes will be
 380          * read according to the length then.
 381          */
 382         if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1)
 383                 return 0;
 384
 385         return i2c->msg_ptr == i2c->msg->len-1;
 386 }
 387
 388 /*
 389  * returns TRUE if we reached the end of the current message
 390  */
 391 static inline int is_msgend(struct s3c24xx_i2c *i2c)
 392 {
 393         return i2c->msg_ptr >= i2c->msg->len;
 394 }
 395
 396 /*
 397  * process an interrupt and work out what to do
 398  */
 399 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
 400 {
 401         unsigned long tmp;
 402         unsigned char byte;
 403         int ret = 0;
 404
 405         switch (i2c->state) {
 406
 407         case STATE_IDLE:
 408                 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__);
 409                 goto out;
 410
 411         case STATE_STOP:
 412                 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
 413                 s3c24xx_i2c_disable_irq(i2c);
 414                 goto out_ack;
 415
 416         case STATE_START:
 417                 /*
 418                  * last thing we did was send a start condition on the
 419                  * bus, or started a new i2c message
 420                  */
 421                 if (iicstat & S3C2410_IICSTAT_LASTBIT &&
 422                     !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
 423                         /* ack was not received... */
 424                         dev_dbg(i2c->dev, "ack was not received\n");
 425                         s3c24xx_i2c_stop(i2c, -ENXIO);
 426                         goto out_ack;
 427                 }
 428
 429                 if (i2c->msg->flags & I2C_M_RD)
 430                         i2c->state = STATE_READ;
 431                 else
 432                         i2c->state = STATE_WRITE;
 433
 434                 /*
 435                  * Terminate the transfer if there is nothing to do
 436                  * as this is used by the i2c probe to find devices.
 437                  */
 438                 if (is_lastmsg(i2c) && i2c->msg->len == 0) {
 439                         s3c24xx_i2c_stop(i2c, 0);
 440                         goto out_ack;
 441                 }
 442
 443                 if (i2c->state == STATE_READ)
 444                         goto prepare_read;
 445
 446                 /*
 447                  * fall through to the write state, as we will need to
 448                  * send a byte as well
 449                  */
 450
 451         case STATE_WRITE:
 452                 /*
 453                  * we are writing data to the device... check for the
 454                  * end of the message, and if so, work out what to do
 455                  */
 456                 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
 457                         if (iicstat & S3C2410_IICSTAT_LASTBIT) {
 458                                 dev_dbg(i2c->dev, "WRITE: No Ack\n");
 459
 460                                 s3c24xx_i2c_stop(i2c, -ECONNREFUSED);
 461                                 goto out_ack;
 462                         }
 463                 }
 464
 465  retry_write:
 466
 467                 if (!is_msgend(i2c)) {
 468                         byte = i2c->msg->buf[i2c->msg_ptr++];
 469                         writeb(byte, i2c->regs + S3C2410_IICDS);
 470
 471                         /*
 472                          * delay after writing the byte to allow the
 473                          * data setup time on the bus, as writing the
 474                          * data to the register causes the first bit
 475                          * to appear on SDA, and SCL will change as
 476                          * soon as the interrupt is acknowledged
 477                          */
 478                         ndelay(i2c->tx_setup);
 479
 480                 } else if (!is_lastmsg(i2c)) {
 481                         /* we need to go to the next i2c message */
 482
 483                         dev_dbg(i2c->dev, "WRITE: Next Message\n");
 484
 485                         i2c->msg_ptr = 0;
 486                         i2c->msg_idx++;
 487                         i2c->msg++;
 488
 489                         /* check to see if we need to do another message */
 490                         if (i2c->msg->flags & I2C_M_NOSTART) {
 491
 492                                 if (i2c->msg->flags & I2C_M_RD) {
 493                                         /*
 494                                          * cannot do this, the controller
 495                                          * forces us to send a new START
 496                                          * when we change direction
 497                                          */
 498                                         dev_dbg(i2c->dev,
 499                                                 "missing START before write->read\n");
 500                                         s3c24xx_i2c_stop(i2c, -EINVAL);
 501                                         break;
 502                                 }
 503
 504                                 goto retry_write;
 505                         } else {
 506                                 /* send the new start */
 507                                 s3c24xx_i2c_message_start(i2c, i2c->msg);
 508                                 i2c->state = STATE_START;
 509                         }
 510
 511                 } else {
 512                         /* send stop */
 513                         s3c24xx_i2c_stop(i2c, 0);
 514                 }
 515                 break;
 516
 517         case STATE_READ:
 518                 /*
 519                  * we have a byte of data in the data register, do
 520                  * something with it, and then work out whether we are
 521                  * going to do any more read/write
 522                  */
 523                 byte = readb(i2c->regs + S3C2410_IICDS);
 524                 i2c->msg->buf[i2c->msg_ptr++] = byte;
 525
 526                 /* Add actual length to read for smbus block read */
 527                 if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1)
 528                         i2c->msg->len += byte;
 529  prepare_read:
 530                 if (is_msglast(i2c)) {
 531                         /* last byte of buffer */
 532
 533                         if (is_lastmsg(i2c))
 534                                 s3c24xx_i2c_disable_ack(i2c);
 535
 536                 } else if (is_msgend(i2c)) {
 537                         /*
 538                          * ok, we've read the entire buffer, see if there
 539                          * is anything else we need to do
 540                          */
 541                         if (is_lastmsg(i2c)) {
 542                                 /* last message, send stop and complete */
 543                                 dev_dbg(i2c->dev, "READ: Send Stop\n");
 544
 545                                 s3c24xx_i2c_stop(i2c, 0);
 546                         } else {
 547                                 /* go to the next transfer */
 548                                 dev_dbg(i2c->dev, "READ: Next Transfer\n");
 549
 550                                 i2c->msg_ptr = 0;
 551                                 i2c->msg_idx++;
 552                                 i2c->msg++;
 553                         }
 554                 }
 555
 556                 break;
 557         }
 558
 559         /* acknowlegde the IRQ and get back on with the work */
 560
 561  out_ack:
 562         tmp = readl(i2c->regs + S3C2410_IICCON);
 563         tmp &= ~S3C2410_IICCON_IRQPEND;
 564         writel(tmp, i2c->regs + S3C2410_IICCON);
 565  out:
 566         return ret;
 567 }
 568
 569 /*
 570  * top level IRQ servicing routine
 571  */
 572 static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id)
 573 {
 574         struct s3c24xx_i2c *i2c = dev_id;
 575         unsigned long status;
 576         unsigned long tmp;
 577
 578         status = readl(i2c->regs + S3C2410_IICSTAT);
 579
 580         if (status & S3C2410_IICSTAT_ARBITR) {
 581                 /* deal with arbitration loss */
 582                 dev_err(i2c->dev, "deal with arbitration loss\n");
 583         }
 584
 585         if (i2c->state == STATE_IDLE) {
 586                 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
 587
 588                 tmp = readl(i2c->regs + S3C2410_IICCON);
 589                 tmp &= ~S3C2410_IICCON_IRQPEND;
 590                 writel(tmp, i2c->regs +  S3C2410_IICCON);
 591                 goto out;
 592         }
 593
 594         /*
 595          * pretty much this leaves us with the fact that we've
 596          * transmitted or received whatever byte we last sent
 597          */
 598         i2c_s3c_irq_nextbyte(i2c, status);
 599
 600  out:
 601         return IRQ_HANDLED;
 602 }
 603
 604 /*
 605  * Disable the bus so that we won't get any interrupts from now on, or try
 606  * to drive any lines. This is the default state when we don't have
 607  * anything to send/receive.
 608  *
 609  * If there is an event on the bus, or we have a pre-existing event at
 610  * kernel boot time, we may not notice the event and the I2C controller
 611  * will lock the bus with the I2C clock line low indefinitely.
 612  */
 613 static inline void s3c24xx_i2c_disable_bus(struct s3c24xx_i2c *i2c)
 614 {
 615         unsigned long tmp;
 616
 617         /* Stop driving the I2C pins */
 618         tmp = readl(i2c->regs + S3C2410_IICSTAT);
 619         tmp &= ~S3C2410_IICSTAT_TXRXEN;
 620         writel(tmp, i2c->regs + S3C2410_IICSTAT);
 621
 622         /* We don't expect any interrupts now, and don't want send acks */
 623         tmp = readl(i2c->regs + S3C2410_IICCON);
 624         tmp &= ~(S3C2410_IICCON_IRQEN | S3C2410_IICCON_IRQPEND |
 625                 S3C2410_IICCON_ACKEN);
 626         writel(tmp, i2c->regs + S3C2410_IICCON);
 627 }
 628
 629
 630 /*
 631  * get the i2c bus for a master transaction
 632  */
 633 static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
 634 {
 635         unsigned long iicstat;
 636         int timeout = 400;
 637
 638         while (timeout-- > 0) {
 639                 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 640
 641                 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
 642                         return 0;
 643
 644                 msleep(1);
 645         }
 646
 647         return -ETIMEDOUT;
 648 }
 649
 650 /*
 651  * wait for the i2c bus to become idle.
 652  */
 653 static void s3c24xx_i2c_wait_idle(struct s3c24xx_i2c *i2c)
 654 {
 655         unsigned long iicstat;
 656         ktime_t start, now;
 657         unsigned long delay;
 658         int spins;
 659
 660         /* ensure the stop has been through the bus */
 661
 662         dev_dbg(i2c->dev, "waiting for bus idle\n");
 663
 664         start = now = ktime_get();
 665
 666         /*
 667          * Most of the time, the bus is already idle within a few usec of the
 668          * end of a transaction.  However, really slow i2c devices can stretch
 669          * the clock, delaying STOP generation.
 670          *
 671          * On slower SoCs this typically happens within a very small number of
 672          * instructions so busy wait briefly to avoid scheduling overhead.
 673          */
 674         spins = 3;
 675         iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 676         while ((iicstat & S3C2410_IICSTAT_START) && --spins) {
 677                 cpu_relax();
 678                 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 679         }
 680
 681         /*
 682          * If we do get an appreciable delay as a compromise between idle
 683          * detection latency for the normal, fast case, and system load in the
 684          * slow device case, use an exponential back off in the polling loop,
 685          * up to 1/10th of the total timeout, then continue to poll at a
 686          * constant rate up to the timeout.
 687          */
 688         delay = 1;
 689         while ((iicstat & S3C2410_IICSTAT_START) &&
 690                ktime_us_delta(now, start) < S3C2410_IDLE_TIMEOUT) {
 691                 usleep_range(delay, 2 * delay);
 692                 if (delay < S3C2410_IDLE_TIMEOUT / 10)
 693                         delay <<= 1;
 694                 now = ktime_get();
 695                 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 696         }
 697
 698         if (iicstat & S3C2410_IICSTAT_START)
 699                 dev_warn(i2c->dev, "timeout waiting for bus idle\n");
 700 }
 701
 702 /*
 703  * this starts an i2c transfer
 704  */
 705 static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
 706                               struct i2c_msg *msgs, int num)
 707 {
 708         unsigned long timeout;
 709         int ret;
 710
 711         if (i2c->suspended)
 712                 return -EIO;
 713
 714         ret = s3c24xx_i2c_set_master(i2c);
 715         if (ret != 0) {
 716                 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
 717                 ret = -EAGAIN;
 718                 goto out;
 719         }
 720
 721         i2c->msg     = msgs;
 722         i2c->msg_num = num;
 723         i2c->msg_ptr = 0;
 724         i2c->msg_idx = 0;
 725         i2c->state   = STATE_START;
 726
 727         s3c24xx_i2c_enable_irq(i2c);
 728         s3c24xx_i2c_message_start(i2c, msgs);
 729
 730         if (i2c->quirks & QUIRK_POLL) {
 731                 ret = i2c->msg_idx;
 732
 733                 if (ret != num)
 734                         dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
 735
 736                 goto out;
 737         }
 738
 739         timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
 740
 741         ret = i2c->msg_idx;
 742
 743         /*
 744          * Having these next two as dev_err() makes life very
 745          * noisy when doing an i2cdetect
 746          */
 747         if (timeout == 0)
 748                 dev_dbg(i2c->dev, "timeout\n");
 749         else if (ret != num)
 750                 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
 751
 752         /* For QUIRK_HDMIPHY, bus is already disabled */
 753         if (i2c->quirks & QUIRK_HDMIPHY)
 754                 goto out;
 755
 756         s3c24xx_i2c_wait_idle(i2c);
 757
 758         s3c24xx_i2c_disable_bus(i2c);
 759
 760  out:
 761         i2c->state = STATE_IDLE;
 762
 763         return ret;
 764 }
 765
 766 /*
 767  * first port of call from the i2c bus code when an message needs
 768  * transferring across the i2c bus.
 769  */
 770 static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
 771                         struct i2c_msg *msgs, int num)
 772 {
 773         struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;
 774         int retry;
 775         int ret;
 776
 777         ret = clk_enable(i2c->clk);
 778         if (ret)
 779                 return ret;
 780
 781         for (retry = 0; retry < adap->retries; retry++) {
 782
 783                 ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
 784
 785                 if (ret != -EAGAIN) {
 786                         clk_disable(i2c->clk);
 787                         return ret;
 788                 }
 789
 790                 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
 791
 792                 udelay(100);
 793         }
 794
 795         clk_disable(i2c->clk);
 796         return -EREMOTEIO;
 797 }
 798
 799 /* declare our i2c functionality */
 800 static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)
 801 {
 802         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART |
 803                 I2C_FUNC_PROTOCOL_MANGLING;
 804 }
 805
 806 /* i2c bus registration info */
 807 static const struct i2c_algorithm s3c24xx_i2c_algorithm = {
 808         .master_xfer            = s3c24xx_i2c_xfer,
 809         .functionality          = s3c24xx_i2c_func,
 810 };
 811
 812 /*
 813  * return the divisor settings for a given frequency
 814  */
 815 static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
 816                                    unsigned int *div1, unsigned int *divs)
 817 {
 818         unsigned int calc_divs = clkin / wanted;
 819         unsigned int calc_div1;
 820
 821         if (calc_divs > (16*16))
 822                 calc_div1 = 512;
 823         else
 824                 calc_div1 = 16;
 825
 826         calc_divs += calc_div1-1;
 827         calc_divs /= calc_div1;
 828
 829         if (calc_divs == 0)
 830                 calc_divs = 1;
 831         if (calc_divs > 17)
 832                 calc_divs = 17;
 833
 834         *divs = calc_divs;
 835         *div1 = calc_div1;
 836
 837         return clkin / (calc_divs * calc_div1);
 838 }
 839
 840 /*
 841  * work out a divisor for the user requested frequency setting,
 842  * either by the requested frequency, or scanning the acceptable
 843  * range of frequencies until something is found
 844  */
 845 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
 846 {
 847         struct s3c2410_platform_i2c *pdata = i2c->pdata;
 848         unsigned long clkin = clk_get_rate(i2c->clk);
 849         unsigned int divs, div1;
 850         unsigned long target_frequency;
 851         u32 iiccon;
 852         int freq;
 853
 854         i2c->clkrate = clkin;
 855         clkin /= 1000;          /* clkin now in KHz */
 856
 857         dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency);
 858
 859         target_frequency = pdata->frequency ? pdata->frequency : 100000;
 860
 861         target_frequency /= 1000; /* Target frequency now in KHz */
 862
 863         freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs);
 864
 865         if (freq > target_frequency) {
 866                 dev_err(i2c->dev,
 867                         "Unable to achieve desired frequency %luKHz."   \
 868                         " Lowest achievable %dKHz\n", target_frequency, freq);
 869                 return -EINVAL;
 870         }
 871
 872         *got = freq;
 873
 874         iiccon = readl(i2c->regs + S3C2410_IICCON);
 875         iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512);
 876         iiccon |= (divs-1);
 877
 878         if (div1 == 512)
 879                 iiccon |= S3C2410_IICCON_TXDIV_512;
 880
 881         if (i2c->quirks & QUIRK_POLL)
 882                 iiccon |= S3C2410_IICCON_SCALE(2);
 883
 884         writel(iiccon, i2c->regs + S3C2410_IICCON);
 885
 886         if (i2c->quirks & QUIRK_S3C2440) {
 887                 unsigned long sda_delay;
 888
 889                 if (pdata->sda_delay) {
 890                         sda_delay = clkin * pdata->sda_delay;
 891                         sda_delay = DIV_ROUND_UP(sda_delay, 1000000);
 892                         sda_delay = DIV_ROUND_UP(sda_delay, 5);
 893                         if (sda_delay > 3)
 894                                 sda_delay = 3;
 895                         sda_delay |= S3C2410_IICLC_FILTER_ON;
 896                 } else
 897                         sda_delay = 0;
 898
 899                 dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay);
 900                 writel(sda_delay, i2c->regs + S3C2440_IICLC);
 901         }
 902
 903         return 0;
 904 }
 905
 906 #if defined(CONFIG_ARM_S3C24XX_CPUFREQ)
 907
 908 #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition)
 909
 910 static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb,
 911                                           unsigned long val, void *data)
 912 {
 913         struct s3c24xx_i2c *i2c = freq_to_i2c(nb);
 914         unsigned int got;
 915         int delta_f;
 916         int ret;
 917
 918         delta_f = clk_get_rate(i2c->clk) - i2c->clkrate;
 919
 920         /* if we're post-change and the input clock has slowed down
 921          * or at pre-change and the clock is about to speed up, then
 922          * adjust our clock rate. <0 is slow, >0 speedup.
 923          */
 924
 925         if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) ||
 926             (val == CPUFREQ_PRECHANGE && delta_f > 0)) {
 927                 i2c_lock_adapter(&i2c->adap);
 928                 ret = s3c24xx_i2c_clockrate(i2c, &got);
 929                 i2c_unlock_adapter(&i2c->adap);
 930
 931                 if (ret < 0)
 932                         dev_err(i2c->dev, "cannot find frequency (%d)\n", ret);
 933                 else
 934                         dev_info(i2c->dev, "setting freq %d\n", got);
 935         }
 936
 937         return 0;
 938 }
 939
 940 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
 941 {
 942         i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition;
 943
 944         return cpufreq_register_notifier(&i2c->freq_transition,
 945                                          CPUFREQ_TRANSITION_NOTIFIER);
 946 }
 947
 948 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
 949 {
 950         cpufreq_unregister_notifier(&i2c->freq_transition,
 951                                     CPUFREQ_TRANSITION_NOTIFIER);
 952 }
 953
 954 #else
 955 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
 956 {
 957         return 0;
 958 }
 959
 960 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
 961 {
 962 }
 963 #endif
 964
 965 #ifdef CONFIG_OF
 966 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
 967 {
 968         int idx, gpio, ret;
 969
 970         if (i2c->quirks & QUIRK_NO_GPIO)
 971                 return 0;
 972
 973         for (idx = 0; idx < 2; idx++) {
 974                 gpio = of_get_gpio(i2c->dev->of_node, idx);
 975                 if (!gpio_is_valid(gpio)) {
 976                         dev_err(i2c->dev, "invalid gpio[%d]: %d\n", idx, gpio);
 977                         goto free_gpio;
 978                 }
 979                 i2c->gpios[idx] = gpio;
 980
 981                 ret = gpio_request(gpio, "i2c-bus");
 982                 if (ret) {
 983                         dev_err(i2c->dev, "gpio [%d] request failed (%d)\n",
 984                                 gpio, ret);
 985                         goto free_gpio;
 986                 }
 987         }
 988         return 0;
 989
 990 free_gpio:
 991         while (--idx >= 0)
 992                 gpio_free(i2c->gpios[idx]);
 993         return -EINVAL;
 994 }
 995
 996 static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c)
 997 {
 998         unsigned int idx;
 999
1000         if (i2c->quirks & QUIRK_NO_GPIO)
1001                 return;
1002
1003         for (idx = 0; idx < 2; idx++)
1004                 gpio_free(i2c->gpios[idx]);
1005 }
1006 #else
1007 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
1008 {
1009         return 0;
1010 }
1011
1012 static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c)
1013 {
1014 }
1015 #endif
1016
1017 /*
1018  * initialise the controller, set the IO lines and frequency
1019  */
1020 static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
1021 {
1022         struct s3c2410_platform_i2c *pdata;
1023         unsigned int freq;
1024
1025         /* get the plafrom data */
1026
1027         pdata = i2c->pdata;
1028
1029         /* write slave address */
1030
1031         writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
1032
1033         dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
1034
1035         writel(0, i2c->regs + S3C2410_IICCON);
1036         writel(0, i2c->regs + S3C2410_IICSTAT);
1037
1038         /* we need to work out the divisors for the clock... */
1039
1040         if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) {
1041                 dev_err(i2c->dev, "cannot meet bus frequency required\n");
1042                 return -EINVAL;
1043         }
1044
1045         /* todo - check that the i2c lines aren't being dragged anywhere */
1046
1047         dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);
1048         dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02x\n",
1049                 readl(i2c->regs + S3C2410_IICCON));
1050
1051         return 0;
1052 }
1053
1054 #ifdef CONFIG_OF
1055 /*
1056  * Parse the device tree node and retreive the platform data.
1057  */
1058 static void
1059 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c)
1060 {
1061         struct s3c2410_platform_i2c *pdata = i2c->pdata;
1062         int id;
1063
1064         if (!np)
1065                 return;
1066
1067         pdata->bus_num = -1; /* i2c bus number is dynamically assigned */
1068         of_property_read_u32(np, "samsung,i2c-sda-delay", &pdata->sda_delay);
1069         of_property_read_u32(np, "samsung,i2c-slave-addr", &pdata->slave_addr);
1070         of_property_read_u32(np, "samsung,i2c-max-bus-freq",
1071                                 (u32 *)&pdata->frequency);
1072         /*
1073          * Exynos5's legacy i2c controller and new high speed i2c
1074          * controller have muxed interrupt sources. By default the
1075          * interrupts for 4-channel HS-I2C controller are enabled.
1076          * If nodes for first four channels of legacy i2c controller
1077          * are available then re-configure the interrupts via the
1078          * system register.
1079          */
1080         id = of_alias_get_id(np, "i2c");
1081         i2c->sysreg = syscon_regmap_lookup_by_phandle(np,
1082                         "samsung,sysreg-phandle");
1083         if (IS_ERR(i2c->sysreg))
1084                 return;
1085
1086         regmap_update_bits(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, BIT(id), 0);
1087 }
1088 #else
1089 static void
1090 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) { }
1091 #endif
1092
1093 static int s3c24xx_i2c_probe(struct platform_device *pdev)
1094 {
1095         struct s3c24xx_i2c *i2c;
1096         struct s3c2410_platform_i2c *pdata = NULL;
1097         struct resource *res;
1098         int ret;
1099
1100         if (!pdev->dev.of_node) {
1101                 pdata = dev_get_platdata(&pdev->dev);
1102                 if (!pdata) {
1103                         dev_err(&pdev->dev, "no platform data\n");
1104                         return -EINVAL;
1105                 }
1106         }
1107
1108         i2c = devm_kzalloc(&pdev->dev, sizeof(struct s3c24xx_i2c), GFP_KERNEL);
1109         if (!i2c)
1110                 return -ENOMEM;
1111
1112         i2c->pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1113         if (!i2c->pdata)
1114                 return -ENOMEM;
1115
1116         i2c->quirks = s3c24xx_get_device_quirks(pdev);
1117         i2c->sysreg = ERR_PTR(-ENOENT);
1118         if (pdata)
1119                 memcpy(i2c->pdata, pdata, sizeof(*pdata));
1120         else
1121                 s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c);
1122
1123         strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
1124         i2c->adap.owner = THIS_MODULE;
1125         i2c->adap.algo = &s3c24xx_i2c_algorithm;
1126         i2c->adap.retries = 2;
1127         i2c->adap.class = I2C_CLASS_DEPRECATED;
1128         i2c->tx_setup = 50;
1129
1130         init_waitqueue_head(&i2c->wait);
1131
1132         /* find the clock and enable it */
1133         i2c->dev = &pdev->dev;
1134         i2c->clk = devm_clk_get(&pdev->dev, "i2c");
1135         if (IS_ERR(i2c->clk)) {
1136                 dev_err(&pdev->dev, "cannot get clock\n");
1137                 return -ENOENT;
1138         }
1139
1140         dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
1141
1142         /* map the registers */
1143         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1144         i2c->regs = devm_ioremap_resource(&pdev->dev, res);
1145
1146         if (IS_ERR(i2c->regs))
1147                 return PTR_ERR(i2c->regs);
1148
1149         dev_dbg(&pdev->dev, "registers %p (%p)\n",
1150                 i2c->regs, res);
1151
1152         /* setup info block for the i2c core */
1153         i2c->adap.algo_data = i2c;
1154         i2c->adap.dev.parent = &pdev->dev;
1155         i2c->pctrl = devm_pinctrl_get_select_default(i2c->dev);
1156
1157         /* inititalise the i2c gpio lines */
1158         if (i2c->pdata->cfg_gpio)
1159                 i2c->pdata->cfg_gpio(to_platform_device(i2c->dev));
1160         else if (IS_ERR(i2c->pctrl) && s3c24xx_i2c_parse_dt_gpio(i2c))
1161                 return -EINVAL;
1162
1163         /* initialise the i2c controller */
1164         ret = clk_prepare_enable(i2c->clk);
1165         if (ret) {
1166                 dev_err(&pdev->dev, "I2C clock enable failed\n");
1167                 return ret;
1168         }
1169
1170         ret = s3c24xx_i2c_init(i2c);
1171         clk_disable(i2c->clk);
1172         if (ret != 0) {
1173                 dev_err(&pdev->dev, "I2C controller init failed\n");
1174                 clk_unprepare(i2c->clk);
1175                 return ret;
1176         }
1177
1178         /*
1179          * find the IRQ for this unit (note, this relies on the init call to
1180          * ensure no current IRQs pending
1181          */
1182         if (!(i2c->quirks & QUIRK_POLL)) {
1183                 i2c->irq = ret = platform_get_irq(pdev, 0);
1184                 if (ret < 0) {
1185                         dev_err(&pdev->dev, "cannot find IRQ\n");
1186                         clk_unprepare(i2c->clk);
1187                         return ret;
1188                 }
1189
1190                 ret = devm_request_irq(&pdev->dev, i2c->irq, s3c24xx_i2c_irq,
1191                                        0, dev_name(&pdev->dev), i2c);
1192                 if (ret != 0) {
1193                         dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
1194                         clk_unprepare(i2c->clk);
1195                         return ret;
1196                 }
1197         }
1198
1199         ret = s3c24xx_i2c_register_cpufreq(i2c);
1200         if (ret < 0) {
1201                 dev_err(&pdev->dev, "failed to register cpufreq notifier\n");
1202                 clk_unprepare(i2c->clk);
1203                 return ret;
1204         }
1205
1206         /*
1207          * Note, previous versions of the driver used i2c_add_adapter()
1208          * to add the bus at any number. We now pass the bus number via
1209          * the platform data, so if unset it will now default to always
1210          * being bus 0.
1211          */
1212         i2c->adap.nr = i2c->pdata->bus_num;
1213         i2c->adap.dev.of_node = pdev->dev.of_node;
1214
1215         platform_set_drvdata(pdev, i2c);
1216
1217         pm_runtime_enable(&pdev->dev);
1218
1219         ret = i2c_add_numbered_adapter(&i2c->adap);
1220         if (ret < 0) {
1221                 pm_runtime_disable(&pdev->dev);
1222                 s3c24xx_i2c_deregister_cpufreq(i2c);
1223                 clk_unprepare(i2c->clk);
1224                 return ret;
1225         }
1226
1227         dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev));
1228         return 0;
1229 }
1230
1231 static int s3c24xx_i2c_remove(struct platform_device *pdev)
1232 {
1233         struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1234
1235         clk_unprepare(i2c->clk);
1236
1237         pm_runtime_disable(&pdev->dev);
1238
1239         s3c24xx_i2c_deregister_cpufreq(i2c);
1240
1241         i2c_del_adapter(&i2c->adap);
1242
1243         if (pdev->dev.of_node && IS_ERR(i2c->pctrl))
1244                 s3c24xx_i2c_dt_gpio_free(i2c);
1245
1246         return 0;
1247 }
1248
1249 #ifdef CONFIG_PM_SLEEP
1250 static int s3c24xx_i2c_suspend_noirq(struct device *dev)
1251 {
1252         struct s3c24xx_i2c *i2c = dev_get_drvdata(dev);
1253
1254         i2c->suspended = 1;
1255
1256         if (!IS_ERR(i2c->sysreg))
1257                 regmap_read(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, &i2c->sys_i2c_cfg);
1258
1259         return 0;
1260 }
1261
1262 static int s3c24xx_i2c_resume_noirq(struct device *dev)
1263 {
1264         struct s3c24xx_i2c *i2c = dev_get_drvdata(dev);
1265         int ret;
1266
1267         if (!IS_ERR(i2c->sysreg))
1268                 regmap_write(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, i2c->sys_i2c_cfg);
1269
1270         ret = clk_enable(i2c->clk);
1271         if (ret)
1272                 return ret;
1273         s3c24xx_i2c_init(i2c);
1274         clk_disable(i2c->clk);
1275         i2c->suspended = 0;
1276
1277         return 0;
1278 }
1279 #endif
1280
1281 #ifdef CONFIG_PM
1282 static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = {
1283         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(s3c24xx_i2c_suspend_noirq,
1284                                       s3c24xx_i2c_resume_noirq)
1285 };
1286
1287 #define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops)
1288 #else
1289 #define S3C24XX_DEV_PM_OPS NULL
1290 #endif
1291
1292 static struct platform_driver s3c24xx_i2c_driver = {
1293         .probe          = s3c24xx_i2c_probe,
1294         .remove         = s3c24xx_i2c_remove,
1295         .id_table       = s3c24xx_driver_ids,
1296         .driver         = {
1297                 .name   = "s3c-i2c",
1298                 .pm     = S3C24XX_DEV_PM_OPS,
1299                 .of_match_table = of_match_ptr(s3c24xx_i2c_match),
1300         },
1301 };
1302
1303 static int __init i2c_adap_s3c_init(void)
1304 {
1305         return platform_driver_register(&s3c24xx_i2c_driver);
1306 }
1307 subsys_initcall(i2c_adap_s3c_init);
1308
1309 static void __exit i2c_adap_s3c_exit(void)
1310 {
1311         platform_driver_unregister(&s3c24xx_i2c_driver);
1312 }
1313 module_exit(i2c_adap_s3c_exit);
1314
1315 MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
1316 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
1317 MODULE_LICENSE("GPL");