drivers/iio/accel/bmc150-accel-core.c

   1 /*
   2  * 3-axis accelerometer driver supporting following Bosch-Sensortec chips:
   3  *  - BMC150
   4  *  - BMI055
   5  *  - BMA255
   6  *  - BMA250E
   7  *  - BMA222E
   8  *  - BMA280
   9  *
  10  * Copyright (c) 2014, Intel Corporation.
  11  *
  12  * This program is free software; you can redistribute it and/or modify it
  13  * under the terms and conditions of the GNU General Public License,
  14  * version 2, as published by the Free Software Foundation.
  15  *
  16  * This program is distributed in the hope it will be useful, but WITHOUT
  17  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  * more details.
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/i2c.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/delay.h>
  26 #include <linux/slab.h>
  27 #include <linux/acpi.h>
  28 #include <linux/pm.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/iio/iio.h>
  31 #include <linux/iio/sysfs.h>
  32 #include <linux/iio/buffer.h>
  33 #include <linux/iio/events.h>
  34 #include <linux/iio/trigger.h>
  35 #include <linux/iio/trigger_consumer.h>
  36 #include <linux/iio/triggered_buffer.h>
  37 #include <linux/regmap.h>
  38
  39 #include "bmc150-accel.h"
  40
  41 #define BMC150_ACCEL_DRV_NAME                   "bmc150_accel"
  42 #define BMC150_ACCEL_IRQ_NAME                   "bmc150_accel_event"
  43
  44 #define BMC150_ACCEL_REG_CHIP_ID                0x00
  45
  46 #define BMC150_ACCEL_REG_INT_STATUS_2           0x0B
  47 #define BMC150_ACCEL_ANY_MOTION_MASK            0x07
  48 #define BMC150_ACCEL_ANY_MOTION_BIT_X           BIT(0)
  49 #define BMC150_ACCEL_ANY_MOTION_BIT_Y           BIT(1)
  50 #define BMC150_ACCEL_ANY_MOTION_BIT_Z           BIT(2)
  51 #define BMC150_ACCEL_ANY_MOTION_BIT_SIGN        BIT(3)
  52
  53 #define BMC150_ACCEL_REG_PMU_LPW                0x11
  54 #define BMC150_ACCEL_PMU_MODE_MASK              0xE0
  55 #define BMC150_ACCEL_PMU_MODE_SHIFT             5
  56 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_MASK     0x17
  57 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT    1
  58
  59 #define BMC150_ACCEL_REG_PMU_RANGE              0x0F
  60
  61 #define BMC150_ACCEL_DEF_RANGE_2G               0x03
  62 #define BMC150_ACCEL_DEF_RANGE_4G               0x05
  63 #define BMC150_ACCEL_DEF_RANGE_8G               0x08
  64 #define BMC150_ACCEL_DEF_RANGE_16G              0x0C
  65
  66 /* Default BW: 125Hz */
  67 #define BMC150_ACCEL_REG_PMU_BW         0x10
  68 #define BMC150_ACCEL_DEF_BW                     125
  69
  70 #define BMC150_ACCEL_REG_RESET                  0x14
  71 #define BMC150_ACCEL_RESET_VAL                  0xB6
  72
  73 #define BMC150_ACCEL_REG_INT_MAP_0              0x19
  74 #define BMC150_ACCEL_INT_MAP_0_BIT_SLOPE        BIT(2)
  75
  76 #define BMC150_ACCEL_REG_INT_MAP_1              0x1A
  77 #define BMC150_ACCEL_INT_MAP_1_BIT_DATA         BIT(0)
  78 #define BMC150_ACCEL_INT_MAP_1_BIT_FWM          BIT(1)
  79 #define BMC150_ACCEL_INT_MAP_1_BIT_FFULL        BIT(2)
  80
  81 #define BMC150_ACCEL_REG_INT_RST_LATCH          0x21
  82 #define BMC150_ACCEL_INT_MODE_LATCH_RESET       0x80
  83 #define BMC150_ACCEL_INT_MODE_LATCH_INT 0x0F
  84 #define BMC150_ACCEL_INT_MODE_NON_LATCH_INT     0x00
  85
  86 #define BMC150_ACCEL_REG_INT_EN_0               0x16
  87 #define BMC150_ACCEL_INT_EN_BIT_SLP_X           BIT(0)
  88 #define BMC150_ACCEL_INT_EN_BIT_SLP_Y           BIT(1)
  89 #define BMC150_ACCEL_INT_EN_BIT_SLP_Z           BIT(2)
  90
  91 #define BMC150_ACCEL_REG_INT_EN_1               0x17
  92 #define BMC150_ACCEL_INT_EN_BIT_DATA_EN         BIT(4)
  93 #define BMC150_ACCEL_INT_EN_BIT_FFULL_EN        BIT(5)
  94 #define BMC150_ACCEL_INT_EN_BIT_FWM_EN          BIT(6)
  95
  96 #define BMC150_ACCEL_REG_INT_OUT_CTRL           0x20
  97 #define BMC150_ACCEL_INT_OUT_CTRL_INT1_LVL      BIT(0)
  98
  99 #define BMC150_ACCEL_REG_INT_5                  0x27
 100 #define BMC150_ACCEL_SLOPE_DUR_MASK             0x03
 101
 102 #define BMC150_ACCEL_REG_INT_6                  0x28
 103 #define BMC150_ACCEL_SLOPE_THRES_MASK           0xFF
 104
 105 /* Slope duration in terms of number of samples */
 106 #define BMC150_ACCEL_DEF_SLOPE_DURATION         1
 107 /* in terms of multiples of g's/LSB, based on range */
 108 #define BMC150_ACCEL_DEF_SLOPE_THRESHOLD        1
 109
 110 #define BMC150_ACCEL_REG_XOUT_L         0x02
 111
 112 #define BMC150_ACCEL_MAX_STARTUP_TIME_MS        100
 113
 114 /* Sleep Duration values */
 115 #define BMC150_ACCEL_SLEEP_500_MICRO            0x05
 116 #define BMC150_ACCEL_SLEEP_1_MS         0x06
 117 #define BMC150_ACCEL_SLEEP_2_MS         0x07
 118 #define BMC150_ACCEL_SLEEP_4_MS         0x08
 119 #define BMC150_ACCEL_SLEEP_6_MS         0x09
 120 #define BMC150_ACCEL_SLEEP_10_MS                0x0A
 121 #define BMC150_ACCEL_SLEEP_25_MS                0x0B
 122 #define BMC150_ACCEL_SLEEP_50_MS                0x0C
 123 #define BMC150_ACCEL_SLEEP_100_MS               0x0D
 124 #define BMC150_ACCEL_SLEEP_500_MS               0x0E
 125 #define BMC150_ACCEL_SLEEP_1_SEC                0x0F
 126
 127 #define BMC150_ACCEL_REG_TEMP                   0x08
 128 #define BMC150_ACCEL_TEMP_CENTER_VAL            23
 129
 130 #define BMC150_ACCEL_AXIS_TO_REG(axis)  (BMC150_ACCEL_REG_XOUT_L + (axis * 2))
 131 #define BMC150_AUTO_SUSPEND_DELAY_MS            2000
 132
 133 #define BMC150_ACCEL_REG_FIFO_STATUS            0x0E
 134 #define BMC150_ACCEL_REG_FIFO_CONFIG0           0x30
 135 #define BMC150_ACCEL_REG_FIFO_CONFIG1           0x3E
 136 #define BMC150_ACCEL_REG_FIFO_DATA              0x3F
 137 #define BMC150_ACCEL_FIFO_LENGTH                32
 138
 139 enum bmc150_accel_axis {
 140         AXIS_X,
 141         AXIS_Y,
 142         AXIS_Z,
 143         AXIS_MAX,
 144 };
 145
 146 enum bmc150_power_modes {
 147         BMC150_ACCEL_SLEEP_MODE_NORMAL,
 148         BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND,
 149         BMC150_ACCEL_SLEEP_MODE_LPM,
 150         BMC150_ACCEL_SLEEP_MODE_SUSPEND = 0x04,
 151 };
 152
 153 struct bmc150_scale_info {
 154         int scale;
 155         u8 reg_range;
 156 };
 157
 158 struct bmc150_accel_chip_info {
 159         const char *name;
 160         u8 chip_id;
 161         const struct iio_chan_spec *channels;
 162         int num_channels;
 163         const struct bmc150_scale_info scale_table[4];
 164 };
 165
 166 struct bmc150_accel_interrupt {
 167         const struct bmc150_accel_interrupt_info *info;
 168         atomic_t users;
 169 };
 170
 171 struct bmc150_accel_trigger {
 172         struct bmc150_accel_data *data;
 173         struct iio_trigger *indio_trig;
 174         int (*setup)(struct bmc150_accel_trigger *t, bool state);
 175         int intr;
 176         bool enabled;
 177 };
 178
 179 enum bmc150_accel_interrupt_id {
 180         BMC150_ACCEL_INT_DATA_READY,
 181         BMC150_ACCEL_INT_ANY_MOTION,
 182         BMC150_ACCEL_INT_WATERMARK,
 183         BMC150_ACCEL_INTERRUPTS,
 184 };
 185
 186 enum bmc150_accel_trigger_id {
 187         BMC150_ACCEL_TRIGGER_DATA_READY,
 188         BMC150_ACCEL_TRIGGER_ANY_MOTION,
 189         BMC150_ACCEL_TRIGGERS,
 190 };
 191
 192 struct bmc150_accel_data {
 193         struct regmap *regmap;
 194         int irq;
 195         struct bmc150_accel_interrupt interrupts[BMC150_ACCEL_INTERRUPTS];
 196         struct bmc150_accel_trigger triggers[BMC150_ACCEL_TRIGGERS];
 197         struct mutex mutex;
 198         u8 fifo_mode, watermark;
 199         s16 buffer[8];
 200         /*
 201          * Ensure there is sufficient space and correct alignment for
 202          * the timestamp if enabled
 203          */
 204         struct {
 205                 __le16 channels[3];
 206                 s64 ts __aligned(8);
 207         } scan;
 208         u8 bw_bits;
 209         u32 slope_dur;
 210         u32 slope_thres;
 211         u32 range;
 212         int ev_enable_state;
 213         int64_t timestamp, old_timestamp; /* Only used in hw fifo mode. */
 214         const struct bmc150_accel_chip_info *chip_info;
 215 };
 216
 217 static const struct {
 218         int val;
 219         int val2;
 220         u8 bw_bits;
 221 } bmc150_accel_samp_freq_table[] = { {15, 620000, 0x08},
 222                                      {31, 260000, 0x09},
 223                                      {62, 500000, 0x0A},
 224                                      {125, 0, 0x0B},
 225                                      {250, 0, 0x0C},
 226                                      {500, 0, 0x0D},
 227                                      {1000, 0, 0x0E},
 228                                      {2000, 0, 0x0F} };
 229
 230 static const struct {
 231         int bw_bits;
 232         int msec;
 233 } bmc150_accel_sample_upd_time[] = { {0x08, 64},
 234                                      {0x09, 32},
 235                                      {0x0A, 16},
 236                                      {0x0B, 8},
 237                                      {0x0C, 4},
 238                                      {0x0D, 2},
 239                                      {0x0E, 1},
 240                                      {0x0F, 1} };
 241
 242 static const struct {
 243         int sleep_dur;
 244         u8 reg_value;
 245 } bmc150_accel_sleep_value_table[] = { {0, 0},
 246                                        {500, BMC150_ACCEL_SLEEP_500_MICRO},
 247                                        {1000, BMC150_ACCEL_SLEEP_1_MS},
 248                                        {2000, BMC150_ACCEL_SLEEP_2_MS},
 249                                        {4000, BMC150_ACCEL_SLEEP_4_MS},
 250                                        {6000, BMC150_ACCEL_SLEEP_6_MS},
 251                                        {10000, BMC150_ACCEL_SLEEP_10_MS},
 252                                        {25000, BMC150_ACCEL_SLEEP_25_MS},
 253                                        {50000, BMC150_ACCEL_SLEEP_50_MS},
 254                                        {100000, BMC150_ACCEL_SLEEP_100_MS},
 255                                        {500000, BMC150_ACCEL_SLEEP_500_MS},
 256                                        {1000000, BMC150_ACCEL_SLEEP_1_SEC} };
 257
 258 const struct regmap_config bmc150_regmap_conf = {
 259         .reg_bits = 8,
 260         .val_bits = 8,
 261         .max_register = 0x3f,
 262 };
 263 EXPORT_SYMBOL_GPL(bmc150_regmap_conf);
 264
 265 static int bmc150_accel_set_mode(struct bmc150_accel_data *data,
 266                                  enum bmc150_power_modes mode,
 267                                  int dur_us)
 268 {
 269         struct device *dev = regmap_get_device(data->regmap);
 270         int i;
 271         int ret;
 272         u8 lpw_bits;
 273         int dur_val = -1;
 274
 275         if (dur_us > 0) {
 276                 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sleep_value_table);
 277                                                                          ++i) {
 278                         if (bmc150_accel_sleep_value_table[i].sleep_dur ==
 279                                                                         dur_us)
 280                                 dur_val =
 281                                 bmc150_accel_sleep_value_table[i].reg_value;
 282                 }
 283         } else {
 284                 dur_val = 0;
 285         }
 286
 287         if (dur_val < 0)
 288                 return -EINVAL;
 289
 290         lpw_bits = mode << BMC150_ACCEL_PMU_MODE_SHIFT;
 291         lpw_bits |= (dur_val << BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT);
 292
 293         dev_dbg(dev, "Set Mode bits %x\n", lpw_bits);
 294
 295         ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_LPW, lpw_bits);
 296         if (ret < 0) {
 297                 dev_err(dev, "Error writing reg_pmu_lpw\n");
 298                 return ret;
 299         }
 300
 301         return 0;
 302 }
 303
 304 static int bmc150_accel_set_bw(struct bmc150_accel_data *data, int val,
 305                                int val2)
 306 {
 307         int i;
 308         int ret;
 309
 310         for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
 311                 if (bmc150_accel_samp_freq_table[i].val == val &&
 312                     bmc150_accel_samp_freq_table[i].val2 == val2) {
 313                         ret = regmap_write(data->regmap,
 314                                 BMC150_ACCEL_REG_PMU_BW,
 315                                 bmc150_accel_samp_freq_table[i].bw_bits);
 316                         if (ret < 0)
 317                                 return ret;
 318
 319                         data->bw_bits =
 320                                 bmc150_accel_samp_freq_table[i].bw_bits;
 321                         return 0;
 322                 }
 323         }
 324
 325         return -EINVAL;
 326 }
 327
 328 static int bmc150_accel_update_slope(struct bmc150_accel_data *data)
 329 {
 330         struct device *dev = regmap_get_device(data->regmap);
 331         int ret;
 332
 333         ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_6,
 334                                         data->slope_thres);
 335         if (ret < 0) {
 336                 dev_err(dev, "Error writing reg_int_6\n");
 337                 return ret;
 338         }
 339
 340         ret = regmap_update_bits(data->regmap, BMC150_ACCEL_REG_INT_5,
 341                                  BMC150_ACCEL_SLOPE_DUR_MASK, data->slope_dur);
 342         if (ret < 0) {
 343                 dev_err(dev, "Error updating reg_int_5\n");
 344                 return ret;
 345         }
 346
 347         dev_dbg(dev, "%s: %x %x\n", __func__, data->slope_thres,
 348                 data->slope_dur);
 349
 350         return ret;
 351 }
 352
 353 static int bmc150_accel_any_motion_setup(struct bmc150_accel_trigger *t,
 354                                          bool state)
 355 {
 356         if (state)
 357                 return bmc150_accel_update_slope(t->data);
 358
 359         return 0;
 360 }
 361
 362 static int bmc150_accel_get_bw(struct bmc150_accel_data *data, int *val,
 363                                int *val2)
 364 {
 365         int i;
 366
 367         for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
 368                 if (bmc150_accel_samp_freq_table[i].bw_bits == data->bw_bits) {
 369                         *val = bmc150_accel_samp_freq_table[i].val;
 370                         *val2 = bmc150_accel_samp_freq_table[i].val2;
 371                         return IIO_VAL_INT_PLUS_MICRO;
 372                 }
 373         }
 374
 375         return -EINVAL;
 376 }
 377
 378 #ifdef CONFIG_PM
 379 static int bmc150_accel_get_startup_times(struct bmc150_accel_data *data)
 380 {
 381         int i;
 382
 383         for (i = 0; i < ARRAY_SIZE(bmc150_accel_sample_upd_time); ++i) {
 384                 if (bmc150_accel_sample_upd_time[i].bw_bits == data->bw_bits)
 385                         return bmc150_accel_sample_upd_time[i].msec;
 386         }
 387
 388         return BMC150_ACCEL_MAX_STARTUP_TIME_MS;
 389 }
 390
 391 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
 392 {
 393         struct device *dev = regmap_get_device(data->regmap);
 394         int ret;
 395
 396         if (on) {
 397                 ret = pm_runtime_get_sync(dev);
 398         } else {
 399                 pm_runtime_mark_last_busy(dev);
 400                 ret = pm_runtime_put_autosuspend(dev);
 401         }
 402
 403         if (ret < 0) {
 404                 dev_err(dev,
 405                         "Failed: bmc150_accel_set_power_state for %d\n", on);
 406                 if (on)
 407                         pm_runtime_put_noidle(dev);
 408
 409                 return ret;
 410         }
 411
 412         return 0;
 413 }
 414 #else
 415 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
 416 {
 417         return 0;
 418 }
 419 #endif
 420
 421 static const struct bmc150_accel_interrupt_info {
 422         u8 map_reg;
 423         u8 map_bitmask;
 424         u8 en_reg;
 425         u8 en_bitmask;
 426 } bmc150_accel_interrupts[BMC150_ACCEL_INTERRUPTS] = {
 427         { /* data ready interrupt */
 428                 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
 429                 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_DATA,
 430                 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
 431                 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_DATA_EN,
 432         },
 433         {  /* motion interrupt */
 434                 .map_reg = BMC150_ACCEL_REG_INT_MAP_0,
 435                 .map_bitmask = BMC150_ACCEL_INT_MAP_0_BIT_SLOPE,
 436                 .en_reg = BMC150_ACCEL_REG_INT_EN_0,
 437                 .en_bitmask =  BMC150_ACCEL_INT_EN_BIT_SLP_X |
 438                         BMC150_ACCEL_INT_EN_BIT_SLP_Y |
 439                         BMC150_ACCEL_INT_EN_BIT_SLP_Z
 440         },
 441         { /* fifo watermark interrupt */
 442                 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
 443                 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_FWM,
 444                 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
 445                 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_FWM_EN,
 446         },
 447 };
 448
 449 static void bmc150_accel_interrupts_setup(struct iio_dev *indio_dev,
 450                                           struct bmc150_accel_data *data)
 451 {
 452         int i;
 453
 454         for (i = 0; i < BMC150_ACCEL_INTERRUPTS; i++)
 455                 data->interrupts[i].info = &bmc150_accel_interrupts[i];
 456 }
 457
 458 static int bmc150_accel_set_interrupt(struct bmc150_accel_data *data, int i,
 459                                       bool state)
 460 {
 461         struct device *dev = regmap_get_device(data->regmap);
 462         struct bmc150_accel_interrupt *intr = &data->interrupts[i];
 463         const struct bmc150_accel_interrupt_info *info = intr->info;
 464         int ret;
 465
 466         if (state) {
 467                 if (atomic_inc_return(&intr->users) > 1)
 468                         return 0;
 469         } else {
 470                 if (atomic_dec_return(&intr->users) > 0)
 471                         return 0;
 472         }
 473
 474         /*
 475          * We will expect the enable and disable to do operation in reverse
 476          * order. This will happen here anyway, as our resume operation uses
 477          * sync mode runtime pm calls. The suspend operation will be delayed
 478          * by autosuspend delay.
 479          * So the disable operation will still happen in reverse order of
 480          * enable operation. When runtime pm is disabled the mode is always on,
 481          * so sequence doesn't matter.
 482          */
 483         ret = bmc150_accel_set_power_state(data, state);
 484         if (ret < 0)
 485                 return ret;
 486
 487         /* map the interrupt to the appropriate pins */
 488         ret = regmap_update_bits(data->regmap, info->map_reg, info->map_bitmask,
 489                                  (state ? info->map_bitmask : 0));
 490         if (ret < 0) {
 491                 dev_err(dev, "Error updating reg_int_map\n");
 492                 goto out_fix_power_state;
 493         }
 494
 495         /* enable/disable the interrupt */
 496         ret = regmap_update_bits(data->regmap, info->en_reg, info->en_bitmask,
 497                                  (state ? info->en_bitmask : 0));
 498         if (ret < 0) {
 499                 dev_err(dev, "Error updating reg_int_en\n");
 500                 goto out_fix_power_state;
 501         }
 502
 503         return 0;
 504
 505 out_fix_power_state:
 506         bmc150_accel_set_power_state(data, false);
 507         return ret;
 508 }
 509
 510 static int bmc150_accel_set_scale(struct bmc150_accel_data *data, int val)
 511 {
 512         struct device *dev = regmap_get_device(data->regmap);
 513         int ret, i;
 514
 515         for (i = 0; i < ARRAY_SIZE(data->chip_info->scale_table); ++i) {
 516                 if (data->chip_info->scale_table[i].scale == val) {
 517                         ret = regmap_write(data->regmap,
 518                                      BMC150_ACCEL_REG_PMU_RANGE,
 519                                      data->chip_info->scale_table[i].reg_range);
 520                         if (ret < 0) {
 521                                 dev_err(dev, "Error writing pmu_range\n");
 522                                 return ret;
 523                         }
 524
 525                         data->range = data->chip_info->scale_table[i].reg_range;
 526                         return 0;
 527                 }
 528         }
 529
 530         return -EINVAL;
 531 }
 532
 533 static int bmc150_accel_get_temp(struct bmc150_accel_data *data, int *val)
 534 {
 535         struct device *dev = regmap_get_device(data->regmap);
 536         int ret;
 537         unsigned int value;
 538
 539         mutex_lock(&data->mutex);
 540
 541         ret = regmap_read(data->regmap, BMC150_ACCEL_REG_TEMP, &value);
 542         if (ret < 0) {
 543                 dev_err(dev, "Error reading reg_temp\n");
 544                 mutex_unlock(&data->mutex);
 545                 return ret;
 546         }
 547         *val = sign_extend32(value, 7);
 548
 549         mutex_unlock(&data->mutex);
 550
 551         return IIO_VAL_INT;
 552 }
 553
 554 static int bmc150_accel_get_axis(struct bmc150_accel_data *data,
 555                                  struct iio_chan_spec const *chan,
 556                                  int *val)
 557 {
 558         struct device *dev = regmap_get_device(data->regmap);
 559         int ret;
 560         int axis = chan->scan_index;
 561         __le16 raw_val;
 562
 563         mutex_lock(&data->mutex);
 564         ret = bmc150_accel_set_power_state(data, true);
 565         if (ret < 0) {
 566                 mutex_unlock(&data->mutex);
 567                 return ret;
 568         }
 569
 570         ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_AXIS_TO_REG(axis),
 571                                &raw_val, sizeof(raw_val));
 572         if (ret < 0) {
 573                 dev_err(dev, "Error reading axis %d\n", axis);
 574                 bmc150_accel_set_power_state(data, false);
 575                 mutex_unlock(&data->mutex);
 576                 return ret;
 577         }
 578         *val = sign_extend32(le16_to_cpu(raw_val) >> chan->scan_type.shift,
 579                              chan->scan_type.realbits - 1);
 580         ret = bmc150_accel_set_power_state(data, false);
 581         mutex_unlock(&data->mutex);
 582         if (ret < 0)
 583                 return ret;
 584
 585         return IIO_VAL_INT;
 586 }
 587
 588 static int bmc150_accel_read_raw(struct iio_dev *indio_dev,
 589                                  struct iio_chan_spec const *chan,
 590                                  int *val, int *val2, long mask)
 591 {
 592         struct bmc150_accel_data *data = iio_priv(indio_dev);
 593         int ret;
 594
 595         switch (mask) {
 596         case IIO_CHAN_INFO_RAW:
 597                 switch (chan->type) {
 598                 case IIO_TEMP:
 599                         return bmc150_accel_get_temp(data, val);
 600                 case IIO_ACCEL:
 601                         if (iio_buffer_enabled(indio_dev))
 602                                 return -EBUSY;
 603                         else
 604                                 return bmc150_accel_get_axis(data, chan, val);
 605                 default:
 606                         return -EINVAL;
 607                 }
 608         case IIO_CHAN_INFO_OFFSET:
 609                 if (chan->type == IIO_TEMP) {
 610                         *val = BMC150_ACCEL_TEMP_CENTER_VAL;
 611                         return IIO_VAL_INT;
 612                 } else {
 613                         return -EINVAL;
 614                 }
 615         case IIO_CHAN_INFO_SCALE:
 616                 *val = 0;
 617                 switch (chan->type) {
 618                 case IIO_TEMP:
 619                         *val2 = 500000;
 620                         return IIO_VAL_INT_PLUS_MICRO;
 621                 case IIO_ACCEL:
 622                 {
 623                         int i;
 624                         const struct bmc150_scale_info *si;
 625                         int st_size = ARRAY_SIZE(data->chip_info->scale_table);
 626
 627                         for (i = 0; i < st_size; ++i) {
 628                                 si = &data->chip_info->scale_table[i];
 629                                 if (si->reg_range == data->range) {
 630                                         *val2 = si->scale;
 631                                         return IIO_VAL_INT_PLUS_MICRO;
 632                                 }
 633                         }
 634                         return -EINVAL;
 635                 }
 636                 default:
 637                         return -EINVAL;
 638                 }
 639         case IIO_CHAN_INFO_SAMP_FREQ:
 640                 mutex_lock(&data->mutex);
 641                 ret = bmc150_accel_get_bw(data, val, val2);
 642                 mutex_unlock(&data->mutex);
 643                 return ret;
 644         default:
 645                 return -EINVAL;
 646         }
 647 }
 648
 649 static int bmc150_accel_write_raw(struct iio_dev *indio_dev,
 650                                   struct iio_chan_spec const *chan,
 651                                   int val, int val2, long mask)
 652 {
 653         struct bmc150_accel_data *data = iio_priv(indio_dev);
 654         int ret;
 655
 656         switch (mask) {
 657         case IIO_CHAN_INFO_SAMP_FREQ:
 658                 mutex_lock(&data->mutex);
 659                 ret = bmc150_accel_set_bw(data, val, val2);
 660                 mutex_unlock(&data->mutex);
 661                 break;
 662         case IIO_CHAN_INFO_SCALE:
 663                 if (val)
 664                         return -EINVAL;
 665
 666                 mutex_lock(&data->mutex);
 667                 ret = bmc150_accel_set_scale(data, val2);
 668                 mutex_unlock(&data->mutex);
 669                 return ret;
 670         default:
 671                 ret = -EINVAL;
 672         }
 673
 674         return ret;
 675 }
 676
 677 static int bmc150_accel_read_event(struct iio_dev *indio_dev,
 678                                    const struct iio_chan_spec *chan,
 679                                    enum iio_event_type type,
 680                                    enum iio_event_direction dir,
 681                                    enum iio_event_info info,
 682                                    int *val, int *val2)
 683 {
 684         struct bmc150_accel_data *data = iio_priv(indio_dev);
 685
 686         *val2 = 0;
 687         switch (info) {
 688         case IIO_EV_INFO_VALUE:
 689                 *val = data->slope_thres;
 690                 break;
 691         case IIO_EV_INFO_PERIOD:
 692                 *val = data->slope_dur;
 693                 break;
 694         default:
 695                 return -EINVAL;
 696         }
 697
 698         return IIO_VAL_INT;
 699 }
 700
 701 static int bmc150_accel_write_event(struct iio_dev *indio_dev,
 702                                     const struct iio_chan_spec *chan,
 703                                     enum iio_event_type type,
 704                                     enum iio_event_direction dir,
 705                                     enum iio_event_info info,
 706                                     int val, int val2)
 707 {
 708         struct bmc150_accel_data *data = iio_priv(indio_dev);
 709
 710         if (data->ev_enable_state)
 711                 return -EBUSY;
 712
 713         switch (info) {
 714         case IIO_EV_INFO_VALUE:
 715                 data->slope_thres = val & BMC150_ACCEL_SLOPE_THRES_MASK;
 716                 break;
 717         case IIO_EV_INFO_PERIOD:
 718                 data->slope_dur = val & BMC150_ACCEL_SLOPE_DUR_MASK;
 719                 break;
 720         default:
 721                 return -EINVAL;
 722         }
 723
 724         return 0;
 725 }
 726
 727 static int bmc150_accel_read_event_config(struct iio_dev *indio_dev,
 728                                           const struct iio_chan_spec *chan,
 729                                           enum iio_event_type type,
 730                                           enum iio_event_direction dir)
 731 {
 732         struct bmc150_accel_data *data = iio_priv(indio_dev);
 733
 734         return data->ev_enable_state;
 735 }
 736
 737 static int bmc150_accel_write_event_config(struct iio_dev *indio_dev,
 738                                            const struct iio_chan_spec *chan,
 739                                            enum iio_event_type type,
 740                                            enum iio_event_direction dir,
 741                                            int state)
 742 {
 743         struct bmc150_accel_data *data = iio_priv(indio_dev);
 744         int ret;
 745
 746         if (state == data->ev_enable_state)
 747                 return 0;
 748
 749         mutex_lock(&data->mutex);
 750
 751         ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_ANY_MOTION,
 752                                          state);
 753         if (ret < 0) {
 754                 mutex_unlock(&data->mutex);
 755                 return ret;
 756         }
 757
 758         data->ev_enable_state = state;
 759         mutex_unlock(&data->mutex);
 760
 761         return 0;
 762 }
 763
 764 static int bmc150_accel_validate_trigger(struct iio_dev *indio_dev,
 765                                          struct iio_trigger *trig)
 766 {
 767         struct bmc150_accel_data *data = iio_priv(indio_dev);
 768         int i;
 769
 770         for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
 771                 if (data->triggers[i].indio_trig == trig)
 772                         return 0;
 773         }
 774
 775         return -EINVAL;
 776 }
 777
 778 static ssize_t bmc150_accel_get_fifo_watermark(struct device *dev,
 779                                                struct device_attribute *attr,
 780                                                char *buf)
 781 {
 782         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 783         struct bmc150_accel_data *data = iio_priv(indio_dev);
 784         int wm;
 785
 786         mutex_lock(&data->mutex);
 787         wm = data->watermark;
 788         mutex_unlock(&data->mutex);
 789
 790         return sprintf(buf, "%d\n", wm);
 791 }
 792
 793 static ssize_t bmc150_accel_get_fifo_state(struct device *dev,
 794                                            struct device_attribute *attr,
 795                                            char *buf)
 796 {
 797         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 798         struct bmc150_accel_data *data = iio_priv(indio_dev);
 799         bool state;
 800
 801         mutex_lock(&data->mutex);
 802         state = data->fifo_mode;
 803         mutex_unlock(&data->mutex);
 804
 805         return sprintf(buf, "%d\n", state);
 806 }
 807
 808 static IIO_CONST_ATTR(hwfifo_watermark_min, "1");
 809 static IIO_CONST_ATTR(hwfifo_watermark_max,
 810                       __stringify(BMC150_ACCEL_FIFO_LENGTH));
 811 static IIO_DEVICE_ATTR(hwfifo_enabled, S_IRUGO,
 812                        bmc150_accel_get_fifo_state, NULL, 0);
 813 static IIO_DEVICE_ATTR(hwfifo_watermark, S_IRUGO,
 814                        bmc150_accel_get_fifo_watermark, NULL, 0);
 815
 816 static const struct attribute *bmc150_accel_fifo_attributes[] = {
 817         &iio_const_attr_hwfifo_watermark_min.dev_attr.attr,
 818         &iio_const_attr_hwfifo_watermark_max.dev_attr.attr,
 819         &iio_dev_attr_hwfifo_watermark.dev_attr.attr,
 820         &iio_dev_attr_hwfifo_enabled.dev_attr.attr,
 821         NULL,
 822 };
 823
 824 static int bmc150_accel_set_watermark(struct iio_dev *indio_dev, unsigned val)
 825 {
 826         struct bmc150_accel_data *data = iio_priv(indio_dev);
 827
 828         if (val > BMC150_ACCEL_FIFO_LENGTH)
 829                 val = BMC150_ACCEL_FIFO_LENGTH;
 830
 831         mutex_lock(&data->mutex);
 832         data->watermark = val;
 833         mutex_unlock(&data->mutex);
 834
 835         return 0;
 836 }
 837
 838 /*
 839  * We must read at least one full frame in one burst, otherwise the rest of the
 840  * frame data is discarded.
 841  */
 842 static int bmc150_accel_fifo_transfer(struct bmc150_accel_data *data,
 843                                       char *buffer, int samples)
 844 {
 845         struct device *dev = regmap_get_device(data->regmap);
 846         int sample_length = 3 * 2;
 847         int ret;
 848         int total_length = samples * sample_length;
 849         int i;
 850         size_t step = regmap_get_raw_read_max(data->regmap);
 851
 852         if (!step || step > total_length)
 853                 step = total_length;
 854         else if (step < total_length)
 855                 step = sample_length;
 856
 857         /*
 858          * Seems we have a bus with size limitation so we have to execute
 859          * multiple reads
 860          */
 861         for (i = 0; i < total_length; i += step) {
 862                 ret = regmap_raw_read(data->regmap, BMC150_ACCEL_REG_FIFO_DATA,
 863                                       &buffer[i], step);
 864                 if (ret)
 865                         break;
 866         }
 867
 868         if (ret)
 869                 dev_err(dev,
 870                         "Error transferring data from fifo in single steps of %zu\n",
 871                         step);
 872
 873         return ret;
 874 }
 875
 876 static int __bmc150_accel_fifo_flush(struct iio_dev *indio_dev,
 877                                      unsigned samples, bool irq)
 878 {
 879         struct bmc150_accel_data *data = iio_priv(indio_dev);
 880         struct device *dev = regmap_get_device(data->regmap);
 881         int ret, i;
 882         u8 count;
 883         u16 buffer[BMC150_ACCEL_FIFO_LENGTH * 3];
 884         int64_t tstamp;
 885         uint64_t sample_period;
 886         unsigned int val;
 887
 888         ret = regmap_read(data->regmap, BMC150_ACCEL_REG_FIFO_STATUS, &val);
 889         if (ret < 0) {
 890                 dev_err(dev, "Error reading reg_fifo_status\n");
 891                 return ret;
 892         }
 893
 894         count = val & 0x7F;
 895
 896         if (!count)
 897                 return 0;
 898
 899         /*
 900          * If we getting called from IRQ handler we know the stored timestamp is
 901          * fairly accurate for the last stored sample. Otherwise, if we are
 902          * called as a result of a read operation from userspace and hence
 903          * before the watermark interrupt was triggered, take a timestamp
 904          * now. We can fall anywhere in between two samples so the error in this
 905          * case is at most one sample period.
 906          */
 907         if (!irq) {
 908                 data->old_timestamp = data->timestamp;
 909                 data->timestamp = iio_get_time_ns(indio_dev);
 910         }
 911
 912         /*
 913          * Approximate timestamps for each of the sample based on the sampling
 914          * frequency, timestamp for last sample and number of samples.
 915          *
 916          * Note that we can't use the current bandwidth settings to compute the
 917          * sample period because the sample rate varies with the device
 918          * (e.g. between 31.70ms to 32.20ms for a bandwidth of 15.63HZ). That
 919          * small variation adds when we store a large number of samples and
 920          * creates significant jitter between the last and first samples in
 921          * different batches (e.g. 32ms vs 21ms).
 922          *
 923          * To avoid this issue we compute the actual sample period ourselves
 924          * based on the timestamp delta between the last two flush operations.
 925          */
 926         sample_period = (data->timestamp - data->old_timestamp);
 927         do_div(sample_period, count);
 928         tstamp = data->timestamp - (count - 1) * sample_period;
 929
 930         if (samples && count > samples)
 931                 count = samples;
 932
 933         ret = bmc150_accel_fifo_transfer(data, (u8 *)buffer, count);
 934         if (ret)
 935                 return ret;
 936
 937         /*
 938          * Ideally we want the IIO core to handle the demux when running in fifo
 939          * mode but not when running in triggered buffer mode. Unfortunately
 940          * this does not seem to be possible, so stick with driver demux for
 941          * now.
 942          */
 943         for (i = 0; i < count; i++) {
 944                 int j, bit;
 945
 946                 j = 0;
 947                 for_each_set_bit(bit, indio_dev->active_scan_mask,
 948                                  indio_dev->masklength)
 949                         memcpy(&data->scan.channels[j++], &buffer[i * 3 + bit],
 950                                sizeof(data->scan.channels[0]));
 951
 952                 iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
 953                                                    tstamp);
 954
 955                 tstamp += sample_period;
 956         }
 957
 958         return count;
 959 }
 960
 961 static int bmc150_accel_fifo_flush(struct iio_dev *indio_dev, unsigned samples)
 962 {
 963         struct bmc150_accel_data *data = iio_priv(indio_dev);
 964         int ret;
 965
 966         mutex_lock(&data->mutex);
 967         ret = __bmc150_accel_fifo_flush(indio_dev, samples, false);
 968         mutex_unlock(&data->mutex);
 969
 970         return ret;
 971 }
 972
 973 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
 974                 "15.620000 31.260000 62.50000 125 250 500 1000 2000");
 975
 976 static struct attribute *bmc150_accel_attributes[] = {
 977         &iio_const_attr_sampling_frequency_available.dev_attr.attr,
 978         NULL,
 979 };
 980
 981 static const struct attribute_group bmc150_accel_attrs_group = {
 982         .attrs = bmc150_accel_attributes,
 983 };
 984
 985 static const struct iio_event_spec bmc150_accel_event = {
 986                 .type = IIO_EV_TYPE_ROC,
 987                 .dir = IIO_EV_DIR_EITHER,
 988                 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
 989                                  BIT(IIO_EV_INFO_ENABLE) |
 990                                  BIT(IIO_EV_INFO_PERIOD)
 991 };
 992
 993 #define BMC150_ACCEL_CHANNEL(_axis, bits) {                             \
 994         .type = IIO_ACCEL,                                              \
 995         .modified = 1,                                                  \
 996         .channel2 = IIO_MOD_##_axis,                                    \
 997         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),                   \
 998         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |          \
 999                                 BIT(IIO_CHAN_INFO_SAMP_FREQ),           \
1000         .scan_index = AXIS_##_axis,                                     \
1001         .scan_type = {                                                  \
1002                 .sign = 's',                                            \
1003                 .realbits = (bits),                                     \
1004                 .storagebits = 16,                                      \
1005                 .shift = 16 - (bits),                                   \
1006                 .endianness = IIO_LE,                                   \
1007         },                                                              \
1008         .event_spec = &bmc150_accel_event,                              \
1009         .num_event_specs = 1                                            \
1010 }
1011
1012 #define BMC150_ACCEL_CHANNELS(bits) {                                   \
1013         {                                                               \
1014                 .type = IIO_TEMP,                                       \
1015                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |          \
1016                                       BIT(IIO_CHAN_INFO_SCALE) |        \
1017                                       BIT(IIO_CHAN_INFO_OFFSET),        \
1018                 .scan_index = -1,                                       \
1019         },                                                              \
1020         BMC150_ACCEL_CHANNEL(X, bits),                                  \
1021         BMC150_ACCEL_CHANNEL(Y, bits),                                  \
1022         BMC150_ACCEL_CHANNEL(Z, bits),                                  \
1023         IIO_CHAN_SOFT_TIMESTAMP(3),                                     \
1024 }
1025
1026 static const struct iio_chan_spec bma222e_accel_channels[] =
1027         BMC150_ACCEL_CHANNELS(8);
1028 static const struct iio_chan_spec bma250e_accel_channels[] =
1029         BMC150_ACCEL_CHANNELS(10);
1030 static const struct iio_chan_spec bmc150_accel_channels[] =
1031         BMC150_ACCEL_CHANNELS(12);
1032 static const struct iio_chan_spec bma280_accel_channels[] =
1033         BMC150_ACCEL_CHANNELS(14);
1034
1035 static const struct bmc150_accel_chip_info bmc150_accel_chip_info_tbl[] = {
1036         [bmc150] = {
1037                 .name = "BMC150A",
1038                 .chip_id = 0xFA,
1039                 .channels = bmc150_accel_channels,
1040                 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1041                 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1042                                  {19122, BMC150_ACCEL_DEF_RANGE_4G},
1043                                  {38344, BMC150_ACCEL_DEF_RANGE_8G},
1044                                  {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1045         },
1046         [bmi055] = {
1047                 .name = "BMI055A",
1048                 .chip_id = 0xFA,
1049                 .channels = bmc150_accel_channels,
1050                 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1051                 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1052                                  {19122, BMC150_ACCEL_DEF_RANGE_4G},
1053                                  {38344, BMC150_ACCEL_DEF_RANGE_8G},
1054                                  {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1055         },
1056         [bma255] = {
1057                 .name = "BMA0255",
1058                 .chip_id = 0xFA,
1059                 .channels = bmc150_accel_channels,
1060                 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1061                 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1062                                  {19122, BMC150_ACCEL_DEF_RANGE_4G},
1063                                  {38344, BMC150_ACCEL_DEF_RANGE_8G},
1064                                  {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1065         },
1066         [bma250e] = {
1067                 .name = "BMA250E",
1068                 .chip_id = 0xF9,
1069                 .channels = bma250e_accel_channels,
1070                 .num_channels = ARRAY_SIZE(bma250e_accel_channels),
1071                 .scale_table = { {38344, BMC150_ACCEL_DEF_RANGE_2G},
1072                                  {76590, BMC150_ACCEL_DEF_RANGE_4G},
1073                                  {153277, BMC150_ACCEL_DEF_RANGE_8G},
1074                                  {306457, BMC150_ACCEL_DEF_RANGE_16G} },
1075         },
1076         [bma222e] = {
1077                 .name = "BMA222E",
1078                 .chip_id = 0xF8,
1079                 .channels = bma222e_accel_channels,
1080                 .num_channels = ARRAY_SIZE(bma222e_accel_channels),
1081                 .scale_table = { {153277, BMC150_ACCEL_DEF_RANGE_2G},
1082                                  {306457, BMC150_ACCEL_DEF_RANGE_4G},
1083                                  {612915, BMC150_ACCEL_DEF_RANGE_8G},
1084                                  {1225831, BMC150_ACCEL_DEF_RANGE_16G} },
1085         },
1086         [bma280] = {
1087                 .name = "BMA0280",
1088                 .chip_id = 0xFB,
1089                 .channels = bma280_accel_channels,
1090                 .num_channels = ARRAY_SIZE(bma280_accel_channels),
1091                 .scale_table = { {2392, BMC150_ACCEL_DEF_RANGE_2G},
1092                                  {4785, BMC150_ACCEL_DEF_RANGE_4G},
1093                                  {9581, BMC150_ACCEL_DEF_RANGE_8G},
1094                                  {19152, BMC150_ACCEL_DEF_RANGE_16G} },
1095         },
1096 };
1097
1098 static const struct iio_info bmc150_accel_info = {
1099         .attrs                  = &bmc150_accel_attrs_group,
1100         .read_raw               = bmc150_accel_read_raw,
1101         .write_raw              = bmc150_accel_write_raw,
1102         .read_event_value       = bmc150_accel_read_event,
1103         .write_event_value      = bmc150_accel_write_event,
1104         .write_event_config     = bmc150_accel_write_event_config,
1105         .read_event_config      = bmc150_accel_read_event_config,
1106         .driver_module          = THIS_MODULE,
1107 };
1108
1109 static const struct iio_info bmc150_accel_info_fifo = {
1110         .attrs                  = &bmc150_accel_attrs_group,
1111         .read_raw               = bmc150_accel_read_raw,
1112         .write_raw              = bmc150_accel_write_raw,
1113         .read_event_value       = bmc150_accel_read_event,
1114         .write_event_value      = bmc150_accel_write_event,
1115         .write_event_config     = bmc150_accel_write_event_config,
1116         .read_event_config      = bmc150_accel_read_event_config,
1117         .validate_trigger       = bmc150_accel_validate_trigger,
1118         .hwfifo_set_watermark   = bmc150_accel_set_watermark,
1119         .hwfifo_flush_to_buffer = bmc150_accel_fifo_flush,
1120         .driver_module          = THIS_MODULE,
1121 };
1122
1123 static const unsigned long bmc150_accel_scan_masks[] = {
1124                                         BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z),
1125                                         0};
1126
1127 static irqreturn_t bmc150_accel_trigger_handler(int irq, void *p)
1128 {
1129         struct iio_poll_func *pf = p;
1130         struct iio_dev *indio_dev = pf->indio_dev;
1131         struct bmc150_accel_data *data = iio_priv(indio_dev);
1132         int ret;
1133
1134         mutex_lock(&data->mutex);
1135         ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_REG_XOUT_L,
1136                                data->buffer, AXIS_MAX * 2);
1137         mutex_unlock(&data->mutex);
1138         if (ret < 0)
1139                 goto err_read;
1140
1141         iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
1142                                            pf->timestamp);
1143 err_read:
1144         iio_trigger_notify_done(indio_dev->trig);
1145
1146         return IRQ_HANDLED;
1147 }
1148
1149 static int bmc150_accel_trig_try_reen(struct iio_trigger *trig)
1150 {
1151         struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1152         struct bmc150_accel_data *data = t->data;
1153         struct device *dev = regmap_get_device(data->regmap);
1154         int ret;
1155
1156         /* new data interrupts don't need ack */
1157         if (t == &t->data->triggers[BMC150_ACCEL_TRIGGER_DATA_READY])
1158                 return 0;
1159
1160         mutex_lock(&data->mutex);
1161         /* clear any latched interrupt */
1162         ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1163                            BMC150_ACCEL_INT_MODE_LATCH_INT |
1164                            BMC150_ACCEL_INT_MODE_LATCH_RESET);
1165         mutex_unlock(&data->mutex);
1166         if (ret < 0) {
1167                 dev_err(dev, "Error writing reg_int_rst_latch\n");
1168                 return ret;
1169         }
1170
1171         return 0;
1172 }
1173
1174 static int bmc150_accel_trigger_set_state(struct iio_trigger *trig,
1175                                           bool state)
1176 {
1177         struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1178         struct bmc150_accel_data *data = t->data;
1179         int ret;
1180
1181         mutex_lock(&data->mutex);
1182
1183         if (t->enabled == state) {
1184                 mutex_unlock(&data->mutex);
1185                 return 0;
1186         }
1187
1188         if (t->setup) {
1189                 ret = t->setup(t, state);
1190                 if (ret < 0) {
1191                         mutex_unlock(&data->mutex);
1192                         return ret;
1193                 }
1194         }
1195
1196         ret = bmc150_accel_set_interrupt(data, t->intr, state);
1197         if (ret < 0) {
1198                 mutex_unlock(&data->mutex);
1199                 return ret;
1200         }
1201
1202         t->enabled = state;
1203
1204         mutex_unlock(&data->mutex);
1205
1206         return ret;
1207 }
1208
1209 static const struct iio_trigger_ops bmc150_accel_trigger_ops = {
1210         .set_trigger_state = bmc150_accel_trigger_set_state,
1211         .try_reenable = bmc150_accel_trig_try_reen,
1212         .owner = THIS_MODULE,
1213 };
1214
1215 static int bmc150_accel_handle_roc_event(struct iio_dev *indio_dev)
1216 {
1217         struct bmc150_accel_data *data = iio_priv(indio_dev);
1218         struct device *dev = regmap_get_device(data->regmap);
1219         int dir;
1220         int ret;
1221         unsigned int val;
1222
1223         ret = regmap_read(data->regmap, BMC150_ACCEL_REG_INT_STATUS_2, &val);
1224         if (ret < 0) {
1225                 dev_err(dev, "Error reading reg_int_status_2\n");
1226                 return ret;
1227         }
1228
1229         if (val & BMC150_ACCEL_ANY_MOTION_BIT_SIGN)
1230                 dir = IIO_EV_DIR_FALLING;
1231         else
1232                 dir = IIO_EV_DIR_RISING;
1233
1234         if (val & BMC150_ACCEL_ANY_MOTION_BIT_X)
1235                 iio_push_event(indio_dev,
1236                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
1237                                                   0,
1238                                                   IIO_MOD_X,
1239                                                   IIO_EV_TYPE_ROC,
1240                                                   dir),
1241                                data->timestamp);
1242
1243         if (val & BMC150_ACCEL_ANY_MOTION_BIT_Y)
1244                 iio_push_event(indio_dev,
1245                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
1246                                                   0,
1247                                                   IIO_MOD_Y,
1248                                                   IIO_EV_TYPE_ROC,
1249                                                   dir),
1250                                data->timestamp);
1251
1252         if (val & BMC150_ACCEL_ANY_MOTION_BIT_Z)
1253                 iio_push_event(indio_dev,
1254                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
1255                                                   0,
1256                                                   IIO_MOD_Z,
1257                                                   IIO_EV_TYPE_ROC,
1258                                                   dir),
1259                                data->timestamp);
1260
1261         return ret;
1262 }
1263
1264 static irqreturn_t bmc150_accel_irq_thread_handler(int irq, void *private)
1265 {
1266         struct iio_dev *indio_dev = private;
1267         struct bmc150_accel_data *data = iio_priv(indio_dev);
1268         struct device *dev = regmap_get_device(data->regmap);
1269         bool ack = false;
1270         int ret;
1271
1272         mutex_lock(&data->mutex);
1273
1274         if (data->fifo_mode) {
1275                 ret = __bmc150_accel_fifo_flush(indio_dev,
1276                                                 BMC150_ACCEL_FIFO_LENGTH, true);
1277                 if (ret > 0)
1278                         ack = true;
1279         }
1280
1281         if (data->ev_enable_state) {
1282                 ret = bmc150_accel_handle_roc_event(indio_dev);
1283                 if (ret > 0)
1284                         ack = true;
1285         }
1286
1287         if (ack) {
1288                 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1289                                    BMC150_ACCEL_INT_MODE_LATCH_INT |
1290                                    BMC150_ACCEL_INT_MODE_LATCH_RESET);
1291                 if (ret)
1292                         dev_err(dev, "Error writing reg_int_rst_latch\n");
1293
1294                 ret = IRQ_HANDLED;
1295         } else {
1296                 ret = IRQ_NONE;
1297         }
1298
1299         mutex_unlock(&data->mutex);
1300
1301         return ret;
1302 }
1303
1304 static irqreturn_t bmc150_accel_irq_handler(int irq, void *private)
1305 {
1306         struct iio_dev *indio_dev = private;
1307         struct bmc150_accel_data *data = iio_priv(indio_dev);
1308         bool ack = false;
1309         int i;
1310
1311         data->old_timestamp = data->timestamp;
1312         data->timestamp = iio_get_time_ns(indio_dev);
1313
1314         for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1315                 if (data->triggers[i].enabled) {
1316                         iio_trigger_poll(data->triggers[i].indio_trig);
1317                         ack = true;
1318                         break;
1319                 }
1320         }
1321
1322         if (data->ev_enable_state || data->fifo_mode)
1323                 return IRQ_WAKE_THREAD;
1324
1325         if (ack)
1326                 return IRQ_HANDLED;
1327
1328         return IRQ_NONE;
1329 }
1330
1331 static const struct {
1332         int intr;
1333         const char *name;
1334         int (*setup)(struct bmc150_accel_trigger *t, bool state);
1335 } bmc150_accel_triggers[BMC150_ACCEL_TRIGGERS] = {
1336         {
1337                 .intr = 0,
1338                 .name = "%s-dev%d",
1339         },
1340         {
1341                 .intr = 1,
1342                 .name = "%s-any-motion-dev%d",
1343                 .setup = bmc150_accel_any_motion_setup,
1344         },
1345 };
1346
1347 static void bmc150_accel_unregister_triggers(struct bmc150_accel_data *data,
1348                                              int from)
1349 {
1350         int i;
1351
1352         for (i = from; i >= 0; i--) {
1353                 if (data->triggers[i].indio_trig) {
1354                         iio_trigger_unregister(data->triggers[i].indio_trig);
1355                         data->triggers[i].indio_trig = NULL;
1356                 }
1357         }
1358 }
1359
1360 static int bmc150_accel_triggers_setup(struct iio_dev *indio_dev,
1361                                        struct bmc150_accel_data *data)
1362 {
1363         struct device *dev = regmap_get_device(data->regmap);
1364         int i, ret;
1365
1366         for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1367                 struct bmc150_accel_trigger *t = &data->triggers[i];
1368
1369                 t->indio_trig = devm_iio_trigger_alloc(dev,
1370                                         bmc150_accel_triggers[i].name,
1371                                                        indio_dev->name,
1372                                                        indio_dev->id);
1373                 if (!t->indio_trig) {
1374                         ret = -ENOMEM;
1375                         break;
1376                 }
1377
1378                 t->indio_trig->dev.parent = dev;
1379                 t->indio_trig->ops = &bmc150_accel_trigger_ops;
1380                 t->intr = bmc150_accel_triggers[i].intr;
1381                 t->data = data;
1382                 t->setup = bmc150_accel_triggers[i].setup;
1383                 iio_trigger_set_drvdata(t->indio_trig, t);
1384
1385                 ret = iio_trigger_register(t->indio_trig);
1386                 if (ret)
1387                         break;
1388         }
1389
1390         if (ret)
1391                 bmc150_accel_unregister_triggers(data, i - 1);
1392
1393         return ret;
1394 }
1395
1396 #define BMC150_ACCEL_FIFO_MODE_STREAM          0x80
1397 #define BMC150_ACCEL_FIFO_MODE_FIFO            0x40
1398 #define BMC150_ACCEL_FIFO_MODE_BYPASS          0x00
1399
1400 static int bmc150_accel_fifo_set_mode(struct bmc150_accel_data *data)
1401 {
1402         struct device *dev = regmap_get_device(data->regmap);
1403         u8 reg = BMC150_ACCEL_REG_FIFO_CONFIG1;
1404         int ret;
1405
1406         ret = regmap_write(data->regmap, reg, data->fifo_mode);
1407         if (ret < 0) {
1408                 dev_err(dev, "Error writing reg_fifo_config1\n");
1409                 return ret;
1410         }
1411
1412         if (!data->fifo_mode)
1413                 return 0;
1414
1415         ret = regmap_write(data->regmap, BMC150_ACCEL_REG_FIFO_CONFIG0,
1416                            data->watermark);
1417         if (ret < 0)
1418                 dev_err(dev, "Error writing reg_fifo_config0\n");
1419
1420         return ret;
1421 }
1422
1423 static int bmc150_accel_buffer_preenable(struct iio_dev *indio_dev)
1424 {
1425         struct bmc150_accel_data *data = iio_priv(indio_dev);
1426
1427         return bmc150_accel_set_power_state(data, true);
1428 }
1429
1430 static int bmc150_accel_buffer_postenable(struct iio_dev *indio_dev)
1431 {
1432         struct bmc150_accel_data *data = iio_priv(indio_dev);
1433         int ret = 0;
1434
1435         if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1436                 return iio_triggered_buffer_postenable(indio_dev);
1437
1438         mutex_lock(&data->mutex);
1439
1440         if (!data->watermark)
1441                 goto out;
1442
1443         ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1444                                          true);
1445         if (ret)
1446                 goto out;
1447
1448         data->fifo_mode = BMC150_ACCEL_FIFO_MODE_FIFO;
1449
1450         ret = bmc150_accel_fifo_set_mode(data);
1451         if (ret) {
1452                 data->fifo_mode = 0;
1453                 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1454                                            false);
1455         }
1456
1457 out:
1458         mutex_unlock(&data->mutex);
1459
1460         return ret;
1461 }
1462
1463 static int bmc150_accel_buffer_predisable(struct iio_dev *indio_dev)
1464 {
1465         struct bmc150_accel_data *data = iio_priv(indio_dev);
1466
1467         if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1468                 return iio_triggered_buffer_predisable(indio_dev);
1469
1470         mutex_lock(&data->mutex);
1471
1472         if (!data->fifo_mode)
1473                 goto out;
1474
1475         bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, false);
1476         __bmc150_accel_fifo_flush(indio_dev, BMC150_ACCEL_FIFO_LENGTH, false);
1477         data->fifo_mode = 0;
1478         bmc150_accel_fifo_set_mode(data);
1479
1480 out:
1481         mutex_unlock(&data->mutex);
1482
1483         return 0;
1484 }
1485
1486 static int bmc150_accel_buffer_postdisable(struct iio_dev *indio_dev)
1487 {
1488         struct bmc150_accel_data *data = iio_priv(indio_dev);
1489
1490         return bmc150_accel_set_power_state(data, false);
1491 }
1492
1493 static const struct iio_buffer_setup_ops bmc150_accel_buffer_ops = {
1494         .preenable = bmc150_accel_buffer_preenable,
1495         .postenable = bmc150_accel_buffer_postenable,
1496         .predisable = bmc150_accel_buffer_predisable,
1497         .postdisable = bmc150_accel_buffer_postdisable,
1498 };
1499
1500 static int bmc150_accel_chip_init(struct bmc150_accel_data *data)
1501 {
1502         struct device *dev = regmap_get_device(data->regmap);
1503         int ret, i;
1504         unsigned int val;
1505
1506         /*
1507          * Reset chip to get it in a known good state. A delay of 1.8ms after
1508          * reset is required according to the data sheets of supported chips.
1509          */
1510         regmap_write(data->regmap, BMC150_ACCEL_REG_RESET,
1511                      BMC150_ACCEL_RESET_VAL);
1512         usleep_range(1800, 2500);
1513
1514         ret = regmap_read(data->regmap, BMC150_ACCEL_REG_CHIP_ID, &val);
1515         if (ret < 0) {
1516                 dev_err(dev, "Error: Reading chip id\n");
1517                 return ret;
1518         }
1519
1520         dev_dbg(dev, "Chip Id %x\n", val);
1521         for (i = 0; i < ARRAY_SIZE(bmc150_accel_chip_info_tbl); i++) {
1522                 if (bmc150_accel_chip_info_tbl[i].chip_id == val) {
1523                         data->chip_info = &bmc150_accel_chip_info_tbl[i];
1524                         break;
1525                 }
1526         }
1527
1528         if (!data->chip_info) {
1529                 dev_err(dev, "Invalid chip %x\n", val);
1530                 return -ENODEV;
1531         }
1532
1533         ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1534         if (ret < 0)
1535                 return ret;
1536
1537         /* Set Bandwidth */
1538         ret = bmc150_accel_set_bw(data, BMC150_ACCEL_DEF_BW, 0);
1539         if (ret < 0)
1540                 return ret;
1541
1542         /* Set Default Range */
1543         ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_RANGE,
1544                            BMC150_ACCEL_DEF_RANGE_4G);
1545         if (ret < 0) {
1546                 dev_err(dev, "Error writing reg_pmu_range\n");
1547                 return ret;
1548         }
1549
1550         data->range = BMC150_ACCEL_DEF_RANGE_4G;
1551
1552         /* Set default slope duration and thresholds */
1553         data->slope_thres = BMC150_ACCEL_DEF_SLOPE_THRESHOLD;
1554         data->slope_dur = BMC150_ACCEL_DEF_SLOPE_DURATION;
1555         ret = bmc150_accel_update_slope(data);
1556         if (ret < 0)
1557                 return ret;
1558
1559         /* Set default as latched interrupts */
1560         ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1561                            BMC150_ACCEL_INT_MODE_LATCH_INT |
1562                            BMC150_ACCEL_INT_MODE_LATCH_RESET);
1563         if (ret < 0) {
1564                 dev_err(dev, "Error writing reg_int_rst_latch\n");
1565                 return ret;
1566         }
1567
1568         return 0;
1569 }
1570
1571 int bmc150_accel_core_probe(struct device *dev, struct regmap *regmap, int irq,
1572                             const char *name, bool block_supported)
1573 {
1574         struct bmc150_accel_data *data;
1575         struct iio_dev *indio_dev;
1576         int ret;
1577
1578         indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
1579         if (!indio_dev)
1580                 return -ENOMEM;
1581
1582         data = iio_priv(indio_dev);
1583         dev_set_drvdata(dev, indio_dev);
1584         data->irq = irq;
1585
1586         data->regmap = regmap;
1587
1588         ret = bmc150_accel_chip_init(data);
1589         if (ret < 0)
1590                 return ret;
1591
1592         mutex_init(&data->mutex);
1593
1594         indio_dev->dev.parent = dev;
1595         indio_dev->channels = data->chip_info->channels;
1596         indio_dev->num_channels = data->chip_info->num_channels;
1597         indio_dev->name = name ? name : data->chip_info->name;
1598         indio_dev->available_scan_masks = bmc150_accel_scan_masks;
1599         indio_dev->modes = INDIO_DIRECT_MODE;
1600         indio_dev->info = &bmc150_accel_info;
1601
1602         ret = iio_triggered_buffer_setup(indio_dev,
1603                                          &iio_pollfunc_store_time,
1604                                          bmc150_accel_trigger_handler,
1605                                          &bmc150_accel_buffer_ops);
1606         if (ret < 0) {
1607                 dev_err(dev, "Failed: iio triggered buffer setup\n");
1608                 return ret;
1609         }
1610
1611         if (data->irq > 0) {
1612                 ret = devm_request_threaded_irq(
1613                                                 dev, data->irq,
1614                                                 bmc150_accel_irq_handler,
1615                                                 bmc150_accel_irq_thread_handler,
1616                                                 IRQF_TRIGGER_RISING,
1617                                                 BMC150_ACCEL_IRQ_NAME,
1618                                                 indio_dev);
1619                 if (ret)
1620                         goto err_buffer_cleanup;
1621
1622                 /*
1623                  * Set latched mode interrupt. While certain interrupts are
1624                  * non-latched regardless of this settings (e.g. new data) we
1625                  * want to use latch mode when we can to prevent interrupt
1626                  * flooding.
1627                  */
1628                 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1629                                    BMC150_ACCEL_INT_MODE_LATCH_RESET);
1630                 if (ret < 0) {
1631                         dev_err(dev, "Error writing reg_int_rst_latch\n");
1632                         goto err_buffer_cleanup;
1633                 }
1634
1635                 bmc150_accel_interrupts_setup(indio_dev, data);
1636
1637                 ret = bmc150_accel_triggers_setup(indio_dev, data);
1638                 if (ret)
1639                         goto err_buffer_cleanup;
1640
1641                 if (block_supported) {
1642                         indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
1643                         indio_dev->info = &bmc150_accel_info_fifo;
1644                         iio_buffer_set_attrs(indio_dev->buffer,
1645                                              bmc150_accel_fifo_attributes);
1646                 }
1647         }
1648
1649         ret = pm_runtime_set_active(dev);
1650         if (ret)
1651                 goto err_trigger_unregister;
1652
1653         pm_runtime_enable(dev);
1654         pm_runtime_set_autosuspend_delay(dev, BMC150_AUTO_SUSPEND_DELAY_MS);
1655         pm_runtime_use_autosuspend(dev);
1656
1657         ret = iio_device_register(indio_dev);
1658         if (ret < 0) {
1659                 dev_err(dev, "Unable to register iio device\n");
1660                 goto err_trigger_unregister;
1661         }
1662
1663         return 0;
1664
1665 err_trigger_unregister:
1666         bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
1667 err_buffer_cleanup:
1668         iio_triggered_buffer_cleanup(indio_dev);
1669
1670         return ret;
1671 }
1672 EXPORT_SYMBOL_GPL(bmc150_accel_core_probe);
1673
1674 int bmc150_accel_core_remove(struct device *dev)
1675 {
1676         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1677         struct bmc150_accel_data *data = iio_priv(indio_dev);
1678
1679         iio_device_unregister(indio_dev);
1680
1681         pm_runtime_disable(dev);
1682         pm_runtime_set_suspended(dev);
1683         pm_runtime_put_noidle(dev);
1684
1685         bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
1686
1687         iio_triggered_buffer_cleanup(indio_dev);
1688
1689         mutex_lock(&data->mutex);
1690         bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, 0);
1691         mutex_unlock(&data->mutex);
1692
1693         return 0;
1694 }
1695 EXPORT_SYMBOL_GPL(bmc150_accel_core_remove);
1696
1697 #ifdef CONFIG_PM_SLEEP
1698 static int bmc150_accel_suspend(struct device *dev)
1699 {
1700         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1701         struct bmc150_accel_data *data = iio_priv(indio_dev);
1702
1703         mutex_lock(&data->mutex);
1704         bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1705         mutex_unlock(&data->mutex);
1706
1707         return 0;
1708 }
1709
1710 static int bmc150_accel_resume(struct device *dev)
1711 {
1712         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1713         struct bmc150_accel_data *data = iio_priv(indio_dev);
1714
1715         mutex_lock(&data->mutex);
1716         bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1717         bmc150_accel_fifo_set_mode(data);
1718         mutex_unlock(&data->mutex);
1719
1720         return 0;
1721 }
1722 #endif
1723
1724 #ifdef CONFIG_PM
1725 static int bmc150_accel_runtime_suspend(struct device *dev)
1726 {
1727         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1728         struct bmc150_accel_data *data = iio_priv(indio_dev);
1729         int ret;
1730
1731         dev_dbg(dev,  __func__);
1732         ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1733         if (ret < 0)
1734                 return -EAGAIN;
1735
1736         return 0;
1737 }
1738
1739 static int bmc150_accel_runtime_resume(struct device *dev)
1740 {
1741         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1742         struct bmc150_accel_data *data = iio_priv(indio_dev);
1743         int ret;
1744         int sleep_val;
1745
1746         dev_dbg(dev,  __func__);
1747
1748         ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1749         if (ret < 0)
1750                 return ret;
1751         ret = bmc150_accel_fifo_set_mode(data);
1752         if (ret < 0)
1753                 return ret;
1754
1755         sleep_val = bmc150_accel_get_startup_times(data);
1756         if (sleep_val < 20)
1757                 usleep_range(sleep_val * 1000, 20000);
1758         else
1759                 msleep_interruptible(sleep_val);
1760
1761         return 0;
1762 }
1763 #endif
1764
1765 const struct dev_pm_ops bmc150_accel_pm_ops = {
1766         SET_SYSTEM_SLEEP_PM_OPS(bmc150_accel_suspend, bmc150_accel_resume)
1767         SET_RUNTIME_PM_OPS(bmc150_accel_runtime_suspend,
1768                            bmc150_accel_runtime_resume, NULL)
1769 };
1770 EXPORT_SYMBOL_GPL(bmc150_accel_pm_ops);
1771
1772 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
1773 MODULE_LICENSE("GPL v2");
1774 MODULE_DESCRIPTION("BMC150 accelerometer driver");