2 * mma8452.c - Support for following Freescale 3-axis accelerometers:
9 * Copyright 2015 Martin Kepplinger <martin.kepplinger@theobroma-systems.com>
10 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net>
12 * This file is subject to the terms and conditions of version 2 of
13 * the GNU General Public License. See the file COPYING in the main
14 * directory of this archive for more details.
16 * 7-bit I2C slave address 0x1c/0x1d (pin selectable)
18 * TODO: orientation / freefall events, autosleep
21 #include <linux/module.h>
22 #include <linux/i2c.h>
23 #include <linux/iio/iio.h>
24 #include <linux/iio/sysfs.h>
25 #include <linux/iio/buffer.h>
26 #include <linux/iio/trigger.h>
27 #include <linux/iio/trigger_consumer.h>
28 #include <linux/iio/triggered_buffer.h>
29 #include <linux/iio/events.h>
30 #include <linux/delay.h>
31 #include <linux/of_device.h>
33 #define MMA8452_STATUS 0x00
34 #define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0))
35 #define MMA8452_OUT_X 0x01 /* MSB first */
36 #define MMA8452_OUT_Y 0x03
37 #define MMA8452_OUT_Z 0x05
38 #define MMA8452_INT_SRC 0x0c
39 #define MMA8452_WHO_AM_I 0x0d
40 #define MMA8452_DATA_CFG 0x0e
41 #define MMA8452_DATA_CFG_FS_MASK GENMASK(1, 0)
42 #define MMA8452_DATA_CFG_FS_2G 0
43 #define MMA8452_DATA_CFG_FS_4G 1
44 #define MMA8452_DATA_CFG_FS_8G 2
45 #define MMA8452_DATA_CFG_HPF_MASK BIT(4)
46 #define MMA8452_HP_FILTER_CUTOFF 0x0f
47 #define MMA8452_HP_FILTER_CUTOFF_SEL_MASK GENMASK(1, 0)
48 #define MMA8452_FF_MT_CFG 0x15
49 #define MMA8452_FF_MT_CFG_OAE BIT(6)
50 #define MMA8452_FF_MT_CFG_ELE BIT(7)
51 #define MMA8452_FF_MT_SRC 0x16
52 #define MMA8452_FF_MT_SRC_XHE BIT(1)
53 #define MMA8452_FF_MT_SRC_YHE BIT(3)
54 #define MMA8452_FF_MT_SRC_ZHE BIT(5)
55 #define MMA8452_FF_MT_THS 0x17
56 #define MMA8452_FF_MT_THS_MASK 0x7f
57 #define MMA8452_FF_MT_COUNT 0x18
58 #define MMA8452_TRANSIENT_CFG 0x1d
59 #define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0)
60 #define MMA8452_TRANSIENT_CFG_CHAN(chan) BIT(chan + 1)
61 #define MMA8452_TRANSIENT_CFG_ELE BIT(4)
62 #define MMA8452_TRANSIENT_SRC 0x1e
63 #define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1)
64 #define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3)
65 #define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5)
66 #define MMA8452_TRANSIENT_THS 0x1f
67 #define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0)
68 #define MMA8452_TRANSIENT_COUNT 0x20
69 #define MMA8452_CTRL_REG1 0x2a
70 #define MMA8452_CTRL_ACTIVE BIT(0)
71 #define MMA8452_CTRL_DR_MASK GENMASK(5, 3)
72 #define MMA8452_CTRL_DR_SHIFT 3
73 #define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */
74 #define MMA8452_CTRL_REG2 0x2b
75 #define MMA8452_CTRL_REG2_RST BIT(6)
76 #define MMA8452_CTRL_REG4 0x2d
77 #define MMA8452_CTRL_REG5 0x2e
78 #define MMA8452_OFF_X 0x2f
79 #define MMA8452_OFF_Y 0x30
80 #define MMA8452_OFF_Z 0x31
82 #define MMA8452_MAX_REG 0x31
84 #define MMA8452_INT_DRDY BIT(0)
85 #define MMA8452_INT_FF_MT BIT(2)
86 #define MMA8452_INT_TRANS BIT(5)
88 #define MMA8452_DEVICE_ID 0x2a
89 #define MMA8453_DEVICE_ID 0x3a
90 #define MMA8652_DEVICE_ID 0x4a
91 #define MMA8653_DEVICE_ID 0x5a
94 struct i2c_client *client;
98 const struct mma_chip_info *chip_info;
100 /* Ensure correct alignment of time stamp when present */
108 * struct mma_chip_info - chip specific data for Freescale's accelerometers
109 * @chip_id: WHO_AM_I register's value
110 * @channels: struct iio_chan_spec matching the device's
112 * @num_channels: number of channels
113 * @mma_scales: scale factors for converting register values
114 * to m/s^2; 3 modes: 2g, 4g, 8g; 2 integers
115 * per mode: m/s^2 and micro m/s^2
116 * @ev_cfg: event config register address
117 * @ev_cfg_ele: latch bit in event config register
118 * @ev_cfg_chan_shift: number of the bit to enable events in X
119 * direction; in event config register
120 * @ev_src: event source register address
121 * @ev_src_xe: bit in event source register that indicates
122 * an event in X direction
123 * @ev_src_ye: bit in event source register that indicates
124 * an event in Y direction
125 * @ev_src_ze: bit in event source register that indicates
126 * an event in Z direction
127 * @ev_ths: event threshold register address
128 * @ev_ths_mask: mask for the threshold value
129 * @ev_count: event count (period) register address
131 * Since not all chips supported by the driver support comparing high pass
132 * filtered data for events (interrupts), different interrupt sources are
133 * used for different chips and the relevant registers are included here.
135 struct mma_chip_info {
137 const struct iio_chan_spec *channels;
139 const int mma_scales[3][2];
142 u8 ev_cfg_chan_shift;
152 static int mma8452_drdy(struct mma8452_data *data)
156 while (tries-- > 0) {
157 int ret = i2c_smbus_read_byte_data(data->client,
161 if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY)
167 dev_err(&data->client->dev, "data not ready\n");
172 static int mma8452_read(struct mma8452_data *data, __be16 buf[3])
174 int ret = mma8452_drdy(data);
179 return i2c_smbus_read_i2c_block_data(data->client, MMA8452_OUT_X,
180 3 * sizeof(__be16), (u8 *)buf);
183 static ssize_t mma8452_show_int_plus_micros(char *buf, const int (*vals)[2],
189 len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ",
190 vals[n][0], vals[n][1]);
192 /* replace trailing space by newline */
198 static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n,
202 if (val == vals[n][0] && val2 == vals[n][1])
208 static int mma8452_get_odr_index(struct mma8452_data *data)
210 return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >>
211 MMA8452_CTRL_DR_SHIFT;
214 static const int mma8452_samp_freq[8][2] = {
215 {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000},
216 {6, 250000}, {1, 560000}
219 /* Datasheet table 35 (step time vs sample frequency) */
220 static const int mma8452_transient_time_step_us[8] = {
231 /* Datasheet table 18 (normal mode) */
232 static const int mma8452_hp_filter_cutoff[8][4][2] = {
233 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 800 Hz sample */
234 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 400 Hz sample */
235 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, /* 200 Hz sample */
236 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, /* 100 Hz sample */
237 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 50 Hz sample */
238 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 12.5 Hz sample */
239 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 6.25 Hz sample */
240 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} } /* 1.56 Hz sample */
243 static ssize_t mma8452_show_samp_freq_avail(struct device *dev,
244 struct device_attribute *attr,
247 return mma8452_show_int_plus_micros(buf, mma8452_samp_freq,
248 ARRAY_SIZE(mma8452_samp_freq));
251 static ssize_t mma8452_show_scale_avail(struct device *dev,
252 struct device_attribute *attr,
255 struct mma8452_data *data = iio_priv(i2c_get_clientdata(
256 to_i2c_client(dev)));
258 return mma8452_show_int_plus_micros(buf, data->chip_info->mma_scales,
259 ARRAY_SIZE(data->chip_info->mma_scales));
262 static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev,
263 struct device_attribute *attr,
266 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
267 struct mma8452_data *data = iio_priv(indio_dev);
268 int i = mma8452_get_odr_index(data);
270 return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[i],
271 ARRAY_SIZE(mma8452_hp_filter_cutoff[0]));
274 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail);
275 static IIO_DEVICE_ATTR(in_accel_scale_available, S_IRUGO,
276 mma8452_show_scale_avail, NULL, 0);
277 static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available,
278 S_IRUGO, mma8452_show_hp_cutoff_avail, NULL, 0);
280 static int mma8452_get_samp_freq_index(struct mma8452_data *data,
283 return mma8452_get_int_plus_micros_index(mma8452_samp_freq,
284 ARRAY_SIZE(mma8452_samp_freq),
288 static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2)
290 return mma8452_get_int_plus_micros_index(data->chip_info->mma_scales,
291 ARRAY_SIZE(data->chip_info->mma_scales), val, val2);
294 static int mma8452_get_hp_filter_index(struct mma8452_data *data,
297 int i = mma8452_get_odr_index(data);
299 return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[i],
300 ARRAY_SIZE(mma8452_hp_filter_cutoff[0]), val, val2);
303 static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz)
307 ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF);
311 i = mma8452_get_odr_index(data);
312 ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
313 *hz = mma8452_hp_filter_cutoff[i][ret][0];
314 *uHz = mma8452_hp_filter_cutoff[i][ret][1];
319 static int mma8452_read_raw(struct iio_dev *indio_dev,
320 struct iio_chan_spec const *chan,
321 int *val, int *val2, long mask)
323 struct mma8452_data *data = iio_priv(indio_dev);
328 case IIO_CHAN_INFO_RAW:
329 if (iio_buffer_enabled(indio_dev))
332 mutex_lock(&data->lock);
333 ret = mma8452_read(data, buffer);
334 mutex_unlock(&data->lock);
338 *val = sign_extend32(be16_to_cpu(
339 buffer[chan->scan_index]) >> chan->scan_type.shift,
340 chan->scan_type.realbits - 1);
343 case IIO_CHAN_INFO_SCALE:
344 i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK;
345 *val = data->chip_info->mma_scales[i][0];
346 *val2 = data->chip_info->mma_scales[i][1];
348 return IIO_VAL_INT_PLUS_MICRO;
349 case IIO_CHAN_INFO_SAMP_FREQ:
350 i = mma8452_get_odr_index(data);
351 *val = mma8452_samp_freq[i][0];
352 *val2 = mma8452_samp_freq[i][1];
354 return IIO_VAL_INT_PLUS_MICRO;
355 case IIO_CHAN_INFO_CALIBBIAS:
356 ret = i2c_smbus_read_byte_data(data->client,
357 MMA8452_OFF_X + chan->scan_index);
361 *val = sign_extend32(ret, 7);
364 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
365 if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) {
366 ret = mma8452_read_hp_filter(data, val, val2);
374 return IIO_VAL_INT_PLUS_MICRO;
380 static int mma8452_standby(struct mma8452_data *data)
382 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
383 data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE);
386 static int mma8452_active(struct mma8452_data *data)
388 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
392 static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val)
396 mutex_lock(&data->lock);
398 /* config can only be changed when in standby */
399 ret = mma8452_standby(data);
403 ret = i2c_smbus_write_byte_data(data->client, reg, val);
407 ret = mma8452_active(data);
413 mutex_unlock(&data->lock);
418 static int mma8452_set_hp_filter_frequency(struct mma8452_data *data,
423 i = mma8452_get_hp_filter_index(data, val, val2);
427 reg = i2c_smbus_read_byte_data(data->client,
428 MMA8452_HP_FILTER_CUTOFF);
432 reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
435 return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg);
438 static int mma8452_write_raw(struct iio_dev *indio_dev,
439 struct iio_chan_spec const *chan,
440 int val, int val2, long mask)
442 struct mma8452_data *data = iio_priv(indio_dev);
445 if (iio_buffer_enabled(indio_dev))
449 case IIO_CHAN_INFO_SAMP_FREQ:
450 i = mma8452_get_samp_freq_index(data, val, val2);
454 data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK;
455 data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT;
457 return mma8452_change_config(data, MMA8452_CTRL_REG1,
459 case IIO_CHAN_INFO_SCALE:
460 i = mma8452_get_scale_index(data, val, val2);
464 data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK;
467 return mma8452_change_config(data, MMA8452_DATA_CFG,
469 case IIO_CHAN_INFO_CALIBBIAS:
470 if (val < -128 || val > 127)
473 return mma8452_change_config(data,
474 MMA8452_OFF_X + chan->scan_index,
477 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
478 if (val == 0 && val2 == 0) {
479 data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK;
481 data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK;
482 ret = mma8452_set_hp_filter_frequency(data, val, val2);
487 return mma8452_change_config(data, MMA8452_DATA_CFG,
495 static int mma8452_read_thresh(struct iio_dev *indio_dev,
496 const struct iio_chan_spec *chan,
497 enum iio_event_type type,
498 enum iio_event_direction dir,
499 enum iio_event_info info,
502 struct mma8452_data *data = iio_priv(indio_dev);
506 case IIO_EV_INFO_VALUE:
507 ret = i2c_smbus_read_byte_data(data->client,
508 data->chip_info->ev_ths);
512 *val = ret & data->chip_info->ev_ths_mask;
516 case IIO_EV_INFO_PERIOD:
517 ret = i2c_smbus_read_byte_data(data->client,
518 data->chip_info->ev_count);
522 us = ret * mma8452_transient_time_step_us[
523 mma8452_get_odr_index(data)];
524 *val = us / USEC_PER_SEC;
525 *val2 = us % USEC_PER_SEC;
527 return IIO_VAL_INT_PLUS_MICRO;
529 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
530 ret = i2c_smbus_read_byte_data(data->client,
531 MMA8452_TRANSIENT_CFG);
535 if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) {
539 ret = mma8452_read_hp_filter(data, val, val2);
544 return IIO_VAL_INT_PLUS_MICRO;
551 static int mma8452_write_thresh(struct iio_dev *indio_dev,
552 const struct iio_chan_spec *chan,
553 enum iio_event_type type,
554 enum iio_event_direction dir,
555 enum iio_event_info info,
558 struct mma8452_data *data = iio_priv(indio_dev);
562 case IIO_EV_INFO_VALUE:
563 if (val < 0 || val > MMA8452_TRANSIENT_THS_MASK)
566 return mma8452_change_config(data, data->chip_info->ev_ths,
569 case IIO_EV_INFO_PERIOD:
570 steps = (val * USEC_PER_SEC + val2) /
571 mma8452_transient_time_step_us[
572 mma8452_get_odr_index(data)];
574 if (steps < 0 || steps > 0xff)
577 return mma8452_change_config(data, data->chip_info->ev_count,
580 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
581 reg = i2c_smbus_read_byte_data(data->client,
582 MMA8452_TRANSIENT_CFG);
586 if (val == 0 && val2 == 0) {
587 reg |= MMA8452_TRANSIENT_CFG_HPF_BYP;
589 reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP;
590 ret = mma8452_set_hp_filter_frequency(data, val, val2);
595 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg);
602 static int mma8452_read_event_config(struct iio_dev *indio_dev,
603 const struct iio_chan_spec *chan,
604 enum iio_event_type type,
605 enum iio_event_direction dir)
607 struct mma8452_data *data = iio_priv(indio_dev);
608 const struct mma_chip_info *chip = data->chip_info;
611 ret = i2c_smbus_read_byte_data(data->client,
612 data->chip_info->ev_cfg);
616 return !!(ret & BIT(chan->scan_index + chip->ev_cfg_chan_shift));
619 static int mma8452_write_event_config(struct iio_dev *indio_dev,
620 const struct iio_chan_spec *chan,
621 enum iio_event_type type,
622 enum iio_event_direction dir,
625 struct mma8452_data *data = iio_priv(indio_dev);
626 const struct mma_chip_info *chip = data->chip_info;
629 val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg);
634 val |= BIT(chan->scan_index + chip->ev_cfg_chan_shift);
636 val &= ~BIT(chan->scan_index + chip->ev_cfg_chan_shift);
638 val |= chip->ev_cfg_ele;
639 val |= MMA8452_FF_MT_CFG_OAE;
641 return mma8452_change_config(data, chip->ev_cfg, val);
644 static void mma8452_transient_interrupt(struct iio_dev *indio_dev)
646 struct mma8452_data *data = iio_priv(indio_dev);
647 s64 ts = iio_get_time_ns();
650 src = i2c_smbus_read_byte_data(data->client, data->chip_info->ev_src);
654 if (src & data->chip_info->ev_src_xe)
655 iio_push_event(indio_dev,
656 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,
661 if (src & data->chip_info->ev_src_ye)
662 iio_push_event(indio_dev,
663 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y,
668 if (src & data->chip_info->ev_src_ze)
669 iio_push_event(indio_dev,
670 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z,
676 static irqreturn_t mma8452_interrupt(int irq, void *p)
678 struct iio_dev *indio_dev = p;
679 struct mma8452_data *data = iio_priv(indio_dev);
680 const struct mma_chip_info *chip = data->chip_info;
684 src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC);
688 if (src & MMA8452_INT_DRDY) {
689 iio_trigger_poll_chained(indio_dev->trig);
693 if ((src & MMA8452_INT_TRANS &&
694 chip->ev_src == MMA8452_TRANSIENT_SRC) ||
695 (src & MMA8452_INT_FF_MT &&
696 chip->ev_src == MMA8452_FF_MT_SRC)) {
697 mma8452_transient_interrupt(indio_dev);
704 static irqreturn_t mma8452_trigger_handler(int irq, void *p)
706 struct iio_poll_func *pf = p;
707 struct iio_dev *indio_dev = pf->indio_dev;
708 struct mma8452_data *data = iio_priv(indio_dev);
711 ret = mma8452_read(data, data->buffer.channels);
715 iio_push_to_buffers_with_timestamp(indio_dev, &data->buffer,
719 iio_trigger_notify_done(indio_dev->trig);
724 static int mma8452_reg_access_dbg(struct iio_dev *indio_dev,
725 unsigned reg, unsigned writeval,
729 struct mma8452_data *data = iio_priv(indio_dev);
731 if (reg > MMA8452_MAX_REG)
735 return mma8452_change_config(data, reg, writeval);
737 ret = i2c_smbus_read_byte_data(data->client, reg);
746 static const struct iio_event_spec mma8452_transient_event[] = {
748 .type = IIO_EV_TYPE_MAG,
749 .dir = IIO_EV_DIR_RISING,
750 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
751 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
752 BIT(IIO_EV_INFO_PERIOD) |
753 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
757 static const struct iio_event_spec mma8452_motion_event[] = {
759 .type = IIO_EV_TYPE_MAG,
760 .dir = IIO_EV_DIR_RISING,
761 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
762 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
763 BIT(IIO_EV_INFO_PERIOD)
768 * Threshold is configured in fixed 8G/127 steps regardless of
769 * currently selected scale for measurement.
771 static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742");
773 static struct attribute *mma8452_event_attributes[] = {
774 &iio_const_attr_accel_transient_scale.dev_attr.attr,
778 static struct attribute_group mma8452_event_attribute_group = {
779 .attrs = mma8452_event_attributes,
782 #define MMA8452_CHANNEL(axis, idx, bits) { \
785 .channel2 = IIO_MOD_##axis, \
786 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
787 BIT(IIO_CHAN_INFO_CALIBBIAS), \
788 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
789 BIT(IIO_CHAN_INFO_SCALE) | \
790 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY), \
794 .realbits = (bits), \
796 .shift = 16 - (bits), \
797 .endianness = IIO_BE, \
799 .event_spec = mma8452_transient_event, \
800 .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \
803 #define MMA8652_CHANNEL(axis, idx, bits) { \
806 .channel2 = IIO_MOD_##axis, \
807 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
808 BIT(IIO_CHAN_INFO_CALIBBIAS), \
809 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
810 BIT(IIO_CHAN_INFO_SCALE), \
814 .realbits = (bits), \
816 .shift = 16 - (bits), \
817 .endianness = IIO_BE, \
819 .event_spec = mma8452_motion_event, \
820 .num_event_specs = ARRAY_SIZE(mma8452_motion_event), \
823 static const struct iio_chan_spec mma8452_channels[] = {
824 MMA8452_CHANNEL(X, 0, 12),
825 MMA8452_CHANNEL(Y, 1, 12),
826 MMA8452_CHANNEL(Z, 2, 12),
827 IIO_CHAN_SOFT_TIMESTAMP(3),
830 static const struct iio_chan_spec mma8453_channels[] = {
831 MMA8452_CHANNEL(X, 0, 10),
832 MMA8452_CHANNEL(Y, 1, 10),
833 MMA8452_CHANNEL(Z, 2, 10),
834 IIO_CHAN_SOFT_TIMESTAMP(3),
837 static const struct iio_chan_spec mma8652_channels[] = {
838 MMA8652_CHANNEL(X, 0, 12),
839 MMA8652_CHANNEL(Y, 1, 12),
840 MMA8652_CHANNEL(Z, 2, 12),
841 IIO_CHAN_SOFT_TIMESTAMP(3),
844 static const struct iio_chan_spec mma8653_channels[] = {
845 MMA8652_CHANNEL(X, 0, 10),
846 MMA8652_CHANNEL(Y, 1, 10),
847 MMA8652_CHANNEL(Z, 2, 10),
848 IIO_CHAN_SOFT_TIMESTAMP(3),
858 static const struct mma_chip_info mma_chip_info_table[] = {
860 .chip_id = MMA8452_DEVICE_ID,
861 .channels = mma8452_channels,
862 .num_channels = ARRAY_SIZE(mma8452_channels),
864 * Hardware has fullscale of -2G, -4G, -8G corresponding to
865 * raw value -2048 for 12 bit or -512 for 10 bit.
866 * The userspace interface uses m/s^2 and we declare micro units
867 * So scale factor for 12 bit here is given by:
868 * g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665
870 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
871 .ev_cfg = MMA8452_TRANSIENT_CFG,
872 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
873 .ev_cfg_chan_shift = 1,
874 .ev_src = MMA8452_TRANSIENT_SRC,
875 .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
876 .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
877 .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
878 .ev_ths = MMA8452_TRANSIENT_THS,
879 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
880 .ev_count = MMA8452_TRANSIENT_COUNT,
883 .chip_id = MMA8453_DEVICE_ID,
884 .channels = mma8453_channels,
885 .num_channels = ARRAY_SIZE(mma8453_channels),
886 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
887 .ev_cfg = MMA8452_TRANSIENT_CFG,
888 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
889 .ev_cfg_chan_shift = 1,
890 .ev_src = MMA8452_TRANSIENT_SRC,
891 .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
892 .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
893 .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
894 .ev_ths = MMA8452_TRANSIENT_THS,
895 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
896 .ev_count = MMA8452_TRANSIENT_COUNT,
899 .chip_id = MMA8652_DEVICE_ID,
900 .channels = mma8652_channels,
901 .num_channels = ARRAY_SIZE(mma8652_channels),
902 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
903 .ev_cfg = MMA8452_FF_MT_CFG,
904 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE,
905 .ev_cfg_chan_shift = 3,
906 .ev_src = MMA8452_FF_MT_SRC,
907 .ev_src_xe = MMA8452_FF_MT_SRC_XHE,
908 .ev_src_ye = MMA8452_FF_MT_SRC_YHE,
909 .ev_src_ze = MMA8452_FF_MT_SRC_ZHE,
910 .ev_ths = MMA8452_FF_MT_THS,
911 .ev_ths_mask = MMA8452_FF_MT_THS_MASK,
912 .ev_count = MMA8452_FF_MT_COUNT,
915 .chip_id = MMA8653_DEVICE_ID,
916 .channels = mma8653_channels,
917 .num_channels = ARRAY_SIZE(mma8653_channels),
918 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
919 .ev_cfg = MMA8452_FF_MT_CFG,
920 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE,
921 .ev_cfg_chan_shift = 3,
922 .ev_src = MMA8452_FF_MT_SRC,
923 .ev_src_xe = MMA8452_FF_MT_SRC_XHE,
924 .ev_src_ye = MMA8452_FF_MT_SRC_YHE,
925 .ev_src_ze = MMA8452_FF_MT_SRC_ZHE,
926 .ev_ths = MMA8452_FF_MT_THS,
927 .ev_ths_mask = MMA8452_FF_MT_THS_MASK,
928 .ev_count = MMA8452_FF_MT_COUNT,
932 static struct attribute *mma8452_attributes[] = {
933 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
934 &iio_dev_attr_in_accel_scale_available.dev_attr.attr,
935 &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr,
939 static const struct attribute_group mma8452_group = {
940 .attrs = mma8452_attributes,
943 static const struct iio_info mma8452_info = {
944 .attrs = &mma8452_group,
945 .read_raw = &mma8452_read_raw,
946 .write_raw = &mma8452_write_raw,
947 .event_attrs = &mma8452_event_attribute_group,
948 .read_event_value = &mma8452_read_thresh,
949 .write_event_value = &mma8452_write_thresh,
950 .read_event_config = &mma8452_read_event_config,
951 .write_event_config = &mma8452_write_event_config,
952 .debugfs_reg_access = &mma8452_reg_access_dbg,
953 .driver_module = THIS_MODULE,
956 static const unsigned long mma8452_scan_masks[] = {0x7, 0};
958 static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig,
961 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
962 struct mma8452_data *data = iio_priv(indio_dev);
965 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG4);
970 reg |= MMA8452_INT_DRDY;
972 reg &= ~MMA8452_INT_DRDY;
974 return mma8452_change_config(data, MMA8452_CTRL_REG4, reg);
977 static int mma8452_validate_device(struct iio_trigger *trig,
978 struct iio_dev *indio_dev)
980 struct iio_dev *indio = iio_trigger_get_drvdata(trig);
982 if (indio != indio_dev)
988 static const struct iio_trigger_ops mma8452_trigger_ops = {
989 .set_trigger_state = mma8452_data_rdy_trigger_set_state,
990 .validate_device = mma8452_validate_device,
991 .owner = THIS_MODULE,
994 static int mma8452_trigger_setup(struct iio_dev *indio_dev)
996 struct mma8452_data *data = iio_priv(indio_dev);
997 struct iio_trigger *trig;
1000 trig = devm_iio_trigger_alloc(&data->client->dev, "%s-dev%d",
1006 trig->dev.parent = &data->client->dev;
1007 trig->ops = &mma8452_trigger_ops;
1008 iio_trigger_set_drvdata(trig, indio_dev);
1010 ret = iio_trigger_register(trig);
1014 indio_dev->trig = trig;
1019 static void mma8452_trigger_cleanup(struct iio_dev *indio_dev)
1021 if (indio_dev->trig)
1022 iio_trigger_unregister(indio_dev->trig);
1025 static int mma8452_reset(struct i2c_client *client)
1030 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2,
1031 MMA8452_CTRL_REG2_RST);
1035 for (i = 0; i < 10; i++) {
1036 usleep_range(100, 200);
1037 ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2);
1039 continue; /* I2C comm reset */
1042 if (!(ret & MMA8452_CTRL_REG2_RST))
1049 static const struct of_device_id mma8452_dt_ids[] = {
1050 { .compatible = "fsl,mma8452", .data = &mma_chip_info_table[mma8452] },
1051 { .compatible = "fsl,mma8453", .data = &mma_chip_info_table[mma8453] },
1052 { .compatible = "fsl,mma8652", .data = &mma_chip_info_table[mma8652] },
1053 { .compatible = "fsl,mma8653", .data = &mma_chip_info_table[mma8653] },
1056 MODULE_DEVICE_TABLE(of, mma8452_dt_ids);
1058 static int mma8452_probe(struct i2c_client *client,
1059 const struct i2c_device_id *id)
1061 struct mma8452_data *data;
1062 struct iio_dev *indio_dev;
1064 const struct of_device_id *match;
1066 match = of_match_device(mma8452_dt_ids, &client->dev);
1068 dev_err(&client->dev, "unknown device model\n");
1072 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
1076 data = iio_priv(indio_dev);
1077 data->client = client;
1078 mutex_init(&data->lock);
1079 data->chip_info = match->data;
1081 ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I);
1086 case MMA8452_DEVICE_ID:
1087 case MMA8453_DEVICE_ID:
1088 case MMA8652_DEVICE_ID:
1089 case MMA8653_DEVICE_ID:
1090 if (ret == data->chip_info->chip_id)
1096 dev_info(&client->dev, "registering %s accelerometer; ID 0x%x\n",
1097 match->compatible, data->chip_info->chip_id);
1099 i2c_set_clientdata(client, indio_dev);
1100 indio_dev->info = &mma8452_info;
1101 indio_dev->name = id->name;
1102 indio_dev->dev.parent = &client->dev;
1103 indio_dev->modes = INDIO_DIRECT_MODE;
1104 indio_dev->channels = data->chip_info->channels;
1105 indio_dev->num_channels = data->chip_info->num_channels;
1106 indio_dev->available_scan_masks = mma8452_scan_masks;
1108 ret = mma8452_reset(client);
1112 data->data_cfg = MMA8452_DATA_CFG_FS_2G;
1113 ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG,
1119 * By default set transient threshold to max to avoid events if
1120 * enabling without configuring threshold.
1122 ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS,
1123 MMA8452_TRANSIENT_THS_MASK);
1129 * Although we enable the interrupt sources once and for
1130 * all here the event detection itself is not enabled until
1131 * userspace asks for it by mma8452_write_event_config()
1133 int supported_interrupts = MMA8452_INT_DRDY |
1136 int enabled_interrupts = MMA8452_INT_TRANS |
1139 /* Assume wired to INT1 pin */
1140 ret = i2c_smbus_write_byte_data(client,
1142 supported_interrupts);
1146 ret = i2c_smbus_write_byte_data(client,
1148 enabled_interrupts);
1152 ret = mma8452_trigger_setup(indio_dev);
1157 data->ctrl_reg1 = MMA8452_CTRL_ACTIVE |
1158 (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT);
1159 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1,
1162 goto trigger_cleanup;
1164 ret = iio_triggered_buffer_setup(indio_dev, NULL,
1165 mma8452_trigger_handler, NULL);
1167 goto trigger_cleanup;
1170 ret = devm_request_threaded_irq(&client->dev,
1172 NULL, mma8452_interrupt,
1173 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1174 client->name, indio_dev);
1176 goto buffer_cleanup;
1179 ret = iio_device_register(indio_dev);
1181 goto buffer_cleanup;
1186 iio_triggered_buffer_cleanup(indio_dev);
1189 mma8452_trigger_cleanup(indio_dev);
1194 static int mma8452_remove(struct i2c_client *client)
1196 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1198 iio_device_unregister(indio_dev);
1199 iio_triggered_buffer_cleanup(indio_dev);
1200 mma8452_trigger_cleanup(indio_dev);
1201 mma8452_standby(iio_priv(indio_dev));
1206 #ifdef CONFIG_PM_SLEEP
1207 static int mma8452_suspend(struct device *dev)
1209 return mma8452_standby(iio_priv(i2c_get_clientdata(
1210 to_i2c_client(dev))));
1213 static int mma8452_resume(struct device *dev)
1215 return mma8452_active(iio_priv(i2c_get_clientdata(
1216 to_i2c_client(dev))));
1219 static SIMPLE_DEV_PM_OPS(mma8452_pm_ops, mma8452_suspend, mma8452_resume);
1220 #define MMA8452_PM_OPS (&mma8452_pm_ops)
1222 #define MMA8452_PM_OPS NULL
1225 static const struct i2c_device_id mma8452_id[] = {
1226 { "mma8452", mma8452 },
1227 { "mma8453", mma8453 },
1228 { "mma8652", mma8652 },
1229 { "mma8653", mma8653 },
1232 MODULE_DEVICE_TABLE(i2c, mma8452_id);
1234 static struct i2c_driver mma8452_driver = {
1237 .of_match_table = of_match_ptr(mma8452_dt_ids),
1238 .pm = MMA8452_PM_OPS,
1240 .probe = mma8452_probe,
1241 .remove = mma8452_remove,
1242 .id_table = mma8452_id,
1244 module_i2c_driver(mma8452_driver);
1246 MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>");
1247 MODULE_DESCRIPTION("Freescale MMA8452 accelerometer driver");
1248 MODULE_LICENSE("GPL");