2 * Atmel ADC driver for SAMA5D2 devices and compatible.
4 * Copyright (C) 2015 Atmel,
5 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/bitops.h>
18 #include <linux/clk.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/dmaengine.h>
21 #include <linux/interrupt.h>
23 #include <linux/module.h>
24 #include <linux/of_device.h>
25 #include <linux/platform_device.h>
26 #include <linux/sched.h>
27 #include <linux/wait.h>
28 #include <linux/iio/iio.h>
29 #include <linux/iio/sysfs.h>
30 #include <linux/iio/buffer.h>
31 #include <linux/iio/trigger.h>
32 #include <linux/iio/trigger_consumer.h>
33 #include <linux/iio/triggered_buffer.h>
34 #include <linux/pinctrl/consumer.h>
35 #include <linux/regulator/consumer.h>
37 /* Control Register */
38 #define AT91_SAMA5D2_CR 0x00
40 #define AT91_SAMA5D2_CR_SWRST BIT(0)
41 /* Start Conversion */
42 #define AT91_SAMA5D2_CR_START BIT(1)
43 /* Touchscreen Calibration */
44 #define AT91_SAMA5D2_CR_TSCALIB BIT(2)
45 /* Comparison Restart */
46 #define AT91_SAMA5D2_CR_CMPRST BIT(4)
49 #define AT91_SAMA5D2_MR 0x04
50 /* Trigger Selection */
51 #define AT91_SAMA5D2_MR_TRGSEL(v) ((v) << 1)
53 #define AT91_SAMA5D2_MR_TRGSEL_TRIG0 0
55 #define AT91_SAMA5D2_MR_TRGSEL_TRIG1 1
57 #define AT91_SAMA5D2_MR_TRGSEL_TRIG2 2
59 #define AT91_SAMA5D2_MR_TRGSEL_TRIG3 3
60 /* PWM event line 0 */
61 #define AT91_SAMA5D2_MR_TRGSEL_TRIG4 4
62 /* PWM event line 1 */
63 #define AT91_SAMA5D2_MR_TRGSEL_TRIG5 5
65 #define AT91_SAMA5D2_MR_TRGSEL_TRIG6 6
67 #define AT91_SAMA5D2_MR_TRGSEL_TRIG7 7
69 #define AT91_SAMA5D2_MR_SLEEP BIT(5)
71 #define AT91_SAMA5D2_MR_FWUP BIT(6)
72 /* Prescaler Rate Selection */
73 #define AT91_SAMA5D2_MR_PRESCAL(v) ((v) << AT91_SAMA5D2_MR_PRESCAL_OFFSET)
74 #define AT91_SAMA5D2_MR_PRESCAL_OFFSET 8
75 #define AT91_SAMA5D2_MR_PRESCAL_MAX 0xff
76 #define AT91_SAMA5D2_MR_PRESCAL_MASK GENMASK(15, 8)
78 #define AT91_SAMA5D2_MR_STARTUP(v) ((v) << 16)
79 #define AT91_SAMA5D2_MR_STARTUP_MASK GENMASK(19, 16)
81 #define AT91_SAMA5D2_MR_ANACH BIT(23)
83 #define AT91_SAMA5D2_MR_TRACKTIM(v) ((v) << 24)
84 #define AT91_SAMA5D2_MR_TRACKTIM_MAX 0xf
86 #define AT91_SAMA5D2_MR_TRANSFER(v) ((v) << 28)
87 #define AT91_SAMA5D2_MR_TRANSFER_MAX 0x3
88 /* Use Sequence Enable */
89 #define AT91_SAMA5D2_MR_USEQ BIT(31)
91 /* Channel Sequence Register 1 */
92 #define AT91_SAMA5D2_SEQR1 0x08
93 /* Channel Sequence Register 2 */
94 #define AT91_SAMA5D2_SEQR2 0x0c
95 /* Channel Enable Register */
96 #define AT91_SAMA5D2_CHER 0x10
97 /* Channel Disable Register */
98 #define AT91_SAMA5D2_CHDR 0x14
99 /* Channel Status Register */
100 #define AT91_SAMA5D2_CHSR 0x18
101 /* Last Converted Data Register */
102 #define AT91_SAMA5D2_LCDR 0x20
103 /* Interrupt Enable Register */
104 #define AT91_SAMA5D2_IER 0x24
105 /* Interrupt Enable Register - TS X measurement ready */
106 #define AT91_SAMA5D2_IER_XRDY BIT(20)
107 /* Interrupt Enable Register - TS Y measurement ready */
108 #define AT91_SAMA5D2_IER_YRDY BIT(21)
109 /* Interrupt Enable Register - TS pressure measurement ready */
110 #define AT91_SAMA5D2_IER_PRDY BIT(22)
111 /* Interrupt Enable Register - general overrun error */
112 #define AT91_SAMA5D2_IER_GOVRE BIT(25)
113 /* Interrupt Enable Register - Pen detect */
114 #define AT91_SAMA5D2_IER_PEN BIT(29)
115 /* Interrupt Enable Register - No pen detect */
116 #define AT91_SAMA5D2_IER_NOPEN BIT(30)
117 /* Interrupt Disable Register */
118 #define AT91_SAMA5D2_IDR 0x28
119 /* Interrupt Mask Register */
120 #define AT91_SAMA5D2_IMR 0x2c
121 /* Interrupt Status Register */
122 #define AT91_SAMA5D2_ISR 0x30
123 /* Interrupt Status Register - Pen touching sense status */
124 #define AT91_SAMA5D2_ISR_PENS BIT(31)
125 /* Last Channel Trigger Mode Register */
126 #define AT91_SAMA5D2_LCTMR 0x34
127 /* Last Channel Compare Window Register */
128 #define AT91_SAMA5D2_LCCWR 0x38
129 /* Overrun Status Register */
130 #define AT91_SAMA5D2_OVER 0x3c
131 /* Extended Mode Register */
132 #define AT91_SAMA5D2_EMR 0x40
133 /* Extended Mode Register - Oversampling rate */
134 #define AT91_SAMA5D2_EMR_OSR(V) ((V) << 16)
135 #define AT91_SAMA5D2_EMR_OSR_MASK GENMASK(17, 16)
136 #define AT91_SAMA5D2_EMR_OSR_1SAMPLES 0
137 #define AT91_SAMA5D2_EMR_OSR_4SAMPLES 1
138 #define AT91_SAMA5D2_EMR_OSR_16SAMPLES 2
140 /* Extended Mode Register - Averaging on single trigger event */
141 #define AT91_SAMA5D2_EMR_ASTE(V) ((V) << 20)
142 /* Compare Window Register */
143 #define AT91_SAMA5D2_CWR 0x44
144 /* Channel Gain Register */
145 #define AT91_SAMA5D2_CGR 0x48
147 /* Channel Offset Register */
148 #define AT91_SAMA5D2_COR 0x4c
149 #define AT91_SAMA5D2_COR_DIFF_OFFSET 16
151 /* Channel Data Register 0 */
152 #define AT91_SAMA5D2_CDR0 0x50
153 /* Analog Control Register */
154 #define AT91_SAMA5D2_ACR 0x94
155 /* Analog Control Register - Pen detect sensitivity mask */
156 #define AT91_SAMA5D2_ACR_PENDETSENS_MASK GENMASK(1, 0)
158 /* Touchscreen Mode Register */
159 #define AT91_SAMA5D2_TSMR 0xb0
160 /* Touchscreen Mode Register - No touch mode */
161 #define AT91_SAMA5D2_TSMR_TSMODE_NONE 0
162 /* Touchscreen Mode Register - 4 wire screen, no pressure measurement */
163 #define AT91_SAMA5D2_TSMR_TSMODE_4WIRE_NO_PRESS 1
164 /* Touchscreen Mode Register - 4 wire screen, pressure measurement */
165 #define AT91_SAMA5D2_TSMR_TSMODE_4WIRE_PRESS 2
166 /* Touchscreen Mode Register - 5 wire screen */
167 #define AT91_SAMA5D2_TSMR_TSMODE_5WIRE 3
168 /* Touchscreen Mode Register - Average samples mask */
169 #define AT91_SAMA5D2_TSMR_TSAV_MASK GENMASK(5, 4)
170 /* Touchscreen Mode Register - Average samples */
171 #define AT91_SAMA5D2_TSMR_TSAV(x) ((x) << 4)
172 /* Touchscreen Mode Register - Touch/trigger frequency ratio mask */
173 #define AT91_SAMA5D2_TSMR_TSFREQ_MASK GENMASK(11, 8)
174 /* Touchscreen Mode Register - Touch/trigger frequency ratio */
175 #define AT91_SAMA5D2_TSMR_TSFREQ(x) ((x) << 8)
176 /* Touchscreen Mode Register - Pen Debounce Time mask */
177 #define AT91_SAMA5D2_TSMR_PENDBC_MASK GENMASK(31, 28)
178 /* Touchscreen Mode Register - Pen Debounce Time */
179 #define AT91_SAMA5D2_TSMR_PENDBC(x) ((x) << 28)
180 /* Touchscreen Mode Register - No DMA for touch measurements */
181 #define AT91_SAMA5D2_TSMR_NOTSDMA BIT(22)
182 /* Touchscreen Mode Register - Disable pen detection */
183 #define AT91_SAMA5D2_TSMR_PENDET_DIS (0 << 24)
184 /* Touchscreen Mode Register - Enable pen detection */
185 #define AT91_SAMA5D2_TSMR_PENDET_ENA BIT(24)
187 /* Touchscreen X Position Register */
188 #define AT91_SAMA5D2_XPOSR 0xb4
189 /* Touchscreen Y Position Register */
190 #define AT91_SAMA5D2_YPOSR 0xb8
191 /* Touchscreen Pressure Register */
192 #define AT91_SAMA5D2_PRESSR 0xbc
193 /* Trigger Register */
194 #define AT91_SAMA5D2_TRGR 0xc0
195 /* Mask for TRGMOD field of TRGR register */
196 #define AT91_SAMA5D2_TRGR_TRGMOD_MASK GENMASK(2, 0)
197 /* No trigger, only software trigger can start conversions */
198 #define AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER 0
199 /* Trigger Mode external trigger rising edge */
200 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_RISE 1
201 /* Trigger Mode external trigger falling edge */
202 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_FALL 2
203 /* Trigger Mode external trigger any edge */
204 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_ANY 3
205 /* Trigger Mode internal periodic */
206 #define AT91_SAMA5D2_TRGR_TRGMOD_PERIODIC 5
207 /* Trigger Mode - trigger period mask */
208 #define AT91_SAMA5D2_TRGR_TRGPER_MASK GENMASK(31, 16)
209 /* Trigger Mode - trigger period */
210 #define AT91_SAMA5D2_TRGR_TRGPER(x) ((x) << 16)
212 /* Correction Select Register */
213 #define AT91_SAMA5D2_COSR 0xd0
214 /* Correction Value Register */
215 #define AT91_SAMA5D2_CVR 0xd4
216 /* Channel Error Correction Register */
217 #define AT91_SAMA5D2_CECR 0xd8
218 /* Write Protection Mode Register */
219 #define AT91_SAMA5D2_WPMR 0xe4
220 /* Write Protection Status Register */
221 #define AT91_SAMA5D2_WPSR 0xe8
222 /* Version Register */
223 #define AT91_SAMA5D2_VERSION 0xfc
225 #define AT91_SAMA5D2_HW_TRIG_CNT 3
226 #define AT91_SAMA5D2_SINGLE_CHAN_CNT 12
227 #define AT91_SAMA5D2_DIFF_CHAN_CNT 6
229 #define AT91_SAMA5D2_TIMESTAMP_CHAN_IDX (AT91_SAMA5D2_SINGLE_CHAN_CNT + \
230 AT91_SAMA5D2_DIFF_CHAN_CNT + 1)
232 #define AT91_SAMA5D2_TOUCH_X_CHAN_IDX (AT91_SAMA5D2_SINGLE_CHAN_CNT + \
233 AT91_SAMA5D2_DIFF_CHAN_CNT * 2)
234 #define AT91_SAMA5D2_TOUCH_Y_CHAN_IDX (AT91_SAMA5D2_TOUCH_X_CHAN_IDX + 1)
235 #define AT91_SAMA5D2_TOUCH_P_CHAN_IDX (AT91_SAMA5D2_TOUCH_Y_CHAN_IDX + 1)
236 #define AT91_SAMA5D2_MAX_CHAN_IDX AT91_SAMA5D2_TOUCH_P_CHAN_IDX
238 #define AT91_SAMA5D2_TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */
239 #define AT91_SAMA5D2_TOUCH_PEN_DETECT_DEBOUNCE_US 200
241 #define AT91_SAMA5D2_XYZ_MASK GENMASK(11, 0)
243 #define AT91_SAMA5D2_MAX_POS_BITS 12
246 * Maximum number of bytes to hold conversion from all channels
247 * without the timestamp.
249 #define AT91_BUFFER_MAX_CONVERSION_BYTES ((AT91_SAMA5D2_SINGLE_CHAN_CNT + \
250 AT91_SAMA5D2_DIFF_CHAN_CNT) * 2)
252 /* This total must also include the timestamp */
253 #define AT91_BUFFER_MAX_BYTES (AT91_BUFFER_MAX_CONVERSION_BYTES + 8)
255 #define AT91_BUFFER_MAX_HWORDS (AT91_BUFFER_MAX_BYTES / 2)
257 #define AT91_HWFIFO_MAX_SIZE_STR "128"
258 #define AT91_HWFIFO_MAX_SIZE 128
260 /* Possible values for oversampling ratio */
261 #define AT91_OSR_1SAMPLES 1
262 #define AT91_OSR_4SAMPLES 4
263 #define AT91_OSR_16SAMPLES 16
265 #define AT91_SAMA5D2_CHAN_SINGLE(num, addr) \
267 .type = IIO_VOLTAGE, \
276 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
277 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
278 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
279 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
280 .datasheet_name = "CH"#num, \
284 #define AT91_SAMA5D2_CHAN_DIFF(num, num2, addr) \
286 .type = IIO_VOLTAGE, \
291 .scan_index = num + AT91_SAMA5D2_SINGLE_CHAN_CNT, \
297 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
298 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
299 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
300 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
301 .datasheet_name = "CH"#num"-CH"#num2, \
305 #define AT91_SAMA5D2_CHAN_TOUCH(num, name, mod) \
307 .type = IIO_POSITIONRELATIVE, \
317 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
318 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
319 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
320 .datasheet_name = name, \
322 #define AT91_SAMA5D2_CHAN_PRESSURE(num, name) \
324 .type = IIO_PRESSURE, \
332 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
333 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
334 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
335 .datasheet_name = name, \
338 #define at91_adc_readl(st, reg) readl_relaxed(st->base + reg)
339 #define at91_adc_writel(st, reg, val) writel_relaxed(val, st->base + reg)
341 struct at91_adc_soc_info {
342 unsigned startup_time;
343 unsigned min_sample_rate;
344 unsigned max_sample_rate;
347 struct at91_adc_trigger {
349 unsigned int trgmod_value;
350 unsigned int edge_type;
355 * at91_adc_dma - at91-sama5d2 dma information struct
356 * @dma_chan: the dma channel acquired
357 * @rx_buf: dma coherent allocated area
358 * @rx_dma_buf: dma handler for the buffer
359 * @phys_addr: physical address of the ADC base register
360 * @buf_idx: index inside the dma buffer where reading was last done
361 * @rx_buf_sz: size of buffer used by DMA operation
362 * @watermark: number of conversions to copy before DMA triggers irq
363 * @dma_ts: hold the start timestamp of dma operation
365 struct at91_adc_dma {
366 struct dma_chan *dma_chan;
368 dma_addr_t rx_dma_buf;
369 phys_addr_t phys_addr;
377 * at91_adc_touch - at91-sama5d2 touchscreen information struct
378 * @sample_period_val: the value for periodic trigger interval
379 * @touching: is the pen touching the screen or not
380 * @x_pos: temporary placeholder for pressure computation
381 * @channels_bitmask: bitmask with the touchscreen channels enabled
382 * @workq: workqueue for buffer data pushing
384 struct at91_adc_touch {
385 u16 sample_period_val;
388 unsigned long channels_bitmask;
389 struct work_struct workq;
392 struct at91_adc_state {
396 struct regulator *reg;
397 struct regulator *vref;
399 unsigned int current_sample_rate;
400 struct iio_trigger *trig;
401 const struct at91_adc_trigger *selected_trig;
402 const struct iio_chan_spec *chan;
403 bool conversion_done;
404 u32 conversion_value;
405 unsigned int oversampling_ratio;
406 struct at91_adc_soc_info soc_info;
407 wait_queue_head_t wq_data_available;
408 struct at91_adc_dma dma_st;
409 struct at91_adc_touch touch_st;
410 u16 buffer[AT91_BUFFER_MAX_HWORDS];
412 * lock to prevent concurrent 'single conversion' requests through
418 static const struct at91_adc_trigger at91_adc_trigger_list[] = {
420 .name = "external_rising",
421 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_RISE,
422 .edge_type = IRQ_TYPE_EDGE_RISING,
426 .name = "external_falling",
427 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_FALL,
428 .edge_type = IRQ_TYPE_EDGE_FALLING,
432 .name = "external_any",
433 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_ANY,
434 .edge_type = IRQ_TYPE_EDGE_BOTH,
439 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER,
440 .edge_type = IRQ_TYPE_NONE,
445 static const struct iio_chan_spec at91_adc_channels[] = {
446 AT91_SAMA5D2_CHAN_SINGLE(0, 0x50),
447 AT91_SAMA5D2_CHAN_SINGLE(1, 0x54),
448 AT91_SAMA5D2_CHAN_SINGLE(2, 0x58),
449 AT91_SAMA5D2_CHAN_SINGLE(3, 0x5c),
450 AT91_SAMA5D2_CHAN_SINGLE(4, 0x60),
451 AT91_SAMA5D2_CHAN_SINGLE(5, 0x64),
452 AT91_SAMA5D2_CHAN_SINGLE(6, 0x68),
453 AT91_SAMA5D2_CHAN_SINGLE(7, 0x6c),
454 AT91_SAMA5D2_CHAN_SINGLE(8, 0x70),
455 AT91_SAMA5D2_CHAN_SINGLE(9, 0x74),
456 AT91_SAMA5D2_CHAN_SINGLE(10, 0x78),
457 AT91_SAMA5D2_CHAN_SINGLE(11, 0x7c),
458 AT91_SAMA5D2_CHAN_DIFF(0, 1, 0x50),
459 AT91_SAMA5D2_CHAN_DIFF(2, 3, 0x58),
460 AT91_SAMA5D2_CHAN_DIFF(4, 5, 0x60),
461 AT91_SAMA5D2_CHAN_DIFF(6, 7, 0x68),
462 AT91_SAMA5D2_CHAN_DIFF(8, 9, 0x70),
463 AT91_SAMA5D2_CHAN_DIFF(10, 11, 0x78),
464 IIO_CHAN_SOFT_TIMESTAMP(AT91_SAMA5D2_TIMESTAMP_CHAN_IDX),
465 AT91_SAMA5D2_CHAN_TOUCH(AT91_SAMA5D2_TOUCH_X_CHAN_IDX, "x", IIO_MOD_X),
466 AT91_SAMA5D2_CHAN_TOUCH(AT91_SAMA5D2_TOUCH_Y_CHAN_IDX, "y", IIO_MOD_Y),
467 AT91_SAMA5D2_CHAN_PRESSURE(AT91_SAMA5D2_TOUCH_P_CHAN_IDX, "pressure"),
470 static int at91_adc_chan_xlate(struct iio_dev *indio_dev, int chan)
474 for (i = 0; i < indio_dev->num_channels; i++) {
475 if (indio_dev->channels[i].scan_index == chan)
481 static inline struct iio_chan_spec const *
482 at91_adc_chan_get(struct iio_dev *indio_dev, int chan)
484 int index = at91_adc_chan_xlate(indio_dev, chan);
488 return indio_dev->channels + index;
491 static inline int at91_adc_of_xlate(struct iio_dev *indio_dev,
492 const struct of_phandle_args *iiospec)
494 return at91_adc_chan_xlate(indio_dev, iiospec->args[0]);
497 static void at91_adc_config_emr(struct at91_adc_state *st)
499 /* configure the extended mode register */
500 unsigned int emr = at91_adc_readl(st, AT91_SAMA5D2_EMR);
502 /* select oversampling per single trigger event */
503 emr |= AT91_SAMA5D2_EMR_ASTE(1);
505 /* delete leftover content if it's the case */
506 emr &= ~AT91_SAMA5D2_EMR_OSR_MASK;
508 /* select oversampling ratio from configuration */
509 switch (st->oversampling_ratio) {
510 case AT91_OSR_1SAMPLES:
511 emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_1SAMPLES) &
512 AT91_SAMA5D2_EMR_OSR_MASK;
514 case AT91_OSR_4SAMPLES:
515 emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_4SAMPLES) &
516 AT91_SAMA5D2_EMR_OSR_MASK;
518 case AT91_OSR_16SAMPLES:
519 emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_16SAMPLES) &
520 AT91_SAMA5D2_EMR_OSR_MASK;
524 at91_adc_writel(st, AT91_SAMA5D2_EMR, emr);
527 static int at91_adc_adjust_val_osr(struct at91_adc_state *st, int *val)
529 if (st->oversampling_ratio == AT91_OSR_1SAMPLES) {
531 * in this case we only have 12 bits of real data, but channel
532 * is registered as 14 bits, so shift left two bits
535 } else if (st->oversampling_ratio == AT91_OSR_4SAMPLES) {
537 * in this case we have 13 bits of real data, but channel
538 * is registered as 14 bits, so left shift one bit
546 static void at91_adc_adjust_val_osr_array(struct at91_adc_state *st, void *buf,
550 u16 *buf_u16 = (u16 *) buf;
553 * We are converting each two bytes (each sample).
554 * First convert the byte based array to u16, and convert each sample
556 * Each value is two bytes in an array of chars, so to not shift
557 * more than we need, save the value separately.
558 * len is in bytes, so divide by two to get number of samples.
560 while (i < len / 2) {
562 at91_adc_adjust_val_osr(st, &val);
568 static int at91_adc_configure_touch(struct at91_adc_state *st, bool state)
570 u32 clk_khz = st->current_sample_rate / 1000;
576 /* disabling touch IRQs and setting mode to no touch enabled */
577 at91_adc_writel(st, AT91_SAMA5D2_IDR,
578 AT91_SAMA5D2_IER_PEN | AT91_SAMA5D2_IER_NOPEN);
579 at91_adc_writel(st, AT91_SAMA5D2_TSMR, 0);
583 * debounce time is in microseconds, we need it in milliseconds to
584 * multiply with kilohertz, so, divide by 1000, but after the multiply.
585 * round up to make sure pendbc is at least 1
587 pendbc = round_up(AT91_SAMA5D2_TOUCH_PEN_DETECT_DEBOUNCE_US *
590 /* get the required exponent */
591 while (pendbc >> i++)
596 tsmr = AT91_SAMA5D2_TSMR_TSMODE_4WIRE_PRESS;
598 tsmr |= AT91_SAMA5D2_TSMR_TSAV(2) & AT91_SAMA5D2_TSMR_TSAV_MASK;
599 tsmr |= AT91_SAMA5D2_TSMR_PENDBC(pendbc) &
600 AT91_SAMA5D2_TSMR_PENDBC_MASK;
601 tsmr |= AT91_SAMA5D2_TSMR_NOTSDMA;
602 tsmr |= AT91_SAMA5D2_TSMR_PENDET_ENA;
603 tsmr |= AT91_SAMA5D2_TSMR_TSFREQ(2) & AT91_SAMA5D2_TSMR_TSFREQ_MASK;
605 at91_adc_writel(st, AT91_SAMA5D2_TSMR, tsmr);
607 acr = at91_adc_readl(st, AT91_SAMA5D2_ACR);
608 acr &= ~AT91_SAMA5D2_ACR_PENDETSENS_MASK;
609 acr |= 0x02 & AT91_SAMA5D2_ACR_PENDETSENS_MASK;
610 at91_adc_writel(st, AT91_SAMA5D2_ACR, acr);
612 /* Sample Period Time = (TRGPER + 1) / ADCClock */
613 st->touch_st.sample_period_val =
614 round_up((AT91_SAMA5D2_TOUCH_SAMPLE_PERIOD_US *
615 clk_khz / 1000) - 1, 1);
616 /* enable pen detect IRQ */
617 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_PEN);
622 static u16 at91_adc_touch_pos(struct at91_adc_state *st, int reg)
625 u32 scale, result, pos;
628 * to obtain the actual position we must divide by scale
629 * and multiply with max, where
630 * max = 2^AT91_SAMA5D2_MAX_POS_BITS - 1
632 /* first half of register is the x or y, second half is the scale */
633 val = at91_adc_readl(st, reg);
635 dev_dbg(&iio_priv_to_dev(st)->dev, "pos is 0\n");
637 pos = val & AT91_SAMA5D2_XYZ_MASK;
638 result = (pos << AT91_SAMA5D2_MAX_POS_BITS) - pos;
639 scale = (val >> 16) & AT91_SAMA5D2_XYZ_MASK;
641 dev_err(&iio_priv_to_dev(st)->dev, "scale is 0\n");
649 static u16 at91_adc_touch_x_pos(struct at91_adc_state *st)
651 st->touch_st.x_pos = at91_adc_touch_pos(st, AT91_SAMA5D2_XPOSR);
652 return st->touch_st.x_pos;
655 static u16 at91_adc_touch_y_pos(struct at91_adc_state *st)
657 return at91_adc_touch_pos(st, AT91_SAMA5D2_YPOSR);
660 static u16 at91_adc_touch_pressure(struct at91_adc_state *st)
668 /* calculate the pressure */
669 val = at91_adc_readl(st, AT91_SAMA5D2_PRESSR);
670 z1 = val & AT91_SAMA5D2_XYZ_MASK;
671 z2 = (val >> 16) & AT91_SAMA5D2_XYZ_MASK;
674 pres = rxp * (st->touch_st.x_pos * factor / 1024) *
675 (z2 * factor / z1 - factor) /
678 pres = 0xFFFF; /* no pen contact */
681 * The pressure from device grows down, minimum is 0xFFFF, maximum 0x0.
682 * We compute it this way, but let's return it in the expected way,
683 * growing from 0 to 0xFFFF.
685 return 0xFFFF - pres;
688 static int at91_adc_read_position(struct at91_adc_state *st, int chan, u16 *val)
691 if (!st->touch_st.touching)
693 if (chan == AT91_SAMA5D2_TOUCH_X_CHAN_IDX)
694 *val = at91_adc_touch_x_pos(st);
695 else if (chan == AT91_SAMA5D2_TOUCH_Y_CHAN_IDX)
696 *val = at91_adc_touch_y_pos(st);
703 static int at91_adc_read_pressure(struct at91_adc_state *st, int chan, u16 *val)
706 if (!st->touch_st.touching)
708 if (chan == AT91_SAMA5D2_TOUCH_P_CHAN_IDX)
709 *val = at91_adc_touch_pressure(st);
716 static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
718 struct iio_dev *indio = iio_trigger_get_drvdata(trig);
719 struct at91_adc_state *st = iio_priv(indio);
720 u32 status = at91_adc_readl(st, AT91_SAMA5D2_TRGR);
724 status &= ~AT91_SAMA5D2_TRGR_TRGMOD_MASK;
727 status |= st->selected_trig->trgmod_value;
729 /* set/unset hw trigger */
730 at91_adc_writel(st, AT91_SAMA5D2_TRGR, status);
732 for_each_set_bit(bit, indio->active_scan_mask, indio->num_channels) {
733 struct iio_chan_spec const *chan = at91_adc_chan_get(indio, bit);
738 /* these channel types cannot be handled by this trigger */
739 if (chan->type == IIO_POSITIONRELATIVE ||
740 chan->type == IIO_PRESSURE)
744 cor = at91_adc_readl(st, AT91_SAMA5D2_COR);
746 if (chan->differential)
747 cor |= (BIT(chan->channel) |
748 BIT(chan->channel2)) <<
749 AT91_SAMA5D2_COR_DIFF_OFFSET;
751 cor &= ~(BIT(chan->channel) <<
752 AT91_SAMA5D2_COR_DIFF_OFFSET);
754 at91_adc_writel(st, AT91_SAMA5D2_COR, cor);
758 at91_adc_writel(st, AT91_SAMA5D2_CHER,
760 /* enable irq only if not using DMA */
761 if (!st->dma_st.dma_chan) {
762 at91_adc_writel(st, AT91_SAMA5D2_IER,
766 /* disable irq only if not using DMA */
767 if (!st->dma_st.dma_chan) {
768 at91_adc_writel(st, AT91_SAMA5D2_IDR,
771 at91_adc_writel(st, AT91_SAMA5D2_CHDR,
779 static int at91_adc_reenable_trigger(struct iio_trigger *trig)
781 struct iio_dev *indio = iio_trigger_get_drvdata(trig);
782 struct at91_adc_state *st = iio_priv(indio);
784 /* if we are using DMA, we must not reenable irq after each trigger */
785 if (st->dma_st.dma_chan)
790 /* Needed to ACK the DRDY interruption */
791 at91_adc_readl(st, AT91_SAMA5D2_LCDR);
795 static const struct iio_trigger_ops at91_adc_trigger_ops = {
796 .set_trigger_state = &at91_adc_configure_trigger,
797 .try_reenable = &at91_adc_reenable_trigger,
798 .validate_device = iio_trigger_validate_own_device,
801 static int at91_adc_dma_size_done(struct at91_adc_state *st)
803 struct dma_tx_state state;
804 enum dma_status status;
807 status = dmaengine_tx_status(st->dma_st.dma_chan,
808 st->dma_st.dma_chan->cookie,
810 if (status != DMA_IN_PROGRESS)
813 /* Transferred length is size in bytes from end of buffer */
814 i = st->dma_st.rx_buf_sz - state.residue;
816 /* Return available bytes */
817 if (i >= st->dma_st.buf_idx)
818 size = i - st->dma_st.buf_idx;
820 size = st->dma_st.rx_buf_sz + i - st->dma_st.buf_idx;
824 static void at91_dma_buffer_done(void *data)
826 struct iio_dev *indio_dev = data;
828 iio_trigger_poll_chained(indio_dev->trig);
831 static int at91_adc_dma_start(struct iio_dev *indio_dev)
833 struct at91_adc_state *st = iio_priv(indio_dev);
834 struct dma_async_tx_descriptor *desc;
839 if (!st->dma_st.dma_chan)
842 /* we start a new DMA, so set buffer index to start */
843 st->dma_st.buf_idx = 0;
846 * compute buffer size w.r.t. watermark and enabled channels.
847 * scan_bytes is aligned so we need an exact size for DMA
849 st->dma_st.rx_buf_sz = 0;
851 for_each_set_bit(bit, indio_dev->active_scan_mask,
852 indio_dev->num_channels) {
853 struct iio_chan_spec const *chan =
854 at91_adc_chan_get(indio_dev, bit);
859 st->dma_st.rx_buf_sz += chan->scan_type.storagebits / 8;
861 st->dma_st.rx_buf_sz *= st->dma_st.watermark;
863 /* Prepare a DMA cyclic transaction */
864 desc = dmaengine_prep_dma_cyclic(st->dma_st.dma_chan,
865 st->dma_st.rx_dma_buf,
866 st->dma_st.rx_buf_sz,
867 st->dma_st.rx_buf_sz / 2,
868 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
871 dev_err(&indio_dev->dev, "cannot prepare DMA cyclic\n");
875 desc->callback = at91_dma_buffer_done;
876 desc->callback_param = indio_dev;
878 cookie = dmaengine_submit(desc);
879 ret = dma_submit_error(cookie);
881 dev_err(&indio_dev->dev, "cannot submit DMA cyclic\n");
882 dmaengine_terminate_async(st->dma_st.dma_chan);
886 /* enable general overrun error signaling */
887 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_GOVRE);
888 /* Issue pending DMA requests */
889 dma_async_issue_pending(st->dma_st.dma_chan);
891 /* consider current time as DMA start time for timestamps */
892 st->dma_st.dma_ts = iio_get_time_ns(indio_dev);
894 dev_dbg(&indio_dev->dev, "DMA cyclic started\n");
899 static int at91_adc_buffer_postenable(struct iio_dev *indio_dev)
902 struct at91_adc_state *st = iio_priv(indio_dev);
904 /* check if we are enabling triggered buffer or the touchscreen */
905 if (bitmap_subset(indio_dev->active_scan_mask,
906 &st->touch_st.channels_bitmask,
907 AT91_SAMA5D2_MAX_CHAN_IDX + 1)) {
908 /* touchscreen enabling */
909 return at91_adc_configure_touch(st, true);
911 /* if we are not in triggered mode, we cannot enable the buffer. */
912 if (!(indio_dev->currentmode & INDIO_ALL_TRIGGERED_MODES))
915 /* we continue with the triggered buffer */
916 ret = at91_adc_dma_start(indio_dev);
918 dev_err(&indio_dev->dev, "buffer postenable failed\n");
922 return iio_triggered_buffer_postenable(indio_dev);
925 static int at91_adc_buffer_predisable(struct iio_dev *indio_dev)
927 struct at91_adc_state *st = iio_priv(indio_dev);
931 /* check if we are disabling triggered buffer or the touchscreen */
932 if (bitmap_subset(indio_dev->active_scan_mask,
933 &st->touch_st.channels_bitmask,
934 AT91_SAMA5D2_MAX_CHAN_IDX + 1)) {
935 /* touchscreen disable */
936 return at91_adc_configure_touch(st, false);
938 /* if we are not in triggered mode, nothing to do here */
939 if (!(indio_dev->currentmode & INDIO_ALL_TRIGGERED_MODES))
942 /* continue with the triggered buffer */
943 ret = iio_triggered_buffer_predisable(indio_dev);
945 dev_err(&indio_dev->dev, "buffer predisable failed\n");
947 if (!st->dma_st.dma_chan)
950 /* if we are using DMA we must clear registers and end DMA */
951 dmaengine_terminate_sync(st->dma_st.dma_chan);
954 * For each enabled channel we must read the last converted value
955 * to clear EOC status and not get a possible interrupt later.
956 * This value is being read by DMA from LCDR anyway
958 for_each_set_bit(bit, indio_dev->active_scan_mask,
959 indio_dev->num_channels) {
960 struct iio_chan_spec const *chan =
961 at91_adc_chan_get(indio_dev, bit);
965 /* these channel types are virtual, no need to do anything */
966 if (chan->type == IIO_POSITIONRELATIVE ||
967 chan->type == IIO_PRESSURE)
969 if (st->dma_st.dma_chan)
970 at91_adc_readl(st, chan->address);
973 /* read overflow register to clear possible overflow status */
974 at91_adc_readl(st, AT91_SAMA5D2_OVER);
978 static const struct iio_buffer_setup_ops at91_buffer_setup_ops = {
979 .postenable = &at91_adc_buffer_postenable,
980 .predisable = &at91_adc_buffer_predisable,
983 static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *indio,
986 struct iio_trigger *trig;
989 trig = devm_iio_trigger_alloc(&indio->dev, "%s-dev%d-%s", indio->name,
990 indio->id, trigger_name);
992 return ERR_PTR(-ENOMEM);
994 trig->dev.parent = indio->dev.parent;
995 iio_trigger_set_drvdata(trig, indio);
996 trig->ops = &at91_adc_trigger_ops;
998 ret = devm_iio_trigger_register(&indio->dev, trig);
1000 return ERR_PTR(ret);
1005 static int at91_adc_trigger_init(struct iio_dev *indio)
1007 struct at91_adc_state *st = iio_priv(indio);
1009 st->trig = at91_adc_allocate_trigger(indio, st->selected_trig->name);
1010 if (IS_ERR(st->trig)) {
1011 dev_err(&indio->dev,
1012 "could not allocate trigger\n");
1013 return PTR_ERR(st->trig);
1019 static void at91_adc_trigger_handler_nodma(struct iio_dev *indio_dev,
1020 struct iio_poll_func *pf)
1022 struct at91_adc_state *st = iio_priv(indio_dev);
1027 for_each_set_bit(bit, indio_dev->active_scan_mask,
1028 indio_dev->num_channels) {
1029 struct iio_chan_spec const *chan =
1030 at91_adc_chan_get(indio_dev, bit);
1035 * Our external trigger only supports the voltage channels.
1036 * In case someone requested a different type of channel
1037 * just put zeroes to buffer.
1038 * This should not happen because we check the scan mode
1039 * and scan mask when we enable the buffer, and we don't allow
1040 * the buffer to start with a mixed mask (voltage and something
1042 * Thus, emit a warning.
1044 if (chan->type == IIO_VOLTAGE) {
1045 val = at91_adc_readl(st, chan->address);
1046 at91_adc_adjust_val_osr(st, &val);
1047 st->buffer[i] = val;
1050 WARN(true, "This trigger cannot handle this type of channel");
1054 iio_push_to_buffers_with_timestamp(indio_dev, st->buffer,
1058 static void at91_adc_trigger_handler_dma(struct iio_dev *indio_dev)
1060 struct at91_adc_state *st = iio_priv(indio_dev);
1061 int transferred_len = at91_adc_dma_size_done(st);
1062 s64 ns = iio_get_time_ns(indio_dev);
1064 int sample_index = 0, sample_count, sample_size;
1066 u32 status = at91_adc_readl(st, AT91_SAMA5D2_ISR);
1067 /* if we reached this point, we cannot sample faster */
1068 if (status & AT91_SAMA5D2_IER_GOVRE)
1069 pr_info_ratelimited("%s: conversion overrun detected\n",
1072 sample_size = div_s64(st->dma_st.rx_buf_sz, st->dma_st.watermark);
1074 sample_count = div_s64(transferred_len, sample_size);
1077 * interval between samples is total time since last transfer handling
1078 * divided by the number of samples (total size divided by sample size)
1080 interval = div_s64((ns - st->dma_st.dma_ts), sample_count);
1082 while (transferred_len >= sample_size) {
1084 * for all the values in the current sample,
1085 * adjust the values inside the buffer for oversampling
1087 at91_adc_adjust_val_osr_array(st,
1088 &st->dma_st.rx_buf[st->dma_st.buf_idx],
1091 iio_push_to_buffers_with_timestamp(indio_dev,
1092 (st->dma_st.rx_buf + st->dma_st.buf_idx),
1093 (st->dma_st.dma_ts + interval * sample_index));
1094 /* adjust remaining length */
1095 transferred_len -= sample_size;
1096 /* adjust buffer index */
1097 st->dma_st.buf_idx += sample_size;
1098 /* in case of reaching end of buffer, reset index */
1099 if (st->dma_st.buf_idx >= st->dma_st.rx_buf_sz)
1100 st->dma_st.buf_idx = 0;
1103 /* adjust saved time for next transfer handling */
1104 st->dma_st.dma_ts = iio_get_time_ns(indio_dev);
1107 static irqreturn_t at91_adc_trigger_handler(int irq, void *p)
1109 struct iio_poll_func *pf = p;
1110 struct iio_dev *indio_dev = pf->indio_dev;
1111 struct at91_adc_state *st = iio_priv(indio_dev);
1113 if (st->dma_st.dma_chan)
1114 at91_adc_trigger_handler_dma(indio_dev);
1116 at91_adc_trigger_handler_nodma(indio_dev, pf);
1118 iio_trigger_notify_done(indio_dev->trig);
1123 static int at91_adc_buffer_init(struct iio_dev *indio)
1125 struct at91_adc_state *st = iio_priv(indio);
1127 if (st->selected_trig->hw_trig) {
1128 return devm_iio_triggered_buffer_setup(&indio->dev, indio,
1129 &iio_pollfunc_store_time,
1130 &at91_adc_trigger_handler, &at91_buffer_setup_ops);
1133 * we need to prepare the buffer ops in case we will get
1134 * another buffer attached (like a callback buffer for the touchscreen)
1136 indio->setup_ops = &at91_buffer_setup_ops;
1141 static unsigned at91_adc_startup_time(unsigned startup_time_min,
1142 unsigned adc_clk_khz)
1144 static const unsigned int startup_lookup[] = {
1150 unsigned ticks_min, i;
1153 * Since the adc frequency is checked before, there is no reason
1154 * to not meet the startup time constraint.
1157 ticks_min = startup_time_min * adc_clk_khz / 1000;
1158 for (i = 0; i < ARRAY_SIZE(startup_lookup); i++)
1159 if (startup_lookup[i] > ticks_min)
1165 static void at91_adc_setup_samp_freq(struct at91_adc_state *st, unsigned freq)
1167 struct iio_dev *indio_dev = iio_priv_to_dev(st);
1168 unsigned f_per, prescal, startup, mr;
1170 f_per = clk_get_rate(st->per_clk);
1171 prescal = (f_per / (2 * freq)) - 1;
1173 startup = at91_adc_startup_time(st->soc_info.startup_time,
1176 mr = at91_adc_readl(st, AT91_SAMA5D2_MR);
1177 mr &= ~(AT91_SAMA5D2_MR_STARTUP_MASK | AT91_SAMA5D2_MR_PRESCAL_MASK);
1178 mr |= AT91_SAMA5D2_MR_STARTUP(startup);
1179 mr |= AT91_SAMA5D2_MR_PRESCAL(prescal);
1180 at91_adc_writel(st, AT91_SAMA5D2_MR, mr);
1182 dev_dbg(&indio_dev->dev, "freq: %u, startup: %u, prescal: %u\n",
1183 freq, startup, prescal);
1184 st->current_sample_rate = freq;
1187 static inline unsigned at91_adc_get_sample_freq(struct at91_adc_state *st)
1189 return st->current_sample_rate;
1192 static void at91_adc_touch_data_handler(struct iio_dev *indio_dev)
1194 struct at91_adc_state *st = iio_priv(indio_dev);
1199 for_each_set_bit(bit, indio_dev->active_scan_mask,
1200 AT91_SAMA5D2_MAX_CHAN_IDX + 1) {
1201 struct iio_chan_spec const *chan =
1202 at91_adc_chan_get(indio_dev, bit);
1204 if (chan->type == IIO_POSITIONRELATIVE)
1205 at91_adc_read_position(st, chan->channel, &val);
1206 else if (chan->type == IIO_PRESSURE)
1207 at91_adc_read_pressure(st, chan->channel, &val);
1210 st->buffer[i] = val;
1214 * Schedule work to push to buffers.
1215 * This is intended to push to the callback buffer that another driver
1216 * registered. We are still in a handler from our IRQ. If we push
1217 * directly, it means the other driver has it's callback called
1218 * from our IRQ context. Which is something we better avoid.
1219 * Let's schedule it after our IRQ is completed.
1221 schedule_work(&st->touch_st.workq);
1224 static void at91_adc_pen_detect_interrupt(struct at91_adc_state *st)
1226 at91_adc_writel(st, AT91_SAMA5D2_IDR, AT91_SAMA5D2_IER_PEN);
1227 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_NOPEN |
1228 AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY |
1229 AT91_SAMA5D2_IER_PRDY);
1230 at91_adc_writel(st, AT91_SAMA5D2_TRGR,
1231 AT91_SAMA5D2_TRGR_TRGMOD_PERIODIC |
1232 AT91_SAMA5D2_TRGR_TRGPER(st->touch_st.sample_period_val));
1233 st->touch_st.touching = true;
1236 static void at91_adc_no_pen_detect_interrupt(struct at91_adc_state *st)
1238 struct iio_dev *indio_dev = iio_priv_to_dev(st);
1240 at91_adc_writel(st, AT91_SAMA5D2_TRGR,
1241 AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER);
1242 at91_adc_writel(st, AT91_SAMA5D2_IDR, AT91_SAMA5D2_IER_NOPEN |
1243 AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY |
1244 AT91_SAMA5D2_IER_PRDY);
1245 st->touch_st.touching = false;
1247 at91_adc_touch_data_handler(indio_dev);
1249 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_PEN);
1252 static void at91_adc_workq_handler(struct work_struct *workq)
1254 struct at91_adc_touch *touch_st = container_of(workq,
1255 struct at91_adc_touch, workq);
1256 struct at91_adc_state *st = container_of(touch_st,
1257 struct at91_adc_state, touch_st);
1258 struct iio_dev *indio_dev = iio_priv_to_dev(st);
1260 iio_push_to_buffers(indio_dev, st->buffer);
1263 static irqreturn_t at91_adc_interrupt(int irq, void *private)
1265 struct iio_dev *indio = private;
1266 struct at91_adc_state *st = iio_priv(indio);
1267 u32 status = at91_adc_readl(st, AT91_SAMA5D2_ISR);
1268 u32 imr = at91_adc_readl(st, AT91_SAMA5D2_IMR);
1269 u32 rdy_mask = AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY |
1270 AT91_SAMA5D2_IER_PRDY;
1272 if (!(status & imr))
1274 if (status & AT91_SAMA5D2_IER_PEN) {
1275 /* pen detected IRQ */
1276 at91_adc_pen_detect_interrupt(st);
1277 } else if ((status & AT91_SAMA5D2_IER_NOPEN)) {
1278 /* nopen detected IRQ */
1279 at91_adc_no_pen_detect_interrupt(st);
1280 } else if ((status & AT91_SAMA5D2_ISR_PENS) &&
1281 ((status & rdy_mask) == rdy_mask)) {
1282 /* periodic trigger IRQ - during pen sense */
1283 at91_adc_touch_data_handler(indio);
1284 } else if (status & AT91_SAMA5D2_ISR_PENS) {
1286 * touching, but the measurements are not ready yet.
1289 status = at91_adc_readl(st, AT91_SAMA5D2_XPOSR);
1290 status = at91_adc_readl(st, AT91_SAMA5D2_YPOSR);
1291 status = at91_adc_readl(st, AT91_SAMA5D2_PRESSR);
1292 } else if (iio_buffer_enabled(indio) && !st->dma_st.dma_chan) {
1293 /* triggered buffer without DMA */
1294 disable_irq_nosync(irq);
1295 iio_trigger_poll(indio->trig);
1296 } else if (iio_buffer_enabled(indio) && st->dma_st.dma_chan) {
1297 /* triggered buffer with DMA - should not happen */
1298 disable_irq_nosync(irq);
1299 WARN(true, "Unexpected irq occurred\n");
1300 } else if (!iio_buffer_enabled(indio)) {
1301 /* software requested conversion */
1302 st->conversion_value = at91_adc_readl(st, st->chan->address);
1303 st->conversion_done = true;
1304 wake_up_interruptible(&st->wq_data_available);
1309 static int at91_adc_read_info_raw(struct iio_dev *indio_dev,
1310 struct iio_chan_spec const *chan, int *val)
1312 struct at91_adc_state *st = iio_priv(indio_dev);
1318 * Keep in mind that we cannot use software trigger or touchscreen
1319 * if external trigger is enabled
1321 if (chan->type == IIO_POSITIONRELATIVE) {
1322 ret = iio_device_claim_direct_mode(indio_dev);
1325 mutex_lock(&st->lock);
1327 ret = at91_adc_read_position(st, chan->channel,
1330 mutex_unlock(&st->lock);
1331 iio_device_release_direct_mode(indio_dev);
1333 ret = at91_adc_adjust_val_osr(st, val);
1337 if (chan->type == IIO_PRESSURE) {
1338 ret = iio_device_claim_direct_mode(indio_dev);
1341 mutex_lock(&st->lock);
1343 ret = at91_adc_read_pressure(st, chan->channel,
1346 mutex_unlock(&st->lock);
1347 iio_device_release_direct_mode(indio_dev);
1349 ret = at91_adc_adjust_val_osr(st, val);
1354 /* in this case we have a voltage channel */
1356 ret = iio_device_claim_direct_mode(indio_dev);
1359 mutex_lock(&st->lock);
1363 if (chan->differential)
1364 cor = (BIT(chan->channel) | BIT(chan->channel2)) <<
1365 AT91_SAMA5D2_COR_DIFF_OFFSET;
1367 at91_adc_writel(st, AT91_SAMA5D2_COR, cor);
1368 at91_adc_writel(st, AT91_SAMA5D2_CHER, BIT(chan->channel));
1369 at91_adc_writel(st, AT91_SAMA5D2_IER, BIT(chan->channel));
1370 at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_START);
1372 ret = wait_event_interruptible_timeout(st->wq_data_available,
1373 st->conversion_done,
1374 msecs_to_jiffies(1000));
1379 *val = st->conversion_value;
1380 ret = at91_adc_adjust_val_osr(st, val);
1381 if (chan->scan_type.sign == 's')
1382 *val = sign_extend32(*val,
1383 chan->scan_type.realbits - 1);
1384 st->conversion_done = false;
1387 at91_adc_writel(st, AT91_SAMA5D2_IDR, BIT(chan->channel));
1388 at91_adc_writel(st, AT91_SAMA5D2_CHDR, BIT(chan->channel));
1390 /* Needed to ACK the DRDY interruption */
1391 at91_adc_readl(st, AT91_SAMA5D2_LCDR);
1393 mutex_unlock(&st->lock);
1395 iio_device_release_direct_mode(indio_dev);
1399 static int at91_adc_read_raw(struct iio_dev *indio_dev,
1400 struct iio_chan_spec const *chan,
1401 int *val, int *val2, long mask)
1403 struct at91_adc_state *st = iio_priv(indio_dev);
1406 case IIO_CHAN_INFO_RAW:
1407 return at91_adc_read_info_raw(indio_dev, chan, val);
1408 case IIO_CHAN_INFO_SCALE:
1409 *val = st->vref_uv / 1000;
1410 if (chan->differential)
1412 *val2 = chan->scan_type.realbits;
1413 return IIO_VAL_FRACTIONAL_LOG2;
1415 case IIO_CHAN_INFO_SAMP_FREQ:
1416 *val = at91_adc_get_sample_freq(st);
1419 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1420 *val = st->oversampling_ratio;
1428 static int at91_adc_write_raw(struct iio_dev *indio_dev,
1429 struct iio_chan_spec const *chan,
1430 int val, int val2, long mask)
1432 struct at91_adc_state *st = iio_priv(indio_dev);
1435 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1436 if ((val != AT91_OSR_1SAMPLES) && (val != AT91_OSR_4SAMPLES) &&
1437 (val != AT91_OSR_16SAMPLES))
1439 /* if no change, optimize out */
1440 if (val == st->oversampling_ratio)
1442 st->oversampling_ratio = val;
1444 at91_adc_config_emr(st);
1446 case IIO_CHAN_INFO_SAMP_FREQ:
1447 if (val < st->soc_info.min_sample_rate ||
1448 val > st->soc_info.max_sample_rate)
1451 at91_adc_setup_samp_freq(st, val);
1458 static void at91_adc_dma_init(struct platform_device *pdev)
1460 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
1461 struct at91_adc_state *st = iio_priv(indio_dev);
1462 struct dma_slave_config config = {0};
1464 * We make the buffer double the size of the fifo,
1465 * such that DMA uses one half of the buffer (full fifo size)
1466 * and the software uses the other half to read/write.
1468 unsigned int pages = DIV_ROUND_UP(AT91_HWFIFO_MAX_SIZE *
1469 AT91_BUFFER_MAX_CONVERSION_BYTES * 2,
1472 if (st->dma_st.dma_chan)
1475 st->dma_st.dma_chan = dma_request_slave_channel(&pdev->dev, "rx");
1477 if (!st->dma_st.dma_chan) {
1478 dev_info(&pdev->dev, "can't get DMA channel\n");
1482 st->dma_st.rx_buf = dma_alloc_coherent(st->dma_st.dma_chan->device->dev,
1484 &st->dma_st.rx_dma_buf,
1486 if (!st->dma_st.rx_buf) {
1487 dev_info(&pdev->dev, "can't allocate coherent DMA area\n");
1488 goto dma_chan_disable;
1491 /* Configure DMA channel to read data register */
1492 config.direction = DMA_DEV_TO_MEM;
1493 config.src_addr = (phys_addr_t)(st->dma_st.phys_addr
1494 + AT91_SAMA5D2_LCDR);
1495 config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1496 config.src_maxburst = 1;
1497 config.dst_maxburst = 1;
1499 if (dmaengine_slave_config(st->dma_st.dma_chan, &config)) {
1500 dev_info(&pdev->dev, "can't configure DMA slave\n");
1504 dev_info(&pdev->dev, "using %s for rx DMA transfers\n",
1505 dma_chan_name(st->dma_st.dma_chan));
1510 dma_free_coherent(st->dma_st.dma_chan->device->dev, pages * PAGE_SIZE,
1511 st->dma_st.rx_buf, st->dma_st.rx_dma_buf);
1513 dma_release_channel(st->dma_st.dma_chan);
1514 st->dma_st.dma_chan = 0;
1516 dev_info(&pdev->dev, "continuing without DMA support\n");
1519 static void at91_adc_dma_disable(struct platform_device *pdev)
1521 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
1522 struct at91_adc_state *st = iio_priv(indio_dev);
1523 unsigned int pages = DIV_ROUND_UP(AT91_HWFIFO_MAX_SIZE *
1524 AT91_BUFFER_MAX_CONVERSION_BYTES * 2,
1527 /* if we are not using DMA, just return */
1528 if (!st->dma_st.dma_chan)
1531 /* wait for all transactions to be terminated first*/
1532 dmaengine_terminate_sync(st->dma_st.dma_chan);
1534 dma_free_coherent(st->dma_st.dma_chan->device->dev, pages * PAGE_SIZE,
1535 st->dma_st.rx_buf, st->dma_st.rx_dma_buf);
1536 dma_release_channel(st->dma_st.dma_chan);
1537 st->dma_st.dma_chan = 0;
1539 dev_info(&pdev->dev, "continuing without DMA support\n");
1542 static int at91_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val)
1544 struct at91_adc_state *st = iio_priv(indio_dev);
1546 if (val > AT91_HWFIFO_MAX_SIZE)
1549 if (!st->selected_trig->hw_trig) {
1550 dev_dbg(&indio_dev->dev, "we need hw trigger for DMA\n");
1554 dev_dbg(&indio_dev->dev, "new watermark is %u\n", val);
1555 st->dma_st.watermark = val;
1558 * The logic here is: if we have watermark 1, it means we do
1559 * each conversion with it's own IRQ, thus we don't need DMA.
1560 * If the watermark is higher, we do DMA to do all the transfers in bulk
1564 at91_adc_dma_disable(to_platform_device(&indio_dev->dev));
1566 at91_adc_dma_init(to_platform_device(&indio_dev->dev));
1571 static int at91_adc_update_scan_mode(struct iio_dev *indio_dev,
1572 const unsigned long *scan_mask)
1574 struct at91_adc_state *st = iio_priv(indio_dev);
1576 if (bitmap_subset(scan_mask, &st->touch_st.channels_bitmask,
1577 AT91_SAMA5D2_MAX_CHAN_IDX + 1))
1580 * if the new bitmap is a combination of touchscreen and regular
1581 * channels, then we are not fine
1583 if (bitmap_intersects(&st->touch_st.channels_bitmask, scan_mask,
1584 AT91_SAMA5D2_MAX_CHAN_IDX + 1))
1589 static void at91_adc_hw_init(struct at91_adc_state *st)
1591 at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_SWRST);
1592 at91_adc_writel(st, AT91_SAMA5D2_IDR, 0xffffffff);
1594 * Transfer field must be set to 2 according to the datasheet and
1595 * allows different analog settings for each channel.
1597 at91_adc_writel(st, AT91_SAMA5D2_MR,
1598 AT91_SAMA5D2_MR_TRANSFER(2) | AT91_SAMA5D2_MR_ANACH);
1600 at91_adc_setup_samp_freq(st, st->soc_info.min_sample_rate);
1602 /* configure extended mode register */
1603 at91_adc_config_emr(st);
1606 static ssize_t at91_adc_get_fifo_state(struct device *dev,
1607 struct device_attribute *attr, char *buf)
1609 struct iio_dev *indio_dev =
1610 platform_get_drvdata(to_platform_device(dev));
1611 struct at91_adc_state *st = iio_priv(indio_dev);
1613 return scnprintf(buf, PAGE_SIZE, "%d\n", !!st->dma_st.dma_chan);
1616 static ssize_t at91_adc_get_watermark(struct device *dev,
1617 struct device_attribute *attr, char *buf)
1619 struct iio_dev *indio_dev =
1620 platform_get_drvdata(to_platform_device(dev));
1621 struct at91_adc_state *st = iio_priv(indio_dev);
1623 return scnprintf(buf, PAGE_SIZE, "%d\n", st->dma_st.watermark);
1626 static IIO_DEVICE_ATTR(hwfifo_enabled, 0444,
1627 at91_adc_get_fifo_state, NULL, 0);
1628 static IIO_DEVICE_ATTR(hwfifo_watermark, 0444,
1629 at91_adc_get_watermark, NULL, 0);
1631 static IIO_CONST_ATTR(hwfifo_watermark_min, "2");
1632 static IIO_CONST_ATTR(hwfifo_watermark_max, AT91_HWFIFO_MAX_SIZE_STR);
1634 static IIO_CONST_ATTR(oversampling_ratio_available,
1635 __stringify(AT91_OSR_1SAMPLES) " "
1636 __stringify(AT91_OSR_4SAMPLES) " "
1637 __stringify(AT91_OSR_16SAMPLES));
1639 static struct attribute *at91_adc_attributes[] = {
1640 &iio_const_attr_oversampling_ratio_available.dev_attr.attr,
1644 static const struct attribute_group at91_adc_attribute_group = {
1645 .attrs = at91_adc_attributes,
1648 static const struct attribute *at91_adc_fifo_attributes[] = {
1649 &iio_const_attr_hwfifo_watermark_min.dev_attr.attr,
1650 &iio_const_attr_hwfifo_watermark_max.dev_attr.attr,
1651 &iio_dev_attr_hwfifo_watermark.dev_attr.attr,
1652 &iio_dev_attr_hwfifo_enabled.dev_attr.attr,
1656 static const struct iio_info at91_adc_info = {
1657 .attrs = &at91_adc_attribute_group,
1658 .read_raw = &at91_adc_read_raw,
1659 .write_raw = &at91_adc_write_raw,
1660 .update_scan_mode = &at91_adc_update_scan_mode,
1661 .of_xlate = &at91_adc_of_xlate,
1662 .hwfifo_set_watermark = &at91_adc_set_watermark,
1665 static int at91_adc_probe(struct platform_device *pdev)
1667 struct iio_dev *indio_dev;
1668 struct at91_adc_state *st;
1669 struct resource *res;
1671 u32 edge_type = IRQ_TYPE_NONE;
1673 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st));
1677 indio_dev->dev.parent = &pdev->dev;
1678 indio_dev->name = dev_name(&pdev->dev);
1679 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
1680 indio_dev->info = &at91_adc_info;
1681 indio_dev->channels = at91_adc_channels;
1682 indio_dev->num_channels = ARRAY_SIZE(at91_adc_channels);
1684 st = iio_priv(indio_dev);
1686 bitmap_set(&st->touch_st.channels_bitmask,
1687 AT91_SAMA5D2_TOUCH_X_CHAN_IDX, 1);
1688 bitmap_set(&st->touch_st.channels_bitmask,
1689 AT91_SAMA5D2_TOUCH_Y_CHAN_IDX, 1);
1690 bitmap_set(&st->touch_st.channels_bitmask,
1691 AT91_SAMA5D2_TOUCH_P_CHAN_IDX, 1);
1693 st->oversampling_ratio = AT91_OSR_1SAMPLES;
1695 ret = of_property_read_u32(pdev->dev.of_node,
1696 "atmel,min-sample-rate-hz",
1697 &st->soc_info.min_sample_rate);
1700 "invalid or missing value for atmel,min-sample-rate-hz\n");
1704 ret = of_property_read_u32(pdev->dev.of_node,
1705 "atmel,max-sample-rate-hz",
1706 &st->soc_info.max_sample_rate);
1709 "invalid or missing value for atmel,max-sample-rate-hz\n");
1713 ret = of_property_read_u32(pdev->dev.of_node, "atmel,startup-time-ms",
1714 &st->soc_info.startup_time);
1717 "invalid or missing value for atmel,startup-time-ms\n");
1721 ret = of_property_read_u32(pdev->dev.of_node,
1722 "atmel,trigger-edge-type", &edge_type);
1725 "atmel,trigger-edge-type not specified, only software trigger available\n");
1728 st->selected_trig = NULL;
1730 /* find the right trigger, or no trigger at all */
1731 for (i = 0; i < AT91_SAMA5D2_HW_TRIG_CNT + 1; i++)
1732 if (at91_adc_trigger_list[i].edge_type == edge_type) {
1733 st->selected_trig = &at91_adc_trigger_list[i];
1737 if (!st->selected_trig) {
1738 dev_err(&pdev->dev, "invalid external trigger edge value\n");
1742 init_waitqueue_head(&st->wq_data_available);
1743 mutex_init(&st->lock);
1744 INIT_WORK(&st->touch_st.workq, at91_adc_workq_handler);
1746 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1750 /* if we plan to use DMA, we need the physical address of the regs */
1751 st->dma_st.phys_addr = res->start;
1753 st->base = devm_ioremap_resource(&pdev->dev, res);
1754 if (IS_ERR(st->base))
1755 return PTR_ERR(st->base);
1757 st->irq = platform_get_irq(pdev, 0);
1765 st->per_clk = devm_clk_get(&pdev->dev, "adc_clk");
1766 if (IS_ERR(st->per_clk))
1767 return PTR_ERR(st->per_clk);
1769 st->reg = devm_regulator_get(&pdev->dev, "vddana");
1770 if (IS_ERR(st->reg))
1771 return PTR_ERR(st->reg);
1773 st->vref = devm_regulator_get(&pdev->dev, "vref");
1774 if (IS_ERR(st->vref))
1775 return PTR_ERR(st->vref);
1777 ret = devm_request_irq(&pdev->dev, st->irq, at91_adc_interrupt, 0,
1778 pdev->dev.driver->name, indio_dev);
1782 ret = regulator_enable(st->reg);
1786 ret = regulator_enable(st->vref);
1790 st->vref_uv = regulator_get_voltage(st->vref);
1791 if (st->vref_uv <= 0) {
1796 at91_adc_hw_init(st);
1798 ret = clk_prepare_enable(st->per_clk);
1802 platform_set_drvdata(pdev, indio_dev);
1804 ret = at91_adc_buffer_init(indio_dev);
1806 dev_err(&pdev->dev, "couldn't initialize the buffer.\n");
1807 goto per_clk_disable_unprepare;
1810 if (st->selected_trig->hw_trig) {
1811 ret = at91_adc_trigger_init(indio_dev);
1813 dev_err(&pdev->dev, "couldn't setup the triggers.\n");
1814 goto per_clk_disable_unprepare;
1817 * Initially the iio buffer has a length of 2 and
1820 st->dma_st.watermark = 1;
1822 iio_buffer_set_attrs(indio_dev->buffer,
1823 at91_adc_fifo_attributes);
1826 if (dma_coerce_mask_and_coherent(&indio_dev->dev, DMA_BIT_MASK(32)))
1827 dev_info(&pdev->dev, "cannot set DMA mask to 32-bit\n");
1829 ret = iio_device_register(indio_dev);
1833 if (st->selected_trig->hw_trig)
1834 dev_info(&pdev->dev, "setting up trigger as %s\n",
1835 st->selected_trig->name);
1837 dev_info(&pdev->dev, "version: %x\n",
1838 readl_relaxed(st->base + AT91_SAMA5D2_VERSION));
1843 at91_adc_dma_disable(pdev);
1844 per_clk_disable_unprepare:
1845 clk_disable_unprepare(st->per_clk);
1847 regulator_disable(st->vref);
1849 regulator_disable(st->reg);
1853 static int at91_adc_remove(struct platform_device *pdev)
1855 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
1856 struct at91_adc_state *st = iio_priv(indio_dev);
1858 iio_device_unregister(indio_dev);
1860 at91_adc_dma_disable(pdev);
1862 clk_disable_unprepare(st->per_clk);
1864 regulator_disable(st->vref);
1865 regulator_disable(st->reg);
1870 static __maybe_unused int at91_adc_suspend(struct device *dev)
1872 struct iio_dev *indio_dev =
1873 platform_get_drvdata(to_platform_device(dev));
1874 struct at91_adc_state *st = iio_priv(indio_dev);
1877 * Do a sofware reset of the ADC before we go to suspend.
1878 * this will ensure that all pins are free from being muxed by the ADC
1879 * and can be used by for other devices.
1880 * Otherwise, ADC will hog them and we can't go to suspend mode.
1882 at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_SWRST);
1884 clk_disable_unprepare(st->per_clk);
1885 regulator_disable(st->vref);
1886 regulator_disable(st->reg);
1888 return pinctrl_pm_select_sleep_state(dev);
1891 static __maybe_unused int at91_adc_resume(struct device *dev)
1893 struct iio_dev *indio_dev =
1894 platform_get_drvdata(to_platform_device(dev));
1895 struct at91_adc_state *st = iio_priv(indio_dev);
1898 ret = pinctrl_pm_select_default_state(dev);
1902 ret = regulator_enable(st->reg);
1906 ret = regulator_enable(st->vref);
1908 goto reg_disable_resume;
1910 ret = clk_prepare_enable(st->per_clk);
1912 goto vref_disable_resume;
1914 at91_adc_hw_init(st);
1916 /* reconfiguring trigger hardware state */
1917 if (!iio_buffer_enabled(indio_dev))
1920 /* check if we are enabling triggered buffer or the touchscreen */
1921 if (bitmap_subset(indio_dev->active_scan_mask,
1922 &st->touch_st.channels_bitmask,
1923 AT91_SAMA5D2_MAX_CHAN_IDX + 1)) {
1924 /* touchscreen enabling */
1925 return at91_adc_configure_touch(st, true);
1927 return at91_adc_configure_trigger(st->trig, true);
1930 /* not needed but more explicit */
1933 vref_disable_resume:
1934 regulator_disable(st->vref);
1936 regulator_disable(st->reg);
1938 dev_err(&indio_dev->dev, "failed to resume\n");
1942 static SIMPLE_DEV_PM_OPS(at91_adc_pm_ops, at91_adc_suspend, at91_adc_resume);
1944 static const struct of_device_id at91_adc_dt_match[] = {
1946 .compatible = "atmel,sama5d2-adc",
1951 MODULE_DEVICE_TABLE(of, at91_adc_dt_match);
1953 static struct platform_driver at91_adc_driver = {
1954 .probe = at91_adc_probe,
1955 .remove = at91_adc_remove,
1957 .name = "at91-sama5d2_adc",
1958 .of_match_table = at91_adc_dt_match,
1959 .pm = &at91_adc_pm_ops,
1962 module_platform_driver(at91_adc_driver)
1964 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
1965 MODULE_DESCRIPTION("Atmel AT91 SAMA5D2 ADC");
1966 MODULE_LICENSE("GPL v2");