2 * Freescale MXS LRADC ADC driver
4 * Copyright (c) 2012 DENX Software Engineering, GmbH.
5 * Copyright (c) 2017 Ksenija Stanojevic <ksenija.stanojevic@gmail.com>
8 * Marek Vasut <marex@denx.de>
9 * Ksenija Stanojevic <ksenija.stanojevic@gmail.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
22 #include <linux/completion.h>
23 #include <linux/device.h>
24 #include <linux/err.h>
25 #include <linux/interrupt.h>
26 #include <linux/mfd/core.h>
27 #include <linux/mfd/mxs-lradc.h>
28 #include <linux/module.h>
29 #include <linux/of_irq.h>
30 #include <linux/platform_device.h>
31 #include <linux/sysfs.h>
33 #include <linux/iio/buffer.h>
34 #include <linux/iio/iio.h>
35 #include <linux/iio/trigger.h>
36 #include <linux/iio/trigger_consumer.h>
37 #include <linux/iio/triggered_buffer.h>
38 #include <linux/iio/sysfs.h>
41 * Make this runtime configurable if necessary. Currently, if the buffered mode
42 * is enabled, the LRADC takes LRADC_DELAY_TIMER_LOOP samples of data before
43 * triggering IRQ. The sampling happens every (LRADC_DELAY_TIMER_PER / 2000)
44 * seconds. The result is that the samples arrive every 500mS.
46 #define LRADC_DELAY_TIMER_PER 200
47 #define LRADC_DELAY_TIMER_LOOP 5
49 #define VREF_MV_BASE 1850
51 static const char *mx23_lradc_adc_irq_names[] = {
60 static const char *mx28_lradc_adc_irq_names[] = {
73 static const u32 mxs_lradc_adc_vref_mv[][LRADC_MAX_TOTAL_CHANS] = {
75 VREF_MV_BASE, /* CH0 */
76 VREF_MV_BASE, /* CH1 */
77 VREF_MV_BASE, /* CH2 */
78 VREF_MV_BASE, /* CH3 */
79 VREF_MV_BASE, /* CH4 */
80 VREF_MV_BASE, /* CH5 */
81 VREF_MV_BASE * 2, /* CH6 VDDIO */
82 VREF_MV_BASE * 4, /* CH7 VBATT */
83 VREF_MV_BASE, /* CH8 Temp sense 0 */
84 VREF_MV_BASE, /* CH9 Temp sense 1 */
85 VREF_MV_BASE, /* CH10 */
86 VREF_MV_BASE, /* CH11 */
87 VREF_MV_BASE, /* CH12 USB_DP */
88 VREF_MV_BASE, /* CH13 USB_DN */
89 VREF_MV_BASE, /* CH14 VBG */
90 VREF_MV_BASE * 4, /* CH15 VDD5V */
93 VREF_MV_BASE, /* CH0 */
94 VREF_MV_BASE, /* CH1 */
95 VREF_MV_BASE, /* CH2 */
96 VREF_MV_BASE, /* CH3 */
97 VREF_MV_BASE, /* CH4 */
98 VREF_MV_BASE, /* CH5 */
99 VREF_MV_BASE, /* CH6 */
100 VREF_MV_BASE * 4, /* CH7 VBATT */
101 VREF_MV_BASE, /* CH8 Temp sense 0 */
102 VREF_MV_BASE, /* CH9 Temp sense 1 */
103 VREF_MV_BASE * 2, /* CH10 VDDIO */
104 VREF_MV_BASE, /* CH11 VTH */
105 VREF_MV_BASE * 2, /* CH12 VDDA */
106 VREF_MV_BASE, /* CH13 VDDD */
107 VREF_MV_BASE, /* CH14 VBG */
108 VREF_MV_BASE * 4, /* CH15 VDD5V */
112 enum mxs_lradc_divbytwo {
113 MXS_LRADC_DIV_DISABLED = 0,
114 MXS_LRADC_DIV_ENABLED,
117 struct mxs_lradc_scale {
118 unsigned int integer;
122 struct mxs_lradc_adc {
123 struct mxs_lradc *lradc;
127 /* Maximum of 8 channels + 8 byte ts */
128 u32 buffer[10] __aligned(8);
129 struct iio_trigger *trig;
130 struct completion completion;
134 struct mxs_lradc_scale scale_avail[LRADC_MAX_TOTAL_CHANS][2];
135 unsigned long is_divided;
139 /* Raw I/O operations */
140 static int mxs_lradc_adc_read_single(struct iio_dev *iio_dev, int chan,
143 struct mxs_lradc_adc *adc = iio_priv(iio_dev);
144 struct mxs_lradc *lradc = adc->lradc;
148 * See if there is no buffered operation in progress. If there is simply
149 * bail out. This can be improved to support both buffered and raw IO at
150 * the same time, yet the code becomes horribly complicated. Therefore I
151 * applied KISS principle here.
153 ret = iio_device_claim_direct_mode(iio_dev);
157 reinit_completion(&adc->completion);
160 * No buffered operation in progress, map the channel and trigger it.
161 * Virtual channel 0 is always used here as the others are always not
162 * used if doing raw sampling.
164 if (lradc->soc == IMX28_LRADC)
165 writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
166 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
167 writel(0x1, adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
169 /* Enable / disable the divider per requirement */
170 if (test_bit(chan, &adc->is_divided))
171 writel(1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
172 adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_SET);
174 writel(1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
175 adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_CLR);
177 /* Clean the slot's previous content, then set new one. */
178 writel(LRADC_CTRL4_LRADCSELECT_MASK(0),
179 adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR);
180 writel(chan, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET);
182 writel(0, adc->base + LRADC_CH(0));
184 /* Enable the IRQ and start sampling the channel. */
185 writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
186 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
187 writel(BIT(0), adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET);
189 /* Wait for completion on the channel, 1 second max. */
190 ret = wait_for_completion_killable_timeout(&adc->completion, HZ);
197 *val = readl(adc->base + LRADC_CH(0)) & LRADC_CH_VALUE_MASK;
201 writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
202 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
204 iio_device_release_direct_mode(iio_dev);
209 static int mxs_lradc_adc_read_temp(struct iio_dev *iio_dev, int *val)
213 ret = mxs_lradc_adc_read_single(iio_dev, 8, &min);
214 if (ret != IIO_VAL_INT)
217 ret = mxs_lradc_adc_read_single(iio_dev, 9, &max);
218 if (ret != IIO_VAL_INT)
226 static int mxs_lradc_adc_read_raw(struct iio_dev *iio_dev,
227 const struct iio_chan_spec *chan,
228 int *val, int *val2, long m)
230 struct mxs_lradc_adc *adc = iio_priv(iio_dev);
233 case IIO_CHAN_INFO_RAW:
234 if (chan->type == IIO_TEMP)
235 return mxs_lradc_adc_read_temp(iio_dev, val);
237 return mxs_lradc_adc_read_single(iio_dev, chan->channel, val);
239 case IIO_CHAN_INFO_SCALE:
240 if (chan->type == IIO_TEMP) {
242 * From the datasheet, we have to multiply by 1.012 and
247 return IIO_VAL_INT_PLUS_MICRO;
250 *val = adc->vref_mv[chan->channel];
251 *val2 = chan->scan_type.realbits -
252 test_bit(chan->channel, &adc->is_divided);
253 return IIO_VAL_FRACTIONAL_LOG2;
255 case IIO_CHAN_INFO_OFFSET:
256 if (chan->type == IIO_TEMP) {
258 * The calculated value from the ADC is in Kelvin, we
259 * want Celsius for hwmon so the offset is -273.15
260 * The offset is applied before scaling so it is
261 * actually -213.15 * 4 / 1.012 = -1079.644268
266 return IIO_VAL_INT_PLUS_MICRO;
278 static int mxs_lradc_adc_write_raw(struct iio_dev *iio_dev,
279 const struct iio_chan_spec *chan,
280 int val, int val2, long m)
282 struct mxs_lradc_adc *adc = iio_priv(iio_dev);
283 struct mxs_lradc_scale *scale_avail =
284 adc->scale_avail[chan->channel];
287 ret = iio_device_claim_direct_mode(iio_dev);
292 case IIO_CHAN_INFO_SCALE:
294 if (val == scale_avail[MXS_LRADC_DIV_DISABLED].integer &&
295 val2 == scale_avail[MXS_LRADC_DIV_DISABLED].nano) {
296 /* divider by two disabled */
297 clear_bit(chan->channel, &adc->is_divided);
299 } else if (val == scale_avail[MXS_LRADC_DIV_ENABLED].integer &&
300 val2 == scale_avail[MXS_LRADC_DIV_ENABLED].nano) {
301 /* divider by two enabled */
302 set_bit(chan->channel, &adc->is_divided);
312 iio_device_release_direct_mode(iio_dev);
317 static int mxs_lradc_adc_write_raw_get_fmt(struct iio_dev *iio_dev,
318 const struct iio_chan_spec *chan,
321 return IIO_VAL_INT_PLUS_NANO;
324 static ssize_t mxs_lradc_adc_show_scale_avail(struct device *dev,
325 struct device_attribute *attr,
328 struct iio_dev *iio = dev_to_iio_dev(dev);
329 struct mxs_lradc_adc *adc = iio_priv(iio);
330 struct iio_dev_attr *iio_attr = to_iio_dev_attr(attr);
333 ch = iio_attr->address;
334 for (i = 0; i < ARRAY_SIZE(adc->scale_avail[ch]); i++)
335 len += sprintf(buf + len, "%u.%09u ",
336 adc->scale_avail[ch][i].integer,
337 adc->scale_avail[ch][i].nano);
339 len += sprintf(buf + len, "\n");
344 #define SHOW_SCALE_AVAILABLE_ATTR(ch)\
345 IIO_DEVICE_ATTR(in_voltage##ch##_scale_available, 0444,\
346 mxs_lradc_adc_show_scale_avail, NULL, ch)
348 static SHOW_SCALE_AVAILABLE_ATTR(0);
349 static SHOW_SCALE_AVAILABLE_ATTR(1);
350 static SHOW_SCALE_AVAILABLE_ATTR(2);
351 static SHOW_SCALE_AVAILABLE_ATTR(3);
352 static SHOW_SCALE_AVAILABLE_ATTR(4);
353 static SHOW_SCALE_AVAILABLE_ATTR(5);
354 static SHOW_SCALE_AVAILABLE_ATTR(6);
355 static SHOW_SCALE_AVAILABLE_ATTR(7);
356 static SHOW_SCALE_AVAILABLE_ATTR(10);
357 static SHOW_SCALE_AVAILABLE_ATTR(11);
358 static SHOW_SCALE_AVAILABLE_ATTR(12);
359 static SHOW_SCALE_AVAILABLE_ATTR(13);
360 static SHOW_SCALE_AVAILABLE_ATTR(14);
361 static SHOW_SCALE_AVAILABLE_ATTR(15);
363 static struct attribute *mxs_lradc_adc_attributes[] = {
364 &iio_dev_attr_in_voltage0_scale_available.dev_attr.attr,
365 &iio_dev_attr_in_voltage1_scale_available.dev_attr.attr,
366 &iio_dev_attr_in_voltage2_scale_available.dev_attr.attr,
367 &iio_dev_attr_in_voltage3_scale_available.dev_attr.attr,
368 &iio_dev_attr_in_voltage4_scale_available.dev_attr.attr,
369 &iio_dev_attr_in_voltage5_scale_available.dev_attr.attr,
370 &iio_dev_attr_in_voltage6_scale_available.dev_attr.attr,
371 &iio_dev_attr_in_voltage7_scale_available.dev_attr.attr,
372 &iio_dev_attr_in_voltage10_scale_available.dev_attr.attr,
373 &iio_dev_attr_in_voltage11_scale_available.dev_attr.attr,
374 &iio_dev_attr_in_voltage12_scale_available.dev_attr.attr,
375 &iio_dev_attr_in_voltage13_scale_available.dev_attr.attr,
376 &iio_dev_attr_in_voltage14_scale_available.dev_attr.attr,
377 &iio_dev_attr_in_voltage15_scale_available.dev_attr.attr,
381 static const struct attribute_group mxs_lradc_adc_attribute_group = {
382 .attrs = mxs_lradc_adc_attributes,
385 static const struct iio_info mxs_lradc_adc_iio_info = {
386 .read_raw = mxs_lradc_adc_read_raw,
387 .write_raw = mxs_lradc_adc_write_raw,
388 .write_raw_get_fmt = mxs_lradc_adc_write_raw_get_fmt,
389 .attrs = &mxs_lradc_adc_attribute_group,
393 static irqreturn_t mxs_lradc_adc_handle_irq(int irq, void *data)
395 struct iio_dev *iio = data;
396 struct mxs_lradc_adc *adc = iio_priv(iio);
397 struct mxs_lradc *lradc = adc->lradc;
398 unsigned long reg = readl(adc->base + LRADC_CTRL1);
401 if (!(reg & mxs_lradc_irq_mask(lradc)))
404 if (iio_buffer_enabled(iio)) {
405 if (reg & lradc->buffer_vchans) {
406 spin_lock_irqsave(&adc->lock, flags);
407 iio_trigger_poll(iio->trig);
408 spin_unlock_irqrestore(&adc->lock, flags);
410 } else if (reg & LRADC_CTRL1_LRADC_IRQ(0)) {
411 complete(&adc->completion);
414 writel(reg & mxs_lradc_irq_mask(lradc),
415 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
421 /* Trigger handling */
422 static irqreturn_t mxs_lradc_adc_trigger_handler(int irq, void *p)
424 struct iio_poll_func *pf = p;
425 struct iio_dev *iio = pf->indio_dev;
426 struct mxs_lradc_adc *adc = iio_priv(iio);
427 const u32 chan_value = LRADC_CH_ACCUMULATE |
428 ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
429 unsigned int i, j = 0;
431 for_each_set_bit(i, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
432 adc->buffer[j] = readl(adc->base + LRADC_CH(j));
433 writel(chan_value, adc->base + LRADC_CH(j));
434 adc->buffer[j] &= LRADC_CH_VALUE_MASK;
435 adc->buffer[j] /= LRADC_DELAY_TIMER_LOOP;
439 iio_push_to_buffers_with_timestamp(iio, adc->buffer, pf->timestamp);
441 iio_trigger_notify_done(iio->trig);
446 static int mxs_lradc_adc_configure_trigger(struct iio_trigger *trig, bool state)
448 struct iio_dev *iio = iio_trigger_get_drvdata(trig);
449 struct mxs_lradc_adc *adc = iio_priv(iio);
450 const u32 st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR;
452 writel(LRADC_DELAY_KICK, adc->base + (LRADC_DELAY(0) + st));
457 static const struct iio_trigger_ops mxs_lradc_adc_trigger_ops = {
458 .set_trigger_state = &mxs_lradc_adc_configure_trigger,
461 static int mxs_lradc_adc_trigger_init(struct iio_dev *iio)
464 struct iio_trigger *trig;
465 struct mxs_lradc_adc *adc = iio_priv(iio);
467 trig = devm_iio_trigger_alloc(&iio->dev, "%s-dev%i", iio->name,
470 trig->dev.parent = adc->dev;
471 iio_trigger_set_drvdata(trig, iio);
472 trig->ops = &mxs_lradc_adc_trigger_ops;
474 ret = iio_trigger_register(trig);
483 static void mxs_lradc_adc_trigger_remove(struct iio_dev *iio)
485 struct mxs_lradc_adc *adc = iio_priv(iio);
487 iio_trigger_unregister(adc->trig);
490 static int mxs_lradc_adc_buffer_preenable(struct iio_dev *iio)
492 struct mxs_lradc_adc *adc = iio_priv(iio);
493 struct mxs_lradc *lradc = adc->lradc;
495 unsigned long enable = 0;
499 const u32 chan_value = LRADC_CH_ACCUMULATE |
500 ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
502 if (lradc->soc == IMX28_LRADC)
503 writel(lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET,
504 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
505 writel(lradc->buffer_vchans,
506 adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
508 for_each_set_bit(chan, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
509 ctrl4_set |= chan << LRADC_CTRL4_LRADCSELECT_OFFSET(ofs);
510 ctrl4_clr |= LRADC_CTRL4_LRADCSELECT_MASK(ofs);
511 ctrl1_irq |= LRADC_CTRL1_LRADC_IRQ_EN(ofs);
512 writel(chan_value, adc->base + LRADC_CH(ofs));
513 bitmap_set(&enable, ofs, 1);
517 writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK,
518 adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);
519 writel(ctrl4_clr, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR);
520 writel(ctrl4_set, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET);
521 writel(ctrl1_irq, adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
522 writel(enable << LRADC_DELAY_TRIGGER_LRADCS_OFFSET,
523 adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_SET);
528 static int mxs_lradc_adc_buffer_postdisable(struct iio_dev *iio)
530 struct mxs_lradc_adc *adc = iio_priv(iio);
531 struct mxs_lradc *lradc = adc->lradc;
533 writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK,
534 adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);
536 writel(lradc->buffer_vchans,
537 adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
538 if (lradc->soc == IMX28_LRADC)
539 writel(lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET,
540 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
545 static bool mxs_lradc_adc_validate_scan_mask(struct iio_dev *iio,
546 const unsigned long *mask)
548 struct mxs_lradc_adc *adc = iio_priv(iio);
549 struct mxs_lradc *lradc = adc->lradc;
550 const int map_chans = bitmap_weight(mask, LRADC_MAX_TOTAL_CHANS);
552 unsigned long rsvd_mask = 0;
554 if (lradc->use_touchbutton)
555 rsvd_mask |= CHAN_MASK_TOUCHBUTTON;
556 if (lradc->touchscreen_wire == MXS_LRADC_TOUCHSCREEN_4WIRE)
557 rsvd_mask |= CHAN_MASK_TOUCHSCREEN_4WIRE;
558 if (lradc->touchscreen_wire == MXS_LRADC_TOUCHSCREEN_5WIRE)
559 rsvd_mask |= CHAN_MASK_TOUCHSCREEN_5WIRE;
561 if (lradc->use_touchbutton)
563 if (lradc->touchscreen_wire)
566 /* Test for attempts to map channels with special mode of operation. */
567 if (bitmap_intersects(mask, &rsvd_mask, LRADC_MAX_TOTAL_CHANS))
570 /* Test for attempts to map more channels then available slots. */
571 if (map_chans + rsvd_chans > LRADC_MAX_MAPPED_CHANS)
577 static const struct iio_buffer_setup_ops mxs_lradc_adc_buffer_ops = {
578 .preenable = &mxs_lradc_adc_buffer_preenable,
579 .postenable = &iio_triggered_buffer_postenable,
580 .predisable = &iio_triggered_buffer_predisable,
581 .postdisable = &mxs_lradc_adc_buffer_postdisable,
582 .validate_scan_mask = &mxs_lradc_adc_validate_scan_mask,
585 /* Driver initialization */
586 #define MXS_ADC_CHAN(idx, chan_type, name) { \
587 .type = (chan_type), \
589 .scan_index = (idx), \
590 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
591 BIT(IIO_CHAN_INFO_SCALE), \
596 .realbits = LRADC_RESOLUTION, \
599 .datasheet_name = (name), \
602 static const struct iio_chan_spec mx23_lradc_chan_spec[] = {
603 MXS_ADC_CHAN(0, IIO_VOLTAGE, "LRADC0"),
604 MXS_ADC_CHAN(1, IIO_VOLTAGE, "LRADC1"),
605 MXS_ADC_CHAN(2, IIO_VOLTAGE, "LRADC2"),
606 MXS_ADC_CHAN(3, IIO_VOLTAGE, "LRADC3"),
607 MXS_ADC_CHAN(4, IIO_VOLTAGE, "LRADC4"),
608 MXS_ADC_CHAN(5, IIO_VOLTAGE, "LRADC5"),
609 MXS_ADC_CHAN(6, IIO_VOLTAGE, "VDDIO"),
610 MXS_ADC_CHAN(7, IIO_VOLTAGE, "VBATT"),
611 /* Combined Temperature sensors */
616 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
617 BIT(IIO_CHAN_INFO_OFFSET) |
618 BIT(IIO_CHAN_INFO_SCALE),
620 .scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,},
621 .datasheet_name = "TEMP_DIE",
623 /* Hidden channel to keep indexes */
630 MXS_ADC_CHAN(10, IIO_VOLTAGE, NULL),
631 MXS_ADC_CHAN(11, IIO_VOLTAGE, NULL),
632 MXS_ADC_CHAN(12, IIO_VOLTAGE, "USB_DP"),
633 MXS_ADC_CHAN(13, IIO_VOLTAGE, "USB_DN"),
634 MXS_ADC_CHAN(14, IIO_VOLTAGE, "VBG"),
635 MXS_ADC_CHAN(15, IIO_VOLTAGE, "VDD5V"),
638 static const struct iio_chan_spec mx28_lradc_chan_spec[] = {
639 MXS_ADC_CHAN(0, IIO_VOLTAGE, "LRADC0"),
640 MXS_ADC_CHAN(1, IIO_VOLTAGE, "LRADC1"),
641 MXS_ADC_CHAN(2, IIO_VOLTAGE, "LRADC2"),
642 MXS_ADC_CHAN(3, IIO_VOLTAGE, "LRADC3"),
643 MXS_ADC_CHAN(4, IIO_VOLTAGE, "LRADC4"),
644 MXS_ADC_CHAN(5, IIO_VOLTAGE, "LRADC5"),
645 MXS_ADC_CHAN(6, IIO_VOLTAGE, "LRADC6"),
646 MXS_ADC_CHAN(7, IIO_VOLTAGE, "VBATT"),
647 /* Combined Temperature sensors */
652 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
653 BIT(IIO_CHAN_INFO_OFFSET) |
654 BIT(IIO_CHAN_INFO_SCALE),
656 .scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,},
657 .datasheet_name = "TEMP_DIE",
659 /* Hidden channel to keep indexes */
666 MXS_ADC_CHAN(10, IIO_VOLTAGE, "VDDIO"),
667 MXS_ADC_CHAN(11, IIO_VOLTAGE, "VTH"),
668 MXS_ADC_CHAN(12, IIO_VOLTAGE, "VDDA"),
669 MXS_ADC_CHAN(13, IIO_VOLTAGE, "VDDD"),
670 MXS_ADC_CHAN(14, IIO_VOLTAGE, "VBG"),
671 MXS_ADC_CHAN(15, IIO_VOLTAGE, "VDD5V"),
674 static void mxs_lradc_adc_hw_init(struct mxs_lradc_adc *adc)
676 /* The ADC always uses DELAY CHANNEL 0. */
678 (1 << (LRADC_DELAY_TRIGGER_DELAYS_OFFSET + 0)) |
679 (LRADC_DELAY_TIMER_PER << LRADC_DELAY_DELAY_OFFSET);
681 /* Configure DELAY CHANNEL 0 for generic ADC sampling. */
682 writel(adc_cfg, adc->base + LRADC_DELAY(0));
685 * Start internal temperature sensing by clearing bit
686 * HW_LRADC_CTRL2_TEMPSENSE_PWD. This bit can be left cleared
689 writel(0, adc->base + LRADC_CTRL2);
692 static void mxs_lradc_adc_hw_stop(struct mxs_lradc_adc *adc)
694 writel(0, adc->base + LRADC_DELAY(0));
697 static int mxs_lradc_adc_probe(struct platform_device *pdev)
699 struct device *dev = &pdev->dev;
700 struct mxs_lradc *lradc = dev_get_drvdata(dev->parent);
701 struct mxs_lradc_adc *adc;
703 struct resource *iores;
704 int ret, irq, virq, i, s, n;
706 const char **irq_name;
708 /* Allocate the IIO device. */
709 iio = devm_iio_device_alloc(dev, sizeof(*adc));
711 dev_err(dev, "Failed to allocate IIO device\n");
719 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
723 adc->base = devm_ioremap(dev, iores->start, resource_size(iores));
727 init_completion(&adc->completion);
728 spin_lock_init(&adc->lock);
730 platform_set_drvdata(pdev, iio);
732 iio->name = pdev->name;
733 iio->dev.parent = dev;
734 iio->dev.of_node = dev->parent->of_node;
735 iio->info = &mxs_lradc_adc_iio_info;
736 iio->modes = INDIO_DIRECT_MODE;
737 iio->masklength = LRADC_MAX_TOTAL_CHANS;
739 if (lradc->soc == IMX23_LRADC) {
740 iio->channels = mx23_lradc_chan_spec;
741 iio->num_channels = ARRAY_SIZE(mx23_lradc_chan_spec);
742 irq_name = mx23_lradc_adc_irq_names;
743 n = ARRAY_SIZE(mx23_lradc_adc_irq_names);
745 iio->channels = mx28_lradc_chan_spec;
746 iio->num_channels = ARRAY_SIZE(mx28_lradc_chan_spec);
747 irq_name = mx28_lradc_adc_irq_names;
748 n = ARRAY_SIZE(mx28_lradc_adc_irq_names);
751 ret = stmp_reset_block(adc->base);
755 for (i = 0; i < n; i++) {
756 irq = platform_get_irq_byname(pdev, irq_name[i]);
760 virq = irq_of_parse_and_map(dev->parent->of_node, irq);
762 ret = devm_request_irq(dev, virq, mxs_lradc_adc_handle_irq,
763 0, irq_name[i], iio);
768 ret = mxs_lradc_adc_trigger_init(iio);
772 ret = iio_triggered_buffer_setup(iio, &iio_pollfunc_store_time,
773 &mxs_lradc_adc_trigger_handler,
774 &mxs_lradc_adc_buffer_ops);
778 adc->vref_mv = mxs_lradc_adc_vref_mv[lradc->soc];
780 /* Populate available ADC input ranges */
781 for (i = 0; i < LRADC_MAX_TOTAL_CHANS; i++) {
782 for (s = 0; s < ARRAY_SIZE(adc->scale_avail[i]); s++) {
784 * [s=0] = optional divider by two disabled (default)
785 * [s=1] = optional divider by two enabled
787 * The scale is calculated by doing:
788 * Vref >> (realbits - s)
789 * which multiplies by two on the second component
792 scale_uv = ((u64)adc->vref_mv[i] * 100000000) >>
793 (LRADC_RESOLUTION - s);
794 adc->scale_avail[i][s].nano =
795 do_div(scale_uv, 100000000) * 10;
796 adc->scale_avail[i][s].integer = scale_uv;
800 /* Configure the hardware. */
801 mxs_lradc_adc_hw_init(adc);
803 /* Register IIO device. */
804 ret = iio_device_register(iio);
806 dev_err(dev, "Failed to register IIO device\n");
813 mxs_lradc_adc_hw_stop(adc);
814 mxs_lradc_adc_trigger_remove(iio);
816 iio_triggered_buffer_cleanup(iio);
820 static int mxs_lradc_adc_remove(struct platform_device *pdev)
822 struct iio_dev *iio = platform_get_drvdata(pdev);
823 struct mxs_lradc_adc *adc = iio_priv(iio);
825 iio_device_unregister(iio);
826 mxs_lradc_adc_hw_stop(adc);
827 mxs_lradc_adc_trigger_remove(iio);
828 iio_triggered_buffer_cleanup(iio);
833 static struct platform_driver mxs_lradc_adc_driver = {
835 .name = "mxs-lradc-adc",
837 .probe = mxs_lradc_adc_probe,
838 .remove = mxs_lradc_adc_remove,
840 module_platform_driver(mxs_lradc_adc_driver);
842 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
843 MODULE_DESCRIPTION("Freescale MXS LRADC driver general purpose ADC driver");
844 MODULE_LICENSE("GPL");
845 MODULE_ALIAS("platform:mxs-lradc-adc");