2 * This file is part of STM32 ADC driver
4 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
5 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
7 * Inspired from: fsl-imx25-tsadc
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published by
13 * the Free Software Foundation.
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 * or FITNESS FOR A PARTICULAR PURPOSE.
18 * See the GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License along with
21 * this program. If not, see <http://www.gnu.org/licenses/>.
24 #include <linux/clk.h>
25 #include <linux/interrupt.h>
26 #include <linux/irqchip/chained_irq.h>
27 #include <linux/irqdesc.h>
28 #include <linux/irqdomain.h>
29 #include <linux/module.h>
30 #include <linux/of_device.h>
31 #include <linux/regulator/consumer.h>
32 #include <linux/slab.h>
34 #include "stm32-adc-core.h"
36 /* STM32 F4 maximum analog clock rate (from datasheet) */
37 #define STM32F4_ADC_MAX_CLK_RATE 36000000
39 /* STM32 H7 maximum analog clock rate (from datasheet) */
40 #define STM32H7_ADC_MAX_CLK_RATE 36000000
43 * stm32_adc_common_regs - stm32 common registers, compatible dependent data
44 * @csr: common status register offset
45 * @eoc1: adc1 end of conversion flag in @csr
46 * @eoc2: adc2 end of conversion flag in @csr
47 * @eoc3: adc3 end of conversion flag in @csr
48 * @ier: interrupt enable register offset for each adc
49 * @eocie_msk: end of conversion interrupt enable mask in @ier
51 struct stm32_adc_common_regs {
60 struct stm32_adc_priv;
63 * stm32_adc_priv_cfg - stm32 core compatible configuration data
64 * @regs: common registers for all instances
65 * @clk_sel: clock selection routine
67 struct stm32_adc_priv_cfg {
68 const struct stm32_adc_common_regs *regs;
69 int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *);
73 * struct stm32_adc_priv - stm32 ADC core private data
74 * @irq: irq for ADC block
75 * @domain: irq domain reference
76 * @aclk: clock reference for the analog circuitry
77 * @bclk: bus clock common for all ADCs, depends on part used
78 * @vref: regulator reference
79 * @cfg: compatible configuration data
80 * @common: common data for all ADC instances
82 struct stm32_adc_priv {
84 struct irq_domain *domain;
87 struct regulator *vref;
88 const struct stm32_adc_priv_cfg *cfg;
89 struct stm32_adc_common common;
92 static struct stm32_adc_priv *to_stm32_adc_priv(struct stm32_adc_common *com)
94 return container_of(com, struct stm32_adc_priv, common);
97 /* STM32F4 ADC internal common clock prescaler division ratios */
98 static int stm32f4_pclk_div[] = {2, 4, 6, 8};
101 * stm32f4_adc_clk_sel() - Select stm32f4 ADC common clock prescaler
102 * @priv: stm32 ADC core private data
103 * Select clock prescaler used for analog conversions, before using ADC.
105 static int stm32f4_adc_clk_sel(struct platform_device *pdev,
106 struct stm32_adc_priv *priv)
112 /* stm32f4 has one clk input for analog (mandatory), enforce it here */
114 dev_err(&pdev->dev, "No 'adc' clock found\n");
118 rate = clk_get_rate(priv->aclk);
119 for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) {
120 if ((rate / stm32f4_pclk_div[i]) <= STM32F4_ADC_MAX_CLK_RATE)
123 if (i >= ARRAY_SIZE(stm32f4_pclk_div)) {
124 dev_err(&pdev->dev, "adc clk selection failed\n");
128 priv->common.rate = rate / stm32f4_pclk_div[i];
129 val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR);
130 val &= ~STM32F4_ADC_ADCPRE_MASK;
131 val |= i << STM32F4_ADC_ADCPRE_SHIFT;
132 writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR);
134 dev_dbg(&pdev->dev, "Using analog clock source at %ld kHz\n",
135 priv->common.rate / 1000);
141 * struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock
142 * @ckmode: ADC clock mode, Async or sync with prescaler.
143 * @presc: prescaler bitfield for async clock mode
144 * @div: prescaler division ratio
146 struct stm32h7_adc_ck_spec {
152 static const struct stm32h7_adc_ck_spec stm32h7_adc_ckmodes_spec[] = {
153 /* 00: CK_ADC[1..3]: Asynchronous clock modes */
166 /* HCLK used: Synchronous clock modes (1, 2 or 4 prescaler) */
172 static int stm32h7_adc_clk_sel(struct platform_device *pdev,
173 struct stm32_adc_priv *priv)
175 u32 ckmode, presc, val;
179 /* stm32h7 bus clock is common for all ADC instances (mandatory) */
181 dev_err(&pdev->dev, "No 'bus' clock found\n");
186 * stm32h7 can use either 'bus' or 'adc' clock for analog circuitry.
187 * So, choice is to have bus clock mandatory and adc clock optional.
188 * If optional 'adc' clock has been found, then try to use it first.
192 * Asynchronous clock modes (e.g. ckmode == 0)
193 * From spec: PLL output musn't exceed max rate
195 rate = clk_get_rate(priv->aclk);
197 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
198 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
199 presc = stm32h7_adc_ckmodes_spec[i].presc;
200 div = stm32h7_adc_ckmodes_spec[i].div;
205 if ((rate / div) <= STM32H7_ADC_MAX_CLK_RATE)
210 /* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */
211 rate = clk_get_rate(priv->bclk);
213 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
214 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
215 presc = stm32h7_adc_ckmodes_spec[i].presc;
216 div = stm32h7_adc_ckmodes_spec[i].div;
221 if ((rate / div) <= STM32H7_ADC_MAX_CLK_RATE)
225 dev_err(&pdev->dev, "adc clk selection failed\n");
229 /* rate used later by each ADC instance to control BOOST mode */
230 priv->common.rate = rate / div;
232 /* Set common clock mode and prescaler */
233 val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR);
234 val &= ~(STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK);
235 val |= ckmode << STM32H7_CKMODE_SHIFT;
236 val |= presc << STM32H7_PRESC_SHIFT;
237 writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR);
239 dev_dbg(&pdev->dev, "Using %s clock/%d source at %ld kHz\n",
240 ckmode ? "bus" : "adc", div, priv->common.rate / 1000);
245 /* STM32F4 common registers definitions */
246 static const struct stm32_adc_common_regs stm32f4_adc_common_regs = {
247 .csr = STM32F4_ADC_CSR,
248 .eoc1_msk = STM32F4_EOC1,
249 .eoc2_msk = STM32F4_EOC2,
250 .eoc3_msk = STM32F4_EOC3,
251 .ier = STM32F4_ADC_CR1,
252 .eocie_msk = STM32F4_EOCIE,
255 /* STM32H7 common registers definitions */
256 static const struct stm32_adc_common_regs stm32h7_adc_common_regs = {
257 .csr = STM32H7_ADC_CSR,
258 .eoc1_msk = STM32H7_EOC_MST,
259 .eoc2_msk = STM32H7_EOC_SLV,
260 .ier = STM32H7_ADC_IER,
261 .eocie_msk = STM32H7_EOCIE,
264 static const unsigned int stm32_adc_offset[STM32_ADC_MAX_ADCS] = {
265 0, STM32_ADC_OFFSET, STM32_ADC_OFFSET * 2,
268 static unsigned int stm32_adc_eoc_enabled(struct stm32_adc_priv *priv,
271 u32 ier, offset = stm32_adc_offset[adc];
273 ier = readl_relaxed(priv->common.base + offset + priv->cfg->regs->ier);
275 return ier & priv->cfg->regs->eocie_msk;
278 /* ADC common interrupt for all instances */
279 static void stm32_adc_irq_handler(struct irq_desc *desc)
281 struct stm32_adc_priv *priv = irq_desc_get_handler_data(desc);
282 struct irq_chip *chip = irq_desc_get_chip(desc);
285 chained_irq_enter(chip, desc);
286 status = readl_relaxed(priv->common.base + priv->cfg->regs->csr);
289 * End of conversion may be handled by using IRQ or DMA. There may be a
290 * race here when two conversions complete at the same time on several
291 * ADCs. EOC may be read 'set' for several ADCs, with:
292 * - an ADC configured to use DMA (EOC triggers the DMA request, and
293 * is then automatically cleared by DR read in hardware)
294 * - an ADC configured to use IRQs (EOCIE bit is set. The handler must
295 * be called in this case)
296 * So both EOC status bit in CSR and EOCIE control bit must be checked
297 * before invoking the interrupt handler (e.g. call ISR only for
300 if (status & priv->cfg->regs->eoc1_msk &&
301 stm32_adc_eoc_enabled(priv, 0))
302 generic_handle_irq(irq_find_mapping(priv->domain, 0));
304 if (status & priv->cfg->regs->eoc2_msk &&
305 stm32_adc_eoc_enabled(priv, 1))
306 generic_handle_irq(irq_find_mapping(priv->domain, 1));
308 if (status & priv->cfg->regs->eoc3_msk &&
309 stm32_adc_eoc_enabled(priv, 2))
310 generic_handle_irq(irq_find_mapping(priv->domain, 2));
312 chained_irq_exit(chip, desc);
315 static int stm32_adc_domain_map(struct irq_domain *d, unsigned int irq,
316 irq_hw_number_t hwirq)
318 irq_set_chip_data(irq, d->host_data);
319 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_level_irq);
324 static void stm32_adc_domain_unmap(struct irq_domain *d, unsigned int irq)
326 irq_set_chip_and_handler(irq, NULL, NULL);
327 irq_set_chip_data(irq, NULL);
330 static const struct irq_domain_ops stm32_adc_domain_ops = {
331 .map = stm32_adc_domain_map,
332 .unmap = stm32_adc_domain_unmap,
333 .xlate = irq_domain_xlate_onecell,
336 static int stm32_adc_irq_probe(struct platform_device *pdev,
337 struct stm32_adc_priv *priv)
339 struct device_node *np = pdev->dev.of_node;
341 priv->irq = platform_get_irq(pdev, 0);
343 dev_err(&pdev->dev, "failed to get irq\n");
347 priv->domain = irq_domain_add_simple(np, STM32_ADC_MAX_ADCS, 0,
348 &stm32_adc_domain_ops,
351 dev_err(&pdev->dev, "Failed to add irq domain\n");
355 irq_set_chained_handler(priv->irq, stm32_adc_irq_handler);
356 irq_set_handler_data(priv->irq, priv);
361 static void stm32_adc_irq_remove(struct platform_device *pdev,
362 struct stm32_adc_priv *priv)
366 for (hwirq = 0; hwirq < STM32_ADC_MAX_ADCS; hwirq++)
367 irq_dispose_mapping(irq_find_mapping(priv->domain, hwirq));
368 irq_domain_remove(priv->domain);
369 irq_set_chained_handler(priv->irq, NULL);
372 static int stm32_adc_probe(struct platform_device *pdev)
374 struct stm32_adc_priv *priv;
375 struct device *dev = &pdev->dev;
376 struct device_node *np = pdev->dev.of_node;
377 struct resource *res;
380 if (!pdev->dev.of_node)
383 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
387 priv->cfg = (const struct stm32_adc_priv_cfg *)
388 of_match_device(dev->driver->of_match_table, dev)->data;
390 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
391 priv->common.base = devm_ioremap_resource(&pdev->dev, res);
392 if (IS_ERR(priv->common.base))
393 return PTR_ERR(priv->common.base);
394 priv->common.phys_base = res->start;
396 priv->vref = devm_regulator_get(&pdev->dev, "vref");
397 if (IS_ERR(priv->vref)) {
398 ret = PTR_ERR(priv->vref);
399 dev_err(&pdev->dev, "vref get failed, %d\n", ret);
403 ret = regulator_enable(priv->vref);
405 dev_err(&pdev->dev, "vref enable failed\n");
409 ret = regulator_get_voltage(priv->vref);
411 dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret);
412 goto err_regulator_disable;
414 priv->common.vref_mv = ret / 1000;
415 dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv);
417 priv->aclk = devm_clk_get(&pdev->dev, "adc");
418 if (IS_ERR(priv->aclk)) {
419 ret = PTR_ERR(priv->aclk);
420 if (ret == -ENOENT) {
423 dev_err(&pdev->dev, "Can't get 'adc' clock\n");
424 goto err_regulator_disable;
429 ret = clk_prepare_enable(priv->aclk);
431 dev_err(&pdev->dev, "adc clk enable failed\n");
432 goto err_regulator_disable;
436 priv->bclk = devm_clk_get(&pdev->dev, "bus");
437 if (IS_ERR(priv->bclk)) {
438 ret = PTR_ERR(priv->bclk);
439 if (ret == -ENOENT) {
442 dev_err(&pdev->dev, "Can't get 'bus' clock\n");
443 goto err_aclk_disable;
448 ret = clk_prepare_enable(priv->bclk);
450 dev_err(&pdev->dev, "adc clk enable failed\n");
451 goto err_aclk_disable;
455 ret = priv->cfg->clk_sel(pdev, priv);
457 goto err_bclk_disable;
459 ret = stm32_adc_irq_probe(pdev, priv);
461 goto err_bclk_disable;
463 platform_set_drvdata(pdev, &priv->common);
465 ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
467 dev_err(&pdev->dev, "failed to populate DT children\n");
474 stm32_adc_irq_remove(pdev, priv);
478 clk_disable_unprepare(priv->bclk);
482 clk_disable_unprepare(priv->aclk);
484 err_regulator_disable:
485 regulator_disable(priv->vref);
490 static int stm32_adc_remove(struct platform_device *pdev)
492 struct stm32_adc_common *common = platform_get_drvdata(pdev);
493 struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
495 of_platform_depopulate(&pdev->dev);
496 stm32_adc_irq_remove(pdev, priv);
498 clk_disable_unprepare(priv->bclk);
500 clk_disable_unprepare(priv->aclk);
501 regulator_disable(priv->vref);
506 static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = {
507 .regs = &stm32f4_adc_common_regs,
508 .clk_sel = stm32f4_adc_clk_sel,
511 static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = {
512 .regs = &stm32h7_adc_common_regs,
513 .clk_sel = stm32h7_adc_clk_sel,
516 static const struct of_device_id stm32_adc_of_match[] = {
518 .compatible = "st,stm32f4-adc-core",
519 .data = (void *)&stm32f4_adc_priv_cfg
521 .compatible = "st,stm32h7-adc-core",
522 .data = (void *)&stm32h7_adc_priv_cfg
526 MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
528 static struct platform_driver stm32_adc_driver = {
529 .probe = stm32_adc_probe,
530 .remove = stm32_adc_remove,
532 .name = "stm32-adc-core",
533 .of_match_table = stm32_adc_of_match,
536 module_platform_driver(stm32_adc_driver);
538 MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
539 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC core driver");
540 MODULE_LICENSE("GPL v2");
541 MODULE_ALIAS("platform:stm32-adc-core");