drivers/iio/adc/vf610_adc.c

   1 /*
   2  * Freescale Vybrid vf610 ADC driver
   3  *
   4  * Copyright 2013 Freescale Semiconductor, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, write to the Free Software
  18  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20
  21 #include <linux/module.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/slab.h>
  27 #include <linux/io.h>
  28 #include <linux/clk.h>
  29 #include <linux/completion.h>
  30 #include <linux/of.h>
  31 #include <linux/of_irq.h>
  32 #include <linux/regulator/consumer.h>
  33 #include <linux/of_platform.h>
  34 #include <linux/err.h>
  35
  36 #include <linux/iio/iio.h>
  37 #include <linux/iio/buffer.h>
  38 #include <linux/iio/sysfs.h>
  39 #include <linux/iio/trigger.h>
  40 #include <linux/iio/trigger_consumer.h>
  41 #include <linux/iio/triggered_buffer.h>
  42
  43 /* This will be the driver name the kernel reports */
  44 #define DRIVER_NAME "vf610-adc"
  45
  46 /* Vybrid/IMX ADC registers */
  47 #define VF610_REG_ADC_HC0               0x00
  48 #define VF610_REG_ADC_HC1               0x04
  49 #define VF610_REG_ADC_HS                0x08
  50 #define VF610_REG_ADC_R0                0x0c
  51 #define VF610_REG_ADC_R1                0x10
  52 #define VF610_REG_ADC_CFG               0x14
  53 #define VF610_REG_ADC_GC                0x18
  54 #define VF610_REG_ADC_GS                0x1c
  55 #define VF610_REG_ADC_CV                0x20
  56 #define VF610_REG_ADC_OFS               0x24
  57 #define VF610_REG_ADC_CAL               0x28
  58 #define VF610_REG_ADC_PCTL              0x30
  59
  60 /* Configuration register field define */
  61 #define VF610_ADC_MODE_BIT8             0x00
  62 #define VF610_ADC_MODE_BIT10            0x04
  63 #define VF610_ADC_MODE_BIT12            0x08
  64 #define VF610_ADC_MODE_MASK             0x0c
  65 #define VF610_ADC_BUSCLK2_SEL           0x01
  66 #define VF610_ADC_ALTCLK_SEL            0x02
  67 #define VF610_ADC_ADACK_SEL             0x03
  68 #define VF610_ADC_ADCCLK_MASK           0x03
  69 #define VF610_ADC_CLK_DIV2              0x20
  70 #define VF610_ADC_CLK_DIV4              0x40
  71 #define VF610_ADC_CLK_DIV8              0x60
  72 #define VF610_ADC_CLK_MASK              0x60
  73 #define VF610_ADC_ADLSMP_LONG           0x10
  74 #define VF610_ADC_ADSTS_SHORT   0x100
  75 #define VF610_ADC_ADSTS_NORMAL  0x200
  76 #define VF610_ADC_ADSTS_LONG    0x300
  77 #define VF610_ADC_ADSTS_MASK            0x300
  78 #define VF610_ADC_ADLPC_EN              0x80
  79 #define VF610_ADC_ADHSC_EN              0x400
  80 #define VF610_ADC_REFSEL_VALT           0x800
  81 #define VF610_ADC_REFSEL_VBG            0x1000
  82 #define VF610_ADC_ADTRG_HARD            0x2000
  83 #define VF610_ADC_AVGS_8                0x4000
  84 #define VF610_ADC_AVGS_16               0x8000
  85 #define VF610_ADC_AVGS_32               0xC000
  86 #define VF610_ADC_AVGS_MASK             0xC000
  87 #define VF610_ADC_OVWREN                0x10000
  88
  89 /* General control register field define */
  90 #define VF610_ADC_ADACKEN               0x1
  91 #define VF610_ADC_DMAEN                 0x2
  92 #define VF610_ADC_ACREN                 0x4
  93 #define VF610_ADC_ACFGT                 0x8
  94 #define VF610_ADC_ACFE                  0x10
  95 #define VF610_ADC_AVGEN                 0x20
  96 #define VF610_ADC_ADCON                 0x40
  97 #define VF610_ADC_CAL                   0x80
  98
  99 /* Other field define */
 100 #define VF610_ADC_ADCHC(x)              ((x) & 0x1F)
 101 #define VF610_ADC_AIEN                  (0x1 << 7)
 102 #define VF610_ADC_CONV_DISABLE          0x1F
 103 #define VF610_ADC_HS_COCO0              0x1
 104 #define VF610_ADC_CALF                  0x2
 105 #define VF610_ADC_TIMEOUT               msecs_to_jiffies(100)
 106
 107 #define DEFAULT_SAMPLE_TIME             1000
 108
 109 /* V at 25°C of 696 mV */
 110 #define VF610_VTEMP25_3V0               950
 111 /* V at 25°C of 699 mV */
 112 #define VF610_VTEMP25_3V3               867
 113 /* Typical sensor slope coefficient at all temperatures */
 114 #define VF610_TEMP_SLOPE_COEFF          1840
 115
 116 enum clk_sel {
 117         VF610_ADCIOC_BUSCLK_SET,
 118         VF610_ADCIOC_ALTCLK_SET,
 119         VF610_ADCIOC_ADACK_SET,
 120 };
 121
 122 enum vol_ref {
 123         VF610_ADCIOC_VR_VREF_SET,
 124         VF610_ADCIOC_VR_VALT_SET,
 125         VF610_ADCIOC_VR_VBG_SET,
 126 };
 127
 128 enum average_sel {
 129         VF610_ADC_SAMPLE_1,
 130         VF610_ADC_SAMPLE_4,
 131         VF610_ADC_SAMPLE_8,
 132         VF610_ADC_SAMPLE_16,
 133         VF610_ADC_SAMPLE_32,
 134 };
 135
 136 enum conversion_mode_sel {
 137         VF610_ADC_CONV_NORMAL,
 138         VF610_ADC_CONV_HIGH_SPEED,
 139         VF610_ADC_CONV_LOW_POWER,
 140 };
 141
 142 enum lst_adder_sel {
 143         VF610_ADCK_CYCLES_3,
 144         VF610_ADCK_CYCLES_5,
 145         VF610_ADCK_CYCLES_7,
 146         VF610_ADCK_CYCLES_9,
 147         VF610_ADCK_CYCLES_13,
 148         VF610_ADCK_CYCLES_17,
 149         VF610_ADCK_CYCLES_21,
 150         VF610_ADCK_CYCLES_25,
 151 };
 152
 153 struct vf610_adc_feature {
 154         enum clk_sel    clk_sel;
 155         enum vol_ref    vol_ref;
 156         enum conversion_mode_sel conv_mode;
 157
 158         int     clk_div;
 159         int     sample_rate;
 160         int     res_mode;
 161         u32 lst_adder_index;
 162         u32 default_sample_time;
 163
 164         bool    calibration;
 165         bool    ovwren;
 166 };
 167
 168 struct vf610_adc {
 169         struct device *dev;
 170         void __iomem *regs;
 171         struct clk *clk;
 172
 173         u32 vref_uv;
 174         u32 value;
 175         struct regulator *vref;
 176
 177         u32 max_adck_rate[3];
 178         struct vf610_adc_feature adc_feature;
 179
 180         u32 sample_freq_avail[5];
 181
 182         struct completion completion;
 183         /* Ensure the timestamp is naturally aligned */
 184         struct {
 185                 u16 chan;
 186                 s64 timestamp __aligned(8);
 187         } scan;
 188 };
 189
 190 static const u32 vf610_hw_avgs[] = { 1, 4, 8, 16, 32 };
 191 static const u32 vf610_lst_adder[] = { 3, 5, 7, 9, 13, 17, 21, 25 };
 192
 193 static inline void vf610_adc_calculate_rates(struct vf610_adc *info)
 194 {
 195         struct vf610_adc_feature *adc_feature = &info->adc_feature;
 196         unsigned long adck_rate, ipg_rate = clk_get_rate(info->clk);
 197         u32 adck_period, lst_addr_min;
 198         int divisor, i;
 199
 200         adck_rate = info->max_adck_rate[adc_feature->conv_mode];
 201
 202         if (adck_rate) {
 203                 /* calculate clk divider which is within specification */
 204                 divisor = ipg_rate / adck_rate;
 205                 adc_feature->clk_div = 1 << fls(divisor + 1);
 206         } else {
 207                 /* fall-back value using a safe divisor */
 208                 adc_feature->clk_div = 8;
 209         }
 210
 211         adck_rate = ipg_rate / adc_feature->clk_div;
 212
 213         /*
 214          * Determine the long sample time adder value to be used based
 215          * on the default minimum sample time provided.
 216          */
 217         adck_period = NSEC_PER_SEC / adck_rate;
 218         lst_addr_min = adc_feature->default_sample_time / adck_period;
 219         for (i = 0; i < ARRAY_SIZE(vf610_lst_adder); i++) {
 220                 if (vf610_lst_adder[i] > lst_addr_min) {
 221                         adc_feature->lst_adder_index = i;
 222                         break;
 223                 }
 224         }
 225
 226         /*
 227          * Calculate ADC sample frequencies
 228          * Sample time unit is ADCK cycles. ADCK clk source is ipg clock,
 229          * which is the same as bus clock.
 230          *
 231          * ADC conversion time = SFCAdder + AverageNum x (BCT + LSTAdder)
 232          * SFCAdder: fixed to 6 ADCK cycles
 233          * AverageNum: 1, 4, 8, 16, 32 samples for hardware average.
 234          * BCT (Base Conversion Time): fixed to 25 ADCK cycles for 12 bit mode
 235          * LSTAdder(Long Sample Time): 3, 5, 7, 9, 13, 17, 21, 25 ADCK cycles
 236          */
 237         for (i = 0; i < ARRAY_SIZE(vf610_hw_avgs); i++)
 238                 info->sample_freq_avail[i] =
 239                         adck_rate / (6 + vf610_hw_avgs[i] *
 240                          (25 + vf610_lst_adder[adc_feature->lst_adder_index]));
 241 }
 242
 243 static inline void vf610_adc_cfg_init(struct vf610_adc *info)
 244 {
 245         struct vf610_adc_feature *adc_feature = &info->adc_feature;
 246
 247         /* set default Configuration for ADC controller */
 248         adc_feature->clk_sel = VF610_ADCIOC_BUSCLK_SET;
 249         adc_feature->vol_ref = VF610_ADCIOC_VR_VREF_SET;
 250
 251         adc_feature->calibration = true;
 252         adc_feature->ovwren = true;
 253
 254         adc_feature->res_mode = 12;
 255         adc_feature->sample_rate = 1;
 256
 257         adc_feature->conv_mode = VF610_ADC_CONV_LOW_POWER;
 258
 259         vf610_adc_calculate_rates(info);
 260 }
 261
 262 static void vf610_adc_cfg_post_set(struct vf610_adc *info)
 263 {
 264         struct vf610_adc_feature *adc_feature = &info->adc_feature;
 265         int cfg_data = 0;
 266         int gc_data = 0;
 267
 268         switch (adc_feature->clk_sel) {
 269         case VF610_ADCIOC_ALTCLK_SET:
 270                 cfg_data |= VF610_ADC_ALTCLK_SEL;
 271                 break;
 272         case VF610_ADCIOC_ADACK_SET:
 273                 cfg_data |= VF610_ADC_ADACK_SEL;
 274                 break;
 275         default:
 276                 break;
 277         }
 278
 279         /* low power set for calibration */
 280         cfg_data |= VF610_ADC_ADLPC_EN;
 281
 282         /* enable high speed for calibration */
 283         cfg_data |= VF610_ADC_ADHSC_EN;
 284
 285         /* voltage reference */
 286         switch (adc_feature->vol_ref) {
 287         case VF610_ADCIOC_VR_VREF_SET:
 288                 break;
 289         case VF610_ADCIOC_VR_VALT_SET:
 290                 cfg_data |= VF610_ADC_REFSEL_VALT;
 291                 break;
 292         case VF610_ADCIOC_VR_VBG_SET:
 293                 cfg_data |= VF610_ADC_REFSEL_VBG;
 294                 break;
 295         default:
 296                 dev_err(info->dev, "error voltage reference\n");
 297         }
 298
 299         /* data overwrite enable */
 300         if (adc_feature->ovwren)
 301                 cfg_data |= VF610_ADC_OVWREN;
 302
 303         writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
 304         writel(gc_data, info->regs + VF610_REG_ADC_GC);
 305 }
 306
 307 static void vf610_adc_calibration(struct vf610_adc *info)
 308 {
 309         int adc_gc, hc_cfg;
 310
 311         if (!info->adc_feature.calibration)
 312                 return;
 313
 314         /* enable calibration interrupt */
 315         hc_cfg = VF610_ADC_AIEN | VF610_ADC_CONV_DISABLE;
 316         writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
 317
 318         adc_gc = readl(info->regs + VF610_REG_ADC_GC);
 319         writel(adc_gc | VF610_ADC_CAL, info->regs + VF610_REG_ADC_GC);
 320
 321         if (!wait_for_completion_timeout(&info->completion, VF610_ADC_TIMEOUT))
 322                 dev_err(info->dev, "Timeout for adc calibration\n");
 323
 324         adc_gc = readl(info->regs + VF610_REG_ADC_GS);
 325         if (adc_gc & VF610_ADC_CALF)
 326                 dev_err(info->dev, "ADC calibration failed\n");
 327
 328         info->adc_feature.calibration = false;
 329 }
 330
 331 static void vf610_adc_cfg_set(struct vf610_adc *info)
 332 {
 333         struct vf610_adc_feature *adc_feature = &(info->adc_feature);
 334         int cfg_data;
 335
 336         cfg_data = readl(info->regs + VF610_REG_ADC_CFG);
 337
 338         cfg_data &= ~VF610_ADC_ADLPC_EN;
 339         if (adc_feature->conv_mode == VF610_ADC_CONV_LOW_POWER)
 340                 cfg_data |= VF610_ADC_ADLPC_EN;
 341
 342         cfg_data &= ~VF610_ADC_ADHSC_EN;
 343         if (adc_feature->conv_mode == VF610_ADC_CONV_HIGH_SPEED)
 344                 cfg_data |= VF610_ADC_ADHSC_EN;
 345
 346         writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
 347 }
 348
 349 static void vf610_adc_sample_set(struct vf610_adc *info)
 350 {
 351         struct vf610_adc_feature *adc_feature = &(info->adc_feature);
 352         int cfg_data, gc_data;
 353
 354         cfg_data = readl(info->regs + VF610_REG_ADC_CFG);
 355         gc_data = readl(info->regs + VF610_REG_ADC_GC);
 356
 357         /* resolution mode */
 358         cfg_data &= ~VF610_ADC_MODE_MASK;
 359         switch (adc_feature->res_mode) {
 360         case 8:
 361                 cfg_data |= VF610_ADC_MODE_BIT8;
 362                 break;
 363         case 10:
 364                 cfg_data |= VF610_ADC_MODE_BIT10;
 365                 break;
 366         case 12:
 367                 cfg_data |= VF610_ADC_MODE_BIT12;
 368                 break;
 369         default:
 370                 dev_err(info->dev, "error resolution mode\n");
 371                 break;
 372         }
 373
 374         /* clock select and clock divider */
 375         cfg_data &= ~(VF610_ADC_CLK_MASK | VF610_ADC_ADCCLK_MASK);
 376         switch (adc_feature->clk_div) {
 377         case 1:
 378                 break;
 379         case 2:
 380                 cfg_data |= VF610_ADC_CLK_DIV2;
 381                 break;
 382         case 4:
 383                 cfg_data |= VF610_ADC_CLK_DIV4;
 384                 break;
 385         case 8:
 386                 cfg_data |= VF610_ADC_CLK_DIV8;
 387                 break;
 388         case 16:
 389                 switch (adc_feature->clk_sel) {
 390                 case VF610_ADCIOC_BUSCLK_SET:
 391                         cfg_data |= VF610_ADC_BUSCLK2_SEL | VF610_ADC_CLK_DIV8;
 392                         break;
 393                 default:
 394                         dev_err(info->dev, "error clk divider\n");
 395                         break;
 396                 }
 397                 break;
 398         }
 399
 400         /*
 401          * Set ADLSMP and ADSTS based on the Long Sample Time Adder value
 402          * determined.
 403          */
 404         switch (adc_feature->lst_adder_index) {
 405         case VF610_ADCK_CYCLES_3:
 406                 break;
 407         case VF610_ADCK_CYCLES_5:
 408                 cfg_data |= VF610_ADC_ADSTS_SHORT;
 409                 break;
 410         case VF610_ADCK_CYCLES_7:
 411                 cfg_data |= VF610_ADC_ADSTS_NORMAL;
 412                 break;
 413         case VF610_ADCK_CYCLES_9:
 414                 cfg_data |= VF610_ADC_ADSTS_LONG;
 415                 break;
 416         case VF610_ADCK_CYCLES_13:
 417                 cfg_data |= VF610_ADC_ADLSMP_LONG;
 418                 break;
 419         case VF610_ADCK_CYCLES_17:
 420                 cfg_data |= VF610_ADC_ADLSMP_LONG;
 421                 cfg_data |= VF610_ADC_ADSTS_SHORT;
 422                 break;
 423         case VF610_ADCK_CYCLES_21:
 424                 cfg_data |= VF610_ADC_ADLSMP_LONG;
 425                 cfg_data |= VF610_ADC_ADSTS_NORMAL;
 426                 break;
 427         case VF610_ADCK_CYCLES_25:
 428                 cfg_data |= VF610_ADC_ADLSMP_LONG;
 429                 cfg_data |= VF610_ADC_ADSTS_NORMAL;
 430                 break;
 431         default:
 432                 dev_err(info->dev, "error in sample time select\n");
 433         }
 434
 435         /* update hardware average selection */
 436         cfg_data &= ~VF610_ADC_AVGS_MASK;
 437         gc_data &= ~VF610_ADC_AVGEN;
 438         switch (adc_feature->sample_rate) {
 439         case VF610_ADC_SAMPLE_1:
 440                 break;
 441         case VF610_ADC_SAMPLE_4:
 442                 gc_data |= VF610_ADC_AVGEN;
 443                 break;
 444         case VF610_ADC_SAMPLE_8:
 445                 gc_data |= VF610_ADC_AVGEN;
 446                 cfg_data |= VF610_ADC_AVGS_8;
 447                 break;
 448         case VF610_ADC_SAMPLE_16:
 449                 gc_data |= VF610_ADC_AVGEN;
 450                 cfg_data |= VF610_ADC_AVGS_16;
 451                 break;
 452         case VF610_ADC_SAMPLE_32:
 453                 gc_data |= VF610_ADC_AVGEN;
 454                 cfg_data |= VF610_ADC_AVGS_32;
 455                 break;
 456         default:
 457                 dev_err(info->dev,
 458                         "error hardware sample average select\n");
 459         }
 460
 461         writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
 462         writel(gc_data, info->regs + VF610_REG_ADC_GC);
 463 }
 464
 465 static void vf610_adc_hw_init(struct vf610_adc *info)
 466 {
 467         /* CFG: Feature set */
 468         vf610_adc_cfg_post_set(info);
 469         vf610_adc_sample_set(info);
 470
 471         /* adc calibration */
 472         vf610_adc_calibration(info);
 473
 474         /* CFG: power and speed set */
 475         vf610_adc_cfg_set(info);
 476 }
 477
 478 static int vf610_set_conversion_mode(struct iio_dev *indio_dev,
 479                                      const struct iio_chan_spec *chan,
 480                                      unsigned int mode)
 481 {
 482         struct vf610_adc *info = iio_priv(indio_dev);
 483
 484         mutex_lock(&indio_dev->mlock);
 485         info->adc_feature.conv_mode = mode;
 486         vf610_adc_calculate_rates(info);
 487         vf610_adc_hw_init(info);
 488         mutex_unlock(&indio_dev->mlock);
 489
 490         return 0;
 491 }
 492
 493 static int vf610_get_conversion_mode(struct iio_dev *indio_dev,
 494                                      const struct iio_chan_spec *chan)
 495 {
 496         struct vf610_adc *info = iio_priv(indio_dev);
 497
 498         return info->adc_feature.conv_mode;
 499 }
 500
 501 static const char * const vf610_conv_modes[] = { "normal", "high-speed",
 502                                                  "low-power" };
 503
 504 static const struct iio_enum vf610_conversion_mode = {
 505         .items = vf610_conv_modes,
 506         .num_items = ARRAY_SIZE(vf610_conv_modes),
 507         .get = vf610_get_conversion_mode,
 508         .set = vf610_set_conversion_mode,
 509 };
 510
 511 static const struct iio_chan_spec_ext_info vf610_ext_info[] = {
 512         IIO_ENUM("conversion_mode", IIO_SHARED_BY_DIR, &vf610_conversion_mode),
 513         {},
 514 };
 515
 516 #define VF610_ADC_CHAN(_idx, _chan_type) {                      \
 517         .type = (_chan_type),                                   \
 518         .indexed = 1,                                           \
 519         .channel = (_idx),                                      \
 520         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),           \
 521         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |  \
 522                                 BIT(IIO_CHAN_INFO_SAMP_FREQ),   \
 523         .ext_info = vf610_ext_info,                             \
 524         .scan_index = (_idx),                   \
 525         .scan_type = {                                  \
 526                 .sign = 'u',                            \
 527                 .realbits = 12,                         \
 528                 .storagebits = 16,                      \
 529         },                                              \
 530 }
 531
 532 #define VF610_ADC_TEMPERATURE_CHAN(_idx, _chan_type) {  \
 533         .type = (_chan_type),   \
 534         .channel = (_idx),              \
 535         .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),     \
 536         .scan_index = (_idx),                                   \
 537         .scan_type = {                                          \
 538                 .sign = 'u',                                    \
 539                 .realbits = 12,                                 \
 540                 .storagebits = 16,                              \
 541         },                                                      \
 542 }
 543
 544 static const struct iio_chan_spec vf610_adc_iio_channels[] = {
 545         VF610_ADC_CHAN(0, IIO_VOLTAGE),
 546         VF610_ADC_CHAN(1, IIO_VOLTAGE),
 547         VF610_ADC_CHAN(2, IIO_VOLTAGE),
 548         VF610_ADC_CHAN(3, IIO_VOLTAGE),
 549         VF610_ADC_CHAN(4, IIO_VOLTAGE),
 550         VF610_ADC_CHAN(5, IIO_VOLTAGE),
 551         VF610_ADC_CHAN(6, IIO_VOLTAGE),
 552         VF610_ADC_CHAN(7, IIO_VOLTAGE),
 553         VF610_ADC_CHAN(8, IIO_VOLTAGE),
 554         VF610_ADC_CHAN(9, IIO_VOLTAGE),
 555         VF610_ADC_CHAN(10, IIO_VOLTAGE),
 556         VF610_ADC_CHAN(11, IIO_VOLTAGE),
 557         VF610_ADC_CHAN(12, IIO_VOLTAGE),
 558         VF610_ADC_CHAN(13, IIO_VOLTAGE),
 559         VF610_ADC_CHAN(14, IIO_VOLTAGE),
 560         VF610_ADC_CHAN(15, IIO_VOLTAGE),
 561         VF610_ADC_TEMPERATURE_CHAN(26, IIO_TEMP),
 562         IIO_CHAN_SOFT_TIMESTAMP(32),
 563         /* sentinel */
 564 };
 565
 566 static int vf610_adc_read_data(struct vf610_adc *info)
 567 {
 568         int result;
 569
 570         result = readl(info->regs + VF610_REG_ADC_R0);
 571
 572         switch (info->adc_feature.res_mode) {
 573         case 8:
 574                 result &= 0xFF;
 575                 break;
 576         case 10:
 577                 result &= 0x3FF;
 578                 break;
 579         case 12:
 580                 result &= 0xFFF;
 581                 break;
 582         default:
 583                 break;
 584         }
 585
 586         return result;
 587 }
 588
 589 static irqreturn_t vf610_adc_isr(int irq, void *dev_id)
 590 {
 591         struct iio_dev *indio_dev = dev_id;
 592         struct vf610_adc *info = iio_priv(indio_dev);
 593         int coco;
 594
 595         coco = readl(info->regs + VF610_REG_ADC_HS);
 596         if (coco & VF610_ADC_HS_COCO0) {
 597                 info->value = vf610_adc_read_data(info);
 598                 if (iio_buffer_enabled(indio_dev)) {
 599                         info->scan.chan = info->value;
 600                         iio_push_to_buffers_with_timestamp(indio_dev,
 601                                         &info->scan,
 602                                         iio_get_time_ns(indio_dev));
 603                         iio_trigger_notify_done(indio_dev->trig);
 604                 } else
 605                         complete(&info->completion);
 606         }
 607
 608         return IRQ_HANDLED;
 609 }
 610
 611 static ssize_t vf610_show_samp_freq_avail(struct device *dev,
 612                                 struct device_attribute *attr, char *buf)
 613 {
 614         struct vf610_adc *info = iio_priv(dev_to_iio_dev(dev));
 615         size_t len = 0;
 616         int i;
 617
 618         for (i = 0; i < ARRAY_SIZE(info->sample_freq_avail); i++)
 619                 len += scnprintf(buf + len, PAGE_SIZE - len,
 620                         "%u ", info->sample_freq_avail[i]);
 621
 622         /* replace trailing space by newline */
 623         buf[len - 1] = '\n';
 624
 625         return len;
 626 }
 627
 628 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(vf610_show_samp_freq_avail);
 629
 630 static struct attribute *vf610_attributes[] = {
 631         &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
 632         NULL
 633 };
 634
 635 static const struct attribute_group vf610_attribute_group = {
 636         .attrs = vf610_attributes,
 637 };
 638
 639 static int vf610_read_raw(struct iio_dev *indio_dev,
 640                         struct iio_chan_spec const *chan,
 641                         int *val,
 642                         int *val2,
 643                         long mask)
 644 {
 645         struct vf610_adc *info = iio_priv(indio_dev);
 646         unsigned int hc_cfg;
 647         long ret;
 648
 649         switch (mask) {
 650         case IIO_CHAN_INFO_RAW:
 651         case IIO_CHAN_INFO_PROCESSED:
 652                 mutex_lock(&indio_dev->mlock);
 653                 if (iio_buffer_enabled(indio_dev)) {
 654                         mutex_unlock(&indio_dev->mlock);
 655                         return -EBUSY;
 656                 }
 657
 658                 reinit_completion(&info->completion);
 659                 hc_cfg = VF610_ADC_ADCHC(chan->channel);
 660                 hc_cfg |= VF610_ADC_AIEN;
 661                 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
 662                 ret = wait_for_completion_interruptible_timeout
 663                                 (&info->completion, VF610_ADC_TIMEOUT);
 664                 if (ret == 0) {
 665                         mutex_unlock(&indio_dev->mlock);
 666                         return -ETIMEDOUT;
 667                 }
 668                 if (ret < 0) {
 669                         mutex_unlock(&indio_dev->mlock);
 670                         return ret;
 671                 }
 672
 673                 switch (chan->type) {
 674                 case IIO_VOLTAGE:
 675                         *val = info->value;
 676                         break;
 677                 case IIO_TEMP:
 678                         /*
 679                          * Calculate in degree Celsius times 1000
 680                          * Using the typical sensor slope of 1.84 mV/°C
 681                          * and VREFH_ADC at 3.3V, V at 25°C of 699 mV
 682                          */
 683                         *val = 25000 - ((int)info->value - VF610_VTEMP25_3V3) *
 684                                         1000000 / VF610_TEMP_SLOPE_COEFF;
 685
 686                         break;
 687                 default:
 688                         mutex_unlock(&indio_dev->mlock);
 689                         return -EINVAL;
 690                 }
 691
 692                 mutex_unlock(&indio_dev->mlock);
 693                 return IIO_VAL_INT;
 694
 695         case IIO_CHAN_INFO_SCALE:
 696                 *val = info->vref_uv / 1000;
 697                 *val2 = info->adc_feature.res_mode;
 698                 return IIO_VAL_FRACTIONAL_LOG2;
 699
 700         case IIO_CHAN_INFO_SAMP_FREQ:
 701                 *val = info->sample_freq_avail[info->adc_feature.sample_rate];
 702                 *val2 = 0;
 703                 return IIO_VAL_INT;
 704
 705         default:
 706                 break;
 707         }
 708
 709         return -EINVAL;
 710 }
 711
 712 static int vf610_write_raw(struct iio_dev *indio_dev,
 713                         struct iio_chan_spec const *chan,
 714                         int val,
 715                         int val2,
 716                         long mask)
 717 {
 718         struct vf610_adc *info = iio_priv(indio_dev);
 719         int i;
 720
 721         switch (mask) {
 722         case IIO_CHAN_INFO_SAMP_FREQ:
 723                 for (i = 0;
 724                         i < ARRAY_SIZE(info->sample_freq_avail);
 725                         i++)
 726                         if (val == info->sample_freq_avail[i]) {
 727                                 info->adc_feature.sample_rate = i;
 728                                 vf610_adc_sample_set(info);
 729                                 return 0;
 730                         }
 731                 break;
 732
 733         default:
 734                 break;
 735         }
 736
 737         return -EINVAL;
 738 }
 739
 740 static int vf610_adc_buffer_postenable(struct iio_dev *indio_dev)
 741 {
 742         struct vf610_adc *info = iio_priv(indio_dev);
 743         unsigned int channel;
 744         int ret;
 745         int val;
 746
 747         ret = iio_triggered_buffer_postenable(indio_dev);
 748         if (ret)
 749                 return ret;
 750
 751         val = readl(info->regs + VF610_REG_ADC_GC);
 752         val |= VF610_ADC_ADCON;
 753         writel(val, info->regs + VF610_REG_ADC_GC);
 754
 755         channel = find_first_bit(indio_dev->active_scan_mask,
 756                                                 indio_dev->masklength);
 757
 758         val = VF610_ADC_ADCHC(channel);
 759         val |= VF610_ADC_AIEN;
 760
 761         writel(val, info->regs + VF610_REG_ADC_HC0);
 762
 763         return 0;
 764 }
 765
 766 static int vf610_adc_buffer_predisable(struct iio_dev *indio_dev)
 767 {
 768         struct vf610_adc *info = iio_priv(indio_dev);
 769         unsigned int hc_cfg = 0;
 770         int val;
 771
 772         val = readl(info->regs + VF610_REG_ADC_GC);
 773         val &= ~VF610_ADC_ADCON;
 774         writel(val, info->regs + VF610_REG_ADC_GC);
 775
 776         hc_cfg |= VF610_ADC_CONV_DISABLE;
 777         hc_cfg &= ~VF610_ADC_AIEN;
 778
 779         writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
 780
 781         return iio_triggered_buffer_predisable(indio_dev);
 782 }
 783
 784 static const struct iio_buffer_setup_ops iio_triggered_buffer_setup_ops = {
 785         .postenable = &vf610_adc_buffer_postenable,
 786         .predisable = &vf610_adc_buffer_predisable,
 787         .validate_scan_mask = &iio_validate_scan_mask_onehot,
 788 };
 789
 790 static int vf610_adc_reg_access(struct iio_dev *indio_dev,
 791                         unsigned reg, unsigned writeval,
 792                         unsigned *readval)
 793 {
 794         struct vf610_adc *info = iio_priv(indio_dev);
 795
 796         if ((readval == NULL) ||
 797                 ((reg % 4) || (reg > VF610_REG_ADC_PCTL)))
 798                 return -EINVAL;
 799
 800         *readval = readl(info->regs + reg);
 801
 802         return 0;
 803 }
 804
 805 static const struct iio_info vf610_adc_iio_info = {
 806         .read_raw = &vf610_read_raw,
 807         .write_raw = &vf610_write_raw,
 808         .debugfs_reg_access = &vf610_adc_reg_access,
 809         .attrs = &vf610_attribute_group,
 810 };
 811
 812 static const struct of_device_id vf610_adc_match[] = {
 813         { .compatible = "fsl,vf610-adc", },
 814         { /* sentinel */ }
 815 };
 816 MODULE_DEVICE_TABLE(of, vf610_adc_match);
 817
 818 static int vf610_adc_probe(struct platform_device *pdev)
 819 {
 820         struct vf610_adc *info;
 821         struct iio_dev *indio_dev;
 822         struct resource *mem;
 823         int irq;
 824         int ret;
 825
 826         indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct vf610_adc));
 827         if (!indio_dev) {
 828                 dev_err(&pdev->dev, "Failed allocating iio device\n");
 829                 return -ENOMEM;
 830         }
 831
 832         info = iio_priv(indio_dev);
 833         info->dev = &pdev->dev;
 834
 835         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 836         info->regs = devm_ioremap_resource(&pdev->dev, mem);
 837         if (IS_ERR(info->regs))
 838                 return PTR_ERR(info->regs);
 839
 840         irq = platform_get_irq(pdev, 0);
 841         if (irq < 0) {
 842                 dev_err(&pdev->dev, "no irq resource?\n");
 843                 return irq;
 844         }
 845
 846         ret = devm_request_irq(info->dev, irq,
 847                                 vf610_adc_isr, 0,
 848                                 dev_name(&pdev->dev), indio_dev);
 849         if (ret < 0) {
 850                 dev_err(&pdev->dev, "failed requesting irq, irq = %d\n", irq);
 851                 return ret;
 852         }
 853
 854         info->clk = devm_clk_get(&pdev->dev, "adc");
 855         if (IS_ERR(info->clk)) {
 856                 dev_err(&pdev->dev, "failed getting clock, err = %ld\n",
 857                                                 PTR_ERR(info->clk));
 858                 return PTR_ERR(info->clk);
 859         }
 860
 861         info->vref = devm_regulator_get(&pdev->dev, "vref");
 862         if (IS_ERR(info->vref))
 863                 return PTR_ERR(info->vref);
 864
 865         ret = regulator_enable(info->vref);
 866         if (ret)
 867                 return ret;
 868
 869         info->vref_uv = regulator_get_voltage(info->vref);
 870
 871         of_property_read_u32_array(pdev->dev.of_node, "fsl,adck-max-frequency",
 872                         info->max_adck_rate, 3);
 873
 874         ret = of_property_read_u32(pdev->dev.of_node, "min-sample-time",
 875                         &info->adc_feature.default_sample_time);
 876         if (ret)
 877                 info->adc_feature.default_sample_time = DEFAULT_SAMPLE_TIME;
 878
 879         platform_set_drvdata(pdev, indio_dev);
 880
 881         init_completion(&info->completion);
 882
 883         indio_dev->name = dev_name(&pdev->dev);
 884         indio_dev->dev.parent = &pdev->dev;
 885         indio_dev->dev.of_node = pdev->dev.of_node;
 886         indio_dev->info = &vf610_adc_iio_info;
 887         indio_dev->modes = INDIO_DIRECT_MODE;
 888         indio_dev->channels = vf610_adc_iio_channels;
 889         indio_dev->num_channels = ARRAY_SIZE(vf610_adc_iio_channels);
 890
 891         ret = clk_prepare_enable(info->clk);
 892         if (ret) {
 893                 dev_err(&pdev->dev,
 894                         "Could not prepare or enable the clock.\n");
 895                 goto error_adc_clk_enable;
 896         }
 897
 898         vf610_adc_cfg_init(info);
 899         vf610_adc_hw_init(info);
 900
 901         ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
 902                                         NULL, &iio_triggered_buffer_setup_ops);
 903         if (ret < 0) {
 904                 dev_err(&pdev->dev, "Couldn't initialise the buffer\n");
 905                 goto error_iio_device_register;
 906         }
 907
 908         ret = iio_device_register(indio_dev);
 909         if (ret) {
 910                 dev_err(&pdev->dev, "Couldn't register the device.\n");
 911                 goto error_adc_buffer_init;
 912         }
 913
 914         return 0;
 915
 916 error_adc_buffer_init:
 917         iio_triggered_buffer_cleanup(indio_dev);
 918 error_iio_device_register:
 919         clk_disable_unprepare(info->clk);
 920 error_adc_clk_enable:
 921         regulator_disable(info->vref);
 922
 923         return ret;
 924 }
 925
 926 static int vf610_adc_remove(struct platform_device *pdev)
 927 {
 928         struct iio_dev *indio_dev = platform_get_drvdata(pdev);
 929         struct vf610_adc *info = iio_priv(indio_dev);
 930
 931         iio_device_unregister(indio_dev);
 932         iio_triggered_buffer_cleanup(indio_dev);
 933         regulator_disable(info->vref);
 934         clk_disable_unprepare(info->clk);
 935
 936         return 0;
 937 }
 938
 939 #ifdef CONFIG_PM_SLEEP
 940 static int vf610_adc_suspend(struct device *dev)
 941 {
 942         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 943         struct vf610_adc *info = iio_priv(indio_dev);
 944         int hc_cfg;
 945
 946         /* ADC controller enters to stop mode */
 947         hc_cfg = readl(info->regs + VF610_REG_ADC_HC0);
 948         hc_cfg |= VF610_ADC_CONV_DISABLE;
 949         writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
 950
 951         clk_disable_unprepare(info->clk);
 952         regulator_disable(info->vref);
 953
 954         return 0;
 955 }
 956
 957 static int vf610_adc_resume(struct device *dev)
 958 {
 959         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 960         struct vf610_adc *info = iio_priv(indio_dev);
 961         int ret;
 962
 963         ret = regulator_enable(info->vref);
 964         if (ret)
 965                 return ret;
 966
 967         ret = clk_prepare_enable(info->clk);
 968         if (ret)
 969                 goto disable_reg;
 970
 971         vf610_adc_hw_init(info);
 972
 973         return 0;
 974
 975 disable_reg:
 976         regulator_disable(info->vref);
 977         return ret;
 978 }
 979 #endif
 980
 981 static SIMPLE_DEV_PM_OPS(vf610_adc_pm_ops, vf610_adc_suspend, vf610_adc_resume);
 982
 983 static struct platform_driver vf610_adc_driver = {
 984         .probe          = vf610_adc_probe,
 985         .remove         = vf610_adc_remove,
 986         .driver         = {
 987                 .name   = DRIVER_NAME,
 988                 .of_match_table = vf610_adc_match,
 989                 .pm     = &vf610_adc_pm_ops,
 990         },
 991 };
 992
 993 module_platform_driver(vf610_adc_driver);
 994
 995 MODULE_AUTHOR("Fugang Duan <B38611@freescale.com>");
 996 MODULE_DESCRIPTION("Freescale VF610 ADC driver");
 997 MODULE_LICENSE("GPL v2");