2 * IIO driver for the ACCES 104-QUAD-8
3 * Copyright (C) 2016 William Breathitt Gray
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License, version 2, as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * This driver supports the ACCES 104-QUAD-8 and ACCES 104-QUAD-4.
16 #include <linux/bitops.h>
17 #include <linux/device.h>
18 #include <linux/errno.h>
19 #include <linux/iio/iio.h>
20 #include <linux/iio/types.h>
22 #include <linux/ioport.h>
23 #include <linux/isa.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/types.h>
29 #define QUAD8_EXTENT 32
31 static unsigned int base[max_num_isa_dev(QUAD8_EXTENT)];
32 static unsigned int num_quad8;
33 module_param_array(base, uint, &num_quad8, 0);
34 MODULE_PARM_DESC(base, "ACCES 104-QUAD-8 base addresses");
36 #define QUAD8_NUM_COUNTERS 8
39 * struct quad8_iio - IIO device private data structure
40 * @preset: array of preset values
41 * @count_mode: array of count mode configurations
42 * @quadrature_mode: array of quadrature mode configurations
43 * @quadrature_scale: array of quadrature mode scale configurations
44 * @ab_enable: array of A and B inputs enable configurations
45 * @preset_enable: array of set_to_preset_on_index attribute configurations
46 * @synchronous_mode: array of index function synchronous mode configurations
47 * @index_polarity: array of index function polarity configurations
48 * @base: base port address of the IIO device
51 unsigned int preset[QUAD8_NUM_COUNTERS];
52 unsigned int count_mode[QUAD8_NUM_COUNTERS];
53 unsigned int quadrature_mode[QUAD8_NUM_COUNTERS];
54 unsigned int quadrature_scale[QUAD8_NUM_COUNTERS];
55 unsigned int ab_enable[QUAD8_NUM_COUNTERS];
56 unsigned int preset_enable[QUAD8_NUM_COUNTERS];
57 unsigned int synchronous_mode[QUAD8_NUM_COUNTERS];
58 unsigned int index_polarity[QUAD8_NUM_COUNTERS];
62 #define QUAD8_REG_CHAN_OP 0x11
63 #define QUAD8_REG_INDEX_INPUT_LEVELS 0x16
65 #define QUAD8_FLAG_E BIT(4)
67 #define QUAD8_FLAG_UD BIT(5)
68 /* Reset and Load Signal Decoders */
69 #define QUAD8_CTR_RLD 0x00
70 /* Counter Mode Register */
71 #define QUAD8_CTR_CMR 0x20
72 /* Input / Output Control Register */
73 #define QUAD8_CTR_IOR 0x40
74 /* Index Control Register */
75 #define QUAD8_CTR_IDR 0x60
76 /* Reset Byte Pointer (three byte data pointer) */
77 #define QUAD8_RLD_RESET_BP 0x01
79 #define QUAD8_RLD_RESET_CNTR 0x02
80 /* Reset Borrow Toggle, Carry Toggle, Compare Toggle, and Sign flags */
81 #define QUAD8_RLD_RESET_FLAGS 0x04
82 /* Reset Error flag */
83 #define QUAD8_RLD_RESET_E 0x06
84 /* Preset Register to Counter */
85 #define QUAD8_RLD_PRESET_CNTR 0x08
86 /* Transfer Counter to Output Latch */
87 #define QUAD8_RLD_CNTR_OUT 0x10
88 #define QUAD8_CHAN_OP_ENABLE_COUNTERS 0x00
89 #define QUAD8_CHAN_OP_RESET_COUNTERS 0x01
91 static int quad8_read_raw(struct iio_dev *indio_dev,
92 struct iio_chan_spec const *chan, int *val, int *val2, long mask)
94 struct quad8_iio *const priv = iio_priv(indio_dev);
95 const int base_offset = priv->base + 2 * chan->channel;
99 case IIO_CHAN_INFO_RAW:
100 if (chan->type == IIO_INDEX) {
101 *val = !!(inb(priv->base + QUAD8_REG_INDEX_INPUT_LEVELS)
102 & BIT(chan->channel));
108 /* Reset Byte Pointer; transfer Counter to Output Latch */
109 outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT,
112 for (i = 0; i < 3; i++)
113 *val |= (unsigned int)inb(base_offset) << (8 * i);
116 case IIO_CHAN_INFO_ENABLE:
117 *val = priv->ab_enable[chan->channel];
119 case IIO_CHAN_INFO_SCALE:
121 *val2 = priv->quadrature_scale[chan->channel];
122 return IIO_VAL_FRACTIONAL_LOG2;
128 static int quad8_write_raw(struct iio_dev *indio_dev,
129 struct iio_chan_spec const *chan, int val, int val2, long mask)
131 struct quad8_iio *const priv = iio_priv(indio_dev);
132 const int base_offset = priv->base + 2 * chan->channel;
134 unsigned int ior_cfg;
137 case IIO_CHAN_INFO_RAW:
138 if (chan->type == IIO_INDEX)
141 /* Only 24-bit values are supported */
142 if ((unsigned int)val > 0xFFFFFF)
145 /* Reset Byte Pointer */
146 outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
148 /* Counter can only be set via Preset Register */
149 for (i = 0; i < 3; i++)
150 outb(val >> (8 * i), base_offset);
152 /* Transfer Preset Register to Counter */
153 outb(QUAD8_CTR_RLD | QUAD8_RLD_PRESET_CNTR, base_offset + 1);
155 /* Reset Byte Pointer */
156 outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
158 /* Set Preset Register back to original value */
159 val = priv->preset[chan->channel];
160 for (i = 0; i < 3; i++)
161 outb(val >> (8 * i), base_offset);
163 /* Reset Borrow, Carry, Compare, and Sign flags */
164 outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1);
165 /* Reset Error flag */
166 outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1);
169 case IIO_CHAN_INFO_ENABLE:
170 /* only boolean values accepted */
171 if (val < 0 || val > 1)
174 priv->ab_enable[chan->channel] = val;
176 ior_cfg = val | priv->preset_enable[chan->channel] << 1;
178 /* Load I/O control configuration */
179 outb(QUAD8_CTR_IOR | ior_cfg, base_offset + 1);
182 case IIO_CHAN_INFO_SCALE:
183 /* Quadrature scaling only available in quadrature mode */
184 if (!priv->quadrature_mode[chan->channel] && (val2 || val != 1))
187 /* Only three gain states (1, 0.5, 0.25) */
188 if (val == 1 && !val2)
189 priv->quadrature_scale[chan->channel] = 0;
193 priv->quadrature_scale[chan->channel] = 1;
196 priv->quadrature_scale[chan->channel] = 2;
210 static const struct iio_info quad8_info = {
211 .read_raw = quad8_read_raw,
212 .write_raw = quad8_write_raw
215 static ssize_t quad8_read_preset(struct iio_dev *indio_dev, uintptr_t private,
216 const struct iio_chan_spec *chan, char *buf)
218 const struct quad8_iio *const priv = iio_priv(indio_dev);
220 return snprintf(buf, PAGE_SIZE, "%u\n", priv->preset[chan->channel]);
223 static ssize_t quad8_write_preset(struct iio_dev *indio_dev, uintptr_t private,
224 const struct iio_chan_spec *chan, const char *buf, size_t len)
226 struct quad8_iio *const priv = iio_priv(indio_dev);
227 const int base_offset = priv->base + 2 * chan->channel;
232 ret = kstrtouint(buf, 0, &preset);
236 /* Only 24-bit values are supported */
237 if (preset > 0xFFFFFF)
240 priv->preset[chan->channel] = preset;
242 /* Reset Byte Pointer */
243 outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
245 /* Set Preset Register */
246 for (i = 0; i < 3; i++)
247 outb(preset >> (8 * i), base_offset);
252 static ssize_t quad8_read_set_to_preset_on_index(struct iio_dev *indio_dev,
253 uintptr_t private, const struct iio_chan_spec *chan, char *buf)
255 const struct quad8_iio *const priv = iio_priv(indio_dev);
257 return snprintf(buf, PAGE_SIZE, "%u\n",
258 !priv->preset_enable[chan->channel]);
261 static ssize_t quad8_write_set_to_preset_on_index(struct iio_dev *indio_dev,
262 uintptr_t private, const struct iio_chan_spec *chan, const char *buf,
265 struct quad8_iio *const priv = iio_priv(indio_dev);
266 const int base_offset = priv->base + 2 * chan->channel + 1;
269 unsigned int ior_cfg;
271 ret = kstrtobool(buf, &preset_enable);
275 /* Preset enable is active low in Input/Output Control register */
276 preset_enable = !preset_enable;
278 priv->preset_enable[chan->channel] = preset_enable;
280 ior_cfg = priv->ab_enable[chan->channel] |
281 (unsigned int)preset_enable << 1;
283 /* Load I/O control configuration to Input / Output Control Register */
284 outb(QUAD8_CTR_IOR | ior_cfg, base_offset);
289 static const char *const quad8_noise_error_states[] = {
290 "No excessive noise is present at the count inputs",
291 "Excessive noise is present at the count inputs"
294 static int quad8_get_noise_error(struct iio_dev *indio_dev,
295 const struct iio_chan_spec *chan)
297 struct quad8_iio *const priv = iio_priv(indio_dev);
298 const int base_offset = priv->base + 2 * chan->channel + 1;
300 return !!(inb(base_offset) & QUAD8_FLAG_E);
303 static const struct iio_enum quad8_noise_error_enum = {
304 .items = quad8_noise_error_states,
305 .num_items = ARRAY_SIZE(quad8_noise_error_states),
306 .get = quad8_get_noise_error
309 static const char *const quad8_count_direction_states[] = {
314 static int quad8_get_count_direction(struct iio_dev *indio_dev,
315 const struct iio_chan_spec *chan)
317 struct quad8_iio *const priv = iio_priv(indio_dev);
318 const int base_offset = priv->base + 2 * chan->channel + 1;
320 return !!(inb(base_offset) & QUAD8_FLAG_UD);
323 static const struct iio_enum quad8_count_direction_enum = {
324 .items = quad8_count_direction_states,
325 .num_items = ARRAY_SIZE(quad8_count_direction_states),
326 .get = quad8_get_count_direction
329 static const char *const quad8_count_modes[] = {
336 static int quad8_set_count_mode(struct iio_dev *indio_dev,
337 const struct iio_chan_spec *chan, unsigned int count_mode)
339 struct quad8_iio *const priv = iio_priv(indio_dev);
340 unsigned int mode_cfg = count_mode << 1;
341 const int base_offset = priv->base + 2 * chan->channel + 1;
343 priv->count_mode[chan->channel] = count_mode;
345 /* Add quadrature mode configuration */
346 if (priv->quadrature_mode[chan->channel])
347 mode_cfg |= (priv->quadrature_scale[chan->channel] + 1) << 3;
349 /* Load mode configuration to Counter Mode Register */
350 outb(QUAD8_CTR_CMR | mode_cfg, base_offset);
355 static int quad8_get_count_mode(struct iio_dev *indio_dev,
356 const struct iio_chan_spec *chan)
358 const struct quad8_iio *const priv = iio_priv(indio_dev);
360 return priv->count_mode[chan->channel];
363 static const struct iio_enum quad8_count_mode_enum = {
364 .items = quad8_count_modes,
365 .num_items = ARRAY_SIZE(quad8_count_modes),
366 .set = quad8_set_count_mode,
367 .get = quad8_get_count_mode
370 static const char *const quad8_synchronous_modes[] = {
375 static int quad8_set_synchronous_mode(struct iio_dev *indio_dev,
376 const struct iio_chan_spec *chan, unsigned int synchronous_mode)
378 struct quad8_iio *const priv = iio_priv(indio_dev);
379 const unsigned int idr_cfg = synchronous_mode |
380 priv->index_polarity[chan->channel] << 1;
381 const int base_offset = priv->base + 2 * chan->channel + 1;
383 /* Index function must be non-synchronous in non-quadrature mode */
384 if (synchronous_mode && !priv->quadrature_mode[chan->channel])
387 priv->synchronous_mode[chan->channel] = synchronous_mode;
389 /* Load Index Control configuration to Index Control Register */
390 outb(QUAD8_CTR_IDR | idr_cfg, base_offset);
395 static int quad8_get_synchronous_mode(struct iio_dev *indio_dev,
396 const struct iio_chan_spec *chan)
398 const struct quad8_iio *const priv = iio_priv(indio_dev);
400 return priv->synchronous_mode[chan->channel];
403 static const struct iio_enum quad8_synchronous_mode_enum = {
404 .items = quad8_synchronous_modes,
405 .num_items = ARRAY_SIZE(quad8_synchronous_modes),
406 .set = quad8_set_synchronous_mode,
407 .get = quad8_get_synchronous_mode
410 static const char *const quad8_quadrature_modes[] = {
415 static int quad8_set_quadrature_mode(struct iio_dev *indio_dev,
416 const struct iio_chan_spec *chan, unsigned int quadrature_mode)
418 struct quad8_iio *const priv = iio_priv(indio_dev);
419 unsigned int mode_cfg = priv->count_mode[chan->channel] << 1;
420 const int base_offset = priv->base + 2 * chan->channel + 1;
423 mode_cfg |= (priv->quadrature_scale[chan->channel] + 1) << 3;
425 /* Quadrature scaling only available in quadrature mode */
426 priv->quadrature_scale[chan->channel] = 0;
428 /* Synchronous function not supported in non-quadrature mode */
429 if (priv->synchronous_mode[chan->channel])
430 quad8_set_synchronous_mode(indio_dev, chan, 0);
433 priv->quadrature_mode[chan->channel] = quadrature_mode;
435 /* Load mode configuration to Counter Mode Register */
436 outb(QUAD8_CTR_CMR | mode_cfg, base_offset);
441 static int quad8_get_quadrature_mode(struct iio_dev *indio_dev,
442 const struct iio_chan_spec *chan)
444 const struct quad8_iio *const priv = iio_priv(indio_dev);
446 return priv->quadrature_mode[chan->channel];
449 static const struct iio_enum quad8_quadrature_mode_enum = {
450 .items = quad8_quadrature_modes,
451 .num_items = ARRAY_SIZE(quad8_quadrature_modes),
452 .set = quad8_set_quadrature_mode,
453 .get = quad8_get_quadrature_mode
456 static const char *const quad8_index_polarity_modes[] = {
461 static int quad8_set_index_polarity(struct iio_dev *indio_dev,
462 const struct iio_chan_spec *chan, unsigned int index_polarity)
464 struct quad8_iio *const priv = iio_priv(indio_dev);
465 const unsigned int idr_cfg = priv->synchronous_mode[chan->channel] |
467 const int base_offset = priv->base + 2 * chan->channel + 1;
469 priv->index_polarity[chan->channel] = index_polarity;
471 /* Load Index Control configuration to Index Control Register */
472 outb(QUAD8_CTR_IDR | idr_cfg, base_offset);
477 static int quad8_get_index_polarity(struct iio_dev *indio_dev,
478 const struct iio_chan_spec *chan)
480 const struct quad8_iio *const priv = iio_priv(indio_dev);
482 return priv->index_polarity[chan->channel];
485 static const struct iio_enum quad8_index_polarity_enum = {
486 .items = quad8_index_polarity_modes,
487 .num_items = ARRAY_SIZE(quad8_index_polarity_modes),
488 .set = quad8_set_index_polarity,
489 .get = quad8_get_index_polarity
492 static const struct iio_chan_spec_ext_info quad8_count_ext_info[] = {
495 .shared = IIO_SEPARATE,
496 .read = quad8_read_preset,
497 .write = quad8_write_preset
500 .name = "set_to_preset_on_index",
501 .shared = IIO_SEPARATE,
502 .read = quad8_read_set_to_preset_on_index,
503 .write = quad8_write_set_to_preset_on_index
505 IIO_ENUM("noise_error", IIO_SEPARATE, &quad8_noise_error_enum),
506 IIO_ENUM_AVAILABLE("noise_error", &quad8_noise_error_enum),
507 IIO_ENUM("count_direction", IIO_SEPARATE, &quad8_count_direction_enum),
508 IIO_ENUM_AVAILABLE("count_direction", &quad8_count_direction_enum),
509 IIO_ENUM("count_mode", IIO_SEPARATE, &quad8_count_mode_enum),
510 IIO_ENUM_AVAILABLE("count_mode", &quad8_count_mode_enum),
511 IIO_ENUM("quadrature_mode", IIO_SEPARATE, &quad8_quadrature_mode_enum),
512 IIO_ENUM_AVAILABLE("quadrature_mode", &quad8_quadrature_mode_enum),
516 static const struct iio_chan_spec_ext_info quad8_index_ext_info[] = {
517 IIO_ENUM("synchronous_mode", IIO_SEPARATE,
518 &quad8_synchronous_mode_enum),
519 IIO_ENUM_AVAILABLE("synchronous_mode", &quad8_synchronous_mode_enum),
520 IIO_ENUM("index_polarity", IIO_SEPARATE, &quad8_index_polarity_enum),
521 IIO_ENUM_AVAILABLE("index_polarity", &quad8_index_polarity_enum),
525 #define QUAD8_COUNT_CHAN(_chan) { \
527 .channel = (_chan), \
528 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
529 BIT(IIO_CHAN_INFO_ENABLE) | BIT(IIO_CHAN_INFO_SCALE), \
530 .ext_info = quad8_count_ext_info, \
534 #define QUAD8_INDEX_CHAN(_chan) { \
536 .channel = (_chan), \
537 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
538 .ext_info = quad8_index_ext_info, \
542 static const struct iio_chan_spec quad8_channels[] = {
543 QUAD8_COUNT_CHAN(0), QUAD8_INDEX_CHAN(0),
544 QUAD8_COUNT_CHAN(1), QUAD8_INDEX_CHAN(1),
545 QUAD8_COUNT_CHAN(2), QUAD8_INDEX_CHAN(2),
546 QUAD8_COUNT_CHAN(3), QUAD8_INDEX_CHAN(3),
547 QUAD8_COUNT_CHAN(4), QUAD8_INDEX_CHAN(4),
548 QUAD8_COUNT_CHAN(5), QUAD8_INDEX_CHAN(5),
549 QUAD8_COUNT_CHAN(6), QUAD8_INDEX_CHAN(6),
550 QUAD8_COUNT_CHAN(7), QUAD8_INDEX_CHAN(7)
553 static int quad8_probe(struct device *dev, unsigned int id)
555 struct iio_dev *indio_dev;
556 struct quad8_iio *priv;
558 unsigned int base_offset;
560 indio_dev = devm_iio_device_alloc(dev, sizeof(*priv));
564 if (!devm_request_region(dev, base[id], QUAD8_EXTENT,
566 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
567 base[id], base[id] + QUAD8_EXTENT);
571 indio_dev->info = &quad8_info;
572 indio_dev->modes = INDIO_DIRECT_MODE;
573 indio_dev->num_channels = ARRAY_SIZE(quad8_channels);
574 indio_dev->channels = quad8_channels;
575 indio_dev->name = dev_name(dev);
576 indio_dev->dev.parent = dev;
578 priv = iio_priv(indio_dev);
579 priv->base = base[id];
581 /* Reset all counters and disable interrupt function */
582 outb(QUAD8_CHAN_OP_RESET_COUNTERS, base[id] + QUAD8_REG_CHAN_OP);
583 /* Set initial configuration for all counters */
584 for (i = 0; i < QUAD8_NUM_COUNTERS; i++) {
585 base_offset = base[id] + 2 * i;
586 /* Reset Byte Pointer */
587 outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
588 /* Reset Preset Register */
589 for (j = 0; j < 3; j++)
590 outb(0x00, base_offset);
591 /* Reset Borrow, Carry, Compare, and Sign flags */
592 outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1);
593 /* Reset Error flag */
594 outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1);
595 /* Binary encoding; Normal count; non-quadrature mode */
596 outb(QUAD8_CTR_CMR, base_offset + 1);
597 /* Disable A and B inputs; preset on index; FLG1 as Carry */
598 outb(QUAD8_CTR_IOR, base_offset + 1);
599 /* Disable index function; negative index polarity */
600 outb(QUAD8_CTR_IDR, base_offset + 1);
602 /* Enable all counters */
603 outb(QUAD8_CHAN_OP_ENABLE_COUNTERS, base[id] + QUAD8_REG_CHAN_OP);
605 return devm_iio_device_register(dev, indio_dev);
608 static struct isa_driver quad8_driver = {
609 .probe = quad8_probe,
615 module_isa_driver(quad8_driver, num_quad8);
617 MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
618 MODULE_DESCRIPTION("ACCES 104-QUAD-8 IIO driver");
619 MODULE_LICENSE("GPL v2");