2 * Copyright (C) 2012 Invensense, Inc.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/i2c.h>
17 #include <linux/err.h>
18 #include <linux/delay.h>
19 #include <linux/sysfs.h>
20 #include <linux/jiffies.h>
21 #include <linux/irq.h>
22 #include <linux/interrupt.h>
23 #include <linux/iio/iio.h>
24 #include <linux/acpi.h>
25 #include <linux/platform_device.h>
26 #include "inv_mpu_iio.h"
29 * this is the gyro scale translated from dynamic range plus/minus
30 * {250, 500, 1000, 2000} to rad/s
32 static const int gyro_scale_6050[] = {133090, 266181, 532362, 1064724};
35 * this is the accel scale translated from dynamic range plus/minus
36 * {2, 4, 8, 16} to m/s^2
38 static const int accel_scale[] = {598, 1196, 2392, 4785};
40 static const struct inv_mpu6050_reg_map reg_set_icm20602 = {
41 .sample_rate_div = INV_MPU6050_REG_SAMPLE_RATE_DIV,
42 .lpf = INV_MPU6050_REG_CONFIG,
43 .accel_lpf = INV_MPU6500_REG_ACCEL_CONFIG_2,
44 .user_ctrl = INV_MPU6050_REG_USER_CTRL,
45 .fifo_en = INV_MPU6050_REG_FIFO_EN,
46 .gyro_config = INV_MPU6050_REG_GYRO_CONFIG,
47 .accl_config = INV_MPU6050_REG_ACCEL_CONFIG,
48 .fifo_count_h = INV_MPU6050_REG_FIFO_COUNT_H,
49 .fifo_r_w = INV_MPU6050_REG_FIFO_R_W,
50 .raw_gyro = INV_MPU6050_REG_RAW_GYRO,
51 .raw_accl = INV_MPU6050_REG_RAW_ACCEL,
52 .temperature = INV_MPU6050_REG_TEMPERATURE,
53 .int_enable = INV_MPU6050_REG_INT_ENABLE,
54 .int_status = INV_MPU6050_REG_INT_STATUS,
55 .pwr_mgmt_1 = INV_MPU6050_REG_PWR_MGMT_1,
56 .pwr_mgmt_2 = INV_MPU6050_REG_PWR_MGMT_2,
57 .int_pin_cfg = INV_MPU6050_REG_INT_PIN_CFG,
58 .accl_offset = INV_MPU6500_REG_ACCEL_OFFSET,
59 .gyro_offset = INV_MPU6050_REG_GYRO_OFFSET,
60 .i2c_if = INV_ICM20602_REG_I2C_IF,
63 static const struct inv_mpu6050_reg_map reg_set_6500 = {
64 .sample_rate_div = INV_MPU6050_REG_SAMPLE_RATE_DIV,
65 .lpf = INV_MPU6050_REG_CONFIG,
66 .accel_lpf = INV_MPU6500_REG_ACCEL_CONFIG_2,
67 .user_ctrl = INV_MPU6050_REG_USER_CTRL,
68 .fifo_en = INV_MPU6050_REG_FIFO_EN,
69 .gyro_config = INV_MPU6050_REG_GYRO_CONFIG,
70 .accl_config = INV_MPU6050_REG_ACCEL_CONFIG,
71 .fifo_count_h = INV_MPU6050_REG_FIFO_COUNT_H,
72 .fifo_r_w = INV_MPU6050_REG_FIFO_R_W,
73 .raw_gyro = INV_MPU6050_REG_RAW_GYRO,
74 .raw_accl = INV_MPU6050_REG_RAW_ACCEL,
75 .temperature = INV_MPU6050_REG_TEMPERATURE,
76 .int_enable = INV_MPU6050_REG_INT_ENABLE,
77 .int_status = INV_MPU6050_REG_INT_STATUS,
78 .pwr_mgmt_1 = INV_MPU6050_REG_PWR_MGMT_1,
79 .pwr_mgmt_2 = INV_MPU6050_REG_PWR_MGMT_2,
80 .int_pin_cfg = INV_MPU6050_REG_INT_PIN_CFG,
81 .accl_offset = INV_MPU6500_REG_ACCEL_OFFSET,
82 .gyro_offset = INV_MPU6050_REG_GYRO_OFFSET,
86 static const struct inv_mpu6050_reg_map reg_set_6050 = {
87 .sample_rate_div = INV_MPU6050_REG_SAMPLE_RATE_DIV,
88 .lpf = INV_MPU6050_REG_CONFIG,
89 .user_ctrl = INV_MPU6050_REG_USER_CTRL,
90 .fifo_en = INV_MPU6050_REG_FIFO_EN,
91 .gyro_config = INV_MPU6050_REG_GYRO_CONFIG,
92 .accl_config = INV_MPU6050_REG_ACCEL_CONFIG,
93 .fifo_count_h = INV_MPU6050_REG_FIFO_COUNT_H,
94 .fifo_r_w = INV_MPU6050_REG_FIFO_R_W,
95 .raw_gyro = INV_MPU6050_REG_RAW_GYRO,
96 .raw_accl = INV_MPU6050_REG_RAW_ACCEL,
97 .temperature = INV_MPU6050_REG_TEMPERATURE,
98 .int_enable = INV_MPU6050_REG_INT_ENABLE,
99 .pwr_mgmt_1 = INV_MPU6050_REG_PWR_MGMT_1,
100 .pwr_mgmt_2 = INV_MPU6050_REG_PWR_MGMT_2,
101 .int_pin_cfg = INV_MPU6050_REG_INT_PIN_CFG,
102 .accl_offset = INV_MPU6050_REG_ACCEL_OFFSET,
103 .gyro_offset = INV_MPU6050_REG_GYRO_OFFSET,
107 static const struct inv_mpu6050_chip_config chip_config_6050 = {
108 .fsr = INV_MPU6050_FSR_2000DPS,
109 .lpf = INV_MPU6050_FILTER_20HZ,
110 .divider = INV_MPU6050_FIFO_RATE_TO_DIVIDER(INV_MPU6050_INIT_FIFO_RATE),
111 .gyro_fifo_enable = false,
112 .accl_fifo_enable = false,
113 .accl_fs = INV_MPU6050_FS_02G,
117 /* Indexed by enum inv_devices */
118 static const struct inv_mpu6050_hw hw_info[] = {
120 .whoami = INV_MPU6050_WHOAMI_VALUE,
122 .reg = ®_set_6050,
123 .config = &chip_config_6050,
125 .temp = {INV_MPU6050_TEMP_OFFSET, INV_MPU6050_TEMP_SCALE},
128 .whoami = INV_MPU6500_WHOAMI_VALUE,
130 .reg = ®_set_6500,
131 .config = &chip_config_6050,
133 .temp = {INV_MPU6500_TEMP_OFFSET, INV_MPU6500_TEMP_SCALE},
136 .whoami = INV_MPU6515_WHOAMI_VALUE,
138 .reg = ®_set_6500,
139 .config = &chip_config_6050,
141 .temp = {INV_MPU6500_TEMP_OFFSET, INV_MPU6500_TEMP_SCALE},
144 .whoami = INV_MPU6000_WHOAMI_VALUE,
146 .reg = ®_set_6050,
147 .config = &chip_config_6050,
149 .temp = {INV_MPU6050_TEMP_OFFSET, INV_MPU6050_TEMP_SCALE},
152 .whoami = INV_MPU9150_WHOAMI_VALUE,
154 .reg = ®_set_6050,
155 .config = &chip_config_6050,
157 .temp = {INV_MPU6050_TEMP_OFFSET, INV_MPU6050_TEMP_SCALE},
160 .whoami = INV_MPU9250_WHOAMI_VALUE,
162 .reg = ®_set_6500,
163 .config = &chip_config_6050,
165 .temp = {INV_MPU6500_TEMP_OFFSET, INV_MPU6500_TEMP_SCALE},
168 .whoami = INV_MPU9255_WHOAMI_VALUE,
170 .reg = ®_set_6500,
171 .config = &chip_config_6050,
173 .temp = {INV_MPU6500_TEMP_OFFSET, INV_MPU6500_TEMP_SCALE},
176 .whoami = INV_ICM20608_WHOAMI_VALUE,
178 .reg = ®_set_6500,
179 .config = &chip_config_6050,
181 .temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
184 .whoami = INV_ICM20602_WHOAMI_VALUE,
186 .reg = ®_set_icm20602,
187 .config = &chip_config_6050,
189 .temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
193 int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, u32 mask)
195 unsigned int d, mgmt_1;
198 * switch clock needs to be careful. Only when gyro is on, can
199 * clock source be switched to gyro. Otherwise, it must be set to
202 if (mask == INV_MPU6050_BIT_PWR_GYRO_STBY) {
203 result = regmap_read(st->map, st->reg->pwr_mgmt_1, &mgmt_1);
207 mgmt_1 &= ~INV_MPU6050_BIT_CLK_MASK;
210 if ((mask == INV_MPU6050_BIT_PWR_GYRO_STBY) && (!en)) {
212 * turning off gyro requires switch to internal clock first.
213 * Then turn off gyro engine
215 mgmt_1 |= INV_CLK_INTERNAL;
216 result = regmap_write(st->map, st->reg->pwr_mgmt_1, mgmt_1);
221 result = regmap_read(st->map, st->reg->pwr_mgmt_2, &d);
228 result = regmap_write(st->map, st->reg->pwr_mgmt_2, d);
233 /* Wait for output to stabilize */
234 msleep(INV_MPU6050_TEMP_UP_TIME);
235 if (mask == INV_MPU6050_BIT_PWR_GYRO_STBY) {
236 /* switch internal clock to PLL */
237 mgmt_1 |= INV_CLK_PLL;
238 result = regmap_write(st->map,
239 st->reg->pwr_mgmt_1, mgmt_1);
248 int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on)
253 if (!st->powerup_count) {
254 result = regmap_write(st->map, st->reg->pwr_mgmt_1, 0);
257 usleep_range(INV_MPU6050_REG_UP_TIME_MIN,
258 INV_MPU6050_REG_UP_TIME_MAX);
262 if (st->powerup_count == 1) {
263 result = regmap_write(st->map, st->reg->pwr_mgmt_1,
264 INV_MPU6050_BIT_SLEEP);
271 dev_dbg(regmap_get_device(st->map), "set power %d, count=%u\n",
272 power_on, st->powerup_count);
276 EXPORT_SYMBOL_GPL(inv_mpu6050_set_power_itg);
279 * inv_mpu6050_set_lpf_regs() - set low pass filter registers, chip dependent
281 * MPU60xx/MPU9150 use only 1 register for accelerometer + gyroscope
282 * MPU6500 and above have a dedicated register for accelerometer
284 static int inv_mpu6050_set_lpf_regs(struct inv_mpu6050_state *st,
285 enum inv_mpu6050_filter_e val)
289 result = regmap_write(st->map, st->reg->lpf, val);
293 switch (st->chip_type) {
297 /* old chips, nothing to do */
302 result = regmap_write(st->map, st->reg->accel_lpf, val);
310 * inv_mpu6050_init_config() - Initialize hardware, disable FIFO.
312 * Initial configuration:
316 * Clock source: Gyro PLL
318 static int inv_mpu6050_init_config(struct iio_dev *indio_dev)
322 struct inv_mpu6050_state *st = iio_priv(indio_dev);
324 result = inv_mpu6050_set_power_itg(st, true);
327 d = (INV_MPU6050_FSR_2000DPS << INV_MPU6050_GYRO_CONFIG_FSR_SHIFT);
328 result = regmap_write(st->map, st->reg->gyro_config, d);
330 goto error_power_off;
332 result = inv_mpu6050_set_lpf_regs(st, INV_MPU6050_FILTER_20HZ);
334 goto error_power_off;
336 d = INV_MPU6050_FIFO_RATE_TO_DIVIDER(INV_MPU6050_INIT_FIFO_RATE);
337 result = regmap_write(st->map, st->reg->sample_rate_div, d);
339 goto error_power_off;
341 d = (INV_MPU6050_FS_02G << INV_MPU6050_ACCL_CONFIG_FSR_SHIFT);
342 result = regmap_write(st->map, st->reg->accl_config, d);
344 goto error_power_off;
346 result = regmap_write(st->map, st->reg->int_pin_cfg, st->irq_mask);
350 memcpy(&st->chip_config, hw_info[st->chip_type].config,
351 sizeof(struct inv_mpu6050_chip_config));
354 * Internal chip period is 1ms (1kHz).
355 * Let's use at the beginning the theorical value before measuring
356 * with interrupt timestamps.
358 st->chip_period = NSEC_PER_MSEC;
360 return inv_mpu6050_set_power_itg(st, false);
363 inv_mpu6050_set_power_itg(st, false);
367 static int inv_mpu6050_sensor_set(struct inv_mpu6050_state *st, int reg,
371 __be16 d = cpu_to_be16(val);
373 ind = (axis - IIO_MOD_X) * 2;
374 result = regmap_bulk_write(st->map, reg + ind, (u8 *)&d, 2);
381 static int inv_mpu6050_sensor_show(struct inv_mpu6050_state *st, int reg,
387 ind = (axis - IIO_MOD_X) * 2;
388 result = regmap_bulk_read(st->map, reg + ind, (u8 *)&d, 2);
391 *val = (short)be16_to_cpup(&d);
396 static int inv_mpu6050_read_channel_data(struct iio_dev *indio_dev,
397 struct iio_chan_spec const *chan,
400 struct inv_mpu6050_state *st = iio_priv(indio_dev);
404 result = inv_mpu6050_set_power_itg(st, true);
408 switch (chan->type) {
410 result = inv_mpu6050_switch_engine(st, true,
411 INV_MPU6050_BIT_PWR_GYRO_STBY);
413 goto error_power_off;
414 ret = inv_mpu6050_sensor_show(st, st->reg->raw_gyro,
415 chan->channel2, val);
416 result = inv_mpu6050_switch_engine(st, false,
417 INV_MPU6050_BIT_PWR_GYRO_STBY);
419 goto error_power_off;
422 result = inv_mpu6050_switch_engine(st, true,
423 INV_MPU6050_BIT_PWR_ACCL_STBY);
425 goto error_power_off;
426 ret = inv_mpu6050_sensor_show(st, st->reg->raw_accl,
427 chan->channel2, val);
428 result = inv_mpu6050_switch_engine(st, false,
429 INV_MPU6050_BIT_PWR_ACCL_STBY);
431 goto error_power_off;
434 /* wait for stablization */
435 msleep(INV_MPU6050_SENSOR_UP_TIME);
436 ret = inv_mpu6050_sensor_show(st, st->reg->temperature,
444 result = inv_mpu6050_set_power_itg(st, false);
446 goto error_power_off;
451 inv_mpu6050_set_power_itg(st, false);
456 inv_mpu6050_read_raw(struct iio_dev *indio_dev,
457 struct iio_chan_spec const *chan,
458 int *val, int *val2, long mask)
460 struct inv_mpu6050_state *st = iio_priv(indio_dev);
464 case IIO_CHAN_INFO_RAW:
465 ret = iio_device_claim_direct_mode(indio_dev);
468 mutex_lock(&st->lock);
469 ret = inv_mpu6050_read_channel_data(indio_dev, chan, val);
470 mutex_unlock(&st->lock);
471 iio_device_release_direct_mode(indio_dev);
473 case IIO_CHAN_INFO_SCALE:
474 switch (chan->type) {
476 mutex_lock(&st->lock);
478 *val2 = gyro_scale_6050[st->chip_config.fsr];
479 mutex_unlock(&st->lock);
481 return IIO_VAL_INT_PLUS_NANO;
483 mutex_lock(&st->lock);
485 *val2 = accel_scale[st->chip_config.accl_fs];
486 mutex_unlock(&st->lock);
488 return IIO_VAL_INT_PLUS_MICRO;
490 *val = st->hw->temp.scale / 1000000;
491 *val2 = st->hw->temp.scale % 1000000;
492 return IIO_VAL_INT_PLUS_MICRO;
496 case IIO_CHAN_INFO_OFFSET:
497 switch (chan->type) {
499 *val = st->hw->temp.offset;
504 case IIO_CHAN_INFO_CALIBBIAS:
505 switch (chan->type) {
507 mutex_lock(&st->lock);
508 ret = inv_mpu6050_sensor_show(st, st->reg->gyro_offset,
509 chan->channel2, val);
510 mutex_unlock(&st->lock);
513 mutex_lock(&st->lock);
514 ret = inv_mpu6050_sensor_show(st, st->reg->accl_offset,
515 chan->channel2, val);
516 mutex_unlock(&st->lock);
527 static int inv_mpu6050_write_gyro_scale(struct inv_mpu6050_state *st, int val)
532 for (i = 0; i < ARRAY_SIZE(gyro_scale_6050); ++i) {
533 if (gyro_scale_6050[i] == val) {
534 d = (i << INV_MPU6050_GYRO_CONFIG_FSR_SHIFT);
535 result = regmap_write(st->map, st->reg->gyro_config, d);
539 st->chip_config.fsr = i;
547 static int inv_write_raw_get_fmt(struct iio_dev *indio_dev,
548 struct iio_chan_spec const *chan, long mask)
551 case IIO_CHAN_INFO_SCALE:
552 switch (chan->type) {
554 return IIO_VAL_INT_PLUS_NANO;
556 return IIO_VAL_INT_PLUS_MICRO;
559 return IIO_VAL_INT_PLUS_MICRO;
565 static int inv_mpu6050_write_accel_scale(struct inv_mpu6050_state *st, int val)
570 for (i = 0; i < ARRAY_SIZE(accel_scale); ++i) {
571 if (accel_scale[i] == val) {
572 d = (i << INV_MPU6050_ACCL_CONFIG_FSR_SHIFT);
573 result = regmap_write(st->map, st->reg->accl_config, d);
577 st->chip_config.accl_fs = i;
585 static int inv_mpu6050_write_raw(struct iio_dev *indio_dev,
586 struct iio_chan_spec const *chan,
587 int val, int val2, long mask)
589 struct inv_mpu6050_state *st = iio_priv(indio_dev);
593 * we should only update scale when the chip is disabled, i.e.
596 result = iio_device_claim_direct_mode(indio_dev);
600 mutex_lock(&st->lock);
601 result = inv_mpu6050_set_power_itg(st, true);
603 goto error_write_raw_unlock;
606 case IIO_CHAN_INFO_SCALE:
607 switch (chan->type) {
609 result = inv_mpu6050_write_gyro_scale(st, val2);
612 result = inv_mpu6050_write_accel_scale(st, val2);
619 case IIO_CHAN_INFO_CALIBBIAS:
620 switch (chan->type) {
622 result = inv_mpu6050_sensor_set(st,
623 st->reg->gyro_offset,
624 chan->channel2, val);
627 result = inv_mpu6050_sensor_set(st,
628 st->reg->accl_offset,
629 chan->channel2, val);
641 result |= inv_mpu6050_set_power_itg(st, false);
642 error_write_raw_unlock:
643 mutex_unlock(&st->lock);
644 iio_device_release_direct_mode(indio_dev);
650 * inv_mpu6050_set_lpf() - set low pass filer based on fifo rate.
652 * Based on the Nyquist principle, the sampling rate must
653 * exceed twice of the bandwidth of the signal, or there
654 * would be alising. This function basically search for the
655 * correct low pass parameters based on the fifo rate, e.g,
656 * sampling frequency.
658 * lpf is set automatically when setting sampling rate to avoid any aliases.
660 static int inv_mpu6050_set_lpf(struct inv_mpu6050_state *st, int rate)
662 static const int hz[] = {188, 98, 42, 20, 10, 5};
663 static const int d[] = {
664 INV_MPU6050_FILTER_188HZ, INV_MPU6050_FILTER_98HZ,
665 INV_MPU6050_FILTER_42HZ, INV_MPU6050_FILTER_20HZ,
666 INV_MPU6050_FILTER_10HZ, INV_MPU6050_FILTER_5HZ
673 while ((h < hz[i]) && (i < ARRAY_SIZE(d) - 1))
676 result = inv_mpu6050_set_lpf_regs(st, data);
679 st->chip_config.lpf = data;
685 * inv_mpu6050_fifo_rate_store() - Set fifo rate.
688 inv_mpu6050_fifo_rate_store(struct device *dev, struct device_attribute *attr,
689 const char *buf, size_t count)
694 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
695 struct inv_mpu6050_state *st = iio_priv(indio_dev);
697 if (kstrtoint(buf, 10, &fifo_rate))
699 if (fifo_rate < INV_MPU6050_MIN_FIFO_RATE ||
700 fifo_rate > INV_MPU6050_MAX_FIFO_RATE)
703 result = iio_device_claim_direct_mode(indio_dev);
707 /* compute the chip sample rate divider */
708 d = INV_MPU6050_FIFO_RATE_TO_DIVIDER(fifo_rate);
709 /* compute back the fifo rate to handle truncation cases */
710 fifo_rate = INV_MPU6050_DIVIDER_TO_FIFO_RATE(d);
712 mutex_lock(&st->lock);
713 if (d == st->chip_config.divider) {
715 goto fifo_rate_fail_unlock;
717 result = inv_mpu6050_set_power_itg(st, true);
719 goto fifo_rate_fail_unlock;
721 result = regmap_write(st->map, st->reg->sample_rate_div, d);
723 goto fifo_rate_fail_power_off;
724 st->chip_config.divider = d;
726 result = inv_mpu6050_set_lpf(st, fifo_rate);
728 goto fifo_rate_fail_power_off;
730 fifo_rate_fail_power_off:
731 result |= inv_mpu6050_set_power_itg(st, false);
732 fifo_rate_fail_unlock:
733 mutex_unlock(&st->lock);
734 iio_device_release_direct_mode(indio_dev);
742 * inv_fifo_rate_show() - Get the current sampling rate.
745 inv_fifo_rate_show(struct device *dev, struct device_attribute *attr,
748 struct inv_mpu6050_state *st = iio_priv(dev_to_iio_dev(dev));
751 mutex_lock(&st->lock);
752 fifo_rate = INV_MPU6050_DIVIDER_TO_FIFO_RATE(st->chip_config.divider);
753 mutex_unlock(&st->lock);
755 return scnprintf(buf, PAGE_SIZE, "%u\n", fifo_rate);
759 * inv_attr_show() - calling this function will show current
762 * Deprecated in favor of IIO mounting matrix API.
764 * See inv_get_mount_matrix()
766 static ssize_t inv_attr_show(struct device *dev, struct device_attribute *attr,
769 struct inv_mpu6050_state *st = iio_priv(dev_to_iio_dev(dev));
770 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
773 switch (this_attr->address) {
775 * In MPU6050, the two matrix are the same because gyro and accel
776 * are integrated in one chip
778 case ATTR_GYRO_MATRIX:
779 case ATTR_ACCL_MATRIX:
780 m = st->plat_data.orientation;
782 return scnprintf(buf, PAGE_SIZE,
783 "%d, %d, %d; %d, %d, %d; %d, %d, %d\n",
784 m[0], m[1], m[2], m[3], m[4], m[5], m[6], m[7], m[8]);
791 * inv_mpu6050_validate_trigger() - validate_trigger callback for invensense
793 * @indio_dev: The IIO device
794 * @trig: The new trigger
796 * Returns: 0 if the 'trig' matches the trigger registered by the MPU6050
797 * device, -EINVAL otherwise.
799 static int inv_mpu6050_validate_trigger(struct iio_dev *indio_dev,
800 struct iio_trigger *trig)
802 struct inv_mpu6050_state *st = iio_priv(indio_dev);
804 if (st->trig != trig)
810 static const struct iio_mount_matrix *
811 inv_get_mount_matrix(const struct iio_dev *indio_dev,
812 const struct iio_chan_spec *chan)
814 return &((struct inv_mpu6050_state *)iio_priv(indio_dev))->orientation;
817 static const struct iio_chan_spec_ext_info inv_ext_info[] = {
818 IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, inv_get_mount_matrix),
822 #define INV_MPU6050_CHAN(_type, _channel2, _index) \
826 .channel2 = _channel2, \
827 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
828 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
829 BIT(IIO_CHAN_INFO_CALIBBIAS), \
830 .scan_index = _index, \
836 .endianness = IIO_BE, \
838 .ext_info = inv_ext_info, \
841 static const struct iio_chan_spec inv_mpu_channels[] = {
842 IIO_CHAN_SOFT_TIMESTAMP(INV_MPU6050_SCAN_TIMESTAMP),
844 * Note that temperature should only be via polled reading only,
845 * not the final scan elements output.
849 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW)
850 | BIT(IIO_CHAN_INFO_OFFSET)
851 | BIT(IIO_CHAN_INFO_SCALE),
854 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_X, INV_MPU6050_SCAN_GYRO_X),
855 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Y, INV_MPU6050_SCAN_GYRO_Y),
856 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Z, INV_MPU6050_SCAN_GYRO_Z),
858 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_X, INV_MPU6050_SCAN_ACCL_X),
859 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Y, INV_MPU6050_SCAN_ACCL_Y),
860 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Z, INV_MPU6050_SCAN_ACCL_Z),
863 static const unsigned long inv_mpu_scan_masks[] = {
865 BIT(INV_MPU6050_SCAN_ACCL_X)
866 | BIT(INV_MPU6050_SCAN_ACCL_Y)
867 | BIT(INV_MPU6050_SCAN_ACCL_Z),
869 BIT(INV_MPU6050_SCAN_GYRO_X)
870 | BIT(INV_MPU6050_SCAN_GYRO_Y)
871 | BIT(INV_MPU6050_SCAN_GYRO_Z),
872 /* 6-axis accel + gyro */
873 BIT(INV_MPU6050_SCAN_ACCL_X)
874 | BIT(INV_MPU6050_SCAN_ACCL_Y)
875 | BIT(INV_MPU6050_SCAN_ACCL_Z)
876 | BIT(INV_MPU6050_SCAN_GYRO_X)
877 | BIT(INV_MPU6050_SCAN_GYRO_Y)
878 | BIT(INV_MPU6050_SCAN_GYRO_Z),
882 static const struct iio_chan_spec inv_icm20602_channels[] = {
883 IIO_CHAN_SOFT_TIMESTAMP(INV_ICM20602_SCAN_TIMESTAMP),
886 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW)
887 | BIT(IIO_CHAN_INFO_OFFSET)
888 | BIT(IIO_CHAN_INFO_SCALE),
889 .scan_index = INV_ICM20602_SCAN_TEMP,
895 .endianness = IIO_BE,
899 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_X, INV_ICM20602_SCAN_GYRO_X),
900 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Y, INV_ICM20602_SCAN_GYRO_Y),
901 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Z, INV_ICM20602_SCAN_GYRO_Z),
903 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Y, INV_ICM20602_SCAN_ACCL_Y),
904 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_X, INV_ICM20602_SCAN_ACCL_X),
905 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Z, INV_ICM20602_SCAN_ACCL_Z),
908 static const unsigned long inv_icm20602_scan_masks[] = {
909 /* 3-axis accel + temp (mandatory) */
910 BIT(INV_ICM20602_SCAN_ACCL_X)
911 | BIT(INV_ICM20602_SCAN_ACCL_Y)
912 | BIT(INV_ICM20602_SCAN_ACCL_Z)
913 | BIT(INV_ICM20602_SCAN_TEMP),
914 /* 3-axis gyro + temp (mandatory) */
915 BIT(INV_ICM20602_SCAN_GYRO_X)
916 | BIT(INV_ICM20602_SCAN_GYRO_Y)
917 | BIT(INV_ICM20602_SCAN_GYRO_Z)
918 | BIT(INV_ICM20602_SCAN_TEMP),
919 /* 6-axis accel + gyro + temp (mandatory) */
920 BIT(INV_ICM20602_SCAN_ACCL_X)
921 | BIT(INV_ICM20602_SCAN_ACCL_Y)
922 | BIT(INV_ICM20602_SCAN_ACCL_Z)
923 | BIT(INV_ICM20602_SCAN_GYRO_X)
924 | BIT(INV_ICM20602_SCAN_GYRO_Y)
925 | BIT(INV_ICM20602_SCAN_GYRO_Z)
926 | BIT(INV_ICM20602_SCAN_TEMP),
931 * The user can choose any frequency between INV_MPU6050_MIN_FIFO_RATE and
932 * INV_MPU6050_MAX_FIFO_RATE, but only these frequencies are matched by the
933 * low-pass filter. Specifically, each of these sampling rates are about twice
934 * the bandwidth of a corresponding low-pass filter, which should eliminate
935 * aliasing following the Nyquist principle. By picking a frequency different
936 * from these, the user risks aliasing effects.
938 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("10 20 50 100 200 500");
939 static IIO_CONST_ATTR(in_anglvel_scale_available,
940 "0.000133090 0.000266181 0.000532362 0.001064724");
941 static IIO_CONST_ATTR(in_accel_scale_available,
942 "0.000598 0.001196 0.002392 0.004785");
943 static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR, inv_fifo_rate_show,
944 inv_mpu6050_fifo_rate_store);
946 /* Deprecated: kept for userspace backward compatibility. */
947 static IIO_DEVICE_ATTR(in_gyro_matrix, S_IRUGO, inv_attr_show, NULL,
949 static IIO_DEVICE_ATTR(in_accel_matrix, S_IRUGO, inv_attr_show, NULL,
952 static struct attribute *inv_attributes[] = {
953 &iio_dev_attr_in_gyro_matrix.dev_attr.attr, /* deprecated */
954 &iio_dev_attr_in_accel_matrix.dev_attr.attr, /* deprecated */
955 &iio_dev_attr_sampling_frequency.dev_attr.attr,
956 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
957 &iio_const_attr_in_accel_scale_available.dev_attr.attr,
958 &iio_const_attr_in_anglvel_scale_available.dev_attr.attr,
962 static const struct attribute_group inv_attribute_group = {
963 .attrs = inv_attributes
966 static const struct iio_info mpu_info = {
967 .read_raw = &inv_mpu6050_read_raw,
968 .write_raw = &inv_mpu6050_write_raw,
969 .write_raw_get_fmt = &inv_write_raw_get_fmt,
970 .attrs = &inv_attribute_group,
971 .validate_trigger = inv_mpu6050_validate_trigger,
975 * inv_check_and_setup_chip() - check and setup chip.
977 static int inv_check_and_setup_chip(struct inv_mpu6050_state *st)
983 st->hw = &hw_info[st->chip_type];
984 st->reg = hw_info[st->chip_type].reg;
986 /* check chip self-identification */
987 result = regmap_read(st->map, INV_MPU6050_REG_WHOAMI, ®val);
990 if (regval != st->hw->whoami) {
991 /* check whoami against all possible values */
992 for (i = 0; i < INV_NUM_PARTS; ++i) {
993 if (regval == hw_info[i].whoami) {
994 dev_warn(regmap_get_device(st->map),
995 "whoami mismatch got %#02x (%s)"
996 "expected %#02hhx (%s)\n",
997 regval, hw_info[i].name,
998 st->hw->whoami, st->hw->name);
1002 if (i >= INV_NUM_PARTS) {
1003 dev_err(regmap_get_device(st->map),
1004 "invalid whoami %#02x expected %#02hhx (%s)\n",
1005 regval, st->hw->whoami, st->hw->name);
1010 /* reset to make sure previous state are not there */
1011 result = regmap_write(st->map, st->reg->pwr_mgmt_1,
1012 INV_MPU6050_BIT_H_RESET);
1015 msleep(INV_MPU6050_POWER_UP_TIME);
1018 * Turn power on. After reset, the sleep bit could be on
1019 * or off depending on the OTP settings. Turning power on
1020 * make it in a definite state as well as making the hardware
1021 * state align with the software state
1023 result = inv_mpu6050_set_power_itg(st, true);
1027 result = inv_mpu6050_switch_engine(st, false,
1028 INV_MPU6050_BIT_PWR_ACCL_STBY);
1030 goto error_power_off;
1031 result = inv_mpu6050_switch_engine(st, false,
1032 INV_MPU6050_BIT_PWR_GYRO_STBY);
1034 goto error_power_off;
1036 return inv_mpu6050_set_power_itg(st, false);
1039 inv_mpu6050_set_power_itg(st, false);
1043 int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name,
1044 int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type)
1046 struct inv_mpu6050_state *st;
1047 struct iio_dev *indio_dev;
1048 struct inv_mpu6050_platform_data *pdata;
1049 struct device *dev = regmap_get_device(regmap);
1051 struct irq_data *desc;
1054 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1058 BUILD_BUG_ON(ARRAY_SIZE(hw_info) != INV_NUM_PARTS);
1059 if (chip_type < 0 || chip_type >= INV_NUM_PARTS) {
1060 dev_err(dev, "Bad invensense chip_type=%d name=%s\n",
1064 st = iio_priv(indio_dev);
1065 mutex_init(&st->lock);
1066 st->chip_type = chip_type;
1067 st->powerup_count = 0;
1071 pdata = dev_get_platdata(dev);
1073 result = of_iio_read_mount_matrix(dev, "mount-matrix",
1076 dev_err(dev, "Failed to retrieve mounting matrix %d\n",
1081 st->plat_data = *pdata;
1084 desc = irq_get_irq_data(irq);
1086 dev_err(dev, "Could not find IRQ %d\n", irq);
1090 irq_type = irqd_get_trigger_type(desc);
1092 irq_type = IRQF_TRIGGER_RISING;
1093 if (irq_type == IRQF_TRIGGER_RISING)
1094 st->irq_mask = INV_MPU6050_ACTIVE_HIGH;
1095 else if (irq_type == IRQF_TRIGGER_FALLING)
1096 st->irq_mask = INV_MPU6050_ACTIVE_LOW;
1097 else if (irq_type == IRQF_TRIGGER_HIGH)
1098 st->irq_mask = INV_MPU6050_ACTIVE_HIGH |
1099 INV_MPU6050_LATCH_INT_EN;
1100 else if (irq_type == IRQF_TRIGGER_LOW)
1101 st->irq_mask = INV_MPU6050_ACTIVE_LOW |
1102 INV_MPU6050_LATCH_INT_EN;
1104 dev_err(dev, "Invalid interrupt type 0x%x specified\n",
1109 /* power is turned on inside check chip type*/
1110 result = inv_check_and_setup_chip(st);
1114 result = inv_mpu6050_init_config(indio_dev);
1116 dev_err(dev, "Could not initialize device.\n");
1120 if (inv_mpu_bus_setup)
1121 inv_mpu_bus_setup(indio_dev);
1123 dev_set_drvdata(dev, indio_dev);
1124 indio_dev->dev.parent = dev;
1125 /* name will be NULL when enumerated via ACPI */
1127 indio_dev->name = name;
1129 indio_dev->name = dev_name(dev);
1131 if (chip_type == INV_ICM20602) {
1132 indio_dev->channels = inv_icm20602_channels;
1133 indio_dev->num_channels = ARRAY_SIZE(inv_icm20602_channels);
1134 indio_dev->available_scan_masks = inv_icm20602_scan_masks;
1136 indio_dev->channels = inv_mpu_channels;
1137 indio_dev->num_channels = ARRAY_SIZE(inv_mpu_channels);
1138 indio_dev->available_scan_masks = inv_mpu_scan_masks;
1141 indio_dev->info = &mpu_info;
1142 indio_dev->modes = INDIO_BUFFER_TRIGGERED;
1144 result = devm_iio_triggered_buffer_setup(dev, indio_dev,
1145 iio_pollfunc_store_time,
1146 inv_mpu6050_read_fifo,
1149 dev_err(dev, "configure buffer fail %d\n", result);
1152 result = inv_mpu6050_probe_trigger(indio_dev, irq_type);
1154 dev_err(dev, "trigger probe fail %d\n", result);
1158 result = devm_iio_device_register(dev, indio_dev);
1160 dev_err(dev, "IIO register fail %d\n", result);
1166 EXPORT_SYMBOL_GPL(inv_mpu_core_probe);
1168 #ifdef CONFIG_PM_SLEEP
1170 static int inv_mpu_resume(struct device *dev)
1172 struct inv_mpu6050_state *st = iio_priv(dev_get_drvdata(dev));
1175 mutex_lock(&st->lock);
1176 result = inv_mpu6050_set_power_itg(st, true);
1177 mutex_unlock(&st->lock);
1182 static int inv_mpu_suspend(struct device *dev)
1184 struct inv_mpu6050_state *st = iio_priv(dev_get_drvdata(dev));
1187 mutex_lock(&st->lock);
1188 result = inv_mpu6050_set_power_itg(st, false);
1189 mutex_unlock(&st->lock);
1193 #endif /* CONFIG_PM_SLEEP */
1195 SIMPLE_DEV_PM_OPS(inv_mpu_pmops, inv_mpu_suspend, inv_mpu_resume);
1196 EXPORT_SYMBOL_GPL(inv_mpu_pmops);
1198 MODULE_AUTHOR("Invensense Corporation");
1199 MODULE_DESCRIPTION("Invensense device MPU6050 driver");
1200 MODULE_LICENSE("GPL");