drivers/iio/trigger/stm32-timer-trigger.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) STMicroelectronics 2016
   4  *
   5  * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
   6  *
   7  */
   8
   9 #include <linux/iio/iio.h>
  10 #include <linux/iio/sysfs.h>
  11 #include <linux/iio/timer/stm32-timer-trigger.h>
  12 #include <linux/iio/trigger.h>
  13 #include <linux/mfd/stm32-timers.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/of_device.h>
  17
  18 #define MAX_TRIGGERS 7
  19 #define MAX_VALIDS 5
  20
  21 /* List the triggers created by each timer */
  22 static const void *triggers_table[][MAX_TRIGGERS] = {
  23         { TIM1_TRGO, TIM1_TRGO2, TIM1_CH1, TIM1_CH2, TIM1_CH3, TIM1_CH4,},
  24         { TIM2_TRGO, TIM2_CH1, TIM2_CH2, TIM2_CH3, TIM2_CH4,},
  25         { TIM3_TRGO, TIM3_CH1, TIM3_CH2, TIM3_CH3, TIM3_CH4,},
  26         { TIM4_TRGO, TIM4_CH1, TIM4_CH2, TIM4_CH3, TIM4_CH4,},
  27         { TIM5_TRGO, TIM5_CH1, TIM5_CH2, TIM5_CH3, TIM5_CH4,},
  28         { TIM6_TRGO,},
  29         { TIM7_TRGO,},
  30         { TIM8_TRGO, TIM8_TRGO2, TIM8_CH1, TIM8_CH2, TIM8_CH3, TIM8_CH4,},
  31         { TIM9_TRGO, TIM9_CH1, TIM9_CH2,},
  32         { TIM10_OC1,},
  33         { TIM11_OC1,},
  34         { TIM12_TRGO, TIM12_CH1, TIM12_CH2,},
  35         { TIM13_OC1,},
  36         { TIM14_OC1,},
  37         { TIM15_TRGO,},
  38         { TIM16_OC1,},
  39         { TIM17_OC1,},
  40 };
  41
  42 /* List the triggers accepted by each timer */
  43 static const void *valids_table[][MAX_VALIDS] = {
  44         { TIM5_TRGO, TIM2_TRGO, TIM3_TRGO, TIM4_TRGO,},
  45         { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
  46         { TIM1_TRGO, TIM2_TRGO, TIM5_TRGO, TIM4_TRGO,},
  47         { TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,},
  48         { TIM2_TRGO, TIM3_TRGO, TIM4_TRGO, TIM8_TRGO,},
  49         { }, /* timer 6 */
  50         { }, /* timer 7 */
  51         { TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,},
  52         { TIM2_TRGO, TIM3_TRGO, TIM10_OC1, TIM11_OC1,},
  53         { }, /* timer 10 */
  54         { }, /* timer 11 */
  55         { TIM4_TRGO, TIM5_TRGO, TIM13_OC1, TIM14_OC1,},
  56 };
  57
  58 static const void *stm32h7_valids_table[][MAX_VALIDS] = {
  59         { TIM15_TRGO, TIM2_TRGO, TIM3_TRGO, TIM4_TRGO,},
  60         { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
  61         { TIM1_TRGO, TIM2_TRGO, TIM15_TRGO, TIM4_TRGO,},
  62         { TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,},
  63         { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
  64         { }, /* timer 6 */
  65         { }, /* timer 7 */
  66         { TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,},
  67         { }, /* timer 9 */
  68         { }, /* timer 10 */
  69         { }, /* timer 11 */
  70         { TIM4_TRGO, TIM5_TRGO, TIM13_OC1, TIM14_OC1,},
  71         { }, /* timer 13 */
  72         { }, /* timer 14 */
  73         { TIM1_TRGO, TIM3_TRGO, TIM16_OC1, TIM17_OC1,},
  74         { }, /* timer 16 */
  75         { }, /* timer 17 */
  76 };
  77
  78 struct stm32_timer_trigger {
  79         struct device *dev;
  80         struct regmap *regmap;
  81         struct clk *clk;
  82         u32 max_arr;
  83         const void *triggers;
  84         const void *valids;
  85         bool has_trgo2;
  86 };
  87
  88 struct stm32_timer_trigger_cfg {
  89         const void *(*valids_table)[MAX_VALIDS];
  90         const unsigned int num_valids_table;
  91 };
  92
  93 static bool stm32_timer_is_trgo2_name(const char *name)
  94 {
  95         return !!strstr(name, "trgo2");
  96 }
  97
  98 static bool stm32_timer_is_trgo_name(const char *name)
  99 {
 100         return (!!strstr(name, "trgo") && !strstr(name, "trgo2"));
 101 }
 102
 103 static int stm32_timer_start(struct stm32_timer_trigger *priv,
 104                              struct iio_trigger *trig,
 105                              unsigned int frequency)
 106 {
 107         unsigned long long prd, div;
 108         int prescaler = 0;
 109         u32 ccer, cr1;
 110
 111         /* Period and prescaler values depends of clock rate */
 112         div = (unsigned long long)clk_get_rate(priv->clk);
 113
 114         do_div(div, frequency);
 115
 116         prd = div;
 117
 118         /*
 119          * Increase prescaler value until we get a result that fit
 120          * with auto reload register maximum value.
 121          */
 122         while (div > priv->max_arr) {
 123                 prescaler++;
 124                 div = prd;
 125                 do_div(div, (prescaler + 1));
 126         }
 127         prd = div;
 128
 129         if (prescaler > MAX_TIM_PSC) {
 130                 dev_err(priv->dev, "prescaler exceeds the maximum value\n");
 131                 return -EINVAL;
 132         }
 133
 134         /* Check if nobody else use the timer */
 135         regmap_read(priv->regmap, TIM_CCER, &ccer);
 136         if (ccer & TIM_CCER_CCXE)
 137                 return -EBUSY;
 138
 139         regmap_read(priv->regmap, TIM_CR1, &cr1);
 140         if (!(cr1 & TIM_CR1_CEN))
 141                 clk_enable(priv->clk);
 142
 143         regmap_write(priv->regmap, TIM_PSC, prescaler);
 144         regmap_write(priv->regmap, TIM_ARR, prd - 1);
 145         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
 146
 147         /* Force master mode to update mode */
 148         if (stm32_timer_is_trgo2_name(trig->name))
 149                 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2,
 150                                    0x2 << TIM_CR2_MMS2_SHIFT);
 151         else
 152                 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS,
 153                                    0x2 << TIM_CR2_MMS_SHIFT);
 154
 155         /* Make sure that registers are updated */
 156         regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
 157
 158         /* Enable controller */
 159         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
 160
 161         return 0;
 162 }
 163
 164 static void stm32_timer_stop(struct stm32_timer_trigger *priv,
 165                              struct iio_trigger *trig)
 166 {
 167         u32 ccer, cr1;
 168
 169         regmap_read(priv->regmap, TIM_CCER, &ccer);
 170         if (ccer & TIM_CCER_CCXE)
 171                 return;
 172
 173         regmap_read(priv->regmap, TIM_CR1, &cr1);
 174         if (cr1 & TIM_CR1_CEN)
 175                 clk_disable(priv->clk);
 176
 177         /* Stop timer */
 178         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
 179         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
 180         regmap_write(priv->regmap, TIM_PSC, 0);
 181         regmap_write(priv->regmap, TIM_ARR, 0);
 182
 183         /* Force disable master mode */
 184         if (stm32_timer_is_trgo2_name(trig->name))
 185                 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0);
 186         else
 187                 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS, 0);
 188
 189         /* Make sure that registers are updated */
 190         regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
 191 }
 192
 193 static ssize_t stm32_tt_store_frequency(struct device *dev,
 194                                         struct device_attribute *attr,
 195                                         const char *buf, size_t len)
 196 {
 197         struct iio_trigger *trig = to_iio_trigger(dev);
 198         struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig);
 199         unsigned int freq;
 200         int ret;
 201
 202         ret = kstrtouint(buf, 10, &freq);
 203         if (ret)
 204                 return ret;
 205
 206         if (freq == 0) {
 207                 stm32_timer_stop(priv, trig);
 208         } else {
 209                 ret = stm32_timer_start(priv, trig, freq);
 210                 if (ret)
 211                         return ret;
 212         }
 213
 214         return len;
 215 }
 216
 217 static ssize_t stm32_tt_read_frequency(struct device *dev,
 218                                        struct device_attribute *attr, char *buf)
 219 {
 220         struct iio_trigger *trig = to_iio_trigger(dev);
 221         struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig);
 222         u32 psc, arr, cr1;
 223         unsigned long long freq = 0;
 224
 225         regmap_read(priv->regmap, TIM_CR1, &cr1);
 226         regmap_read(priv->regmap, TIM_PSC, &psc);
 227         regmap_read(priv->regmap, TIM_ARR, &arr);
 228
 229         if (cr1 & TIM_CR1_CEN) {
 230                 freq = (unsigned long long)clk_get_rate(priv->clk);
 231                 do_div(freq, psc + 1);
 232                 do_div(freq, arr + 1);
 233         }
 234
 235         return sprintf(buf, "%d\n", (unsigned int)freq);
 236 }
 237
 238 static IIO_DEV_ATTR_SAMP_FREQ(0660,
 239                               stm32_tt_read_frequency,
 240                               stm32_tt_store_frequency);
 241
 242 #define MASTER_MODE_MAX         7
 243 #define MASTER_MODE2_MAX        15
 244
 245 static char *master_mode_table[] = {
 246         "reset",
 247         "enable",
 248         "update",
 249         "compare_pulse",
 250         "OC1REF",
 251         "OC2REF",
 252         "OC3REF",
 253         "OC4REF",
 254         /* Master mode selection 2 only */
 255         "OC5REF",
 256         "OC6REF",
 257         "compare_pulse_OC4REF",
 258         "compare_pulse_OC6REF",
 259         "compare_pulse_OC4REF_r_or_OC6REF_r",
 260         "compare_pulse_OC4REF_r_or_OC6REF_f",
 261         "compare_pulse_OC5REF_r_or_OC6REF_r",
 262         "compare_pulse_OC5REF_r_or_OC6REF_f",
 263 };
 264
 265 static ssize_t stm32_tt_show_master_mode(struct device *dev,
 266                                          struct device_attribute *attr,
 267                                          char *buf)
 268 {
 269         struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
 270         struct iio_trigger *trig = to_iio_trigger(dev);
 271         u32 cr2;
 272
 273         regmap_read(priv->regmap, TIM_CR2, &cr2);
 274
 275         if (stm32_timer_is_trgo2_name(trig->name))
 276                 cr2 = (cr2 & TIM_CR2_MMS2) >> TIM_CR2_MMS2_SHIFT;
 277         else
 278                 cr2 = (cr2 & TIM_CR2_MMS) >> TIM_CR2_MMS_SHIFT;
 279
 280         return snprintf(buf, PAGE_SIZE, "%s\n", master_mode_table[cr2]);
 281 }
 282
 283 static ssize_t stm32_tt_store_master_mode(struct device *dev,
 284                                           struct device_attribute *attr,
 285                                           const char *buf, size_t len)
 286 {
 287         struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
 288         struct iio_trigger *trig = to_iio_trigger(dev);
 289         u32 mask, shift, master_mode_max;
 290         int i;
 291
 292         if (stm32_timer_is_trgo2_name(trig->name)) {
 293                 mask = TIM_CR2_MMS2;
 294                 shift = TIM_CR2_MMS2_SHIFT;
 295                 master_mode_max = MASTER_MODE2_MAX;
 296         } else {
 297                 mask = TIM_CR2_MMS;
 298                 shift = TIM_CR2_MMS_SHIFT;
 299                 master_mode_max = MASTER_MODE_MAX;
 300         }
 301
 302         for (i = 0; i <= master_mode_max; i++) {
 303                 if (!strncmp(master_mode_table[i], buf,
 304                              strlen(master_mode_table[i]))) {
 305                         regmap_update_bits(priv->regmap, TIM_CR2, mask,
 306                                            i << shift);
 307                         /* Make sure that registers are updated */
 308                         regmap_update_bits(priv->regmap, TIM_EGR,
 309                                            TIM_EGR_UG, TIM_EGR_UG);
 310                         return len;
 311                 }
 312         }
 313
 314         return -EINVAL;
 315 }
 316
 317 static ssize_t stm32_tt_show_master_mode_avail(struct device *dev,
 318                                                struct device_attribute *attr,
 319                                                char *buf)
 320 {
 321         struct iio_trigger *trig = to_iio_trigger(dev);
 322         unsigned int i, master_mode_max;
 323         size_t len = 0;
 324
 325         if (stm32_timer_is_trgo2_name(trig->name))
 326                 master_mode_max = MASTER_MODE2_MAX;
 327         else
 328                 master_mode_max = MASTER_MODE_MAX;
 329
 330         for (i = 0; i <= master_mode_max; i++)
 331                 len += scnprintf(buf + len, PAGE_SIZE - len,
 332                         "%s ", master_mode_table[i]);
 333
 334         /* replace trailing space by newline */
 335         buf[len - 1] = '\n';
 336
 337         return len;
 338 }
 339
 340 static IIO_DEVICE_ATTR(master_mode_available, 0444,
 341                        stm32_tt_show_master_mode_avail, NULL, 0);
 342
 343 static IIO_DEVICE_ATTR(master_mode, 0660,
 344                        stm32_tt_show_master_mode,
 345                        stm32_tt_store_master_mode,
 346                        0);
 347
 348 static struct attribute *stm32_trigger_attrs[] = {
 349         &iio_dev_attr_sampling_frequency.dev_attr.attr,
 350         &iio_dev_attr_master_mode.dev_attr.attr,
 351         &iio_dev_attr_master_mode_available.dev_attr.attr,
 352         NULL,
 353 };
 354
 355 static const struct attribute_group stm32_trigger_attr_group = {
 356         .attrs = stm32_trigger_attrs,
 357 };
 358
 359 static const struct attribute_group *stm32_trigger_attr_groups[] = {
 360         &stm32_trigger_attr_group,
 361         NULL,
 362 };
 363
 364 static const struct iio_trigger_ops timer_trigger_ops = {
 365 };
 366
 367 static int stm32_setup_iio_triggers(struct stm32_timer_trigger *priv)
 368 {
 369         int ret;
 370         const char * const *cur = priv->triggers;
 371
 372         while (cur && *cur) {
 373                 struct iio_trigger *trig;
 374                 bool cur_is_trgo = stm32_timer_is_trgo_name(*cur);
 375                 bool cur_is_trgo2 = stm32_timer_is_trgo2_name(*cur);
 376
 377                 if (cur_is_trgo2 && !priv->has_trgo2) {
 378                         cur++;
 379                         continue;
 380                 }
 381
 382                 trig = devm_iio_trigger_alloc(priv->dev, "%s", *cur);
 383                 if  (!trig)
 384                         return -ENOMEM;
 385
 386                 trig->dev.parent = priv->dev->parent;
 387                 trig->ops = &timer_trigger_ops;
 388
 389                 /*
 390                  * sampling frequency and master mode attributes
 391                  * should only be available on trgo/trgo2 triggers
 392                  */
 393                 if (cur_is_trgo || cur_is_trgo2)
 394                         trig->dev.groups = stm32_trigger_attr_groups;
 395
 396                 iio_trigger_set_drvdata(trig, priv);
 397
 398                 ret = devm_iio_trigger_register(priv->dev, trig);
 399                 if (ret)
 400                         return ret;
 401                 cur++;
 402         }
 403
 404         return 0;
 405 }
 406
 407 static int stm32_counter_read_raw(struct iio_dev *indio_dev,
 408                                   struct iio_chan_spec const *chan,
 409                                   int *val, int *val2, long mask)
 410 {
 411         struct stm32_timer_trigger *priv = iio_priv(indio_dev);
 412         u32 dat;
 413
 414         switch (mask) {
 415         case IIO_CHAN_INFO_RAW:
 416                 regmap_read(priv->regmap, TIM_CNT, &dat);
 417                 *val = dat;
 418                 return IIO_VAL_INT;
 419
 420         case IIO_CHAN_INFO_ENABLE:
 421                 regmap_read(priv->regmap, TIM_CR1, &dat);
 422                 *val = (dat & TIM_CR1_CEN) ? 1 : 0;
 423                 return IIO_VAL_INT;
 424
 425         case IIO_CHAN_INFO_SCALE:
 426                 regmap_read(priv->regmap, TIM_SMCR, &dat);
 427                 dat &= TIM_SMCR_SMS;
 428
 429                 *val = 1;
 430                 *val2 = 0;
 431
 432                 /* in quadrature case scale = 0.25 */
 433                 if (dat == 3)
 434                         *val2 = 2;
 435
 436                 return IIO_VAL_FRACTIONAL_LOG2;
 437         }
 438
 439         return -EINVAL;
 440 }
 441
 442 static int stm32_counter_write_raw(struct iio_dev *indio_dev,
 443                                    struct iio_chan_spec const *chan,
 444                                    int val, int val2, long mask)
 445 {
 446         struct stm32_timer_trigger *priv = iio_priv(indio_dev);
 447         u32 dat;
 448
 449         switch (mask) {
 450         case IIO_CHAN_INFO_RAW:
 451                 return regmap_write(priv->regmap, TIM_CNT, val);
 452
 453         case IIO_CHAN_INFO_SCALE:
 454                 /* fixed scale */
 455                 return -EINVAL;
 456
 457         case IIO_CHAN_INFO_ENABLE:
 458                 if (val) {
 459                         regmap_read(priv->regmap, TIM_CR1, &dat);
 460                         if (!(dat & TIM_CR1_CEN))
 461                                 clk_enable(priv->clk);
 462                         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
 463                                            TIM_CR1_CEN);
 464                 } else {
 465                         regmap_read(priv->regmap, TIM_CR1, &dat);
 466                         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
 467                                            0);
 468                         if (dat & TIM_CR1_CEN)
 469                                 clk_disable(priv->clk);
 470                 }
 471                 return 0;
 472         }
 473
 474         return -EINVAL;
 475 }
 476
 477 static int stm32_counter_validate_trigger(struct iio_dev *indio_dev,
 478                                           struct iio_trigger *trig)
 479 {
 480         struct stm32_timer_trigger *priv = iio_priv(indio_dev);
 481         const char * const *cur = priv->valids;
 482         unsigned int i = 0;
 483
 484         if (!is_stm32_timer_trigger(trig))
 485                 return -EINVAL;
 486
 487         while (cur && *cur) {
 488                 if (!strncmp(trig->name, *cur, strlen(trig->name))) {
 489                         regmap_update_bits(priv->regmap,
 490                                            TIM_SMCR, TIM_SMCR_TS,
 491                                            i << TIM_SMCR_TS_SHIFT);
 492                         return 0;
 493                 }
 494                 cur++;
 495                 i++;
 496         }
 497
 498         return -EINVAL;
 499 }
 500
 501 static const struct iio_info stm32_trigger_info = {
 502         .validate_trigger = stm32_counter_validate_trigger,
 503         .read_raw = stm32_counter_read_raw,
 504         .write_raw = stm32_counter_write_raw
 505 };
 506
 507 static const char *const stm32_trigger_modes[] = {
 508         "trigger",
 509 };
 510
 511 static int stm32_set_trigger_mode(struct iio_dev *indio_dev,
 512                                   const struct iio_chan_spec *chan,
 513                                   unsigned int mode)
 514 {
 515         struct stm32_timer_trigger *priv = iio_priv(indio_dev);
 516
 517         regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, TIM_SMCR_SMS);
 518
 519         return 0;
 520 }
 521
 522 static int stm32_get_trigger_mode(struct iio_dev *indio_dev,
 523                                   const struct iio_chan_spec *chan)
 524 {
 525         struct stm32_timer_trigger *priv = iio_priv(indio_dev);
 526         u32 smcr;
 527
 528         regmap_read(priv->regmap, TIM_SMCR, &smcr);
 529
 530         return (smcr & TIM_SMCR_SMS) == TIM_SMCR_SMS ? 0 : -EINVAL;
 531 }
 532
 533 static const struct iio_enum stm32_trigger_mode_enum = {
 534         .items = stm32_trigger_modes,
 535         .num_items = ARRAY_SIZE(stm32_trigger_modes),
 536         .set = stm32_set_trigger_mode,
 537         .get = stm32_get_trigger_mode
 538 };
 539
 540 static const char *const stm32_enable_modes[] = {
 541         "always",
 542         "gated",
 543         "triggered",
 544 };
 545
 546 static int stm32_enable_mode2sms(int mode)
 547 {
 548         switch (mode) {
 549         case 0:
 550                 return 0;
 551         case 1:
 552                 return 5;
 553         case 2:
 554                 return 6;
 555         }
 556
 557         return -EINVAL;
 558 }
 559
 560 static int stm32_set_enable_mode(struct iio_dev *indio_dev,
 561                                  const struct iio_chan_spec *chan,
 562                                  unsigned int mode)
 563 {
 564         struct stm32_timer_trigger *priv = iio_priv(indio_dev);
 565         int sms = stm32_enable_mode2sms(mode);
 566         u32 val;
 567
 568         if (sms < 0)
 569                 return sms;
 570         /*
 571          * Triggered mode sets CEN bit automatically by hardware. So, first
 572          * enable counter clock, so it can use it. Keeps it in sync with CEN.
 573          */
 574         if (sms == 6) {
 575                 regmap_read(priv->regmap, TIM_CR1, &val);
 576                 if (!(val & TIM_CR1_CEN))
 577                         clk_enable(priv->clk);
 578         }
 579
 580         regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms);
 581
 582         return 0;
 583 }
 584
 585 static int stm32_sms2enable_mode(int mode)
 586 {
 587         switch (mode) {
 588         case 0:
 589                 return 0;
 590         case 5:
 591                 return 1;
 592         case 6:
 593                 return 2;
 594         }
 595
 596         return -EINVAL;
 597 }
 598
 599 static int stm32_get_enable_mode(struct iio_dev *indio_dev,
 600                                  const struct iio_chan_spec *chan)
 601 {
 602         struct stm32_timer_trigger *priv = iio_priv(indio_dev);
 603         u32 smcr;
 604
 605         regmap_read(priv->regmap, TIM_SMCR, &smcr);
 606         smcr &= TIM_SMCR_SMS;
 607
 608         return stm32_sms2enable_mode(smcr);
 609 }
 610
 611 static const struct iio_enum stm32_enable_mode_enum = {
 612         .items = stm32_enable_modes,
 613         .num_items = ARRAY_SIZE(stm32_enable_modes),
 614         .set = stm32_set_enable_mode,
 615         .get = stm32_get_enable_mode
 616 };
 617
 618 static const char *const stm32_quadrature_modes[] = {
 619         "channel_A",
 620         "channel_B",
 621         "quadrature",
 622 };
 623
 624 static int stm32_set_quadrature_mode(struct iio_dev *indio_dev,
 625                                      const struct iio_chan_spec *chan,
 626                                      unsigned int mode)
 627 {
 628         struct stm32_timer_trigger *priv = iio_priv(indio_dev);
 629
 630         regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, mode + 1);
 631
 632         return 0;
 633 }
 634
 635 static int stm32_get_quadrature_mode(struct iio_dev *indio_dev,
 636                                      const struct iio_chan_spec *chan)
 637 {
 638         struct stm32_timer_trigger *priv = iio_priv(indio_dev);
 639         u32 smcr;
 640         int mode;
 641
 642         regmap_read(priv->regmap, TIM_SMCR, &smcr);
 643         mode = (smcr & TIM_SMCR_SMS) - 1;
 644         if ((mode < 0) || (mode > ARRAY_SIZE(stm32_quadrature_modes)))
 645                 return -EINVAL;
 646
 647         return mode;
 648 }
 649
 650 static const struct iio_enum stm32_quadrature_mode_enum = {
 651         .items = stm32_quadrature_modes,
 652         .num_items = ARRAY_SIZE(stm32_quadrature_modes),
 653         .set = stm32_set_quadrature_mode,
 654         .get = stm32_get_quadrature_mode
 655 };
 656
 657 static const char *const stm32_count_direction_states[] = {
 658         "up",
 659         "down"
 660 };
 661
 662 static int stm32_set_count_direction(struct iio_dev *indio_dev,
 663                                      const struct iio_chan_spec *chan,
 664                                      unsigned int dir)
 665 {
 666         struct stm32_timer_trigger *priv = iio_priv(indio_dev);
 667         u32 val;
 668         int mode;
 669
 670         /* In encoder mode, direction is RO (given by TI1/TI2 signals) */
 671         regmap_read(priv->regmap, TIM_SMCR, &val);
 672         mode = (val & TIM_SMCR_SMS) - 1;
 673         if ((mode >= 0) || (mode < ARRAY_SIZE(stm32_quadrature_modes)))
 674                 return -EBUSY;
 675
 676         return regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_DIR,
 677                                   dir ? TIM_CR1_DIR : 0);
 678 }
 679
 680 static int stm32_get_count_direction(struct iio_dev *indio_dev,
 681                                      const struct iio_chan_spec *chan)
 682 {
 683         struct stm32_timer_trigger *priv = iio_priv(indio_dev);
 684         u32 cr1;
 685
 686         regmap_read(priv->regmap, TIM_CR1, &cr1);
 687
 688         return ((cr1 & TIM_CR1_DIR) ? 1 : 0);
 689 }
 690
 691 static const struct iio_enum stm32_count_direction_enum = {
 692         .items = stm32_count_direction_states,
 693         .num_items = ARRAY_SIZE(stm32_count_direction_states),
 694         .set = stm32_set_count_direction,
 695         .get = stm32_get_count_direction
 696 };
 697
 698 static ssize_t stm32_count_get_preset(struct iio_dev *indio_dev,
 699                                       uintptr_t private,
 700                                       const struct iio_chan_spec *chan,
 701                                       char *buf)
 702 {
 703         struct stm32_timer_trigger *priv = iio_priv(indio_dev);
 704         u32 arr;
 705
 706         regmap_read(priv->regmap, TIM_ARR, &arr);
 707
 708         return snprintf(buf, PAGE_SIZE, "%u\n", arr);
 709 }
 710
 711 static ssize_t stm32_count_set_preset(struct iio_dev *indio_dev,
 712                                       uintptr_t private,
 713                                       const struct iio_chan_spec *chan,
 714                                       const char *buf, size_t len)
 715 {
 716         struct stm32_timer_trigger *priv = iio_priv(indio_dev);
 717         unsigned int preset;
 718         int ret;
 719
 720         ret = kstrtouint(buf, 0, &preset);
 721         if (ret)
 722                 return ret;
 723
 724         /* TIMx_ARR register shouldn't be buffered (ARPE=0) */
 725         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
 726         regmap_write(priv->regmap, TIM_ARR, preset);
 727
 728         return len;
 729 }
 730
 731 static const struct iio_chan_spec_ext_info stm32_trigger_count_info[] = {
 732         {
 733                 .name = "preset",
 734                 .shared = IIO_SEPARATE,
 735                 .read = stm32_count_get_preset,
 736                 .write = stm32_count_set_preset
 737         },
 738         IIO_ENUM("count_direction", IIO_SEPARATE, &stm32_count_direction_enum),
 739         IIO_ENUM_AVAILABLE("count_direction", &stm32_count_direction_enum),
 740         IIO_ENUM("quadrature_mode", IIO_SEPARATE, &stm32_quadrature_mode_enum),
 741         IIO_ENUM_AVAILABLE("quadrature_mode", &stm32_quadrature_mode_enum),
 742         IIO_ENUM("enable_mode", IIO_SEPARATE, &stm32_enable_mode_enum),
 743         IIO_ENUM_AVAILABLE("enable_mode", &stm32_enable_mode_enum),
 744         IIO_ENUM("trigger_mode", IIO_SEPARATE, &stm32_trigger_mode_enum),
 745         IIO_ENUM_AVAILABLE("trigger_mode", &stm32_trigger_mode_enum),
 746         {}
 747 };
 748
 749 static const struct iio_chan_spec stm32_trigger_channel = {
 750         .type = IIO_COUNT,
 751         .channel = 0,
 752         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
 753                               BIT(IIO_CHAN_INFO_ENABLE) |
 754                               BIT(IIO_CHAN_INFO_SCALE),
 755         .ext_info = stm32_trigger_count_info,
 756         .indexed = 1
 757 };
 758
 759 static struct stm32_timer_trigger *stm32_setup_counter_device(struct device *dev)
 760 {
 761         struct iio_dev *indio_dev;
 762         int ret;
 763
 764         indio_dev = devm_iio_device_alloc(dev,
 765                                           sizeof(struct stm32_timer_trigger));
 766         if (!indio_dev)
 767                 return NULL;
 768
 769         indio_dev->name = dev_name(dev);
 770         indio_dev->dev.parent = dev;
 771         indio_dev->info = &stm32_trigger_info;
 772         indio_dev->modes = INDIO_HARDWARE_TRIGGERED;
 773         indio_dev->num_channels = 1;
 774         indio_dev->channels = &stm32_trigger_channel;
 775         indio_dev->dev.of_node = dev->of_node;
 776
 777         ret = devm_iio_device_register(dev, indio_dev);
 778         if (ret)
 779                 return NULL;
 780
 781         return iio_priv(indio_dev);
 782 }
 783
 784 /**
 785  * is_stm32_timer_trigger
 786  * @trig: trigger to be checked
 787  *
 788  * return true if the trigger is a valid stm32 iio timer trigger
 789  * either return false
 790  */
 791 bool is_stm32_timer_trigger(struct iio_trigger *trig)
 792 {
 793         return (trig->ops == &timer_trigger_ops);
 794 }
 795 EXPORT_SYMBOL(is_stm32_timer_trigger);
 796
 797 static void stm32_timer_detect_trgo2(struct stm32_timer_trigger *priv)
 798 {
 799         u32 val;
 800
 801         /*
 802          * Master mode selection 2 bits can only be written and read back when
 803          * timer supports it.
 804          */
 805         regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, TIM_CR2_MMS2);
 806         regmap_read(priv->regmap, TIM_CR2, &val);
 807         regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0);
 808         priv->has_trgo2 = !!val;
 809 }
 810
 811 static int stm32_timer_trigger_probe(struct platform_device *pdev)
 812 {
 813         struct device *dev = &pdev->dev;
 814         struct stm32_timer_trigger *priv;
 815         struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
 816         const struct stm32_timer_trigger_cfg *cfg;
 817         unsigned int index;
 818         int ret;
 819
 820         if (of_property_read_u32(dev->of_node, "reg", &index))
 821                 return -EINVAL;
 822
 823         cfg = (const struct stm32_timer_trigger_cfg *)
 824                 of_match_device(dev->driver->of_match_table, dev)->data;
 825
 826         if (index >= ARRAY_SIZE(triggers_table) ||
 827             index >= cfg->num_valids_table)
 828                 return -EINVAL;
 829
 830         /* Create an IIO device only if we have triggers to be validated */
 831         if (*cfg->valids_table[index])
 832                 priv = stm32_setup_counter_device(dev);
 833         else
 834                 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 835
 836         if (!priv)
 837                 return -ENOMEM;
 838
 839         priv->dev = dev;
 840         priv->regmap = ddata->regmap;
 841         priv->clk = ddata->clk;
 842         priv->max_arr = ddata->max_arr;
 843         priv->triggers = triggers_table[index];
 844         priv->valids = cfg->valids_table[index];
 845         stm32_timer_detect_trgo2(priv);
 846
 847         ret = stm32_setup_iio_triggers(priv);
 848         if (ret)
 849                 return ret;
 850
 851         platform_set_drvdata(pdev, priv);
 852
 853         return 0;
 854 }
 855
 856 static const struct stm32_timer_trigger_cfg stm32_timer_trg_cfg = {
 857         .valids_table = valids_table,
 858         .num_valids_table = ARRAY_SIZE(valids_table),
 859 };
 860
 861 static const struct stm32_timer_trigger_cfg stm32h7_timer_trg_cfg = {
 862         .valids_table = stm32h7_valids_table,
 863         .num_valids_table = ARRAY_SIZE(stm32h7_valids_table),
 864 };
 865
 866 static const struct of_device_id stm32_trig_of_match[] = {
 867         {
 868                 .compatible = "st,stm32-timer-trigger",
 869                 .data = (void *)&stm32_timer_trg_cfg,
 870         }, {
 871                 .compatible = "st,stm32h7-timer-trigger",
 872                 .data = (void *)&stm32h7_timer_trg_cfg,
 873         },
 874         { /* end node */ },
 875 };
 876 MODULE_DEVICE_TABLE(of, stm32_trig_of_match);
 877
 878 static struct platform_driver stm32_timer_trigger_driver = {
 879         .probe = stm32_timer_trigger_probe,
 880         .driver = {
 881                 .name = "stm32-timer-trigger",
 882                 .of_match_table = stm32_trig_of_match,
 883         },
 884 };
 885 module_platform_driver(stm32_timer_trigger_driver);
 886
 887 MODULE_ALIAS("platform:stm32-timer-trigger");
 888 MODULE_DESCRIPTION("STMicroelectronics STM32 Timer Trigger driver");
 889 MODULE_LICENSE("GPL v2");