drivers/infiniband/hw/bnxt_re/qplib_rcfw.c

   1 /*
   2  * Broadcom NetXtreme-E RoCE driver.
   3  *
   4  * Copyright (c) 2016 - 2017, Broadcom. All rights reserved.  The term
   5  * Broadcom refers to Broadcom Limited and/or its subsidiaries.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * BSD license below:
  12  *
  13  * Redistribution and use in source and binary forms, with or without
  14  * modification, are permitted provided that the following conditions
  15  * are met:
  16  *
  17  * 1. Redistributions of source code must retain the above copyright
  18  *    notice, this list of conditions and the following disclaimer.
  19  * 2. Redistributions in binary form must reproduce the above copyright
  20  *    notice, this list of conditions and the following disclaimer in
  21  *    the documentation and/or other materials provided with the
  22  *    distribution.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
  25  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
  28  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  29  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  31  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  32  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  33  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  34  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  *
  36  * Description: RDMA Controller HW interface
  37  */
  38 #include <linux/interrupt.h>
  39 #include <linux/spinlock.h>
  40 #include <linux/pci.h>
  41 #include <linux/prefetch.h>
  42 #include <linux/delay.h>
  43
  44 #include "roce_hsi.h"
  45 #include "qplib_res.h"
  46 #include "qplib_rcfw.h"
  47 #include "qplib_sp.h"
  48 #include "qplib_fp.h"
  49
  50 static void bnxt_qplib_service_creq(unsigned long data);
  51
  52 /* Hardware communication channel */
  53 static int __wait_for_resp(struct bnxt_qplib_rcfw *rcfw, u16 cookie)
  54 {
  55         u16 cbit;
  56         int rc;
  57
  58         cbit = cookie % RCFW_MAX_OUTSTANDING_CMD;
  59         rc = wait_event_timeout(rcfw->waitq,
  60                                 !test_bit(cbit, rcfw->cmdq_bitmap),
  61                                 msecs_to_jiffies(RCFW_CMD_WAIT_TIME_MS));
  62         return rc ? 0 : -ETIMEDOUT;
  63 };
  64
  65 static int __block_for_resp(struct bnxt_qplib_rcfw *rcfw, u16 cookie)
  66 {
  67         u32 count = RCFW_BLOCKED_CMD_WAIT_COUNT;
  68         u16 cbit;
  69
  70         cbit = cookie % RCFW_MAX_OUTSTANDING_CMD;
  71         if (!test_bit(cbit, rcfw->cmdq_bitmap))
  72                 goto done;
  73         do {
  74                 mdelay(1); /* 1m sec */
  75                 bnxt_qplib_service_creq((unsigned long)rcfw);
  76         } while (test_bit(cbit, rcfw->cmdq_bitmap) && --count);
  77 done:
  78         return count ? 0 : -ETIMEDOUT;
  79 };
  80
  81 static int __send_message(struct bnxt_qplib_rcfw *rcfw, struct cmdq_base *req,
  82                           struct creq_base *resp, void *sb, u8 is_block)
  83 {
  84         struct bnxt_qplib_cmdqe *cmdqe, **cmdq_ptr;
  85         struct bnxt_qplib_hwq *cmdq = &rcfw->cmdq;
  86         struct bnxt_qplib_crsq *crsqe;
  87         u32 sw_prod, cmdq_prod;
  88         unsigned long flags;
  89         u32 size, opcode;
  90         u16 cookie, cbit;
  91         int pg, idx;
  92         u8 *preq;
  93
  94         opcode = req->opcode;
  95         if (!test_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->flags) &&
  96             (opcode != CMDQ_BASE_OPCODE_QUERY_FUNC &&
  97              opcode != CMDQ_BASE_OPCODE_INITIALIZE_FW)) {
  98                 dev_err(&rcfw->pdev->dev,
  99                         "QPLIB: RCFW not initialized, reject opcode 0x%x",
 100                         opcode);
 101                 return -EINVAL;
 102         }
 103
 104         if (test_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->flags) &&
 105             opcode == CMDQ_BASE_OPCODE_INITIALIZE_FW) {
 106                 dev_err(&rcfw->pdev->dev, "QPLIB: RCFW already initialized!");
 107                 return -EINVAL;
 108         }
 109
 110         if (test_bit(FIRMWARE_TIMED_OUT, &rcfw->flags))
 111                 return -ETIMEDOUT;
 112
 113         /* Cmdq are in 16-byte units, each request can consume 1 or more
 114          * cmdqe
 115          */
 116         spin_lock_irqsave(&cmdq->lock, flags);
 117         if (req->cmd_size >= HWQ_FREE_SLOTS(cmdq)) {
 118                 dev_err(&rcfw->pdev->dev, "QPLIB: RCFW: CMDQ is full!");
 119                 spin_unlock_irqrestore(&cmdq->lock, flags);
 120                 return -EAGAIN;
 121         }
 122
 123
 124         cookie = rcfw->seq_num & RCFW_MAX_COOKIE_VALUE;
 125         cbit = cookie % RCFW_MAX_OUTSTANDING_CMD;
 126         if (is_block)
 127                 cookie |= RCFW_CMD_IS_BLOCKING;
 128
 129         set_bit(cbit, rcfw->cmdq_bitmap);
 130         req->cookie = cpu_to_le16(cookie);
 131         crsqe = &rcfw->crsqe_tbl[cbit];
 132         if (crsqe->resp) {
 133                 spin_unlock_irqrestore(&cmdq->lock, flags);
 134                 return -EBUSY;
 135         }
 136         memset(resp, 0, sizeof(*resp));
 137         crsqe->resp = (struct creq_qp_event *)resp;
 138         crsqe->resp->cookie = req->cookie;
 139         crsqe->req_size = req->cmd_size;
 140         if (req->resp_size && sb) {
 141                 struct bnxt_qplib_rcfw_sbuf *sbuf = sb;
 142
 143                 req->resp_addr = cpu_to_le64(sbuf->dma_addr);
 144                 req->resp_size = (sbuf->size + BNXT_QPLIB_CMDQE_UNITS - 1) /
 145                                   BNXT_QPLIB_CMDQE_UNITS;
 146         }
 147
 148         cmdq_ptr = (struct bnxt_qplib_cmdqe **)cmdq->pbl_ptr;
 149         preq = (u8 *)req;
 150         size = req->cmd_size * BNXT_QPLIB_CMDQE_UNITS;
 151         do {
 152                 pg = 0;
 153                 idx = 0;
 154
 155                 /* Locate the next cmdq slot */
 156                 sw_prod = HWQ_CMP(cmdq->prod, cmdq);
 157                 cmdqe = &cmdq_ptr[get_cmdq_pg(sw_prod)][get_cmdq_idx(sw_prod)];
 158                 if (!cmdqe) {
 159                         dev_err(&rcfw->pdev->dev,
 160                                 "QPLIB: RCFW request failed with no cmdqe!");
 161                         goto done;
 162                 }
 163                 /* Copy a segment of the req cmd to the cmdq */
 164                 memset(cmdqe, 0, sizeof(*cmdqe));
 165                 memcpy(cmdqe, preq, min_t(u32, size, sizeof(*cmdqe)));
 166                 preq += min_t(u32, size, sizeof(*cmdqe));
 167                 size -= min_t(u32, size, sizeof(*cmdqe));
 168                 cmdq->prod++;
 169                 rcfw->seq_num++;
 170         } while (size > 0);
 171
 172         rcfw->seq_num++;
 173
 174         cmdq_prod = cmdq->prod;
 175         if (rcfw->flags & FIRMWARE_FIRST_FLAG) {
 176                 /* The very first doorbell write
 177                  * is required to set this flag
 178                  * which prompts the FW to reset
 179                  * its internal pointers
 180                  */
 181                 cmdq_prod |= FIRMWARE_FIRST_FLAG;
 182                 rcfw->flags &= ~FIRMWARE_FIRST_FLAG;
 183         }
 184
 185         /* ring CMDQ DB */
 186         wmb();
 187         writel(cmdq_prod, rcfw->cmdq_bar_reg_iomem +
 188                rcfw->cmdq_bar_reg_prod_off);
 189         writel(RCFW_CMDQ_TRIG_VAL, rcfw->cmdq_bar_reg_iomem +
 190                rcfw->cmdq_bar_reg_trig_off);
 191 done:
 192         spin_unlock_irqrestore(&cmdq->lock, flags);
 193         /* Return the CREQ response pointer */
 194         return 0;
 195 }
 196
 197 int bnxt_qplib_rcfw_send_message(struct bnxt_qplib_rcfw *rcfw,
 198                                  struct cmdq_base *req,
 199                                  struct creq_base *resp,
 200                                  void *sb, u8 is_block)
 201 {
 202         struct creq_qp_event *evnt = (struct creq_qp_event *)resp;
 203         u16 cookie;
 204         u8 opcode, retry_cnt = 0xFF;
 205         int rc = 0;
 206
 207         do {
 208                 opcode = req->opcode;
 209                 rc = __send_message(rcfw, req, resp, sb, is_block);
 210                 cookie = le16_to_cpu(req->cookie) & RCFW_MAX_COOKIE_VALUE;
 211                 if (!rc)
 212                         break;
 213
 214                 if (!retry_cnt || (rc != -EAGAIN && rc != -EBUSY)) {
 215                         /* send failed */
 216                         dev_err(&rcfw->pdev->dev, "QPLIB: cmdq[%#x]=%#x send failed",
 217                                 cookie, opcode);
 218                         return rc;
 219                 }
 220                 is_block ? mdelay(1) : usleep_range(500, 1000);
 221
 222         } while (retry_cnt--);
 223
 224         if (is_block)
 225                 rc = __block_for_resp(rcfw, cookie);
 226         else
 227                 rc = __wait_for_resp(rcfw, cookie);
 228         if (rc) {
 229                 /* timed out */
 230                 dev_err(&rcfw->pdev->dev, "QPLIB: cmdq[%#x]=%#x timedout (%d)msec",
 231                         cookie, opcode, RCFW_CMD_WAIT_TIME_MS);
 232                 set_bit(FIRMWARE_TIMED_OUT, &rcfw->flags);
 233                 return rc;
 234         }
 235
 236         if (evnt->status) {
 237                 /* failed with status */
 238                 dev_err(&rcfw->pdev->dev, "QPLIB: cmdq[%#x]=%#x status %#x",
 239                         cookie, opcode, evnt->status);
 240                 rc = -EFAULT;
 241         }
 242
 243         return rc;
 244 }
 245 /* Completions */
 246 static int bnxt_qplib_process_func_event(struct bnxt_qplib_rcfw *rcfw,
 247                                          struct creq_func_event *func_event)
 248 {
 249         switch (func_event->event) {
 250         case CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR:
 251                 break;
 252         case CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR:
 253                 break;
 254         case CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR:
 255                 break;
 256         case CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR:
 257                 break;
 258         case CREQ_FUNC_EVENT_EVENT_CQ_ERROR:
 259                 break;
 260         case CREQ_FUNC_EVENT_EVENT_TQM_ERROR:
 261                 break;
 262         case CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR:
 263                 break;
 264         case CREQ_FUNC_EVENT_EVENT_CFCS_ERROR:
 265                 /* SRQ ctx error, call srq_handler??
 266                  * But there's no SRQ handle!
 267                  */
 268                 break;
 269         case CREQ_FUNC_EVENT_EVENT_CFCC_ERROR:
 270                 break;
 271         case CREQ_FUNC_EVENT_EVENT_CFCM_ERROR:
 272                 break;
 273         case CREQ_FUNC_EVENT_EVENT_TIM_ERROR:
 274                 break;
 275         case CREQ_FUNC_EVENT_EVENT_VF_COMM_REQUEST:
 276                 break;
 277         case CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED:
 278                 break;
 279         default:
 280                 return -EINVAL;
 281         }
 282         return 0;
 283 }
 284
 285 static int bnxt_qplib_process_qp_event(struct bnxt_qplib_rcfw *rcfw,
 286                                        struct creq_qp_event *qp_event)
 287 {
 288         struct bnxt_qplib_hwq *cmdq = &rcfw->cmdq;
 289         struct creq_qp_error_notification *err_event;
 290         struct bnxt_qplib_crsq *crsqe;
 291         unsigned long flags;
 292         struct bnxt_qplib_qp *qp;
 293         u16 cbit, blocked = 0;
 294         u16 cookie;
 295         __le16  mcookie;
 296         u32 qp_id;
 297
 298         switch (qp_event->event) {
 299         case CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION:
 300                 err_event = (struct creq_qp_error_notification *)qp_event;
 301                 qp_id = le32_to_cpu(err_event->xid);
 302                 qp = rcfw->qp_tbl[qp_id].qp_handle;
 303                 dev_dbg(&rcfw->pdev->dev,
 304                         "QPLIB: Received QP error notification");
 305                 dev_dbg(&rcfw->pdev->dev,
 306                         "QPLIB: qpid 0x%x, req_err=0x%x, resp_err=0x%x\n",
 307                         qp_id, err_event->req_err_state_reason,
 308                         err_event->res_err_state_reason);
 309                 bnxt_qplib_acquire_cq_locks(qp, &flags);
 310                 bnxt_qplib_mark_qp_error(qp);
 311                 bnxt_qplib_release_cq_locks(qp, &flags);
 312                 break;
 313         default:
 314                 /*
 315                  * Command Response
 316                  * cmdq->lock needs to be acquired to synchronie
 317                  * the command send and completion reaping. This function
 318                  * is always called with creq->lock held. Using
 319                  * the nested variant of spin_lock.
 320                  *
 321                  */
 322
 323                 spin_lock_irqsave_nested(&cmdq->lock, flags,
 324                                          SINGLE_DEPTH_NESTING);
 325                 cookie = le16_to_cpu(qp_event->cookie);
 326                 mcookie = qp_event->cookie;
 327                 blocked = cookie & RCFW_CMD_IS_BLOCKING;
 328                 cookie &= RCFW_MAX_COOKIE_VALUE;
 329                 cbit = cookie % RCFW_MAX_OUTSTANDING_CMD;
 330                 crsqe = &rcfw->crsqe_tbl[cbit];
 331                 if (crsqe->resp &&
 332                     crsqe->resp->cookie  == mcookie) {
 333                         memcpy(crsqe->resp, qp_event, sizeof(*qp_event));
 334                         crsqe->resp = NULL;
 335                 } else {
 336                         dev_err(&rcfw->pdev->dev,
 337                                 "QPLIB: CMD %s resp->cookie = %#x, evnt->cookie = %#x",
 338                                 crsqe->resp ? "mismatch" : "collision",
 339                                 crsqe->resp ? crsqe->resp->cookie : 0, mcookie);
 340                 }
 341                 if (!test_and_clear_bit(cbit, rcfw->cmdq_bitmap))
 342                         dev_warn(&rcfw->pdev->dev,
 343                                  "QPLIB: CMD bit %d was not requested", cbit);
 344                 cmdq->cons += crsqe->req_size;
 345                 crsqe->req_size = 0;
 346
 347                 if (!blocked)
 348                         wake_up(&rcfw->waitq);
 349                 spin_unlock_irqrestore(&cmdq->lock, flags);
 350         }
 351         return 0;
 352 }
 353
 354 /* SP - CREQ Completion handlers */
 355 static void bnxt_qplib_service_creq(unsigned long data)
 356 {
 357         struct bnxt_qplib_rcfw *rcfw = (struct bnxt_qplib_rcfw *)data;
 358         struct bnxt_qplib_hwq *creq = &rcfw->creq;
 359         struct creq_base *creqe, **creq_ptr;
 360         u32 sw_cons, raw_cons;
 361         unsigned long flags;
 362         u32 type, budget = CREQ_ENTRY_POLL_BUDGET;
 363
 364         /* Service the CREQ until budget is over */
 365         spin_lock_irqsave(&creq->lock, flags);
 366         raw_cons = creq->cons;
 367         while (budget > 0) {
 368                 sw_cons = HWQ_CMP(raw_cons, creq);
 369                 creq_ptr = (struct creq_base **)creq->pbl_ptr;
 370                 creqe = &creq_ptr[get_creq_pg(sw_cons)][get_creq_idx(sw_cons)];
 371                 if (!CREQ_CMP_VALID(creqe, raw_cons, creq->max_elements))
 372                         break;
 373
 374                 type = creqe->type & CREQ_BASE_TYPE_MASK;
 375                 switch (type) {
 376                 case CREQ_BASE_TYPE_QP_EVENT:
 377                         bnxt_qplib_process_qp_event
 378                                 (rcfw, (struct creq_qp_event *)creqe);
 379                         rcfw->creq_qp_event_processed++;
 380                         break;
 381                 case CREQ_BASE_TYPE_FUNC_EVENT:
 382                         if (!bnxt_qplib_process_func_event
 383                             (rcfw, (struct creq_func_event *)creqe))
 384                                 rcfw->creq_func_event_processed++;
 385                         else
 386                                 dev_warn
 387                                 (&rcfw->pdev->dev, "QPLIB:aeqe:%#x Not handled",
 388                                  type);
 389                         break;
 390                 default:
 391                         dev_warn(&rcfw->pdev->dev, "QPLIB: creqe with ");
 392                         dev_warn(&rcfw->pdev->dev,
 393                                  "QPLIB: op_event = 0x%x not handled", type);
 394                         break;
 395                 }
 396                 raw_cons++;
 397                 budget--;
 398         }
 399
 400         if (creq->cons != raw_cons) {
 401                 creq->cons = raw_cons;
 402                 CREQ_DB_REARM(rcfw->creq_bar_reg_iomem, raw_cons,
 403                               creq->max_elements);
 404         }
 405         spin_unlock_irqrestore(&creq->lock, flags);
 406 }
 407
 408 static irqreturn_t bnxt_qplib_creq_irq(int irq, void *dev_instance)
 409 {
 410         struct bnxt_qplib_rcfw *rcfw = dev_instance;
 411         struct bnxt_qplib_hwq *creq = &rcfw->creq;
 412         struct creq_base **creq_ptr;
 413         u32 sw_cons;
 414
 415         /* Prefetch the CREQ element */
 416         sw_cons = HWQ_CMP(creq->cons, creq);
 417         creq_ptr = (struct creq_base **)rcfw->creq.pbl_ptr;
 418         prefetch(&creq_ptr[get_creq_pg(sw_cons)][get_creq_idx(sw_cons)]);
 419
 420         tasklet_schedule(&rcfw->worker);
 421
 422         return IRQ_HANDLED;
 423 }
 424
 425 /* RCFW */
 426 int bnxt_qplib_deinit_rcfw(struct bnxt_qplib_rcfw *rcfw)
 427 {
 428         struct cmdq_deinitialize_fw req;
 429         struct creq_deinitialize_fw_resp resp;
 430         u16 cmd_flags = 0;
 431         int rc;
 432
 433         RCFW_CMD_PREP(req, DEINITIALIZE_FW, cmd_flags);
 434         rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, (void *)&resp,
 435                                           NULL, 0);
 436         if (rc)
 437                 return rc;
 438
 439         clear_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->flags);
 440         return 0;
 441 }
 442
 443 static int __get_pbl_pg_idx(struct bnxt_qplib_pbl *pbl)
 444 {
 445         return (pbl->pg_size == ROCE_PG_SIZE_4K ?
 446                                       CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_4K :
 447                 pbl->pg_size == ROCE_PG_SIZE_8K ?
 448                                       CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8K :
 449                 pbl->pg_size == ROCE_PG_SIZE_64K ?
 450                                       CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_64K :
 451                 pbl->pg_size == ROCE_PG_SIZE_2M ?
 452                                       CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_2M :
 453                 pbl->pg_size == ROCE_PG_SIZE_8M ?
 454                                       CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8M :
 455                 pbl->pg_size == ROCE_PG_SIZE_1G ?
 456                                       CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_1G :
 457                                       CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_4K);
 458 }
 459
 460 int bnxt_qplib_init_rcfw(struct bnxt_qplib_rcfw *rcfw,
 461                          struct bnxt_qplib_ctx *ctx, int is_virtfn)
 462 {
 463         struct cmdq_initialize_fw req;
 464         struct creq_initialize_fw_resp resp;
 465         u16 cmd_flags = 0, level;
 466         int rc;
 467
 468         RCFW_CMD_PREP(req, INITIALIZE_FW, cmd_flags);
 469         /* Supply (log-base-2-of-host-page-size - base-page-shift)
 470          * to bono to adjust the doorbell page sizes.
 471          */
 472         req.log2_dbr_pg_size = cpu_to_le16(PAGE_SHIFT -
 473                                            RCFW_DBR_BASE_PAGE_SHIFT);
 474         /*
 475          * VFs need not setup the HW context area, PF
 476          * shall setup this area for VF. Skipping the
 477          * HW programming
 478          */
 479         if (is_virtfn)
 480                 goto skip_ctx_setup;
 481
 482         level = ctx->qpc_tbl.level;
 483         req.qpc_pg_size_qpc_lvl = (level << CMDQ_INITIALIZE_FW_QPC_LVL_SFT) |
 484                                 __get_pbl_pg_idx(&ctx->qpc_tbl.pbl[level]);
 485         level = ctx->mrw_tbl.level;
 486         req.mrw_pg_size_mrw_lvl = (level << CMDQ_INITIALIZE_FW_MRW_LVL_SFT) |
 487                                 __get_pbl_pg_idx(&ctx->mrw_tbl.pbl[level]);
 488         level = ctx->srqc_tbl.level;
 489         req.srq_pg_size_srq_lvl = (level << CMDQ_INITIALIZE_FW_SRQ_LVL_SFT) |
 490                                 __get_pbl_pg_idx(&ctx->srqc_tbl.pbl[level]);
 491         level = ctx->cq_tbl.level;
 492         req.cq_pg_size_cq_lvl = (level << CMDQ_INITIALIZE_FW_CQ_LVL_SFT) |
 493                                 __get_pbl_pg_idx(&ctx->cq_tbl.pbl[level]);
 494         level = ctx->srqc_tbl.level;
 495         req.srq_pg_size_srq_lvl = (level << CMDQ_INITIALIZE_FW_SRQ_LVL_SFT) |
 496                                 __get_pbl_pg_idx(&ctx->srqc_tbl.pbl[level]);
 497         level = ctx->cq_tbl.level;
 498         req.cq_pg_size_cq_lvl = (level << CMDQ_INITIALIZE_FW_CQ_LVL_SFT) |
 499                                 __get_pbl_pg_idx(&ctx->cq_tbl.pbl[level]);
 500         level = ctx->tim_tbl.level;
 501         req.tim_pg_size_tim_lvl = (level << CMDQ_INITIALIZE_FW_TIM_LVL_SFT) |
 502                                   __get_pbl_pg_idx(&ctx->tim_tbl.pbl[level]);
 503         level = ctx->tqm_pde_level;
 504         req.tqm_pg_size_tqm_lvl = (level << CMDQ_INITIALIZE_FW_TQM_LVL_SFT) |
 505                                   __get_pbl_pg_idx(&ctx->tqm_pde.pbl[level]);
 506
 507         req.qpc_page_dir =
 508                 cpu_to_le64(ctx->qpc_tbl.pbl[PBL_LVL_0].pg_map_arr[0]);
 509         req.mrw_page_dir =
 510                 cpu_to_le64(ctx->mrw_tbl.pbl[PBL_LVL_0].pg_map_arr[0]);
 511         req.srq_page_dir =
 512                 cpu_to_le64(ctx->srqc_tbl.pbl[PBL_LVL_0].pg_map_arr[0]);
 513         req.cq_page_dir =
 514                 cpu_to_le64(ctx->cq_tbl.pbl[PBL_LVL_0].pg_map_arr[0]);
 515         req.tim_page_dir =
 516                 cpu_to_le64(ctx->tim_tbl.pbl[PBL_LVL_0].pg_map_arr[0]);
 517         req.tqm_page_dir =
 518                 cpu_to_le64(ctx->tqm_pde.pbl[PBL_LVL_0].pg_map_arr[0]);
 519
 520         req.number_of_qp = cpu_to_le32(ctx->qpc_tbl.max_elements);
 521         req.number_of_mrw = cpu_to_le32(ctx->mrw_tbl.max_elements);
 522         req.number_of_srq = cpu_to_le32(ctx->srqc_tbl.max_elements);
 523         req.number_of_cq = cpu_to_le32(ctx->cq_tbl.max_elements);
 524
 525         req.max_qp_per_vf = cpu_to_le32(ctx->vf_res.max_qp_per_vf);
 526         req.max_mrw_per_vf = cpu_to_le32(ctx->vf_res.max_mrw_per_vf);
 527         req.max_srq_per_vf = cpu_to_le32(ctx->vf_res.max_srq_per_vf);
 528         req.max_cq_per_vf = cpu_to_le32(ctx->vf_res.max_cq_per_vf);
 529         req.max_gid_per_vf = cpu_to_le32(ctx->vf_res.max_gid_per_vf);
 530
 531 skip_ctx_setup:
 532         req.stat_ctx_id = cpu_to_le32(ctx->stats.fw_id);
 533         rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, (void *)&resp,
 534                                           NULL, 0);
 535         if (rc)
 536                 return rc;
 537         set_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->flags);
 538         return 0;
 539 }
 540
 541 void bnxt_qplib_free_rcfw_channel(struct bnxt_qplib_rcfw *rcfw)
 542 {
 543         kfree(rcfw->qp_tbl);
 544         kfree(rcfw->crsqe_tbl);
 545         bnxt_qplib_free_hwq(rcfw->pdev, &rcfw->cmdq);
 546         bnxt_qplib_free_hwq(rcfw->pdev, &rcfw->creq);
 547         rcfw->pdev = NULL;
 548 }
 549
 550 int bnxt_qplib_alloc_rcfw_channel(struct pci_dev *pdev,
 551                                   struct bnxt_qplib_rcfw *rcfw,
 552                                   int qp_tbl_sz)
 553 {
 554         rcfw->pdev = pdev;
 555         rcfw->creq.max_elements = BNXT_QPLIB_CREQE_MAX_CNT;
 556         if (bnxt_qplib_alloc_init_hwq(rcfw->pdev, &rcfw->creq, NULL, 0,
 557                                       &rcfw->creq.max_elements,
 558                                       BNXT_QPLIB_CREQE_UNITS, 0, PAGE_SIZE,
 559                                       HWQ_TYPE_L2_CMPL)) {
 560                 dev_err(&rcfw->pdev->dev,
 561                         "QPLIB: HW channel CREQ allocation failed");
 562                 goto fail;
 563         }
 564         rcfw->cmdq.max_elements = BNXT_QPLIB_CMDQE_MAX_CNT;
 565         if (bnxt_qplib_alloc_init_hwq(rcfw->pdev, &rcfw->cmdq, NULL, 0,
 566                                       &rcfw->cmdq.max_elements,
 567                                       BNXT_QPLIB_CMDQE_UNITS, 0, PAGE_SIZE,
 568                                       HWQ_TYPE_CTX)) {
 569                 dev_err(&rcfw->pdev->dev,
 570                         "QPLIB: HW channel CMDQ allocation failed");
 571                 goto fail;
 572         }
 573
 574         rcfw->crsqe_tbl = kcalloc(rcfw->cmdq.max_elements,
 575                                   sizeof(*rcfw->crsqe_tbl), GFP_KERNEL);
 576         if (!rcfw->crsqe_tbl)
 577                 goto fail;
 578
 579         rcfw->qp_tbl_size = qp_tbl_sz;
 580         rcfw->qp_tbl = kcalloc(qp_tbl_sz, sizeof(struct bnxt_qplib_qp_node),
 581                                GFP_KERNEL);
 582         if (!rcfw->qp_tbl)
 583                 goto fail;
 584
 585         return 0;
 586
 587 fail:
 588         bnxt_qplib_free_rcfw_channel(rcfw);
 589         return -ENOMEM;
 590 }
 591
 592 void bnxt_qplib_disable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw)
 593 {
 594         unsigned long indx;
 595
 596         /* Make sure the HW channel is stopped! */
 597         synchronize_irq(rcfw->vector);
 598         tasklet_disable(&rcfw->worker);
 599         tasklet_kill(&rcfw->worker);
 600
 601         if (rcfw->requested) {
 602                 free_irq(rcfw->vector, rcfw);
 603                 rcfw->requested = false;
 604         }
 605         if (rcfw->cmdq_bar_reg_iomem)
 606                 iounmap(rcfw->cmdq_bar_reg_iomem);
 607         rcfw->cmdq_bar_reg_iomem = NULL;
 608
 609         if (rcfw->creq_bar_reg_iomem)
 610                 iounmap(rcfw->creq_bar_reg_iomem);
 611         rcfw->creq_bar_reg_iomem = NULL;
 612
 613         indx = find_first_bit(rcfw->cmdq_bitmap, rcfw->bmap_size);
 614         if (indx != rcfw->bmap_size)
 615                 dev_err(&rcfw->pdev->dev,
 616                         "QPLIB: disabling RCFW with pending cmd-bit %lx", indx);
 617         kfree(rcfw->cmdq_bitmap);
 618         rcfw->bmap_size = 0;
 619
 620         rcfw->aeq_handler = NULL;
 621         rcfw->vector = 0;
 622 }
 623
 624 int bnxt_qplib_enable_rcfw_channel(struct pci_dev *pdev,
 625                                    struct bnxt_qplib_rcfw *rcfw,
 626                                    int msix_vector,
 627                                    int cp_bar_reg_off, int virt_fn,
 628                                    int (*aeq_handler)(struct bnxt_qplib_rcfw *,
 629                                                       struct creq_func_event *))
 630 {
 631         resource_size_t res_base;
 632         struct cmdq_init init;
 633         u16 bmap_size;
 634         int rc;
 635
 636         /* General */
 637         rcfw->seq_num = 0;
 638         rcfw->flags = FIRMWARE_FIRST_FLAG;
 639         bmap_size = BITS_TO_LONGS(RCFW_MAX_OUTSTANDING_CMD *
 640                                   sizeof(unsigned long));
 641         rcfw->cmdq_bitmap = kzalloc(bmap_size, GFP_KERNEL);
 642         if (!rcfw->cmdq_bitmap)
 643                 return -ENOMEM;
 644         rcfw->bmap_size = bmap_size;
 645
 646         /* CMDQ */
 647         rcfw->cmdq_bar_reg = RCFW_COMM_PCI_BAR_REGION;
 648         res_base = pci_resource_start(pdev, rcfw->cmdq_bar_reg);
 649         if (!res_base)
 650                 return -ENOMEM;
 651
 652         rcfw->cmdq_bar_reg_iomem = ioremap_nocache(res_base +
 653                                               RCFW_COMM_BASE_OFFSET,
 654                                               RCFW_COMM_SIZE);
 655         if (!rcfw->cmdq_bar_reg_iomem) {
 656                 dev_err(&rcfw->pdev->dev,
 657                         "QPLIB: CMDQ BAR region %d mapping failed",
 658                         rcfw->cmdq_bar_reg);
 659                 return -ENOMEM;
 660         }
 661
 662         rcfw->cmdq_bar_reg_prod_off = virt_fn ? RCFW_VF_COMM_PROD_OFFSET :
 663                                         RCFW_PF_COMM_PROD_OFFSET;
 664
 665         rcfw->cmdq_bar_reg_trig_off = RCFW_COMM_TRIG_OFFSET;
 666
 667         /* CREQ */
 668         rcfw->creq_bar_reg = RCFW_COMM_CONS_PCI_BAR_REGION;
 669         res_base = pci_resource_start(pdev, rcfw->creq_bar_reg);
 670         if (!res_base)
 671                 dev_err(&rcfw->pdev->dev,
 672                         "QPLIB: CREQ BAR region %d resc start is 0!",
 673                         rcfw->creq_bar_reg);
 674         rcfw->creq_bar_reg_iomem = ioremap_nocache(res_base + cp_bar_reg_off,
 675                                                    4);
 676         if (!rcfw->creq_bar_reg_iomem) {
 677                 dev_err(&rcfw->pdev->dev,
 678                         "QPLIB: CREQ BAR region %d mapping failed",
 679                         rcfw->creq_bar_reg);
 680                 return -ENOMEM;
 681         }
 682         rcfw->creq_qp_event_processed = 0;
 683         rcfw->creq_func_event_processed = 0;
 684
 685         rcfw->vector = msix_vector;
 686         if (aeq_handler)
 687                 rcfw->aeq_handler = aeq_handler;
 688
 689         tasklet_init(&rcfw->worker, bnxt_qplib_service_creq,
 690                      (unsigned long)rcfw);
 691
 692         rcfw->requested = false;
 693         rc = request_irq(rcfw->vector, bnxt_qplib_creq_irq, 0,
 694                          "bnxt_qplib_creq", rcfw);
 695         if (rc) {
 696                 dev_err(&rcfw->pdev->dev,
 697                         "QPLIB: Failed to request IRQ for CREQ rc = 0x%x", rc);
 698                 bnxt_qplib_disable_rcfw_channel(rcfw);
 699                 return rc;
 700         }
 701         rcfw->requested = true;
 702
 703         init_waitqueue_head(&rcfw->waitq);
 704
 705         CREQ_DB_REARM(rcfw->creq_bar_reg_iomem, 0, rcfw->creq.max_elements);
 706
 707         init.cmdq_pbl = cpu_to_le64(rcfw->cmdq.pbl[PBL_LVL_0].pg_map_arr[0]);
 708         init.cmdq_size_cmdq_lvl = cpu_to_le16(
 709                 ((BNXT_QPLIB_CMDQE_MAX_CNT << CMDQ_INIT_CMDQ_SIZE_SFT) &
 710                  CMDQ_INIT_CMDQ_SIZE_MASK) |
 711                 ((rcfw->cmdq.level << CMDQ_INIT_CMDQ_LVL_SFT) &
 712                  CMDQ_INIT_CMDQ_LVL_MASK));
 713         init.creq_ring_id = cpu_to_le16(rcfw->creq_ring_id);
 714
 715         /* Write to the Bono mailbox register */
 716         __iowrite32_copy(rcfw->cmdq_bar_reg_iomem, &init, sizeof(init) / 4);
 717         return 0;
 718 }
 719
 720 struct bnxt_qplib_rcfw_sbuf *bnxt_qplib_rcfw_alloc_sbuf(
 721                 struct bnxt_qplib_rcfw *rcfw,
 722                 u32 size)
 723 {
 724         struct bnxt_qplib_rcfw_sbuf *sbuf;
 725
 726         sbuf = kzalloc(sizeof(*sbuf), GFP_ATOMIC);
 727         if (!sbuf)
 728                 return NULL;
 729
 730         sbuf->size = size;
 731         sbuf->sb = dma_zalloc_coherent(&rcfw->pdev->dev, sbuf->size,
 732                                        &sbuf->dma_addr, GFP_ATOMIC);
 733         if (!sbuf->sb)
 734                 goto bail;
 735
 736         return sbuf;
 737 bail:
 738         kfree(sbuf);
 739         return NULL;
 740 }
 741
 742 void bnxt_qplib_rcfw_free_sbuf(struct bnxt_qplib_rcfw *rcfw,
 743                                struct bnxt_qplib_rcfw_sbuf *sbuf)
 744 {
 745         if (sbuf->sb)
 746                 dma_free_coherent(&rcfw->pdev->dev, sbuf->size,
 747                                   sbuf->sb, sbuf->dma_addr);
 748         kfree(sbuf);
 749 }