drivers/infiniband/hw/bnxt_re/roce_hsi.h

   1 /*
   2  * Broadcom NetXtreme-E RoCE driver.
   3  *
   4  * Copyright (c) 2016 - 2017, Broadcom. All rights reserved.  The term
   5  * Broadcom refers to Broadcom Limited and/or its subsidiaries.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * BSD license below:
  12  *
  13  * Redistribution and use in source and binary forms, with or without
  14  * modification, are permitted provided that the following conditions
  15  * are met:
  16  *
  17  * 1. Redistributions of source code must retain the above copyright
  18  *    notice, this list of conditions and the following disclaimer.
  19  * 2. Redistributions in binary form must reproduce the above copyright
  20  *    notice, this list of conditions and the following disclaimer in
  21  *    the documentation and/or other materials provided with the
  22  *    distribution.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
  25  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
  28  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  29  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  31  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  32  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  33  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  34  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  *
  36  * Description: RoCE HSI File - Autogenerated
  37  */
  38
  39 #ifndef __BNXT_RE_HSI_H__
  40 #define __BNXT_RE_HSI_H__
  41
  42 /* include bnxt_hsi.h from bnxt_en driver */
  43 #include "bnxt_hsi.h"
  44
  45 /* CMP Door Bell Format (4 bytes) */
  46 struct cmpl_doorbell {
  47         __le32 key_mask_valid_idx;
  48         #define CMPL_DOORBELL_IDX_MASK                              0xffffffUL
  49         #define CMPL_DOORBELL_IDX_SFT                               0
  50         #define CMPL_DOORBELL_RESERVED_MASK                         0x3000000UL
  51         #define CMPL_DOORBELL_RESERVED_SFT                          24
  52         #define CMPL_DOORBELL_IDX_VALID                     0x4000000UL
  53         #define CMPL_DOORBELL_MASK                                  0x8000000UL
  54         #define CMPL_DOORBELL_KEY_MASK                              0xf0000000UL
  55         #define CMPL_DOORBELL_KEY_SFT                               28
  56         #define CMPL_DOORBELL_KEY_CMPL                             (0x2UL << 28)
  57 };
  58
  59 /* Status Door Bell Format (4 bytes) */
  60 struct status_doorbell {
  61         __le32 key_idx;
  62         #define STATUS_DOORBELL_IDX_MASK                            0xffffffUL
  63         #define STATUS_DOORBELL_IDX_SFT                     0
  64         #define STATUS_DOORBELL_RESERVED_MASK                       0xf000000UL
  65         #define STATUS_DOORBELL_RESERVED_SFT                        24
  66         #define STATUS_DOORBELL_KEY_MASK                            0xf0000000UL
  67         #define STATUS_DOORBELL_KEY_SFT                     28
  68         #define STATUS_DOORBELL_KEY_STAT                           (0x3UL << 28)
  69 };
  70
  71 /* RoCE Host Structures */
  72
  73 /* Doorbell Structures */
  74 /* 64b Doorbell Format (8 bytes) */
  75 struct dbr_dbr {
  76         __le32 index;
  77         #define DBR_DBR_INDEX_MASK                                  0xfffffUL
  78         #define DBR_DBR_INDEX_SFT                                   0
  79         #define DBR_DBR_RESERVED12_MASK                     0xfff00000UL
  80         #define DBR_DBR_RESERVED12_SFT                              20
  81         __le32 type_xid;
  82         #define DBR_DBR_XID_MASK                                    0xfffffUL
  83         #define DBR_DBR_XID_SFT                             0
  84         #define DBR_DBR_RESERVED8_MASK                              0xff00000UL
  85         #define DBR_DBR_RESERVED8_SFT                               20
  86         #define DBR_DBR_TYPE_MASK                                   0xf0000000UL
  87         #define DBR_DBR_TYPE_SFT                                    28
  88         #define DBR_DBR_TYPE_SQ                            (0x0UL << 28)
  89         #define DBR_DBR_TYPE_RQ                            (0x1UL << 28)
  90         #define DBR_DBR_TYPE_SRQ                                   (0x2UL << 28)
  91         #define DBR_DBR_TYPE_SRQ_ARM                               (0x3UL << 28)
  92         #define DBR_DBR_TYPE_CQ                            (0x4UL << 28)
  93         #define DBR_DBR_TYPE_CQ_ARMSE                              (0x5UL << 28)
  94         #define DBR_DBR_TYPE_CQ_ARMALL                             (0x6UL << 28)
  95         #define DBR_DBR_TYPE_CQ_ARMENA                             (0x7UL << 28)
  96         #define DBR_DBR_TYPE_SRQ_ARMENA                    (0x8UL << 28)
  97         #define DBR_DBR_TYPE_CQ_CUTOFF_ACK                         (0x9UL << 28)
  98         #define DBR_DBR_TYPE_NULL                                  (0xfUL << 28)
  99 };
 100
 101 /* 32b Doorbell Format (4 bytes) */
 102 struct dbr_dbr32 {
 103         __le32 type_abs_incr_xid;
 104         #define DBR_DBR32_XID_MASK                                  0xfffffUL
 105         #define DBR_DBR32_XID_SFT                                   0
 106         #define DBR_DBR32_RESERVED4_MASK                            0xf00000UL
 107         #define DBR_DBR32_RESERVED4_SFT                     20
 108         #define DBR_DBR32_INCR_MASK                                 0xf000000UL
 109         #define DBR_DBR32_INCR_SFT                                  24
 110         #define DBR_DBR32_ABS                                       0x10000000UL
 111         #define DBR_DBR32_TYPE_MASK                                 0xe0000000UL
 112         #define DBR_DBR32_TYPE_SFT                                  29
 113         #define DBR_DBR32_TYPE_SQ                                  (0x0UL << 29)
 114 };
 115
 116 /* SQ WQE Structures */
 117 /* Base SQ WQE (8 bytes) */
 118 struct sq_base {
 119         u8 wqe_type;
 120         #define SQ_BASE_WQE_TYPE_SEND                              0x0UL
 121         #define SQ_BASE_WQE_TYPE_SEND_W_IMMEAD                     0x1UL
 122         #define SQ_BASE_WQE_TYPE_SEND_W_INVALID            0x2UL
 123         #define SQ_BASE_WQE_TYPE_WRITE_WQE                         0x4UL
 124         #define SQ_BASE_WQE_TYPE_WRITE_W_IMMEAD            0x5UL
 125         #define SQ_BASE_WQE_TYPE_READ_WQE                          0x6UL
 126         #define SQ_BASE_WQE_TYPE_ATOMIC_CS                         0x8UL
 127         #define SQ_BASE_WQE_TYPE_ATOMIC_FA                         0xbUL
 128         #define SQ_BASE_WQE_TYPE_LOCAL_INVALID                     0xcUL
 129         #define SQ_BASE_WQE_TYPE_FR_PMR                    0xdUL
 130         #define SQ_BASE_WQE_TYPE_BIND                              0xeUL
 131         u8 unused_0[7];
 132 };
 133
 134 /* WQE SGE (16 bytes) */
 135 struct sq_sge {
 136         __le64 va_or_pa;
 137         __le32 l_key;
 138         __le32 size;
 139 };
 140
 141 /* PSN Search Structure (8 bytes) */
 142 struct sq_psn_search {
 143         __le32 opcode_start_psn;
 144         #define SQ_PSN_SEARCH_START_PSN_MASK                        0xffffffUL
 145         #define SQ_PSN_SEARCH_START_PSN_SFT                         0
 146         #define SQ_PSN_SEARCH_OPCODE_MASK                           0xff000000UL
 147         #define SQ_PSN_SEARCH_OPCODE_SFT                            24
 148         __le32 flags_next_psn;
 149         #define SQ_PSN_SEARCH_NEXT_PSN_MASK                         0xffffffUL
 150         #define SQ_PSN_SEARCH_NEXT_PSN_SFT                          0
 151         #define SQ_PSN_SEARCH_FLAGS_MASK                            0xff000000UL
 152         #define SQ_PSN_SEARCH_FLAGS_SFT                     24
 153 };
 154
 155 /* Send SQ WQE (40 bytes) */
 156 struct sq_send {
 157         u8 wqe_type;
 158         #define SQ_SEND_WQE_TYPE_SEND                              0x0UL
 159         #define SQ_SEND_WQE_TYPE_SEND_W_IMMEAD                     0x1UL
 160         #define SQ_SEND_WQE_TYPE_SEND_W_INVALID            0x2UL
 161         u8 flags;
 162         #define SQ_SEND_FLAGS_SIGNAL_COMP                           0x1UL
 163         #define SQ_SEND_FLAGS_RD_OR_ATOMIC_FENCE                    0x2UL
 164         #define SQ_SEND_FLAGS_UC_FENCE                              0x4UL
 165         #define SQ_SEND_FLAGS_SE                                    0x8UL
 166         #define SQ_SEND_FLAGS_INLINE                                0x10UL
 167         u8 wqe_size;
 168         u8 reserved8_1;
 169         __le32 inv_key_or_imm_data;
 170         __le32 length;
 171         __le32 q_key;
 172         __le32 dst_qp;
 173         #define SQ_SEND_DST_QP_MASK                                 0xffffffUL
 174         #define SQ_SEND_DST_QP_SFT                                  0
 175         #define SQ_SEND_RESERVED8_2_MASK                            0xff000000UL
 176         #define SQ_SEND_RESERVED8_2_SFT                     24
 177         __le32 avid;
 178         #define SQ_SEND_AVID_MASK                                   0xfffffUL
 179         #define SQ_SEND_AVID_SFT                                    0
 180         #define SQ_SEND_RESERVED_AVID_MASK                          0xfff00000UL
 181         #define SQ_SEND_RESERVED_AVID_SFT                           20
 182         __le64 reserved64;
 183         __le32 data[24];
 184 };
 185
 186 /* Send Raw Ethernet and QP1 SQ WQE (40 bytes) */
 187 struct sq_send_raweth_qp1 {
 188         u8 wqe_type;
 189         #define SQ_SEND_RAWETH_QP1_WQE_TYPE_SEND                   0x0UL
 190         u8 flags;
 191         #define SQ_SEND_RAWETH_QP1_FLAGS_SIGNAL_COMP                0x1UL
 192         #define SQ_SEND_RAWETH_QP1_FLAGS_RD_OR_ATOMIC_FENCE         0x2UL
 193         #define SQ_SEND_RAWETH_QP1_FLAGS_UC_FENCE                   0x4UL
 194         #define SQ_SEND_RAWETH_QP1_FLAGS_SE                         0x8UL
 195         #define SQ_SEND_RAWETH_QP1_FLAGS_INLINE             0x10UL
 196         u8 wqe_size;
 197         u8 reserved8;
 198         __le16 lflags;
 199         #define SQ_SEND_RAWETH_QP1_LFLAGS_TCP_UDP_CHKSUM            0x1UL
 200         #define SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM                 0x2UL
 201         #define SQ_SEND_RAWETH_QP1_LFLAGS_NOCRC             0x4UL
 202         #define SQ_SEND_RAWETH_QP1_LFLAGS_STAMP             0x8UL
 203         #define SQ_SEND_RAWETH_QP1_LFLAGS_T_IP_CHKSUM               0x10UL
 204         #define SQ_SEND_RAWETH_QP1_LFLAGS_RESERVED1_1               0x20UL
 205         #define SQ_SEND_RAWETH_QP1_LFLAGS_RESERVED1_2               0x40UL
 206         #define SQ_SEND_RAWETH_QP1_LFLAGS_RESERVED1_3               0x80UL
 207         #define SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC                  0x100UL
 208         #define SQ_SEND_RAWETH_QP1_LFLAGS_FCOE_CRC                  0x200UL
 209         __le16 cfa_action;
 210         __le32 length;
 211         __le32 reserved32_1;
 212         __le32 cfa_meta;
 213         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_MASK           0xfffUL
 214         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_SFT            0
 215         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_DE                 0x1000UL
 216         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_PRI_MASK           0xe000UL
 217         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_PRI_SFT            13
 218         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_MASK          0x70000UL
 219         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_SFT           16
 220         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID88A8    (0x0UL << 16)
 221         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID8100    (0x1UL << 16)
 222         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9100    (0x2UL << 16)
 223         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9200    (0x3UL << 16)
 224         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9300    (0x4UL << 16)
 225         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPIDCFG     (0x5UL << 16)
 226         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_LAST      \
 227                                 SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPIDCFG
 228         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_RESERVED_MASK     0xff80000UL
 229         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_RESERVED_SFT      19
 230         #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_MASK                0xf0000000UL
 231         #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_SFT                 28
 232         #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_NONE               (0x0UL << 28)
 233         #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_VLAN_TAG           (0x1UL << 28)
 234         #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_LAST            \
 235                                 SQ_SEND_RAWETH_QP1_CFA_META_KEY_VLAN_TAG
 236         __le32 reserved32_2;
 237         __le64 reserved64;
 238         __le32 data[24];
 239 };
 240
 241 /* RDMA SQ WQE (40 bytes) */
 242 struct sq_rdma {
 243         u8 wqe_type;
 244         #define SQ_RDMA_WQE_TYPE_WRITE_WQE                         0x4UL
 245         #define SQ_RDMA_WQE_TYPE_WRITE_W_IMMEAD            0x5UL
 246         #define SQ_RDMA_WQE_TYPE_READ_WQE                          0x6UL
 247         u8 flags;
 248         #define SQ_RDMA_FLAGS_SIGNAL_COMP                           0x1UL
 249         #define SQ_RDMA_FLAGS_RD_OR_ATOMIC_FENCE                    0x2UL
 250         #define SQ_RDMA_FLAGS_UC_FENCE                              0x4UL
 251         #define SQ_RDMA_FLAGS_SE                                    0x8UL
 252         #define SQ_RDMA_FLAGS_INLINE                                0x10UL
 253         u8 wqe_size;
 254         u8 reserved8;
 255         __le32 imm_data;
 256         __le32 length;
 257         __le32 reserved32_1;
 258         __le64 remote_va;
 259         __le32 remote_key;
 260         __le32 reserved32_2;
 261         __le32 data[24];
 262 };
 263
 264 /* Atomic SQ WQE (40 bytes) */
 265 struct sq_atomic {
 266         u8 wqe_type;
 267         #define SQ_ATOMIC_WQE_TYPE_ATOMIC_CS                       0x8UL
 268         #define SQ_ATOMIC_WQE_TYPE_ATOMIC_FA                       0xbUL
 269         u8 flags;
 270         #define SQ_ATOMIC_FLAGS_SIGNAL_COMP                         0x1UL
 271         #define SQ_ATOMIC_FLAGS_RD_OR_ATOMIC_FENCE                  0x2UL
 272         #define SQ_ATOMIC_FLAGS_UC_FENCE                            0x4UL
 273         #define SQ_ATOMIC_FLAGS_SE                                  0x8UL
 274         #define SQ_ATOMIC_FLAGS_INLINE                              0x10UL
 275         __le16 reserved16;
 276         __le32 remote_key;
 277         __le64 remote_va;
 278         __le64 swap_data;
 279         __le64 cmp_data;
 280         __le32 data[24];
 281 };
 282
 283 /* Local Invalidate SQ WQE (40 bytes) */
 284 struct sq_localinvalidate {
 285         u8 wqe_type;
 286         #define SQ_LOCALINVALIDATE_WQE_TYPE_LOCAL_INVALID          0xcUL
 287         u8 flags;
 288         #define SQ_LOCALINVALIDATE_FLAGS_SIGNAL_COMP                0x1UL
 289         #define SQ_LOCALINVALIDATE_FLAGS_RD_OR_ATOMIC_FENCE         0x2UL
 290         #define SQ_LOCALINVALIDATE_FLAGS_UC_FENCE                   0x4UL
 291         #define SQ_LOCALINVALIDATE_FLAGS_SE                         0x8UL
 292         #define SQ_LOCALINVALIDATE_FLAGS_INLINE             0x10UL
 293         __le16 reserved16;
 294         __le32 inv_l_key;
 295         __le64 reserved64;
 296         __le32 reserved128[4];
 297         __le32 data[24];
 298 };
 299
 300 /* FR-PMR SQ WQE (40 bytes) */
 301 struct sq_fr_pmr {
 302         u8 wqe_type;
 303         #define SQ_FR_PMR_WQE_TYPE_FR_PMR                          0xdUL
 304         u8 flags;
 305         #define SQ_FR_PMR_FLAGS_SIGNAL_COMP                         0x1UL
 306         #define SQ_FR_PMR_FLAGS_RD_OR_ATOMIC_FENCE                  0x2UL
 307         #define SQ_FR_PMR_FLAGS_UC_FENCE                            0x4UL
 308         #define SQ_FR_PMR_FLAGS_SE                                  0x8UL
 309         #define SQ_FR_PMR_FLAGS_INLINE                              0x10UL
 310         u8 access_cntl;
 311         #define SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE                   0x1UL
 312         #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ                   0x2UL
 313         #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE                  0x4UL
 314         #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC                 0x8UL
 315         #define SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND                   0x10UL
 316         u8 zero_based_page_size_log;
 317         #define SQ_FR_PMR_PAGE_SIZE_LOG_MASK                        0x1fUL
 318         #define SQ_FR_PMR_PAGE_SIZE_LOG_SFT                         0
 319         #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4K            0x0UL
 320         #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8K            0x1UL
 321         #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64K                   0x4UL
 322         #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256K                  0x6UL
 323         #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1M            0x8UL
 324         #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2M            0x9UL
 325         #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4M            0xaUL
 326         #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1G            0x12UL
 327         #define SQ_FR_PMR_ZERO_BASED                                0x20UL
 328         #define SQ_FR_PMR_RESERVED2_MASK                            0xc0UL
 329         #define SQ_FR_PMR_RESERVED2_SFT                     6
 330         __le32 l_key;
 331         u8 length[5];
 332         u8 reserved8_1;
 333         u8 reserved8_2;
 334         u8 numlevels_pbl_page_size_log;
 335         #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_MASK                    0x1fUL
 336         #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_SFT             0
 337         #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4K                0x0UL
 338         #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8K                0x1UL
 339         #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64K               0x4UL
 340         #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256K              0x6UL
 341         #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1M                0x8UL
 342         #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2M                0x9UL
 343         #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4M                0xaUL
 344         #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1G                0x12UL
 345         #define SQ_FR_PMR_RESERVED1                                 0x20UL
 346         #define SQ_FR_PMR_NUMLEVELS_MASK                            0xc0UL
 347         #define SQ_FR_PMR_NUMLEVELS_SFT                     6
 348         #define SQ_FR_PMR_NUMLEVELS_PHYSICAL                       (0x0UL << 6)
 349         #define SQ_FR_PMR_NUMLEVELS_LAYER1                         (0x1UL << 6)
 350         #define SQ_FR_PMR_NUMLEVELS_LAYER2                         (0x2UL << 6)
 351         __le64 pblptr;
 352         __le64 va;
 353         __le32 data[24];
 354 };
 355
 356 /* Bind SQ WQE (40 bytes) */
 357 struct sq_bind {
 358         u8 wqe_type;
 359         #define SQ_BIND_WQE_TYPE_BIND                              0xeUL
 360         u8 flags;
 361         #define SQ_BIND_FLAGS_SIGNAL_COMP                           0x1UL
 362         #define SQ_BIND_FLAGS_RD_OR_ATOMIC_FENCE                    0x2UL
 363         #define SQ_BIND_FLAGS_UC_FENCE                              0x4UL
 364         #define SQ_BIND_FLAGS_SE                                    0x8UL
 365         #define SQ_BIND_FLAGS_INLINE                                0x10UL
 366         u8 access_cntl;
 367         #define SQ_BIND_ACCESS_CNTL_LOCAL_WRITE             0x1UL
 368         #define SQ_BIND_ACCESS_CNTL_REMOTE_READ             0x2UL
 369         #define SQ_BIND_ACCESS_CNTL_REMOTE_WRITE                    0x4UL
 370         #define SQ_BIND_ACCESS_CNTL_REMOTE_ATOMIC                   0x8UL
 371         #define SQ_BIND_ACCESS_CNTL_WINDOW_BIND             0x10UL
 372         u8 reserved8_1;
 373         u8 mw_type_zero_based;
 374         #define SQ_BIND_ZERO_BASED                                  0x1UL
 375         #define SQ_BIND_MW_TYPE                             0x2UL
 376         #define SQ_BIND_MW_TYPE_TYPE1                              (0x0UL << 1)
 377         #define SQ_BIND_MW_TYPE_TYPE2                              (0x1UL << 1)
 378         #define SQ_BIND_RESERVED6_MASK                              0xfcUL
 379         #define SQ_BIND_RESERVED6_SFT                               2
 380         u8 reserved8_2;
 381         __le16 reserved16;
 382         __le32 parent_l_key;
 383         __le32 l_key;
 384         __le64 va;
 385         u8 length[5];
 386         u8 data_reserved24[99];
 387         #define SQ_BIND_RESERVED24_MASK                     0xffffff00UL
 388         #define SQ_BIND_RESERVED24_SFT                              8
 389         #define SQ_BIND_DATA_MASK                                   0xffffffffUL
 390         #define SQ_BIND_DATA_SFT                                    0
 391 };
 392
 393 /* RQ/SRQ WQE Structures */
 394 /* RQ/SRQ WQE (40 bytes) */
 395 struct rq_wqe {
 396         u8 wqe_type;
 397         #define RQ_WQE_WQE_TYPE_RCV                                0x80UL
 398         u8 flags;
 399         u8 wqe_size;
 400         u8 reserved8;
 401         __le32 reserved32;
 402         __le32 wr_id[2];
 403         #define RQ_WQE_WR_ID_MASK                                   0xfffffUL
 404         #define RQ_WQE_WR_ID_SFT                                    0
 405         #define RQ_WQE_RESERVED44_MASK                              0xfff00000UL
 406         #define RQ_WQE_RESERVED44_SFT                               20
 407         __le32 reserved128[4];
 408         __le32 data[24];
 409 };
 410
 411 /* CQ CQE Structures */
 412 /* Base CQE (32 bytes) */
 413 struct cq_base {
 414         __le64 reserved64_1;
 415         __le64 reserved64_2;
 416         __le64 reserved64_3;
 417         u8 cqe_type_toggle;
 418         #define CQ_BASE_TOGGLE                                      0x1UL
 419         #define CQ_BASE_CQE_TYPE_MASK                               0x1eUL
 420         #define CQ_BASE_CQE_TYPE_SFT                                1
 421         #define CQ_BASE_CQE_TYPE_REQ                               (0x0UL << 1)
 422         #define CQ_BASE_CQE_TYPE_RES_RC                    (0x1UL << 1)
 423         #define CQ_BASE_CQE_TYPE_RES_UD                    (0x2UL << 1)
 424         #define CQ_BASE_CQE_TYPE_RES_RAWETH_QP1            (0x3UL << 1)
 425         #define CQ_BASE_CQE_TYPE_TERMINAL                          (0xeUL << 1)
 426         #define CQ_BASE_CQE_TYPE_CUT_OFF                           (0xfUL << 1)
 427         #define CQ_BASE_RESERVED3_MASK                              0xe0UL
 428         #define CQ_BASE_RESERVED3_SFT                               5
 429         u8 status;
 430         __le16 reserved16;
 431         __le32 reserved32;
 432 };
 433
 434 /* Requester CQ CQE (32 bytes) */
 435 struct cq_req {
 436         __le64 qp_handle;
 437         __le16 sq_cons_idx;
 438         __le16 reserved16_1;
 439         __le32 reserved32_2;
 440         __le64 reserved64;
 441         u8 cqe_type_toggle;
 442         #define CQ_REQ_TOGGLE                                       0x1UL
 443         #define CQ_REQ_CQE_TYPE_MASK                                0x1eUL
 444         #define CQ_REQ_CQE_TYPE_SFT                                 1
 445         #define CQ_REQ_CQE_TYPE_REQ                                (0x0UL << 1)
 446         #define CQ_REQ_RESERVED3_MASK                               0xe0UL
 447         #define CQ_REQ_RESERVED3_SFT                                5
 448         u8 status;
 449         #define CQ_REQ_STATUS_OK                                   0x0UL
 450         #define CQ_REQ_STATUS_BAD_RESPONSE_ERR                     0x1UL
 451         #define CQ_REQ_STATUS_LOCAL_LENGTH_ERR                     0x2UL
 452         #define CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR               0x3UL
 453         #define CQ_REQ_STATUS_LOCAL_PROTECTION_ERR                 0x4UL
 454         #define CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR             0x5UL
 455         #define CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR           0x6UL
 456         #define CQ_REQ_STATUS_REMOTE_ACCESS_ERR            0x7UL
 457         #define CQ_REQ_STATUS_REMOTE_OPERATION_ERR                 0x8UL
 458         #define CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR                0x9UL
 459         #define CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR              0xaUL
 460         #define CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR             0xbUL
 461         __le16 reserved16_2;
 462         __le32 reserved32_1;
 463 };
 464
 465 /* Responder RC CQE (32 bytes) */
 466 struct cq_res_rc {
 467         __le32 length;
 468         __le32 imm_data_or_inv_r_key;
 469         __le64 qp_handle;
 470         __le64 mr_handle;
 471         u8 cqe_type_toggle;
 472         #define CQ_RES_RC_TOGGLE                                    0x1UL
 473         #define CQ_RES_RC_CQE_TYPE_MASK                     0x1eUL
 474         #define CQ_RES_RC_CQE_TYPE_SFT                              1
 475         #define CQ_RES_RC_CQE_TYPE_RES_RC                          (0x1UL << 1)
 476         #define CQ_RES_RC_RESERVED3_MASK                            0xe0UL
 477         #define CQ_RES_RC_RESERVED3_SFT                     5
 478         u8 status;
 479         #define CQ_RES_RC_STATUS_OK                                0x0UL
 480         #define CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR                0x1UL
 481         #define CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR                  0x2UL
 482         #define CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR              0x3UL
 483         #define CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR    0x4UL
 484         #define CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR          0x5UL
 485         #define CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR       0x6UL
 486         #define CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR          0x7UL
 487         #define CQ_RES_RC_STATUS_HW_FLUSH_ERR                      0x8UL
 488         __le16 flags;
 489         #define CQ_RES_RC_FLAGS_SRQ                                 0x1UL
 490         #define CQ_RES_RC_FLAGS_SRQ_RQ                             (0x0UL << 0)
 491         #define CQ_RES_RC_FLAGS_SRQ_SRQ                    (0x1UL << 0)
 492         #define CQ_RES_RC_FLAGS_SRQ_LAST    CQ_RES_RC_FLAGS_SRQ_SRQ
 493         #define CQ_RES_RC_FLAGS_IMM                                 0x2UL
 494         #define CQ_RES_RC_FLAGS_INV                                 0x4UL
 495         #define CQ_RES_RC_FLAGS_RDMA                                0x8UL
 496         #define CQ_RES_RC_FLAGS_RDMA_SEND                          (0x0UL << 3)
 497         #define CQ_RES_RC_FLAGS_RDMA_RDMA_WRITE            (0x1UL << 3)
 498         #define CQ_RES_RC_FLAGS_RDMA_LAST    CQ_RES_RC_FLAGS_RDMA_RDMA_WRITE
 499         __le32 srq_or_rq_wr_id;
 500         #define CQ_RES_RC_SRQ_OR_RQ_WR_ID_MASK                      0xfffffUL
 501         #define CQ_RES_RC_SRQ_OR_RQ_WR_ID_SFT                       0
 502         #define CQ_RES_RC_RESERVED12_MASK                           0xfff00000UL
 503         #define CQ_RES_RC_RESERVED12_SFT                            20
 504 };
 505
 506 /* Responder UD CQE (32 bytes) */
 507 struct cq_res_ud {
 508         __le32 length;
 509         #define CQ_RES_UD_LENGTH_MASK                               0x3fffUL
 510         #define CQ_RES_UD_LENGTH_SFT                                0
 511         #define CQ_RES_UD_RESERVED18_MASK                           0xffffc000UL
 512         #define CQ_RES_UD_RESERVED18_SFT                            14
 513         __le32 imm_data;
 514         __le64 qp_handle;
 515         __le16 src_mac[3];
 516         __le16 src_qp_low;
 517         u8 cqe_type_toggle;
 518         #define CQ_RES_UD_TOGGLE                                    0x1UL
 519         #define CQ_RES_UD_CQE_TYPE_MASK                     0x1eUL
 520         #define CQ_RES_UD_CQE_TYPE_SFT                              1
 521         #define CQ_RES_UD_CQE_TYPE_RES_UD                          (0x2UL << 1)
 522         #define CQ_RES_UD_RESERVED3_MASK                            0xe0UL
 523         #define CQ_RES_UD_RESERVED3_SFT                     5
 524         u8 status;
 525         #define CQ_RES_UD_STATUS_OK                                0x0UL
 526         #define CQ_RES_UD_STATUS_LOCAL_ACCESS_ERROR                0x1UL
 527         #define CQ_RES_UD_STATUS_HW_LOCAL_LENGTH_ERR               0x2UL
 528         #define CQ_RES_UD_STATUS_LOCAL_PROTECTION_ERR              0x3UL
 529         #define CQ_RES_UD_STATUS_LOCAL_QP_OPERATION_ERR    0x4UL
 530         #define CQ_RES_UD_STATUS_MEMORY_MGT_OPERATION_ERR          0x5UL
 531         #define CQ_RES_UD_STATUS_WORK_REQUEST_FLUSHED_ERR          0x7UL
 532         #define CQ_RES_UD_STATUS_HW_FLUSH_ERR                      0x8UL
 533         __le16 flags;
 534         #define CQ_RES_UD_FLAGS_SRQ                                 0x1UL
 535         #define CQ_RES_UD_FLAGS_SRQ_RQ                             (0x0UL << 0)
 536         #define CQ_RES_UD_FLAGS_SRQ_SRQ                    (0x1UL << 0)
 537         #define CQ_RES_UD_FLAGS_SRQ_LAST    CQ_RES_UD_FLAGS_SRQ_SRQ
 538         #define CQ_RES_UD_FLAGS_IMM                                 0x2UL
 539         #define CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK                    0xcUL
 540         #define CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT             2
 541         #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V1                     (0x0UL << 2)
 542         #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV4                 (0x2UL << 2)
 543         #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6                 (0x3UL << 2)
 544         #define CQ_RES_UD_FLAGS_ROCE_IP_VER_LAST                \
 545                                         CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6
 546         __le32 src_qp_high_srq_or_rq_wr_id;
 547         #define CQ_RES_UD_SRQ_OR_RQ_WR_ID_MASK                      0xfffffUL
 548         #define CQ_RES_UD_SRQ_OR_RQ_WR_ID_SFT                       0
 549         #define CQ_RES_UD_RESERVED4_MASK                            0xf00000UL
 550         #define CQ_RES_UD_RESERVED4_SFT                     20
 551         #define CQ_RES_UD_SRC_QP_HIGH_MASK                          0xff000000UL
 552         #define CQ_RES_UD_SRC_QP_HIGH_SFT                           24
 553 };
 554
 555 /* Responder RawEth and QP1 CQE (32 bytes) */
 556 struct cq_res_raweth_qp1 {
 557         __le16 length;
 558         #define CQ_RES_RAWETH_QP1_LENGTH_MASK                       0x3fffUL
 559         #define CQ_RES_RAWETH_QP1_LENGTH_SFT                        0
 560         #define CQ_RES_RAWETH_QP1_RESERVED2_MASK                    0xc000UL
 561         #define CQ_RES_RAWETH_QP1_RESERVED2_SFT             14
 562         __le16 raweth_qp1_flags;
 563         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ERROR            0x1UL
 564         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_RESERVED5_1_MASK 0x3eUL
 565         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_RESERVED5_1_SFT 1
 566         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_MASK      0x3c0UL
 567         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_SFT       6
 568         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_NOT_KNOWN (0x0UL << 6)
 569         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_IP       (0x1UL << 6)
 570         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_TCP      (0x2UL << 6)
 571         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_UDP      (0x3UL << 6)
 572         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_FCOE     (0x4UL << 6)
 573         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE     (0x5UL << 6)
 574         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ICMP     (0x7UL << 6)
 575         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
 576                                                                  (0x8UL << 6)
 577         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP \
 578                                                                  (0x9UL << 6)
 579         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_LAST   \
 580                 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP
 581         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_MASK     0x3ffUL
 582         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_SFT              0
 583         #define CQ_RES_RAWETH_QP1_RESERVED6_MASK                    0xfc00UL
 584         #define CQ_RES_RAWETH_QP1_RESERVED6_SFT             10
 585         __le16 raweth_qp1_errors;
 586         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_RESERVED4_MASK 0xfUL
 587         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_RESERVED4_SFT  0
 588         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_IP_CS_ERROR    0x10UL
 589         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_L4_CS_ERROR    0x20UL
 590         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_IP_CS_ERROR  0x40UL
 591         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_L4_CS_ERROR  0x80UL
 592         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_CRC_ERROR      0x100UL
 593         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK 0xe00UL
 594         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_SFT 9
 595         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR \
 596                                                                 (0x0UL << 9)
 597         #define \
 598            CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
 599                                                                 (0x1UL << 9)
 600         #define \
 601            CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
 602                                                                 (0x2UL << 9)
 603         #define \
 604            CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR \
 605                                                                 (0x3UL << 9)
 606         #define \
 607            CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
 608                                                                 (0x4UL << 9)
 609         #define \
 610            CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
 611                                                                 (0x5UL << 9)
 612         #define \
 613            CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
 614                                                                 (0x6UL << 9)
 615         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_LAST \
 616                 CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
 617         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_MASK 0xf000UL
 618         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_SFT  12
 619         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR \
 620                                                                 (0x0UL << 12)
 621         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION \
 622                                                                 (0x1UL << 12)
 623         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
 624                                                                  (0x2UL << 12)
 625         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL \
 626                                                                  (0x3UL << 12)
 627         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
 628                                                                  (0x4UL << 12)
 629         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
 630                                                                  (0x5UL << 12)
 631         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
 632                                                                  (0x6UL << 12)
 633         #define \
 634          CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL\
 635                                                                  (0x7UL << 12)
 636         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
 637                                                                  (0x8UL << 12)
 638         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_LAST \
 639                 CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
 640         __le16 raweth_qp1_cfa_code;
 641         __le64 qp_handle;
 642         __le32 raweth_qp1_flags2;
 643         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC     0x1UL
 644         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC     0x2UL
 645         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_IP_CS_CALC   0x4UL
 646         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_L4_CS_CALC   0x8UL
 647         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_MASK 0xf0UL
 648         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_SFT 4
 649         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_NONE \
 650                                                                 (0x0UL << 4)
 651         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN \
 652                                                                 (0x1UL << 4)
 653         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_LAST\
 654                         CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN
 655         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE         0x100UL
 656         __le32 raweth_qp1_metadata;
 657         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK     0xfffUL
 658         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_SFT      0
 659         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_DE            0x1000UL
 660         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK     0xe000UL
 661         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT      13
 662         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK    0xffff0000UL
 663         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT     16
 664         u8 cqe_type_toggle;
 665         #define CQ_RES_RAWETH_QP1_TOGGLE                            0x1UL
 666         #define CQ_RES_RAWETH_QP1_CQE_TYPE_MASK             0x1eUL
 667         #define CQ_RES_RAWETH_QP1_CQE_TYPE_SFT                      1
 668         #define CQ_RES_RAWETH_QP1_CQE_TYPE_RES_RAWETH_QP1          (0x3UL << 1)
 669         #define CQ_RES_RAWETH_QP1_RESERVED3_MASK                    0xe0UL
 670         #define CQ_RES_RAWETH_QP1_RESERVED3_SFT             5
 671         u8 status;
 672         #define CQ_RES_RAWETH_QP1_STATUS_OK                        0x0UL
 673         #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR       0x1UL
 674         #define CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR      0x2UL
 675         #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR     0x3UL
 676         #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR   0x4UL
 677         #define CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL
 678         #define CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL
 679         #define CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR              0x8UL
 680         __le16 flags;
 681         #define CQ_RES_RAWETH_QP1_FLAGS_SRQ                         0x1UL
 682         #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_RQ                     0x0UL
 683         #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ            0x1UL
 684         #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_LAST \
 685                                         CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ
 686         __le32 raweth_qp1_payload_offset_srq_or_rq_wr_id;
 687         #define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_MASK              0xfffffUL
 688         #define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_SFT               0
 689         #define CQ_RES_RAWETH_QP1_RESERVED4_MASK                    0xf00000UL
 690         #define CQ_RES_RAWETH_QP1_RESERVED4_SFT             20
 691         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_MASK   0xff000000UL
 692         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_SFT    24
 693 };
 694
 695 /* Terminal CQE (32 bytes) */
 696 struct cq_terminal {
 697         __le64 qp_handle;
 698         __le16 sq_cons_idx;
 699         __le16 rq_cons_idx;
 700         __le32 reserved32_1;
 701         __le64 reserved64_3;
 702         u8 cqe_type_toggle;
 703         #define CQ_TERMINAL_TOGGLE                                  0x1UL
 704         #define CQ_TERMINAL_CQE_TYPE_MASK                           0x1eUL
 705         #define CQ_TERMINAL_CQE_TYPE_SFT                            1
 706         #define CQ_TERMINAL_CQE_TYPE_TERMINAL                      (0xeUL << 1)
 707         #define CQ_TERMINAL_RESERVED3_MASK                          0xe0UL
 708         #define CQ_TERMINAL_RESERVED3_SFT                           5
 709         u8 status;
 710         #define CQ_TERMINAL_STATUS_OK                              0x0UL
 711         __le16 reserved16;
 712         __le32 reserved32_2;
 713 };
 714
 715 /* Cutoff CQE (32 bytes) */
 716 struct cq_cutoff {
 717         __le64 reserved64_1;
 718         __le64 reserved64_2;
 719         __le64 reserved64_3;
 720         u8 cqe_type_toggle;
 721         #define CQ_CUTOFF_TOGGLE                                    0x1UL
 722         #define CQ_CUTOFF_CQE_TYPE_MASK                     0x1eUL
 723         #define CQ_CUTOFF_CQE_TYPE_SFT                              1
 724         #define CQ_CUTOFF_CQE_TYPE_CUT_OFF                         (0xfUL << 1)
 725         #define CQ_CUTOFF_RESERVED3_MASK                            0xe0UL
 726         #define CQ_CUTOFF_RESERVED3_SFT                     5
 727         u8 status;
 728         #define CQ_CUTOFF_STATUS_OK                                0x0UL
 729         __le16 reserved16;
 730         __le32 reserved32;
 731 };
 732
 733 /* Notification Queue (NQ) Structures */
 734 /* Base NQ Record (16 bytes) */
 735 struct nq_base {
 736         __le16 info10_type;
 737         #define NQ_BASE_TYPE_MASK                                   0x3fUL
 738         #define NQ_BASE_TYPE_SFT                                    0
 739         #define NQ_BASE_TYPE_CQ_NOTIFICATION                       0x30UL
 740         #define NQ_BASE_TYPE_SRQ_EVENT                             0x32UL
 741         #define NQ_BASE_TYPE_DBQ_EVENT                             0x34UL
 742         #define NQ_BASE_TYPE_QP_EVENT                              0x38UL
 743         #define NQ_BASE_TYPE_FUNC_EVENT                    0x3aUL
 744         #define NQ_BASE_INFO10_MASK                                 0xffc0UL
 745         #define NQ_BASE_INFO10_SFT                                  6
 746         __le16 info16;
 747         __le32 info32;
 748         __le32 info63_v[2];
 749         #define NQ_BASE_V                                           0x1UL
 750         #define NQ_BASE_INFO63_MASK                                 0xfffffffeUL
 751         #define NQ_BASE_INFO63_SFT                                  1
 752 };
 753
 754 /* Completion Queue Notification (16 bytes) */
 755 struct nq_cn {
 756         __le16 type;
 757         #define NQ_CN_TYPE_MASK                             0x3fUL
 758         #define NQ_CN_TYPE_SFT                                      0
 759         #define NQ_CN_TYPE_CQ_NOTIFICATION                         0x30UL
 760         #define NQ_CN_RESERVED9_MASK                                0xffc0UL
 761         #define NQ_CN_RESERVED9_SFT                                 6
 762         __le16 reserved16;
 763         __le32 cq_handle_low;
 764         __le32 v;
 765         #define NQ_CN_V                                     0x1UL
 766         #define NQ_CN_RESERVED31_MASK                               0xfffffffeUL
 767         #define NQ_CN_RESERVED31_SFT                                1
 768         __le32 cq_handle_high;
 769 };
 770
 771 /* SRQ Event Notification (16 bytes) */
 772 struct nq_srq_event {
 773         u8 type;
 774         #define NQ_SRQ_EVENT_TYPE_MASK                              0x3fUL
 775         #define NQ_SRQ_EVENT_TYPE_SFT                               0
 776         #define NQ_SRQ_EVENT_TYPE_SRQ_EVENT                        0x32UL
 777         #define NQ_SRQ_EVENT_RESERVED1_MASK                         0xc0UL
 778         #define NQ_SRQ_EVENT_RESERVED1_SFT                          6
 779         u8 event;
 780         #define NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT             0x1UL
 781         __le16 reserved16;
 782         __le32 srq_handle_low;
 783         __le32 v;
 784         #define NQ_SRQ_EVENT_V                                      0x1UL
 785         #define NQ_SRQ_EVENT_RESERVED31_MASK                        0xfffffffeUL
 786         #define NQ_SRQ_EVENT_RESERVED31_SFT                         1
 787         __le32 srq_handle_high;
 788 };
 789
 790 /* DBQ Async Event Notification (16 bytes) */
 791 struct nq_dbq_event {
 792         u8 type;
 793         #define NQ_DBQ_EVENT_TYPE_MASK                              0x3fUL
 794         #define NQ_DBQ_EVENT_TYPE_SFT                               0
 795         #define NQ_DBQ_EVENT_TYPE_DBQ_EVENT                        0x34UL
 796         #define NQ_DBQ_EVENT_RESERVED1_MASK                         0xc0UL
 797         #define NQ_DBQ_EVENT_RESERVED1_SFT                          6
 798         u8 event;
 799         #define NQ_DBQ_EVENT_EVENT_DBQ_THRESHOLD_EVENT             0x1UL
 800         __le16 db_pfid;
 801         #define NQ_DBQ_EVENT_DB_PFID_MASK                           0xfUL
 802         #define NQ_DBQ_EVENT_DB_PFID_SFT                            0
 803         #define NQ_DBQ_EVENT_RESERVED12_MASK                        0xfff0UL
 804         #define NQ_DBQ_EVENT_RESERVED12_SFT                         4
 805         __le32 db_dpi;
 806         #define NQ_DBQ_EVENT_DB_DPI_MASK                            0xfffffUL
 807         #define NQ_DBQ_EVENT_DB_DPI_SFT                     0
 808         #define NQ_DBQ_EVENT_RESERVED12_2_MASK                      0xfff00000UL
 809         #define NQ_DBQ_EVENT_RESERVED12_2_SFT                       20
 810         __le32 v;
 811         #define NQ_DBQ_EVENT_V                                      0x1UL
 812         #define NQ_DBQ_EVENT_RESERVED32_MASK                        0xfffffffeUL
 813         #define NQ_DBQ_EVENT_RESERVED32_SFT                         1
 814         __le32 db_type_db_xid;
 815         #define NQ_DBQ_EVENT_DB_XID_MASK                            0xfffffUL
 816         #define NQ_DBQ_EVENT_DB_XID_SFT                     0
 817         #define NQ_DBQ_EVENT_RESERVED8_MASK                         0xff00000UL
 818         #define NQ_DBQ_EVENT_RESERVED8_SFT                          20
 819         #define NQ_DBQ_EVENT_DB_TYPE_MASK                           0xf0000000UL
 820         #define NQ_DBQ_EVENT_DB_TYPE_SFT                            28
 821 };
 822
 823 /* Read Request/Response Queue Structures */
 824 /* Input Read Request Queue (IRRQ) Message (32 bytes) */
 825 struct xrrq_irrq {
 826         __le16 credits_type;
 827         #define XRRQ_IRRQ_TYPE                                      0x1UL
 828         #define XRRQ_IRRQ_TYPE_READ_REQ                    0x0UL
 829         #define XRRQ_IRRQ_TYPE_ATOMIC_REQ                          0x1UL
 830         #define XRRQ_IRRQ_RESERVED10_MASK                           0x7feUL
 831         #define XRRQ_IRRQ_RESERVED10_SFT                            1
 832         #define XRRQ_IRRQ_CREDITS_MASK                              0xf800UL
 833         #define XRRQ_IRRQ_CREDITS_SFT                               11
 834         __le16 reserved16;
 835         __le32 reserved32;
 836         __le32 psn;
 837         #define XRRQ_IRRQ_PSN_MASK                                  0xffffffUL
 838         #define XRRQ_IRRQ_PSN_SFT                                   0
 839         #define XRRQ_IRRQ_RESERVED8_1_MASK                          0xff000000UL
 840         #define XRRQ_IRRQ_RESERVED8_1_SFT                           24
 841         __le32 msn;
 842         #define XRRQ_IRRQ_MSN_MASK                                  0xffffffUL
 843         #define XRRQ_IRRQ_MSN_SFT                                   0
 844         #define XRRQ_IRRQ_RESERVED8_2_MASK                          0xff000000UL
 845         #define XRRQ_IRRQ_RESERVED8_2_SFT                           24
 846         __le64 va_or_atomic_result;
 847         __le32 rdma_r_key;
 848         __le32 length;
 849 };
 850
 851 /* Output Read Request Queue (ORRQ) Message (32 bytes) */
 852 struct xrrq_orrq {
 853         __le16 num_sges_type;
 854         #define XRRQ_ORRQ_TYPE                                      0x1UL
 855         #define XRRQ_ORRQ_TYPE_READ_REQ                    0x0UL
 856         #define XRRQ_ORRQ_TYPE_ATOMIC_REQ                          0x1UL
 857         #define XRRQ_ORRQ_RESERVED10_MASK                           0x7feUL
 858         #define XRRQ_ORRQ_RESERVED10_SFT                            1
 859         #define XRRQ_ORRQ_NUM_SGES_MASK                     0xf800UL
 860         #define XRRQ_ORRQ_NUM_SGES_SFT                              11
 861         __le16 reserved16;
 862         __le32 length;
 863         __le32 psn;
 864         #define XRRQ_ORRQ_PSN_MASK                                  0xffffffUL
 865         #define XRRQ_ORRQ_PSN_SFT                                   0
 866         #define XRRQ_ORRQ_RESERVED8_1_MASK                          0xff000000UL
 867         #define XRRQ_ORRQ_RESERVED8_1_SFT                           24
 868         __le32 end_psn;
 869         #define XRRQ_ORRQ_END_PSN_MASK                              0xffffffUL
 870         #define XRRQ_ORRQ_END_PSN_SFT                               0
 871         #define XRRQ_ORRQ_RESERVED8_2_MASK                          0xff000000UL
 872         #define XRRQ_ORRQ_RESERVED8_2_SFT                           24
 873         __le64 first_sge_phy_or_sing_sge_va;
 874         __le32 single_sge_l_key;
 875         __le32 single_sge_size;
 876 };
 877
 878 /* Page Buffer List Memory Structures (PBL) */
 879 /* Page Table Entry (PTE) (8 bytes) */
 880 struct ptu_pte {
 881         __le32 page_next_to_last_last_valid[2];
 882         #define PTU_PTE_VALID                                       0x1UL
 883         #define PTU_PTE_LAST                                        0x2UL
 884         #define PTU_PTE_NEXT_TO_LAST                                0x4UL
 885         #define PTU_PTE_PAGE_MASK                                   0xfffff000UL
 886         #define PTU_PTE_PAGE_SFT                                    12
 887 };
 888
 889 /* Page Directory Entry (PDE) (8 bytes) */
 890 struct ptu_pde {
 891         __le32 page_valid[2];
 892         #define PTU_PDE_VALID                                       0x1UL
 893         #define PTU_PDE_PAGE_MASK                                   0xfffff000UL
 894         #define PTU_PDE_PAGE_SFT                                    12
 895 };
 896
 897 /* RoCE Fastpath Host Structures */
 898 /* Command Queue (CMDQ) Interface */
 899 /* Init CMDQ (16 bytes) */
 900 struct cmdq_init {
 901         __le64 cmdq_pbl;
 902         __le16 cmdq_size_cmdq_lvl;
 903         #define CMDQ_INIT_CMDQ_LVL_MASK                     0x3UL
 904         #define CMDQ_INIT_CMDQ_LVL_SFT                              0
 905         #define CMDQ_INIT_CMDQ_SIZE_MASK                            0xfffcUL
 906         #define CMDQ_INIT_CMDQ_SIZE_SFT                     2
 907         __le16 creq_ring_id;
 908         __le32 prod_idx;
 909 };
 910
 911 /* Update CMDQ producer index (16 bytes) */
 912 struct cmdq_update {
 913         __le64 reserved64;
 914         __le32 reserved32;
 915         __le32 prod_idx;
 916 };
 917
 918 /* CMDQ common header structure (16 bytes) */
 919 struct cmdq_base {
 920         u8 opcode;
 921         #define CMDQ_BASE_OPCODE_CREATE_QP                         0x1UL
 922         #define CMDQ_BASE_OPCODE_DESTROY_QP                        0x2UL
 923         #define CMDQ_BASE_OPCODE_MODIFY_QP                         0x3UL
 924         #define CMDQ_BASE_OPCODE_QUERY_QP                          0x4UL
 925         #define CMDQ_BASE_OPCODE_CREATE_SRQ                        0x5UL
 926         #define CMDQ_BASE_OPCODE_DESTROY_SRQ                       0x6UL
 927         #define CMDQ_BASE_OPCODE_QUERY_SRQ                         0x8UL
 928         #define CMDQ_BASE_OPCODE_CREATE_CQ                         0x9UL
 929         #define CMDQ_BASE_OPCODE_DESTROY_CQ                        0xaUL
 930         #define CMDQ_BASE_OPCODE_RESIZE_CQ                         0xcUL
 931         #define CMDQ_BASE_OPCODE_ALLOCATE_MRW                      0xdUL
 932         #define CMDQ_BASE_OPCODE_DEALLOCATE_KEY            0xeUL
 933         #define CMDQ_BASE_OPCODE_REGISTER_MR                       0xfUL
 934         #define CMDQ_BASE_OPCODE_DEREGISTER_MR                     0x10UL
 935         #define CMDQ_BASE_OPCODE_ADD_GID                           0x11UL
 936         #define CMDQ_BASE_OPCODE_DELETE_GID                        0x12UL
 937         #define CMDQ_BASE_OPCODE_MODIFY_GID                        0x17UL
 938         #define CMDQ_BASE_OPCODE_QUERY_GID                         0x18UL
 939         #define CMDQ_BASE_OPCODE_CREATE_QP1                        0x13UL
 940         #define CMDQ_BASE_OPCODE_DESTROY_QP1                       0x14UL
 941         #define CMDQ_BASE_OPCODE_CREATE_AH                         0x15UL
 942         #define CMDQ_BASE_OPCODE_DESTROY_AH                        0x16UL
 943         #define CMDQ_BASE_OPCODE_INITIALIZE_FW                     0x80UL
 944         #define CMDQ_BASE_OPCODE_DEINITIALIZE_FW                   0x81UL
 945         #define CMDQ_BASE_OPCODE_STOP_FUNC                         0x82UL
 946         #define CMDQ_BASE_OPCODE_QUERY_FUNC                        0x83UL
 947         #define CMDQ_BASE_OPCODE_SET_FUNC_RESOURCES                0x84UL
 948         #define CMDQ_BASE_OPCODE_READ_CONTEXT                      0x85UL
 949         #define CMDQ_BASE_OPCODE_VF_BACKCHANNEL_REQUEST    0x86UL
 950         #define CMDQ_BASE_OPCODE_READ_VF_MEMORY            0x87UL
 951         #define CMDQ_BASE_OPCODE_COMPLETE_VF_REQUEST               0x88UL
 952         #define CMDQ_BASE_OPCODE_EXTEND_CONTEXT_ARRRAY             0x89UL
 953         #define CMDQ_BASE_OPCODE_MAP_TC_TO_COS                     0x8aUL
 954         #define CMDQ_BASE_OPCODE_QUERY_VERSION                     0x8bUL
 955         #define CMDQ_BASE_OPCODE_MODIFY_CC                         0x8cUL
 956         #define CMDQ_BASE_OPCODE_QUERY_CC                          0x8dUL
 957         #define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS          0x8eUL
 958         u8 cmd_size;
 959         __le16 flags;
 960         __le16 cookie;
 961         u8 resp_size;
 962         u8 reserved8;
 963         __le64 resp_addr;
 964 };
 965
 966 /* Create QP command (96 bytes) */
 967 struct cmdq_create_qp {
 968         u8 opcode;
 969         #define CMDQ_CREATE_QP_OPCODE_CREATE_QP            0x1UL
 970         u8 cmd_size;
 971         __le16 flags;
 972         __le16 cookie;
 973         u8 resp_size;
 974         u8 reserved8;
 975         __le64 resp_addr;
 976         __le64 qp_handle;
 977         __le32 qp_flags;
 978         #define CMDQ_CREATE_QP_QP_FLAGS_SRQ_USED                   0x1UL
 979         #define CMDQ_CREATE_QP_QP_FLAGS_FORCE_COMPLETION           0x2UL
 980         #define CMDQ_CREATE_QP_QP_FLAGS_RESERVED_LKEY_ENABLE      0x4UL
 981         #define CMDQ_CREATE_QP_QP_FLAGS_FR_PMR_ENABLED             0x8UL
 982         u8 type;
 983         #define CMDQ_CREATE_QP_TYPE_RC                             0x2UL
 984         #define CMDQ_CREATE_QP_TYPE_UD                             0x4UL
 985         #define CMDQ_CREATE_QP_TYPE_RAW_ETHERTYPE                  0x6UL
 986         u8 sq_pg_size_sq_lvl;
 987         #define CMDQ_CREATE_QP_SQ_LVL_MASK                          0xfUL
 988         #define CMDQ_CREATE_QP_SQ_LVL_SFT                           0
 989         #define CMDQ_CREATE_QP_SQ_LVL_LVL_0                        0x0UL
 990         #define CMDQ_CREATE_QP_SQ_LVL_LVL_1                        0x1UL
 991         #define CMDQ_CREATE_QP_SQ_LVL_LVL_2                        0x2UL
 992         #define CMDQ_CREATE_QP_SQ_PG_SIZE_MASK                      0xf0UL
 993         #define CMDQ_CREATE_QP_SQ_PG_SIZE_SFT                       4
 994         #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_4K            (0x0UL << 4)
 995         #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8K            (0x1UL << 4)
 996         #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_64K                   (0x2UL << 4)
 997         #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_2M            (0x3UL << 4)
 998         #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8M            (0x4UL << 4)
 999         #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_1G            (0x5UL << 4)
1000         u8 rq_pg_size_rq_lvl;
1001         #define CMDQ_CREATE_QP_RQ_LVL_MASK                          0xfUL
1002         #define CMDQ_CREATE_QP_RQ_LVL_SFT                           0
1003         #define CMDQ_CREATE_QP_RQ_LVL_LVL_0                        0x0UL
1004         #define CMDQ_CREATE_QP_RQ_LVL_LVL_1                        0x1UL
1005         #define CMDQ_CREATE_QP_RQ_LVL_LVL_2                        0x2UL
1006         #define CMDQ_CREATE_QP_RQ_PG_SIZE_MASK                      0xf0UL
1007         #define CMDQ_CREATE_QP_RQ_PG_SIZE_SFT                       4
1008         #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_4K            (0x0UL << 4)
1009         #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8K            (0x1UL << 4)
1010         #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_64K                   (0x2UL << 4)
1011         #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_2M            (0x3UL << 4)
1012         #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8M            (0x4UL << 4)
1013         #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_1G            (0x5UL << 4)
1014         u8 unused_0;
1015         __le32 dpi;
1016         __le32 sq_size;
1017         __le32 rq_size;
1018         __le16 sq_fwo_sq_sge;
1019         #define CMDQ_CREATE_QP_SQ_SGE_MASK                          0xfUL
1020         #define CMDQ_CREATE_QP_SQ_SGE_SFT                           0
1021         #define CMDQ_CREATE_QP_SQ_FWO_MASK                          0xfff0UL
1022         #define CMDQ_CREATE_QP_SQ_FWO_SFT                           4
1023         __le16 rq_fwo_rq_sge;
1024         #define CMDQ_CREATE_QP_RQ_SGE_MASK                          0xfUL
1025         #define CMDQ_CREATE_QP_RQ_SGE_SFT                           0
1026         #define CMDQ_CREATE_QP_RQ_FWO_MASK                          0xfff0UL
1027         #define CMDQ_CREATE_QP_RQ_FWO_SFT                           4
1028         __le32 scq_cid;
1029         __le32 rcq_cid;
1030         __le32 srq_cid;
1031         __le32 pd_id;
1032         __le64 sq_pbl;
1033         __le64 rq_pbl;
1034         __le64 irrq_addr;
1035         __le64 orrq_addr;
1036 };
1037
1038 /* Destroy QP command (24 bytes) */
1039 struct cmdq_destroy_qp {
1040         u8 opcode;
1041         #define CMDQ_DESTROY_QP_OPCODE_DESTROY_QP                  0x2UL
1042         u8 cmd_size;
1043         __le16 flags;
1044         __le16 cookie;
1045         u8 resp_size;
1046         u8 reserved8;
1047         __le64 resp_addr;
1048         __le32 qp_cid;
1049         __le32 unused_0;
1050 };
1051
1052 /* Modify QP command (112 bytes) */
1053 struct cmdq_modify_qp {
1054         u8 opcode;
1055         #define CMDQ_MODIFY_QP_OPCODE_MODIFY_QP            0x3UL
1056         u8 cmd_size;
1057         __le16 flags;
1058         __le16 cookie;
1059         u8 resp_size;
1060         u8 reserved8;
1061         __le64 resp_addr;
1062         __le32 modify_mask;
1063         #define CMDQ_MODIFY_QP_MODIFY_MASK_STATE                    0x1UL
1064         #define CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY     0x2UL
1065         #define CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS                   0x4UL
1066         #define CMDQ_MODIFY_QP_MODIFY_MASK_PKEY             0x8UL
1067         #define CMDQ_MODIFY_QP_MODIFY_MASK_QKEY             0x10UL
1068         #define CMDQ_MODIFY_QP_MODIFY_MASK_DGID             0x20UL
1069         #define CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL               0x40UL
1070         #define CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX               0x80UL
1071         #define CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT                0x100UL
1072         #define CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS            0x200UL
1073         #define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC                 0x400UL
1074         #define CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU                 0x1000UL
1075         #define CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT                  0x2000UL
1076         #define CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT                0x4000UL
1077         #define CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY                0x8000UL
1078         #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN                   0x10000UL
1079         #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC            0x20000UL
1080         #define CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER            0x40000UL
1081         #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN                   0x80000UL
1082         #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC      0x100000UL
1083         #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE                  0x200000UL
1084         #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE                  0x400000UL
1085         #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE                   0x800000UL
1086         #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE                   0x1000000UL
1087         #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA          0x2000000UL
1088         #define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID               0x4000000UL
1089         #define CMDQ_MODIFY_QP_MODIFY_MASK_SRC_MAC                  0x8000000UL
1090         #define CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID                  0x10000000UL
1091         #define CMDQ_MODIFY_QP_MODIFY_MASK_ENABLE_CC                0x20000000UL
1092         #define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_ECN                  0x40000000UL
1093         #define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_DSCP                 0x80000000UL
1094         __le32 qp_cid;
1095         u8 network_type_en_sqd_async_notify_new_state;
1096         #define CMDQ_MODIFY_QP_NEW_STATE_MASK                       0xfUL
1097         #define CMDQ_MODIFY_QP_NEW_STATE_SFT                        0
1098         #define CMDQ_MODIFY_QP_NEW_STATE_RESET                     0x0UL
1099         #define CMDQ_MODIFY_QP_NEW_STATE_INIT                      0x1UL
1100         #define CMDQ_MODIFY_QP_NEW_STATE_RTR                       0x2UL
1101         #define CMDQ_MODIFY_QP_NEW_STATE_RTS                       0x3UL
1102         #define CMDQ_MODIFY_QP_NEW_STATE_SQD                       0x4UL
1103         #define CMDQ_MODIFY_QP_NEW_STATE_SQE                       0x5UL
1104         #define CMDQ_MODIFY_QP_NEW_STATE_ERR                       0x6UL
1105         #define CMDQ_MODIFY_QP_EN_SQD_ASYNC_NOTIFY                  0x10UL
1106         #define CMDQ_MODIFY_QP_NETWORK_TYPE_MASK                    0xc0UL
1107         #define CMDQ_MODIFY_QP_NETWORK_TYPE_SFT             6
1108         #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1                 (0x0UL << 6)
1109         #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4    (0x2UL << 6)
1110         #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6    (0x3UL << 6)
1111         u8 access;
1112         #define CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE                   0x1UL
1113         #define CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE                  0x2UL
1114         #define CMDQ_MODIFY_QP_ACCESS_REMOTE_READ                   0x4UL
1115         #define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC                 0x8UL
1116         __le16 pkey;
1117         __le32 qkey;
1118         __le32 dgid[4];
1119         __le32 flow_label;
1120         __le16 sgid_index;
1121         u8 hop_limit;
1122         u8 traffic_class;
1123         __le16 dest_mac[3];
1124         u8 tos_dscp_tos_ecn;
1125         #define CMDQ_MODIFY_QP_TOS_ECN_MASK                         0x3UL
1126         #define CMDQ_MODIFY_QP_TOS_ECN_SFT                          0
1127         #define CMDQ_MODIFY_QP_TOS_DSCP_MASK                        0xfcUL
1128         #define CMDQ_MODIFY_QP_TOS_DSCP_SFT                         2
1129         u8 path_mtu;
1130         #define CMDQ_MODIFY_QP_PATH_MTU_MASK                        0xf0UL
1131         #define CMDQ_MODIFY_QP_PATH_MTU_SFT                         4
1132         #define CMDQ_MODIFY_QP_PATH_MTU_MTU_256            (0x0UL << 4)
1133         #define CMDQ_MODIFY_QP_PATH_MTU_MTU_512            (0x1UL << 4)
1134         #define CMDQ_MODIFY_QP_PATH_MTU_MTU_1024                   (0x2UL << 4)
1135         #define CMDQ_MODIFY_QP_PATH_MTU_MTU_2048                   (0x3UL << 4)
1136         #define CMDQ_MODIFY_QP_PATH_MTU_MTU_4096                   (0x4UL << 4)
1137         #define CMDQ_MODIFY_QP_PATH_MTU_MTU_8192                   (0x5UL << 4)
1138         u8 timeout;
1139         u8 retry_cnt;
1140         u8 rnr_retry;
1141         u8 min_rnr_timer;
1142         __le32 rq_psn;
1143         __le32 sq_psn;
1144         u8 max_rd_atomic;
1145         u8 max_dest_rd_atomic;
1146         __le16 enable_cc;
1147         #define CMDQ_MODIFY_QP_ENABLE_CC                            0x1UL
1148         __le32 sq_size;
1149         __le32 rq_size;
1150         __le16 sq_sge;
1151         __le16 rq_sge;
1152         __le32 max_inline_data;
1153         __le32 dest_qp_id;
1154         __le32 unused_3;
1155         __le16 src_mac[3];
1156         __le16 vlan_pcp_vlan_dei_vlan_id;
1157         #define CMDQ_MODIFY_QP_VLAN_ID_MASK                         0xfffUL
1158         #define CMDQ_MODIFY_QP_VLAN_ID_SFT                          0
1159         #define CMDQ_MODIFY_QP_VLAN_DEI                     0x1000UL
1160         #define CMDQ_MODIFY_QP_VLAN_PCP_MASK                        0xe000UL
1161         #define CMDQ_MODIFY_QP_VLAN_PCP_SFT                         13
1162 };
1163
1164 /* Query QP command (24 bytes) */
1165 struct cmdq_query_qp {
1166         u8 opcode;
1167         #define CMDQ_QUERY_QP_OPCODE_QUERY_QP                      0x4UL
1168         u8 cmd_size;
1169         __le16 flags;
1170         __le16 cookie;
1171         u8 resp_size;
1172         u8 reserved8;
1173         __le64 resp_addr;
1174         __le32 qp_cid;
1175         __le32 unused_0;
1176 };
1177
1178 /* Create SRQ command (48 bytes) */
1179 struct cmdq_create_srq {
1180         u8 opcode;
1181         #define CMDQ_CREATE_SRQ_OPCODE_CREATE_SRQ                  0x5UL
1182         u8 cmd_size;
1183         __le16 flags;
1184         __le16 cookie;
1185         u8 resp_size;
1186         u8 reserved8;
1187         __le64 resp_addr;
1188         __le64 srq_handle;
1189         __le16 pg_size_lvl;
1190         #define CMDQ_CREATE_SRQ_LVL_MASK                            0x3UL
1191         #define CMDQ_CREATE_SRQ_LVL_SFT                     0
1192         #define CMDQ_CREATE_SRQ_LVL_LVL_0                          0x0UL
1193         #define CMDQ_CREATE_SRQ_LVL_LVL_1                          0x1UL
1194         #define CMDQ_CREATE_SRQ_LVL_LVL_2                          0x2UL
1195         #define CMDQ_CREATE_SRQ_PG_SIZE_MASK                        0x1cUL
1196         #define CMDQ_CREATE_SRQ_PG_SIZE_SFT                         2
1197         #define CMDQ_CREATE_SRQ_PG_SIZE_PG_4K                      (0x0UL << 2)
1198         #define CMDQ_CREATE_SRQ_PG_SIZE_PG_8K                      (0x1UL << 2)
1199         #define CMDQ_CREATE_SRQ_PG_SIZE_PG_64K                     (0x2UL << 2)
1200         #define CMDQ_CREATE_SRQ_PG_SIZE_PG_2M                      (0x3UL << 2)
1201         #define CMDQ_CREATE_SRQ_PG_SIZE_PG_8M                      (0x4UL << 2)
1202         #define CMDQ_CREATE_SRQ_PG_SIZE_PG_1G                      (0x5UL << 2)
1203         __le16 eventq_id;
1204         #define CMDQ_CREATE_SRQ_EVENTQ_ID_MASK                      0xfffUL
1205         #define CMDQ_CREATE_SRQ_EVENTQ_ID_SFT                       0
1206         __le16 srq_size;
1207         __le16 srq_fwo;
1208         __le32 dpi;
1209         __le32 pd_id;
1210         __le64 pbl;
1211 };
1212
1213 /* Destroy SRQ command (24 bytes) */
1214 struct cmdq_destroy_srq {
1215         u8 opcode;
1216         #define CMDQ_DESTROY_SRQ_OPCODE_DESTROY_SRQ                0x6UL
1217         u8 cmd_size;
1218         __le16 flags;
1219         __le16 cookie;
1220         u8 resp_size;
1221         u8 reserved8;
1222         __le64 resp_addr;
1223         __le32 srq_cid;
1224         __le32 unused_0;
1225 };
1226
1227 /* Query SRQ command (24 bytes) */
1228 struct cmdq_query_srq {
1229         u8 opcode;
1230         #define CMDQ_QUERY_SRQ_OPCODE_QUERY_SRQ            0x8UL
1231         u8 cmd_size;
1232         __le16 flags;
1233         __le16 cookie;
1234         u8 resp_size;
1235         u8 reserved8;
1236         __le64 resp_addr;
1237         __le32 srq_cid;
1238         __le32 unused_0;
1239 };
1240
1241 /* Create CQ command (48 bytes) */
1242 struct cmdq_create_cq {
1243         u8 opcode;
1244         #define CMDQ_CREATE_CQ_OPCODE_CREATE_CQ            0x9UL
1245         u8 cmd_size;
1246         __le16 flags;
1247         __le16 cookie;
1248         u8 resp_size;
1249         u8 reserved8;
1250         __le64 resp_addr;
1251         __le64 cq_handle;
1252         __le32 pg_size_lvl;
1253         #define CMDQ_CREATE_CQ_LVL_MASK                     0x3UL
1254         #define CMDQ_CREATE_CQ_LVL_SFT                              0
1255         #define CMDQ_CREATE_CQ_LVL_LVL_0                           0x0UL
1256         #define CMDQ_CREATE_CQ_LVL_LVL_1                           0x1UL
1257         #define CMDQ_CREATE_CQ_LVL_LVL_2                           0x2UL
1258         #define CMDQ_CREATE_CQ_PG_SIZE_MASK                         0x1cUL
1259         #define CMDQ_CREATE_CQ_PG_SIZE_SFT                          2
1260         #define CMDQ_CREATE_CQ_PG_SIZE_PG_4K                       (0x0UL << 2)
1261         #define CMDQ_CREATE_CQ_PG_SIZE_PG_8K                       (0x1UL << 2)
1262         #define CMDQ_CREATE_CQ_PG_SIZE_PG_64K                      (0x2UL << 2)
1263         #define CMDQ_CREATE_CQ_PG_SIZE_PG_2M                       (0x3UL << 2)
1264         #define CMDQ_CREATE_CQ_PG_SIZE_PG_8M                       (0x4UL << 2)
1265         #define CMDQ_CREATE_CQ_PG_SIZE_PG_1G                       (0x5UL << 2)
1266         __le32 cq_fco_cnq_id;
1267         #define CMDQ_CREATE_CQ_CNQ_ID_MASK                          0xfffUL
1268         #define CMDQ_CREATE_CQ_CNQ_ID_SFT                           0
1269         #define CMDQ_CREATE_CQ_CQ_FCO_MASK                          0xfffff000UL
1270         #define CMDQ_CREATE_CQ_CQ_FCO_SFT                           12
1271         __le32 dpi;
1272         __le32 cq_size;
1273         __le64 pbl;
1274 };
1275
1276 /* Destroy CQ command (24 bytes) */
1277 struct cmdq_destroy_cq {
1278         u8 opcode;
1279         #define CMDQ_DESTROY_CQ_OPCODE_DESTROY_CQ                  0xaUL
1280         u8 cmd_size;
1281         __le16 flags;
1282         __le16 cookie;
1283         u8 resp_size;
1284         u8 reserved8;
1285         __le64 resp_addr;
1286         __le32 cq_cid;
1287         __le32 unused_0;
1288 };
1289
1290 /* Resize CQ command (40 bytes) */
1291 struct cmdq_resize_cq {
1292         u8 opcode;
1293         #define CMDQ_RESIZE_CQ_OPCODE_RESIZE_CQ            0xcUL
1294         u8 cmd_size;
1295         __le16 flags;
1296         __le16 cookie;
1297         u8 resp_size;
1298         u8 reserved8;
1299         __le64 resp_addr;
1300         __le32 cq_cid;
1301         __le32 new_cq_size_pg_size_lvl;
1302         #define CMDQ_RESIZE_CQ_LVL_MASK                     0x3UL
1303         #define CMDQ_RESIZE_CQ_LVL_SFT                              0
1304         #define CMDQ_RESIZE_CQ_LVL_LVL_0                           0x0UL
1305         #define CMDQ_RESIZE_CQ_LVL_LVL_1                           0x1UL
1306         #define CMDQ_RESIZE_CQ_LVL_LVL_2                           0x2UL
1307         #define CMDQ_RESIZE_CQ_PG_SIZE_MASK                         0x1cUL
1308         #define CMDQ_RESIZE_CQ_PG_SIZE_SFT                          2
1309         #define CMDQ_RESIZE_CQ_PG_SIZE_PG_4K                       (0x0UL << 2)
1310         #define CMDQ_RESIZE_CQ_PG_SIZE_PG_8K                       (0x1UL << 2)
1311         #define CMDQ_RESIZE_CQ_PG_SIZE_PG_64K                      (0x2UL << 2)
1312         #define CMDQ_RESIZE_CQ_PG_SIZE_PG_2M                       (0x3UL << 2)
1313         #define CMDQ_RESIZE_CQ_PG_SIZE_PG_8M                       (0x4UL << 2)
1314         #define CMDQ_RESIZE_CQ_PG_SIZE_PG_1G                       (0x5UL << 2)
1315         #define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_MASK             0x1fffe0UL
1316         #define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_SFT                      5
1317         __le64 new_pbl;
1318         __le32 new_cq_fco;
1319         __le32 unused_2;
1320 };
1321
1322 /* Allocate MRW command (32 bytes) */
1323 struct cmdq_allocate_mrw {
1324         u8 opcode;
1325         #define CMDQ_ALLOCATE_MRW_OPCODE_ALLOCATE_MRW              0xdUL
1326         u8 cmd_size;
1327         __le16 flags;
1328         __le16 cookie;
1329         u8 resp_size;
1330         u8 reserved8;
1331         __le64 resp_addr;
1332         __le64 mrw_handle;
1333         u8 mrw_flags;
1334         #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MASK                    0xfUL
1335         #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_SFT             0
1336         #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR                     0x0UL
1337         #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR            0x1UL
1338         #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1               0x2UL
1339         #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A              0x3UL
1340         #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B              0x4UL
1341         u8 access;
1342         #define CMDQ_ALLOCATE_MRW_ACCESS_RESERVED_MASK              0x1fUL
1343         #define CMDQ_ALLOCATE_MRW_ACCESS_RESERVED_SFT               0
1344         #define CMDQ_ALLOCATE_MRW_ACCESS_CONSUMER_OWNED_KEY         0x20UL
1345         __le16 unused_1;
1346         __le32 pd_id;
1347 };
1348
1349 /* De-allocate key command (24 bytes) */
1350 struct cmdq_deallocate_key {
1351         u8 opcode;
1352         #define CMDQ_DEALLOCATE_KEY_OPCODE_DEALLOCATE_KEY          0xeUL
1353         u8 cmd_size;
1354         __le16 flags;
1355         __le16 cookie;
1356         u8 resp_size;
1357         u8 reserved8;
1358         __le64 resp_addr;
1359         u8 mrw_flags;
1360         #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MASK                  0xfUL
1361         #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_SFT                   0
1362         #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MR                   0x0UL
1363         #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_PMR                  0x1UL
1364         #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE1             0x2UL
1365         #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2A    0x3UL
1366         #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2B    0x4UL
1367         u8 unused_1[3];
1368         __le32 key;
1369 };
1370
1371 /* Register MR command (48 bytes) */
1372 struct cmdq_register_mr {
1373         u8 opcode;
1374         #define CMDQ_REGISTER_MR_OPCODE_REGISTER_MR                0xfUL
1375         u8 cmd_size;
1376         __le16 flags;
1377         __le16 cookie;
1378         u8 resp_size;
1379         u8 reserved8;
1380         __le64 resp_addr;
1381         u8 log2_pg_size_lvl;
1382         #define CMDQ_REGISTER_MR_LVL_MASK                           0x3UL
1383         #define CMDQ_REGISTER_MR_LVL_SFT                            0
1384         #define CMDQ_REGISTER_MR_LVL_LVL_0                         0x0UL
1385         #define CMDQ_REGISTER_MR_LVL_LVL_1                         0x1UL
1386         #define CMDQ_REGISTER_MR_LVL_LVL_2                         0x2UL
1387         #define CMDQ_REGISTER_MR_LVL_LAST             CMDQ_REGISTER_MR_LVL_LVL_2
1388         #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_MASK                  0x7cUL
1389         #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_SFT                   2
1390         #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4K    (0xcUL << 2)
1391         #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_8K    (0xdUL << 2)
1392         #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_64K   (0x10UL << 2)
1393         #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_256K  (0x12UL << 2)
1394         #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1M    (0x14UL << 2)
1395         #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_2M    (0x15UL << 2)
1396         #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4M    (0x16UL << 2)
1397         #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1G    (0x1eUL << 2)
1398         #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_LAST      \
1399                                         CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1G
1400         #define CMDQ_REGISTER_MR_UNUSED1             0x80UL
1401         u8 access;
1402         #define CMDQ_REGISTER_MR_ACCESS_LOCAL_WRITE                 0x1UL
1403         #define CMDQ_REGISTER_MR_ACCESS_REMOTE_READ                 0x2UL
1404         #define CMDQ_REGISTER_MR_ACCESS_REMOTE_WRITE                0x4UL
1405         #define CMDQ_REGISTER_MR_ACCESS_REMOTE_ATOMIC               0x8UL
1406         #define CMDQ_REGISTER_MR_ACCESS_MW_BIND             0x10UL
1407         #define CMDQ_REGISTER_MR_ACCESS_ZERO_BASED                  0x20UL
1408         __le16  log2_pbl_pg_size;
1409         #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_MASK   0x1fUL
1410         #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_SFT    0
1411         #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4K    0xcUL
1412         #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_8K    0xdUL
1413         #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_64K   0x10UL
1414         #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_256K  0x12UL
1415         #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1M    0x14UL
1416         #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_2M    0x15UL
1417         #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4M    0x16UL
1418         #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G    0x1eUL
1419         #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_LAST    \
1420                                 CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G
1421         #define CMDQ_REGISTER_MR_UNUSED11_MASK           0xffe0UL
1422         #define CMDQ_REGISTER_MR_UNUSED11_SFT            5
1423         __le32 key;
1424         __le64 pbl;
1425         __le64 va;
1426         __le64 mr_size;
1427 };
1428
1429 /* Deregister MR command (24 bytes) */
1430 struct cmdq_deregister_mr {
1431         u8 opcode;
1432         #define CMDQ_DEREGISTER_MR_OPCODE_DEREGISTER_MR    0x10UL
1433         u8 cmd_size;
1434         __le16 flags;
1435         __le16 cookie;
1436         u8 resp_size;
1437         u8 reserved8;
1438         __le64 resp_addr;
1439         __le32 lkey;
1440         __le32 unused_0;
1441 };
1442
1443 /* Add GID command (48 bytes) */
1444 struct cmdq_add_gid {
1445         u8 opcode;
1446         #define CMDQ_ADD_GID_OPCODE_ADD_GID                        0x11UL
1447         u8 cmd_size;
1448         __le16 flags;
1449         __le16 cookie;
1450         u8 resp_size;
1451         u8 reserved8;
1452         __le64 resp_addr;
1453         __be32 gid[4];
1454         __be16 src_mac[3];
1455         __le16 vlan;
1456         #define CMDQ_ADD_GID_VLAN_VLAN_ID_MASK                      0xfffUL
1457         #define CMDQ_ADD_GID_VLAN_VLAN_ID_SFT                       0
1458         #define CMDQ_ADD_GID_VLAN_TPID_MASK                         0x7000UL
1459         #define CMDQ_ADD_GID_VLAN_TPID_SFT                          12
1460         #define CMDQ_ADD_GID_VLAN_TPID_TPID_88A8                   (0x0UL << 12)
1461         #define CMDQ_ADD_GID_VLAN_TPID_TPID_8100                   (0x1UL << 12)
1462         #define CMDQ_ADD_GID_VLAN_TPID_TPID_9100                   (0x2UL << 12)
1463         #define CMDQ_ADD_GID_VLAN_TPID_TPID_9200                   (0x3UL << 12)
1464         #define CMDQ_ADD_GID_VLAN_TPID_TPID_9300                   (0x4UL << 12)
1465         #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG1                   (0x5UL << 12)
1466         #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG2                   (0x6UL << 12)
1467         #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3                   (0x7UL << 12)
1468         #define CMDQ_ADD_GID_VLAN_TPID_LAST    CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3
1469         #define CMDQ_ADD_GID_VLAN_VLAN_EN                           0x8000UL
1470         __le16 ipid;
1471         __le16 stats_ctx;
1472         #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_MASK            0x7fffUL
1473         #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_SFT     0
1474         #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID              0x8000UL
1475         __le32 unused_0;
1476 };
1477
1478 /* Delete GID command (24 bytes) */
1479 struct cmdq_delete_gid {
1480         u8 opcode;
1481         #define CMDQ_DELETE_GID_OPCODE_DELETE_GID                  0x12UL
1482         u8 cmd_size;
1483         __le16 flags;
1484         __le16 cookie;
1485         u8 resp_size;
1486         u8 reserved8;
1487         __le64 resp_addr;
1488         __le16 gid_index;
1489         __le16 unused_0;
1490         __le32 unused_1;
1491 };
1492
1493 /* Modify GID command (48 bytes) */
1494 struct cmdq_modify_gid {
1495         u8 opcode;
1496         #define CMDQ_MODIFY_GID_OPCODE_MODIFY_GID                  0x17UL
1497         u8 cmd_size;
1498         __le16 flags;
1499         __le16 cookie;
1500         u8 resp_size;
1501         u8 reserved8;
1502         __le64 resp_addr;
1503         __be32 gid[4];
1504         __be16 src_mac[3];
1505         __le16 vlan;
1506         #define CMDQ_MODIFY_GID_VLAN_VLAN_ID_MASK                   0xfffUL
1507         #define CMDQ_MODIFY_GID_VLAN_VLAN_ID_SFT                    0
1508         #define CMDQ_MODIFY_GID_VLAN_TPID_MASK                      0x7000UL
1509         #define CMDQ_MODIFY_GID_VLAN_TPID_SFT                       12
1510         #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_88A8                (0x0UL << 12)
1511         #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_8100                (0x1UL << 12)
1512         #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9100                (0x2UL << 12)
1513         #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9200                (0x3UL << 12)
1514         #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9300                (0x4UL << 12)
1515         #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG1                (0x5UL << 12)
1516         #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG2                (0x6UL << 12)
1517         #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3                (0x7UL << 12)
1518         #define CMDQ_MODIFY_GID_VLAN_TPID_LAST          \
1519                                         CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3
1520         #define CMDQ_MODIFY_GID_VLAN_VLAN_EN                        0x8000UL
1521         __le16 ipid;
1522         __le16 gid_index;
1523         __le16 stats_ctx;
1524         #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_MASK         0x7fffUL
1525         #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_SFT          0
1526         #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_VALID           0x8000UL
1527         __le16 unused_0;
1528 };
1529
1530 /* Query GID command (24 bytes) */
1531 struct cmdq_query_gid {
1532         u8 opcode;
1533         #define CMDQ_QUERY_GID_OPCODE_QUERY_GID            0x18UL
1534         u8 cmd_size;
1535         __le16 flags;
1536         __le16 cookie;
1537         u8 resp_size;
1538         u8 reserved8;
1539         __le64 resp_addr;
1540         __le16 gid_index;
1541         __le16 unused_0;
1542         __le32 unused_1;
1543 };
1544
1545 /* Create QP1 command (80 bytes) */
1546 struct cmdq_create_qp1 {
1547         u8 opcode;
1548         #define CMDQ_CREATE_QP1_OPCODE_CREATE_QP1                  0x13UL
1549         u8 cmd_size;
1550         __le16 flags;
1551         __le16 cookie;
1552         u8 resp_size;
1553         u8 reserved8;
1554         __le64 resp_addr;
1555         __le64 qp_handle;
1556         __le32 qp_flags;
1557         #define CMDQ_CREATE_QP1_QP_FLAGS_SRQ_USED                  0x1UL
1558         #define CMDQ_CREATE_QP1_QP_FLAGS_FORCE_COMPLETION          0x2UL
1559         #define CMDQ_CREATE_QP1_QP_FLAGS_RESERVED_LKEY_ENABLE     0x4UL
1560         u8 type;
1561         #define CMDQ_CREATE_QP1_TYPE_GSI                           0x1UL
1562         u8 sq_pg_size_sq_lvl;
1563         #define CMDQ_CREATE_QP1_SQ_LVL_MASK                         0xfUL
1564         #define CMDQ_CREATE_QP1_SQ_LVL_SFT                          0
1565         #define CMDQ_CREATE_QP1_SQ_LVL_LVL_0                       0x0UL
1566         #define CMDQ_CREATE_QP1_SQ_LVL_LVL_1                       0x1UL
1567         #define CMDQ_CREATE_QP1_SQ_LVL_LVL_2                       0x2UL
1568         #define CMDQ_CREATE_QP1_SQ_PG_SIZE_MASK             0xf0UL
1569         #define CMDQ_CREATE_QP1_SQ_PG_SIZE_SFT                      4
1570         #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_4K                   (0x0UL << 4)
1571         #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8K                   (0x1UL << 4)
1572         #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_64K                  (0x2UL << 4)
1573         #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_2M                   (0x3UL << 4)
1574         #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8M                   (0x4UL << 4)
1575         #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_1G                   (0x5UL << 4)
1576         u8 rq_pg_size_rq_lvl;
1577         #define CMDQ_CREATE_QP1_RQ_LVL_MASK                         0xfUL
1578         #define CMDQ_CREATE_QP1_RQ_LVL_SFT                          0
1579         #define CMDQ_CREATE_QP1_RQ_LVL_LVL_0                       0x0UL
1580         #define CMDQ_CREATE_QP1_RQ_LVL_LVL_1                       0x1UL
1581         #define CMDQ_CREATE_QP1_RQ_LVL_LVL_2                       0x2UL
1582         #define CMDQ_CREATE_QP1_RQ_PG_SIZE_MASK             0xf0UL
1583         #define CMDQ_CREATE_QP1_RQ_PG_SIZE_SFT                      4
1584         #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_4K                   (0x0UL << 4)
1585         #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8K                   (0x1UL << 4)
1586         #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_64K                  (0x2UL << 4)
1587         #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_2M                   (0x3UL << 4)
1588         #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8M                   (0x4UL << 4)
1589         #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_1G                   (0x5UL << 4)
1590         u8 unused_0;
1591         __le32 dpi;
1592         __le32 sq_size;
1593         __le32 rq_size;
1594         __le16 sq_fwo_sq_sge;
1595         #define CMDQ_CREATE_QP1_SQ_SGE_MASK                         0xfUL
1596         #define CMDQ_CREATE_QP1_SQ_SGE_SFT                          0
1597         #define CMDQ_CREATE_QP1_SQ_FWO_MASK                         0xfff0UL
1598         #define CMDQ_CREATE_QP1_SQ_FWO_SFT                          4
1599         __le16 rq_fwo_rq_sge;
1600         #define CMDQ_CREATE_QP1_RQ_SGE_MASK                         0xfUL
1601         #define CMDQ_CREATE_QP1_RQ_SGE_SFT                          0
1602         #define CMDQ_CREATE_QP1_RQ_FWO_MASK                         0xfff0UL
1603         #define CMDQ_CREATE_QP1_RQ_FWO_SFT                          4
1604         __le32 scq_cid;
1605         __le32 rcq_cid;
1606         __le32 srq_cid;
1607         __le32 pd_id;
1608         __le64 sq_pbl;
1609         __le64 rq_pbl;
1610 };
1611
1612 /* Destroy QP1 command (24 bytes) */
1613 struct cmdq_destroy_qp1 {
1614         u8 opcode;
1615         #define CMDQ_DESTROY_QP1_OPCODE_DESTROY_QP1                0x14UL
1616         u8 cmd_size;
1617         __le16 flags;
1618         __le16 cookie;
1619         u8 resp_size;
1620         u8 reserved8;
1621         __le64 resp_addr;
1622         __le32 qp1_cid;
1623         __le32 unused_0;
1624 };
1625
1626 /* Create AH command (64 bytes) */
1627 struct cmdq_create_ah {
1628         u8 opcode;
1629         #define CMDQ_CREATE_AH_OPCODE_CREATE_AH            0x15UL
1630         u8 cmd_size;
1631         __le16 flags;
1632         __le16 cookie;
1633         u8 resp_size;
1634         u8 reserved8;
1635         __le64 resp_addr;
1636         __le64 ah_handle;
1637         __le32 dgid[4];
1638         u8 type;
1639         #define CMDQ_CREATE_AH_TYPE_V1                             0x0UL
1640         #define CMDQ_CREATE_AH_TYPE_V2IPV4                         0x2UL
1641         #define CMDQ_CREATE_AH_TYPE_V2IPV6                         0x3UL
1642         u8 hop_limit;
1643         __le16 sgid_index;
1644         __le32 dest_vlan_id_flow_label;
1645         #define CMDQ_CREATE_AH_FLOW_LABEL_MASK                      0xfffffUL
1646         #define CMDQ_CREATE_AH_FLOW_LABEL_SFT                       0
1647         #define CMDQ_CREATE_AH_DEST_VLAN_ID_MASK                    0xfff00000UL
1648         #define CMDQ_CREATE_AH_DEST_VLAN_ID_SFT             20
1649         __le32 pd_id;
1650         __le32 unused_0;
1651         __le16 dest_mac[3];
1652         u8 traffic_class;
1653         u8 unused_1;
1654 };
1655
1656 /* Destroy AH command (24 bytes) */
1657 struct cmdq_destroy_ah {
1658         u8 opcode;
1659         #define CMDQ_DESTROY_AH_OPCODE_DESTROY_AH                  0x16UL
1660         u8 cmd_size;
1661         __le16 flags;
1662         __le16 cookie;
1663         u8 resp_size;
1664         u8 reserved8;
1665         __le64 resp_addr;
1666         __le32 ah_cid;
1667         __le32 unused_0;
1668 };
1669
1670 /* Initialize Firmware command (112 bytes) */
1671 struct cmdq_initialize_fw {
1672         u8 opcode;
1673         #define CMDQ_INITIALIZE_FW_OPCODE_INITIALIZE_FW    0x80UL
1674         u8 cmd_size;
1675         __le16 flags;
1676         __le16 cookie;
1677         u8 resp_size;
1678         u8 reserved8;
1679         __le64 resp_addr;
1680         u8 qpc_pg_size_qpc_lvl;
1681         #define CMDQ_INITIALIZE_FW_QPC_LVL_MASK             0xfUL
1682         #define CMDQ_INITIALIZE_FW_QPC_LVL_SFT                      0
1683         #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_0                   0x0UL
1684         #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_1                   0x1UL
1685         #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_2                   0x2UL
1686         #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_MASK                 0xf0UL
1687         #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT                  4
1688         #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_4K               (0x0UL << 4)
1689         #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8K               (0x1UL << 4)
1690         #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_64K              (0x2UL << 4)
1691         #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_2M               (0x3UL << 4)
1692         #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8M               (0x4UL << 4)
1693         #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_1G               (0x5UL << 4)
1694         u8 mrw_pg_size_mrw_lvl;
1695         #define CMDQ_INITIALIZE_FW_MRW_LVL_MASK             0xfUL
1696         #define CMDQ_INITIALIZE_FW_MRW_LVL_SFT                      0
1697         #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_0                   0x0UL
1698         #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_1                   0x1UL
1699         #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_2                   0x2UL
1700         #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_MASK                 0xf0UL
1701         #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_SFT                  4
1702         #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_4K               (0x0UL << 4)
1703         #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8K               (0x1UL << 4)
1704         #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_64K              (0x2UL << 4)
1705         #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_2M               (0x3UL << 4)
1706         #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8M               (0x4UL << 4)
1707         #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_1G               (0x5UL << 4)
1708         u8 srq_pg_size_srq_lvl;
1709         #define CMDQ_INITIALIZE_FW_SRQ_LVL_MASK             0xfUL
1710         #define CMDQ_INITIALIZE_FW_SRQ_LVL_SFT                      0
1711         #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_0                   0x0UL
1712         #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_1                   0x1UL
1713         #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_2                   0x2UL
1714         #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_MASK                 0xf0UL
1715         #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_SFT                  4
1716         #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_4K               (0x0UL << 4)
1717         #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8K               (0x1UL << 4)
1718         #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_64K              (0x2UL << 4)
1719         #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_2M               (0x3UL << 4)
1720         #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8M               (0x4UL << 4)
1721         #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_1G               (0x5UL << 4)
1722         u8 cq_pg_size_cq_lvl;
1723         #define CMDQ_INITIALIZE_FW_CQ_LVL_MASK                      0xfUL
1724         #define CMDQ_INITIALIZE_FW_CQ_LVL_SFT                       0
1725         #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_0            0x0UL
1726         #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_1            0x1UL
1727         #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_2            0x2UL
1728         #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_MASK                  0xf0UL
1729         #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_SFT                   4
1730         #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_4K                (0x0UL << 4)
1731         #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8K                (0x1UL << 4)
1732         #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_64K               (0x2UL << 4)
1733         #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_2M                (0x3UL << 4)
1734         #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8M                (0x4UL << 4)
1735         #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_1G                (0x5UL << 4)
1736         u8 tqm_pg_size_tqm_lvl;
1737         #define CMDQ_INITIALIZE_FW_TQM_LVL_MASK             0xfUL
1738         #define CMDQ_INITIALIZE_FW_TQM_LVL_SFT                      0
1739         #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_0                   0x0UL
1740         #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_1                   0x1UL
1741         #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_2                   0x2UL
1742         #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_MASK                 0xf0UL
1743         #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_SFT                  4
1744         #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_4K               (0x0UL << 4)
1745         #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8K               (0x1UL << 4)
1746         #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_64K              (0x2UL << 4)
1747         #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_2M               (0x3UL << 4)
1748         #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8M               (0x4UL << 4)
1749         #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_1G               (0x5UL << 4)
1750         u8 tim_pg_size_tim_lvl;
1751         #define CMDQ_INITIALIZE_FW_TIM_LVL_MASK             0xfUL
1752         #define CMDQ_INITIALIZE_FW_TIM_LVL_SFT                      0
1753         #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_0                   0x0UL
1754         #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_1                   0x1UL
1755         #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_2                   0x2UL
1756         #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_MASK                 0xf0UL
1757         #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_SFT                  4
1758         #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_4K               (0x0UL << 4)
1759         #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8K               (0x1UL << 4)
1760         #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_64K              (0x2UL << 4)
1761         #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_2M               (0x3UL << 4)
1762         #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8M               (0x4UL << 4)
1763         #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_1G               (0x5UL << 4)
1764         /* This value is (log-base-2-of-DBR-page-size - 12).
1765          * 0 for 4KB. HW supported values are enumerated below.
1766          */
1767         __le16  log2_dbr_pg_size;
1768         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_MASK        0xfUL
1769         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_SFT         0
1770         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4K       0x0UL
1771         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8K       0x1UL
1772         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16K      0x2UL
1773         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32K      0x3UL
1774         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64K      0x4UL
1775         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128K     0x5UL
1776         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_256K     0x6UL
1777         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_512K     0x7UL
1778         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_1M       0x8UL
1779         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_2M       0x9UL
1780         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4M       0xaUL
1781         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8M       0xbUL
1782         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16M      0xcUL
1783         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32M      0xdUL
1784         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64M      0xeUL
1785         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128M     0xfUL
1786         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_LAST                \
1787                         CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128M
1788         __le64 qpc_page_dir;
1789         __le64 mrw_page_dir;
1790         __le64 srq_page_dir;
1791         __le64 cq_page_dir;
1792         __le64 tqm_page_dir;
1793         __le64 tim_page_dir;
1794         __le32 number_of_qp;
1795         __le32 number_of_mrw;
1796         __le32 number_of_srq;
1797         __le32 number_of_cq;
1798         __le32 max_qp_per_vf;
1799         __le32 max_mrw_per_vf;
1800         __le32 max_srq_per_vf;
1801         __le32 max_cq_per_vf;
1802         __le32 max_gid_per_vf;
1803         __le32 stat_ctx_id;
1804 };
1805
1806 /* De-initialize Firmware command (16 bytes) */
1807 struct cmdq_deinitialize_fw {
1808         u8 opcode;
1809         #define CMDQ_DEINITIALIZE_FW_OPCODE_DEINITIALIZE_FW       0x81UL
1810         u8 cmd_size;
1811         __le16 flags;
1812         __le16 cookie;
1813         u8 resp_size;
1814         u8 reserved8;
1815         __le64 resp_addr;
1816 };
1817
1818 /* Stop function command (16 bytes) */
1819 struct cmdq_stop_func {
1820         u8 opcode;
1821         #define CMDQ_STOP_FUNC_OPCODE_STOP_FUNC            0x82UL
1822         u8 cmd_size;
1823         __le16 flags;
1824         __le16 cookie;
1825         u8 resp_size;
1826         u8 reserved8;
1827         __le64 resp_addr;
1828 };
1829
1830 /* Query function command (16 bytes) */
1831 struct cmdq_query_func {
1832         u8 opcode;
1833         #define CMDQ_QUERY_FUNC_OPCODE_QUERY_FUNC                  0x83UL
1834         u8 cmd_size;
1835         __le16 flags;
1836         __le16 cookie;
1837         u8 resp_size;
1838         u8 reserved8;
1839         __le64 resp_addr;
1840 };
1841
1842 /* Set function resources command (16 bytes) */
1843 struct cmdq_set_func_resources {
1844         u8 opcode;
1845         #define CMDQ_SET_FUNC_RESOURCES_OPCODE_SET_FUNC_RESOURCES 0x84UL
1846         u8 cmd_size;
1847         __le16 flags;
1848         __le16 cookie;
1849         u8 resp_size;
1850         u8 reserved8;
1851         __le64 resp_addr;
1852         __le32 number_of_qp;
1853         __le32 number_of_mrw;
1854         __le32 number_of_srq;
1855         __le32 number_of_cq;
1856         __le32 max_qp_per_vf;
1857         __le32 max_mrw_per_vf;
1858         __le32 max_srq_per_vf;
1859         __le32 max_cq_per_vf;
1860         __le32 max_gid_per_vf;
1861         __le32 stat_ctx_id;
1862 };
1863
1864 /* Read hardware resource context command (24 bytes) */
1865 struct cmdq_read_context {
1866         u8 opcode;
1867         #define CMDQ_READ_CONTEXT_OPCODE_READ_CONTEXT              0x85UL
1868         u8 cmd_size;
1869         __le16 flags;
1870         __le16 cookie;
1871         u8 resp_size;
1872         u8 reserved8;
1873         __le64 resp_addr;
1874         __le32 type_xid;
1875         #define CMDQ_READ_CONTEXT_XID_MASK                          0xffffffUL
1876         #define CMDQ_READ_CONTEXT_XID_SFT                           0
1877         #define CMDQ_READ_CONTEXT_TYPE_MASK                         0xff000000UL
1878         #define CMDQ_READ_CONTEXT_TYPE_SFT                          24
1879         #define CMDQ_READ_CONTEXT_TYPE_QPC                         (0x0UL << 24)
1880         #define CMDQ_READ_CONTEXT_TYPE_CQ                          (0x1UL << 24)
1881         #define CMDQ_READ_CONTEXT_TYPE_MRW                         (0x2UL << 24)
1882         #define CMDQ_READ_CONTEXT_TYPE_SRQ                         (0x3UL << 24)
1883         __le32 unused_0;
1884 };
1885
1886 /* Map TC to COS. Can only be issued from a PF (24 bytes) */
1887 struct cmdq_map_tc_to_cos {
1888         u8 opcode;
1889         #define CMDQ_MAP_TC_TO_COS_OPCODE_MAP_TC_TO_COS    0x8aUL
1890         u8 cmd_size;
1891         __le16 flags;
1892         __le16 cookie;
1893         u8 resp_size;
1894         u8 reserved8;
1895         __le64 resp_addr;
1896         __le16 cos0;
1897         #define CMDQ_MAP_TC_TO_COS_COS0_NO_CHANGE                  0xffffUL
1898         __le16 cos1;
1899         #define CMDQ_MAP_TC_TO_COS_COS1_DISABLE            0x8000UL
1900         #define CMDQ_MAP_TC_TO_COS_COS1_NO_CHANGE                  0xffffUL
1901         __le32 unused_0;
1902 };
1903
1904 /* Query version command (16 bytes) */
1905 struct cmdq_query_version {
1906         u8 opcode;
1907         #define CMDQ_QUERY_VERSION_OPCODE_QUERY_VERSION    0x8bUL
1908         u8 cmd_size;
1909         __le16 flags;
1910         __le16 cookie;
1911         u8 resp_size;
1912         u8 reserved8;
1913         __le64 resp_addr;
1914 };
1915
1916 /* Command-Response Event Queue (CREQ) Structures */
1917 /* Base CREQ Record (16 bytes) */
1918 struct creq_base {
1919         u8 type;
1920         #define CREQ_BASE_TYPE_MASK                                 0x3fUL
1921         #define CREQ_BASE_TYPE_SFT                                  0
1922         #define CREQ_BASE_TYPE_QP_EVENT                    0x38UL
1923         #define CREQ_BASE_TYPE_FUNC_EVENT                          0x3aUL
1924         #define CREQ_BASE_RESERVED2_MASK                            0xc0UL
1925         #define CREQ_BASE_RESERVED2_SFT                     6
1926         u8 reserved56[7];
1927         u8 v;
1928         #define CREQ_BASE_V                                         0x1UL
1929         #define CREQ_BASE_RESERVED7_MASK                            0xfeUL
1930         #define CREQ_BASE_RESERVED7_SFT                     1
1931         u8 event;
1932         __le16 reserved48[3];
1933 };
1934
1935 /* RoCE Function Async Event Notification (16 bytes) */
1936 struct creq_func_event {
1937         u8 type;
1938         #define CREQ_FUNC_EVENT_TYPE_MASK                           0x3fUL
1939         #define CREQ_FUNC_EVENT_TYPE_SFT                            0
1940         #define CREQ_FUNC_EVENT_TYPE_FUNC_EVENT            0x3aUL
1941         #define CREQ_FUNC_EVENT_RESERVED2_MASK                      0xc0UL
1942         #define CREQ_FUNC_EVENT_RESERVED2_SFT                       6
1943         u8 reserved56[7];
1944         u8 v;
1945         #define CREQ_FUNC_EVENT_V                                   0x1UL
1946         #define CREQ_FUNC_EVENT_RESERVED7_MASK                      0xfeUL
1947         #define CREQ_FUNC_EVENT_RESERVED7_SFT                       1
1948         u8 event;
1949         #define CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR                 0x1UL
1950         #define CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR                0x2UL
1951         #define CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR                 0x3UL
1952         #define CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR                0x4UL
1953         #define CREQ_FUNC_EVENT_EVENT_CQ_ERROR                     0x5UL
1954         #define CREQ_FUNC_EVENT_EVENT_TQM_ERROR            0x6UL
1955         #define CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR                   0x7UL
1956         #define CREQ_FUNC_EVENT_EVENT_CFCS_ERROR                   0x8UL
1957         #define CREQ_FUNC_EVENT_EVENT_CFCC_ERROR                   0x9UL
1958         #define CREQ_FUNC_EVENT_EVENT_CFCM_ERROR                   0xaUL
1959         #define CREQ_FUNC_EVENT_EVENT_TIM_ERROR            0xbUL
1960         #define CREQ_FUNC_EVENT_EVENT_VF_COMM_REQUEST              0x80UL
1961         #define CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED           0x81UL
1962         __le16 reserved48[3];
1963 };
1964
1965 /* RoCE Slowpath Command Completion (16 bytes) */
1966 struct creq_qp_event {
1967         u8 type;
1968         #define CREQ_QP_EVENT_TYPE_MASK                     0x3fUL
1969         #define CREQ_QP_EVENT_TYPE_SFT                              0
1970         #define CREQ_QP_EVENT_TYPE_QP_EVENT                        0x38UL
1971         #define CREQ_QP_EVENT_RESERVED2_MASK                        0xc0UL
1972         #define CREQ_QP_EVENT_RESERVED2_SFT                         6
1973         u8 status;
1974         __le16 cookie;
1975         __le32 reserved32;
1976         u8 v;
1977         #define CREQ_QP_EVENT_V                             0x1UL
1978         #define CREQ_QP_EVENT_RESERVED7_MASK                        0xfeUL
1979         #define CREQ_QP_EVENT_RESERVED7_SFT                         1
1980         u8 event;
1981         #define CREQ_QP_EVENT_EVENT_CREATE_QP                      0x1UL
1982         #define CREQ_QP_EVENT_EVENT_DESTROY_QP                     0x2UL
1983         #define CREQ_QP_EVENT_EVENT_MODIFY_QP                      0x3UL
1984         #define CREQ_QP_EVENT_EVENT_QUERY_QP                       0x4UL
1985         #define CREQ_QP_EVENT_EVENT_CREATE_SRQ                     0x5UL
1986         #define CREQ_QP_EVENT_EVENT_DESTROY_SRQ            0x6UL
1987         #define CREQ_QP_EVENT_EVENT_QUERY_SRQ                      0x8UL
1988         #define CREQ_QP_EVENT_EVENT_CREATE_CQ                      0x9UL
1989         #define CREQ_QP_EVENT_EVENT_DESTROY_CQ                     0xaUL
1990         #define CREQ_QP_EVENT_EVENT_RESIZE_CQ                      0xcUL
1991         #define CREQ_QP_EVENT_EVENT_ALLOCATE_MRW                   0xdUL
1992         #define CREQ_QP_EVENT_EVENT_DEALLOCATE_KEY                 0xeUL
1993         #define CREQ_QP_EVENT_EVENT_REGISTER_MR            0xfUL
1994         #define CREQ_QP_EVENT_EVENT_DEREGISTER_MR                  0x10UL
1995         #define CREQ_QP_EVENT_EVENT_ADD_GID                        0x11UL
1996         #define CREQ_QP_EVENT_EVENT_DELETE_GID                     0x12UL
1997         #define CREQ_QP_EVENT_EVENT_MODIFY_GID                     0x17UL
1998         #define CREQ_QP_EVENT_EVENT_QUERY_GID                      0x18UL
1999         #define CREQ_QP_EVENT_EVENT_CREATE_QP1                     0x13UL
2000         #define CREQ_QP_EVENT_EVENT_DESTROY_QP1            0x14UL
2001         #define CREQ_QP_EVENT_EVENT_CREATE_AH                      0x15UL
2002         #define CREQ_QP_EVENT_EVENT_DESTROY_AH                     0x16UL
2003         #define CREQ_QP_EVENT_EVENT_INITIALIZE_FW                  0x80UL
2004         #define CREQ_QP_EVENT_EVENT_DEINITIALIZE_FW                0x81UL
2005         #define CREQ_QP_EVENT_EVENT_STOP_FUNC                      0x82UL
2006         #define CREQ_QP_EVENT_EVENT_QUERY_FUNC                     0x83UL
2007         #define CREQ_QP_EVENT_EVENT_SET_FUNC_RESOURCES             0x84UL
2008         #define CREQ_QP_EVENT_EVENT_MAP_TC_TO_COS                  0x8aUL
2009         #define CREQ_QP_EVENT_EVENT_QUERY_VERSION                  0x8bUL
2010         #define CREQ_QP_EVENT_EVENT_MODIFY_CC                      0x8cUL
2011         #define CREQ_QP_EVENT_EVENT_QUERY_CC                       0x8dUL
2012         #define CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION          0xc0UL
2013         __le16 reserved48[3];
2014 };
2015
2016 /* Create QP command response (16 bytes) */
2017 struct creq_create_qp_resp {
2018         u8 type;
2019         #define CREQ_CREATE_QP_RESP_TYPE_MASK                       0x3fUL
2020         #define CREQ_CREATE_QP_RESP_TYPE_SFT                        0
2021         #define CREQ_CREATE_QP_RESP_TYPE_QP_EVENT                  0x38UL
2022         #define CREQ_CREATE_QP_RESP_RESERVED2_MASK                  0xc0UL
2023         #define CREQ_CREATE_QP_RESP_RESERVED2_SFT                   6
2024         u8 status;
2025         __le16 cookie;
2026         __le32 xid;
2027         u8 v;
2028         #define CREQ_CREATE_QP_RESP_V                               0x1UL
2029         #define CREQ_CREATE_QP_RESP_RESERVED7_MASK                  0xfeUL
2030         #define CREQ_CREATE_QP_RESP_RESERVED7_SFT                   1
2031         u8 event;
2032         #define CREQ_CREATE_QP_RESP_EVENT_CREATE_QP                0x1UL
2033         __le16 reserved48[3];
2034 };
2035
2036 /* Destroy QP command response (16 bytes) */
2037 struct creq_destroy_qp_resp {
2038         u8 type;
2039         #define CREQ_DESTROY_QP_RESP_TYPE_MASK                      0x3fUL
2040         #define CREQ_DESTROY_QP_RESP_TYPE_SFT                       0
2041         #define CREQ_DESTROY_QP_RESP_TYPE_QP_EVENT                 0x38UL
2042         #define CREQ_DESTROY_QP_RESP_RESERVED2_MASK                 0xc0UL
2043         #define CREQ_DESTROY_QP_RESP_RESERVED2_SFT                  6
2044         u8 status;
2045         __le16 cookie;
2046         __le32 xid;
2047         u8 v;
2048         #define CREQ_DESTROY_QP_RESP_V                              0x1UL
2049         #define CREQ_DESTROY_QP_RESP_RESERVED7_MASK                 0xfeUL
2050         #define CREQ_DESTROY_QP_RESP_RESERVED7_SFT                  1
2051         u8 event;
2052         #define CREQ_DESTROY_QP_RESP_EVENT_DESTROY_QP              0x2UL
2053         __le16 reserved48[3];
2054 };
2055
2056 /* Modify QP command response (16 bytes) */
2057 struct creq_modify_qp_resp {
2058         u8 type;
2059         #define CREQ_MODIFY_QP_RESP_TYPE_MASK                       0x3fUL
2060         #define CREQ_MODIFY_QP_RESP_TYPE_SFT                        0
2061         #define CREQ_MODIFY_QP_RESP_TYPE_QP_EVENT                  0x38UL
2062         #define CREQ_MODIFY_QP_RESP_RESERVED2_MASK                  0xc0UL
2063         #define CREQ_MODIFY_QP_RESP_RESERVED2_SFT                   6
2064         u8 status;
2065         __le16 cookie;
2066         __le32 xid;
2067         u8 v;
2068         #define CREQ_MODIFY_QP_RESP_V                               0x1UL
2069         #define CREQ_MODIFY_QP_RESP_RESERVED7_MASK                  0xfeUL
2070         #define CREQ_MODIFY_QP_RESP_RESERVED7_SFT                   1
2071         u8 event;
2072         #define CREQ_MODIFY_QP_RESP_EVENT_MODIFY_QP                0x3UL
2073         __le16 reserved48[3];
2074 };
2075
2076 /* cmdq_query_roce_stats (size:128b/16B) */
2077 struct cmdq_query_roce_stats {
2078         u8      opcode;
2079         #define CMDQ_QUERY_ROCE_STATS_OPCODE_QUERY_ROCE_STATS 0x8eUL
2080         #define CMDQ_QUERY_ROCE_STATS_OPCODE_LAST       \
2081                                 CMDQ_QUERY_ROCE_STATS_OPCODE_QUERY_ROCE_STATS
2082         u8      cmd_size;
2083         __le16  flags;
2084         __le16  cookie;
2085         u8      resp_size;
2086         u8      reserved8;
2087         __le64  resp_addr;
2088 };
2089
2090 /* Query QP command response (16 bytes) */
2091 struct creq_query_qp_resp {
2092         u8 type;
2093         #define CREQ_QUERY_QP_RESP_TYPE_MASK                        0x3fUL
2094         #define CREQ_QUERY_QP_RESP_TYPE_SFT                         0
2095         #define CREQ_QUERY_QP_RESP_TYPE_QP_EVENT                   0x38UL
2096         #define CREQ_QUERY_QP_RESP_RESERVED2_MASK                   0xc0UL
2097         #define CREQ_QUERY_QP_RESP_RESERVED2_SFT                    6
2098         u8 status;
2099         __le16 cookie;
2100         __le32 size;
2101         u8 v;
2102         #define CREQ_QUERY_QP_RESP_V                                0x1UL
2103         #define CREQ_QUERY_QP_RESP_RESERVED7_MASK                   0xfeUL
2104         #define CREQ_QUERY_QP_RESP_RESERVED7_SFT                    1
2105         u8 event;
2106         #define CREQ_QUERY_QP_RESP_EVENT_QUERY_QP                  0x4UL
2107         __le16 reserved48[3];
2108 };
2109
2110 /* Query QP command response side buffer structure (104 bytes) */
2111 struct creq_query_qp_resp_sb {
2112         u8 opcode;
2113         #define CREQ_QUERY_QP_RESP_SB_OPCODE_QUERY_QP              0x4UL
2114         u8 status;
2115         __le16 cookie;
2116         __le16 flags;
2117         u8 resp_size;
2118         u8 reserved8;
2119         __le32 xid;
2120         u8 en_sqd_async_notify_state;
2121         #define CREQ_QUERY_QP_RESP_SB_STATE_MASK                    0xfUL
2122         #define CREQ_QUERY_QP_RESP_SB_STATE_SFT             0
2123         #define CREQ_QUERY_QP_RESP_SB_STATE_RESET                  0x0UL
2124         #define CREQ_QUERY_QP_RESP_SB_STATE_INIT                   0x1UL
2125         #define CREQ_QUERY_QP_RESP_SB_STATE_RTR            0x2UL
2126         #define CREQ_QUERY_QP_RESP_SB_STATE_RTS            0x3UL
2127         #define CREQ_QUERY_QP_RESP_SB_STATE_SQD            0x4UL
2128         #define CREQ_QUERY_QP_RESP_SB_STATE_SQE            0x5UL
2129         #define CREQ_QUERY_QP_RESP_SB_STATE_ERR            0x6UL
2130         #define CREQ_QUERY_QP_RESP_SB_EN_SQD_ASYNC_NOTIFY           0x10UL
2131         u8 access;
2132         #define CREQ_QUERY_QP_RESP_SB_ACCESS_LOCAL_WRITE            0x1UL
2133         #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_WRITE           0x2UL
2134         #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_READ            0x4UL
2135         #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC          0x8UL
2136         __le16 pkey;
2137         __le32 qkey;
2138         __le32 reserved32;
2139         __le32 dgid[4];
2140         __le32 flow_label;
2141         __le16 sgid_index;
2142         u8 hop_limit;
2143         u8 traffic_class;
2144         __le16 dest_mac[3];
2145         __le16 path_mtu_dest_vlan_id;
2146         #define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_MASK     0xfffUL
2147         #define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_SFT              0
2148         #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK                 0xf000UL
2149         #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_SFT                  12
2150         #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_256             (0x0UL << 12)
2151         #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_512             (0x1UL << 12)
2152         #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_1024    (0x2UL << 12)
2153         #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_2048    (0x3UL << 12)
2154         #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_4096    (0x4UL << 12)
2155         #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_8192    (0x5UL << 12)
2156         u8 timeout;
2157         u8 retry_cnt;
2158         u8 rnr_retry;
2159         u8 min_rnr_timer;
2160         __le32 rq_psn;
2161         __le32 sq_psn;
2162         u8 max_rd_atomic;
2163         u8 max_dest_rd_atomic;
2164         u8 tos_dscp_tos_ecn;
2165         #define CREQ_QUERY_QP_RESP_SB_TOS_ECN_MASK                  0x3UL
2166         #define CREQ_QUERY_QP_RESP_SB_TOS_ECN_SFT                   0
2167         #define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_MASK                 0xfcUL
2168         #define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_SFT                  2
2169         u8 enable_cc;
2170         #define CREQ_QUERY_QP_RESP_SB_ENABLE_CC             0x1UL
2171         #define CREQ_QUERY_QP_RESP_SB_RESERVED7_MASK                0xfeUL
2172         #define CREQ_QUERY_QP_RESP_SB_RESERVED7_SFT                 1
2173         __le32 sq_size;
2174         __le32 rq_size;
2175         __le16 sq_sge;
2176         __le16 rq_sge;
2177         __le32 max_inline_data;
2178         __le32 dest_qp_id;
2179         __le32 unused_1;
2180         __le16 src_mac[3];
2181         __le16 vlan_pcp_vlan_dei_vlan_id;
2182         #define CREQ_QUERY_QP_RESP_SB_VLAN_ID_MASK                  0xfffUL
2183         #define CREQ_QUERY_QP_RESP_SB_VLAN_ID_SFT                   0
2184         #define CREQ_QUERY_QP_RESP_SB_VLAN_DEI                      0x1000UL
2185         #define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_MASK                 0xe000UL
2186         #define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_SFT                  13
2187 };
2188
2189 /* Create SRQ command response (16 bytes) */
2190 struct creq_create_srq_resp {
2191         u8 type;
2192         #define CREQ_CREATE_SRQ_RESP_TYPE_MASK                      0x3fUL
2193         #define CREQ_CREATE_SRQ_RESP_TYPE_SFT                       0
2194         #define CREQ_CREATE_SRQ_RESP_TYPE_QP_EVENT                 0x38UL
2195         #define CREQ_CREATE_SRQ_RESP_RESERVED2_MASK                 0xc0UL
2196         #define CREQ_CREATE_SRQ_RESP_RESERVED2_SFT                  6
2197         u8 status;
2198         __le16 cookie;
2199         __le32 xid;
2200         u8 v;
2201         #define CREQ_CREATE_SRQ_RESP_V                              0x1UL
2202         #define CREQ_CREATE_SRQ_RESP_RESERVED7_MASK                 0xfeUL
2203         #define CREQ_CREATE_SRQ_RESP_RESERVED7_SFT                  1
2204         u8 event;
2205         #define CREQ_CREATE_SRQ_RESP_EVENT_CREATE_SRQ              0x5UL
2206         __le16 reserved48[3];
2207 };
2208
2209 /* Destroy SRQ command response (16 bytes) */
2210 struct creq_destroy_srq_resp {
2211         u8 type;
2212         #define CREQ_DESTROY_SRQ_RESP_TYPE_MASK             0x3fUL
2213         #define CREQ_DESTROY_SRQ_RESP_TYPE_SFT                      0
2214         #define CREQ_DESTROY_SRQ_RESP_TYPE_QP_EVENT                0x38UL
2215         #define CREQ_DESTROY_SRQ_RESP_RESERVED2_MASK                0xc0UL
2216         #define CREQ_DESTROY_SRQ_RESP_RESERVED2_SFT                 6
2217         u8 status;
2218         __le16 cookie;
2219         __le32 xid;
2220         u8 v;
2221         #define CREQ_DESTROY_SRQ_RESP_V                     0x1UL
2222         #define CREQ_DESTROY_SRQ_RESP_RESERVED7_MASK                0xfeUL
2223         #define CREQ_DESTROY_SRQ_RESP_RESERVED7_SFT                 1
2224         u8 event;
2225         #define CREQ_DESTROY_SRQ_RESP_EVENT_DESTROY_SRQ    0x6UL
2226         __le16 enable_for_arm[3];
2227         #define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_MASK           0x30000UL
2228         #define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_SFT            16
2229         #define CREQ_DESTROY_SRQ_RESP_RESERVED46_MASK               0xfffc0000UL
2230         #define CREQ_DESTROY_SRQ_RESP_RESERVED46_SFT                18
2231 };
2232
2233 /* Query SRQ command response (16 bytes) */
2234 struct creq_query_srq_resp {
2235         u8 type;
2236         #define CREQ_QUERY_SRQ_RESP_TYPE_MASK                       0x3fUL
2237         #define CREQ_QUERY_SRQ_RESP_TYPE_SFT                        0
2238         #define CREQ_QUERY_SRQ_RESP_TYPE_QP_EVENT                  0x38UL
2239         #define CREQ_QUERY_SRQ_RESP_RESERVED2_MASK                  0xc0UL
2240         #define CREQ_QUERY_SRQ_RESP_RESERVED2_SFT                   6
2241         u8 status;
2242         __le16 cookie;
2243         __le32 size;
2244         u8 v;
2245         #define CREQ_QUERY_SRQ_RESP_V                               0x1UL
2246         #define CREQ_QUERY_SRQ_RESP_RESERVED7_MASK                  0xfeUL
2247         #define CREQ_QUERY_SRQ_RESP_RESERVED7_SFT                   1
2248         u8 event;
2249         #define CREQ_QUERY_SRQ_RESP_EVENT_QUERY_SRQ                0x8UL
2250         __le16 reserved48[3];
2251 };
2252
2253 /* Query SRQ command response side buffer structure (24 bytes) */
2254 struct creq_query_srq_resp_sb {
2255         u8 opcode;
2256         #define CREQ_QUERY_SRQ_RESP_SB_OPCODE_QUERY_SRQ    0x8UL
2257         u8 status;
2258         __le16 cookie;
2259         __le16 flags;
2260         u8 resp_size;
2261         u8 reserved8;
2262         __le32 xid;
2263         __le16 srq_limit;
2264         __le16 reserved16;
2265         __le32 data[4];
2266 };
2267
2268 /* Create CQ command Response (16 bytes) */
2269 struct creq_create_cq_resp {
2270         u8 type;
2271         #define CREQ_CREATE_CQ_RESP_TYPE_MASK                       0x3fUL
2272         #define CREQ_CREATE_CQ_RESP_TYPE_SFT                        0
2273         #define CREQ_CREATE_CQ_RESP_TYPE_QP_EVENT                  0x38UL
2274         #define CREQ_CREATE_CQ_RESP_RESERVED2_MASK                  0xc0UL
2275         #define CREQ_CREATE_CQ_RESP_RESERVED2_SFT                   6
2276         u8 status;
2277         __le16 cookie;
2278         __le32 xid;
2279         u8 v;
2280         #define CREQ_CREATE_CQ_RESP_V                               0x1UL
2281         #define CREQ_CREATE_CQ_RESP_RESERVED7_MASK                  0xfeUL
2282         #define CREQ_CREATE_CQ_RESP_RESERVED7_SFT                   1
2283         u8 event;
2284         #define CREQ_CREATE_CQ_RESP_EVENT_CREATE_CQ                0x9UL
2285         __le16 reserved48[3];
2286 };
2287
2288 /* Destroy CQ command response (16 bytes) */
2289 struct creq_destroy_cq_resp {
2290         u8 type;
2291         #define CREQ_DESTROY_CQ_RESP_TYPE_MASK                      0x3fUL
2292         #define CREQ_DESTROY_CQ_RESP_TYPE_SFT                       0
2293         #define CREQ_DESTROY_CQ_RESP_TYPE_QP_EVENT                 0x38UL
2294         #define CREQ_DESTROY_CQ_RESP_RESERVED2_MASK                 0xc0UL
2295         #define CREQ_DESTROY_CQ_RESP_RESERVED2_SFT                  6
2296         u8 status;
2297         __le16 cookie;
2298         __le32 xid;
2299         u8 v;
2300         #define CREQ_DESTROY_CQ_RESP_V                              0x1UL
2301         #define CREQ_DESTROY_CQ_RESP_RESERVED7_MASK                 0xfeUL
2302         #define CREQ_DESTROY_CQ_RESP_RESERVED7_SFT                  1
2303         u8 event;
2304         #define CREQ_DESTROY_CQ_RESP_EVENT_DESTROY_CQ              0xaUL
2305         __le16 cq_arm_lvl;
2306         #define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_MASK                0x3UL
2307         #define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_SFT                 0
2308         #define CREQ_DESTROY_CQ_RESP_RESERVED14_MASK                0xfffcUL
2309         #define CREQ_DESTROY_CQ_RESP_RESERVED14_SFT                 2
2310         __le16 total_cnq_events;
2311         __le16 reserved16;
2312 };
2313
2314 /* Resize CQ command response (16 bytes) */
2315 struct creq_resize_cq_resp {
2316         u8 type;
2317         #define CREQ_RESIZE_CQ_RESP_TYPE_MASK                       0x3fUL
2318         #define CREQ_RESIZE_CQ_RESP_TYPE_SFT                        0
2319         #define CREQ_RESIZE_CQ_RESP_TYPE_QP_EVENT                  0x38UL
2320         #define CREQ_RESIZE_CQ_RESP_RESERVED2_MASK                  0xc0UL
2321         #define CREQ_RESIZE_CQ_RESP_RESERVED2_SFT                   6
2322         u8 status;
2323         __le16 cookie;
2324         __le32 xid;
2325         u8 v;
2326         #define CREQ_RESIZE_CQ_RESP_V                               0x1UL
2327         #define CREQ_RESIZE_CQ_RESP_RESERVED7_MASK                  0xfeUL
2328         #define CREQ_RESIZE_CQ_RESP_RESERVED7_SFT                   1
2329         u8 event;
2330         #define CREQ_RESIZE_CQ_RESP_EVENT_RESIZE_CQ                0xcUL
2331         __le16 reserved48[3];
2332 };
2333
2334 /* Allocate MRW command response (16 bytes) */
2335 struct creq_allocate_mrw_resp {
2336         u8 type;
2337         #define CREQ_ALLOCATE_MRW_RESP_TYPE_MASK                    0x3fUL
2338         #define CREQ_ALLOCATE_MRW_RESP_TYPE_SFT             0
2339         #define CREQ_ALLOCATE_MRW_RESP_TYPE_QP_EVENT               0x38UL
2340         #define CREQ_ALLOCATE_MRW_RESP_RESERVED2_MASK               0xc0UL
2341         #define CREQ_ALLOCATE_MRW_RESP_RESERVED2_SFT                6
2342         u8 status;
2343         __le16 cookie;
2344         __le32 xid;
2345         u8 v;
2346         #define CREQ_ALLOCATE_MRW_RESP_V                            0x1UL
2347         #define CREQ_ALLOCATE_MRW_RESP_RESERVED7_MASK               0xfeUL
2348         #define CREQ_ALLOCATE_MRW_RESP_RESERVED7_SFT                1
2349         u8 event;
2350         #define CREQ_ALLOCATE_MRW_RESP_EVENT_ALLOCATE_MRW          0xdUL
2351         __le16 reserved48[3];
2352 };
2353
2354 /* De-allocate key command response (16 bytes) */
2355 struct creq_deallocate_key_resp {
2356         u8 type;
2357         #define CREQ_DEALLOCATE_KEY_RESP_TYPE_MASK                  0x3fUL
2358         #define CREQ_DEALLOCATE_KEY_RESP_TYPE_SFT                   0
2359         #define CREQ_DEALLOCATE_KEY_RESP_TYPE_QP_EVENT             0x38UL
2360         #define CREQ_DEALLOCATE_KEY_RESP_RESERVED2_MASK     0xc0UL
2361         #define CREQ_DEALLOCATE_KEY_RESP_RESERVED2_SFT              6
2362         u8 status;
2363         __le16 cookie;
2364         __le32 xid;
2365         u8 v;
2366         #define CREQ_DEALLOCATE_KEY_RESP_V                          0x1UL
2367         #define CREQ_DEALLOCATE_KEY_RESP_RESERVED7_MASK     0xfeUL
2368         #define CREQ_DEALLOCATE_KEY_RESP_RESERVED7_SFT              1
2369         u8 event;
2370         #define CREQ_DEALLOCATE_KEY_RESP_EVENT_DEALLOCATE_KEY     0xeUL
2371         __le16 reserved16;
2372         __le32 bound_window_info;
2373 };
2374
2375 /* Register MR command response (16 bytes) */
2376 struct creq_register_mr_resp {
2377         u8 type;
2378         #define CREQ_REGISTER_MR_RESP_TYPE_MASK             0x3fUL
2379         #define CREQ_REGISTER_MR_RESP_TYPE_SFT                      0
2380         #define CREQ_REGISTER_MR_RESP_TYPE_QP_EVENT                0x38UL
2381         #define CREQ_REGISTER_MR_RESP_RESERVED2_MASK                0xc0UL
2382         #define CREQ_REGISTER_MR_RESP_RESERVED2_SFT                 6
2383         u8 status;
2384         __le16 cookie;
2385         __le32 xid;
2386         u8 v;
2387         #define CREQ_REGISTER_MR_RESP_V                     0x1UL
2388         #define CREQ_REGISTER_MR_RESP_RESERVED7_MASK                0xfeUL
2389         #define CREQ_REGISTER_MR_RESP_RESERVED7_SFT                 1
2390         u8 event;
2391         #define CREQ_REGISTER_MR_RESP_EVENT_REGISTER_MR    0xfUL
2392         __le16 reserved48[3];
2393 };
2394
2395 /* Deregister MR command response (16 bytes) */
2396 struct creq_deregister_mr_resp {
2397         u8 type;
2398         #define CREQ_DEREGISTER_MR_RESP_TYPE_MASK                   0x3fUL
2399         #define CREQ_DEREGISTER_MR_RESP_TYPE_SFT                    0
2400         #define CREQ_DEREGISTER_MR_RESP_TYPE_QP_EVENT              0x38UL
2401         #define CREQ_DEREGISTER_MR_RESP_RESERVED2_MASK              0xc0UL
2402         #define CREQ_DEREGISTER_MR_RESP_RESERVED2_SFT               6
2403         u8 status;
2404         __le16 cookie;
2405         __le32 xid;
2406         u8 v;
2407         #define CREQ_DEREGISTER_MR_RESP_V                           0x1UL
2408         #define CREQ_DEREGISTER_MR_RESP_RESERVED7_MASK              0xfeUL
2409         #define CREQ_DEREGISTER_MR_RESP_RESERVED7_SFT               1
2410         u8 event;
2411         #define CREQ_DEREGISTER_MR_RESP_EVENT_DEREGISTER_MR       0x10UL
2412         __le16 reserved16;
2413         __le32 bound_windows;
2414 };
2415
2416 /* Add GID command response (16 bytes) */
2417 struct creq_add_gid_resp {
2418         u8 type;
2419         #define CREQ_ADD_GID_RESP_TYPE_MASK                         0x3fUL
2420         #define CREQ_ADD_GID_RESP_TYPE_SFT                          0
2421         #define CREQ_ADD_GID_RESP_TYPE_QP_EVENT            0x38UL
2422         #define CREQ_ADD_GID_RESP_RESERVED2_MASK                    0xc0UL
2423         #define CREQ_ADD_GID_RESP_RESERVED2_SFT             6
2424         u8 status;
2425         __le16 cookie;
2426         __le32 xid;
2427         u8 v;
2428         #define CREQ_ADD_GID_RESP_V                                 0x1UL
2429         #define CREQ_ADD_GID_RESP_RESERVED7_MASK                    0xfeUL
2430         #define CREQ_ADD_GID_RESP_RESERVED7_SFT             1
2431         u8 event;
2432         #define CREQ_ADD_GID_RESP_EVENT_ADD_GID            0x11UL
2433         __le16 reserved48[3];
2434 };
2435
2436 /* Delete GID command response (16 bytes) */
2437 struct creq_delete_gid_resp {
2438         u8 type;
2439         #define CREQ_DELETE_GID_RESP_TYPE_MASK                      0x3fUL
2440         #define CREQ_DELETE_GID_RESP_TYPE_SFT                       0
2441         #define CREQ_DELETE_GID_RESP_TYPE_QP_EVENT                 0x38UL
2442         #define CREQ_DELETE_GID_RESP_RESERVED2_MASK                 0xc0UL
2443         #define CREQ_DELETE_GID_RESP_RESERVED2_SFT                  6
2444         u8 status;
2445         __le16 cookie;
2446         __le32 xid;
2447         u8 v;
2448         #define CREQ_DELETE_GID_RESP_V                              0x1UL
2449         #define CREQ_DELETE_GID_RESP_RESERVED7_MASK                 0xfeUL
2450         #define CREQ_DELETE_GID_RESP_RESERVED7_SFT                  1
2451         u8 event;
2452         #define CREQ_DELETE_GID_RESP_EVENT_DELETE_GID              0x12UL
2453         __le16 reserved48[3];
2454 };
2455
2456 /* Modify GID command response (16 bytes) */
2457 struct creq_modify_gid_resp {
2458         u8 type;
2459         #define CREQ_MODIFY_GID_RESP_TYPE_MASK                      0x3fUL
2460         #define CREQ_MODIFY_GID_RESP_TYPE_SFT                       0
2461         #define CREQ_MODIFY_GID_RESP_TYPE_QP_EVENT                 0x38UL
2462         #define CREQ_MODIFY_GID_RESP_RESERVED2_MASK                 0xc0UL
2463         #define CREQ_MODIFY_GID_RESP_RESERVED2_SFT                  6
2464         u8 status;
2465         __le16 cookie;
2466         __le32 xid;
2467         u8 v;
2468         #define CREQ_MODIFY_GID_RESP_V                              0x1UL
2469         #define CREQ_MODIFY_GID_RESP_RESERVED7_MASK                 0xfeUL
2470         #define CREQ_MODIFY_GID_RESP_RESERVED7_SFT                  1
2471         u8 event;
2472         #define CREQ_MODIFY_GID_RESP_EVENT_ADD_GID                 0x11UL
2473         __le16 reserved48[3];
2474 };
2475
2476 /* Query GID command response (16 bytes) */
2477 struct creq_query_gid_resp {
2478         u8 type;
2479         #define CREQ_QUERY_GID_RESP_TYPE_MASK                       0x3fUL
2480         #define CREQ_QUERY_GID_RESP_TYPE_SFT                        0
2481         #define CREQ_QUERY_GID_RESP_TYPE_QP_EVENT                  0x38UL
2482         #define CREQ_QUERY_GID_RESP_RESERVED2_MASK                  0xc0UL
2483         #define CREQ_QUERY_GID_RESP_RESERVED2_SFT                   6
2484         u8 status;
2485         __le16 cookie;
2486         __le32 size;
2487         u8 v;
2488         #define CREQ_QUERY_GID_RESP_V                               0x1UL
2489         #define CREQ_QUERY_GID_RESP_RESERVED7_MASK                  0xfeUL
2490         #define CREQ_QUERY_GID_RESP_RESERVED7_SFT                   1
2491         u8 event;
2492         #define CREQ_QUERY_GID_RESP_EVENT_QUERY_GID                0x18UL
2493         __le16 reserved48[3];
2494 };
2495
2496 /* Query GID command response side buffer structure (40 bytes) */
2497 struct creq_query_gid_resp_sb {
2498         u8 opcode;
2499         #define CREQ_QUERY_GID_RESP_SB_OPCODE_QUERY_GID    0x18UL
2500         u8 status;
2501         __le16 cookie;
2502         __le16 flags;
2503         u8 resp_size;
2504         u8 reserved8;
2505         __le32 gid[4];
2506         __le16 src_mac[3];
2507         __le16 vlan;
2508         #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_MASK            0xfffUL
2509         #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_SFT     0
2510         #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_MASK               0x7000UL
2511         #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_SFT                12
2512         #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_88A8         (0x0UL << 12)
2513         #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_8100         (0x1UL << 12)
2514         #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9100         (0x2UL << 12)
2515         #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9200         (0x3UL << 12)
2516         #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9300         (0x4UL << 12)
2517         #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG1         (0x5UL << 12)
2518         #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG2         (0x6UL << 12)
2519         #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3         (0x7UL << 12)
2520         #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_LAST   \
2521                                 CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3
2522         #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN                 0x8000UL
2523         __le16 ipid;
2524         __le16 gid_index;
2525         __le32 unused_0;
2526 };
2527
2528 /* Create QP1 command response (16 bytes) */
2529 struct creq_create_qp1_resp {
2530         u8 type;
2531         #define CREQ_CREATE_QP1_RESP_TYPE_MASK                      0x3fUL
2532         #define CREQ_CREATE_QP1_RESP_TYPE_SFT                       0
2533         #define CREQ_CREATE_QP1_RESP_TYPE_QP_EVENT                 0x38UL
2534         #define CREQ_CREATE_QP1_RESP_RESERVED2_MASK                 0xc0UL
2535         #define CREQ_CREATE_QP1_RESP_RESERVED2_SFT                  6
2536         u8 status;
2537         __le16 cookie;
2538         __le32 xid;
2539         u8 v;
2540         #define CREQ_CREATE_QP1_RESP_V                              0x1UL
2541         #define CREQ_CREATE_QP1_RESP_RESERVED7_MASK                 0xfeUL
2542         #define CREQ_CREATE_QP1_RESP_RESERVED7_SFT                  1
2543         u8 event;
2544         #define CREQ_CREATE_QP1_RESP_EVENT_CREATE_QP1              0x13UL
2545         __le16 reserved48[3];
2546 };
2547
2548 /* Destroy QP1 command response (16 bytes) */
2549 struct creq_destroy_qp1_resp {
2550         u8 type;
2551         #define CREQ_DESTROY_QP1_RESP_TYPE_MASK             0x3fUL
2552         #define CREQ_DESTROY_QP1_RESP_TYPE_SFT                      0
2553         #define CREQ_DESTROY_QP1_RESP_TYPE_QP_EVENT                0x38UL
2554         #define CREQ_DESTROY_QP1_RESP_RESERVED2_MASK                0xc0UL
2555         #define CREQ_DESTROY_QP1_RESP_RESERVED2_SFT                 6
2556         u8 status;
2557         __le16 cookie;
2558         __le32 xid;
2559         u8 v;
2560         #define CREQ_DESTROY_QP1_RESP_V                     0x1UL
2561         #define CREQ_DESTROY_QP1_RESP_RESERVED7_MASK                0xfeUL
2562         #define CREQ_DESTROY_QP1_RESP_RESERVED7_SFT                 1
2563         u8 event;
2564         #define CREQ_DESTROY_QP1_RESP_EVENT_DESTROY_QP1    0x14UL
2565         __le16 reserved48[3];
2566 };
2567
2568 /* Create AH command response (16 bytes) */
2569 struct creq_create_ah_resp {
2570         u8 type;
2571         #define CREQ_CREATE_AH_RESP_TYPE_MASK                       0x3fUL
2572         #define CREQ_CREATE_AH_RESP_TYPE_SFT                        0
2573         #define CREQ_CREATE_AH_RESP_TYPE_QP_EVENT                  0x38UL
2574         #define CREQ_CREATE_AH_RESP_RESERVED2_MASK                  0xc0UL
2575         #define CREQ_CREATE_AH_RESP_RESERVED2_SFT                   6
2576         u8 status;
2577         __le16 cookie;
2578         __le32 xid;
2579         u8 v;
2580         #define CREQ_CREATE_AH_RESP_V                               0x1UL
2581         #define CREQ_CREATE_AH_RESP_RESERVED7_MASK                  0xfeUL
2582         #define CREQ_CREATE_AH_RESP_RESERVED7_SFT                   1
2583         u8 event;
2584         #define CREQ_CREATE_AH_RESP_EVENT_CREATE_AH                0x15UL
2585         __le16 reserved48[3];
2586 };
2587
2588 /* Destroy AH command response (16 bytes) */
2589 struct creq_destroy_ah_resp {
2590         u8 type;
2591         #define CREQ_DESTROY_AH_RESP_TYPE_MASK                      0x3fUL
2592         #define CREQ_DESTROY_AH_RESP_TYPE_SFT                       0
2593         #define CREQ_DESTROY_AH_RESP_TYPE_QP_EVENT                 0x38UL
2594         #define CREQ_DESTROY_AH_RESP_RESERVED2_MASK                 0xc0UL
2595         #define CREQ_DESTROY_AH_RESP_RESERVED2_SFT                  6
2596         u8 status;
2597         __le16 cookie;
2598         __le32 xid;
2599         u8 v;
2600         #define CREQ_DESTROY_AH_RESP_V                              0x1UL
2601         #define CREQ_DESTROY_AH_RESP_RESERVED7_MASK                 0xfeUL
2602         #define CREQ_DESTROY_AH_RESP_RESERVED7_SFT                  1
2603         u8 event;
2604         #define CREQ_DESTROY_AH_RESP_EVENT_DESTROY_AH              0x16UL
2605         __le16 reserved48[3];
2606 };
2607
2608 /* Initialize Firmware command response (16 bytes) */
2609 struct creq_initialize_fw_resp {
2610         u8 type;
2611         #define CREQ_INITIALIZE_FW_RESP_TYPE_MASK                   0x3fUL
2612         #define CREQ_INITIALIZE_FW_RESP_TYPE_SFT                    0
2613         #define CREQ_INITIALIZE_FW_RESP_TYPE_QP_EVENT              0x38UL
2614         #define CREQ_INITIALIZE_FW_RESP_RESERVED2_MASK              0xc0UL
2615         #define CREQ_INITIALIZE_FW_RESP_RESERVED2_SFT               6
2616         u8 status;
2617         __le16 cookie;
2618         __le32 reserved32;
2619         u8 v;
2620         #define CREQ_INITIALIZE_FW_RESP_V                           0x1UL
2621         #define CREQ_INITIALIZE_FW_RESP_RESERVED7_MASK              0xfeUL
2622         #define CREQ_INITIALIZE_FW_RESP_RESERVED7_SFT               1
2623         u8 event;
2624         #define CREQ_INITIALIZE_FW_RESP_EVENT_INITIALIZE_FW       0x80UL
2625         __le16 reserved48[3];
2626 };
2627
2628 /* De-initialize Firmware command response (16 bytes) */
2629 struct creq_deinitialize_fw_resp {
2630         u8 type;
2631         #define CREQ_DEINITIALIZE_FW_RESP_TYPE_MASK                 0x3fUL
2632         #define CREQ_DEINITIALIZE_FW_RESP_TYPE_SFT                  0
2633         #define CREQ_DEINITIALIZE_FW_RESP_TYPE_QP_EVENT    0x38UL
2634         #define CREQ_DEINITIALIZE_FW_RESP_RESERVED2_MASK            0xc0UL
2635         #define CREQ_DEINITIALIZE_FW_RESP_RESERVED2_SFT     6
2636         u8 status;
2637         __le16 cookie;
2638         __le32 reserved32;
2639         u8 v;
2640         #define CREQ_DEINITIALIZE_FW_RESP_V                         0x1UL
2641         #define CREQ_DEINITIALIZE_FW_RESP_RESERVED7_MASK            0xfeUL
2642         #define CREQ_DEINITIALIZE_FW_RESP_RESERVED7_SFT     1
2643         u8 event;
2644         #define CREQ_DEINITIALIZE_FW_RESP_EVENT_DEINITIALIZE_FW   0x81UL
2645         __le16 reserved48[3];
2646 };
2647
2648 /* Stop function command response (16 bytes) */
2649 struct creq_stop_func_resp {
2650         u8 type;
2651         #define CREQ_STOP_FUNC_RESP_TYPE_MASK                       0x3fUL
2652         #define CREQ_STOP_FUNC_RESP_TYPE_SFT                        0
2653         #define CREQ_STOP_FUNC_RESP_TYPE_QP_EVENT                  0x38UL
2654         #define CREQ_STOP_FUNC_RESP_RESERVED2_MASK                  0xc0UL
2655         #define CREQ_STOP_FUNC_RESP_RESERVED2_SFT                   6
2656         u8 status;
2657         __le16 cookie;
2658         __le32 reserved32;
2659         u8 v;
2660         #define CREQ_STOP_FUNC_RESP_V                               0x1UL
2661         #define CREQ_STOP_FUNC_RESP_RESERVED7_MASK                  0xfeUL
2662         #define CREQ_STOP_FUNC_RESP_RESERVED7_SFT                   1
2663         u8 event;
2664         #define CREQ_STOP_FUNC_RESP_EVENT_STOP_FUNC                0x82UL
2665         __le16 reserved48[3];
2666 };
2667
2668 /* Query function command response (16 bytes) */
2669 struct creq_query_func_resp {
2670         u8 type;
2671         #define CREQ_QUERY_FUNC_RESP_TYPE_MASK                      0x3fUL
2672         #define CREQ_QUERY_FUNC_RESP_TYPE_SFT                       0
2673         #define CREQ_QUERY_FUNC_RESP_TYPE_QP_EVENT                 0x38UL
2674         #define CREQ_QUERY_FUNC_RESP_RESERVED2_MASK                 0xc0UL
2675         #define CREQ_QUERY_FUNC_RESP_RESERVED2_SFT                  6
2676         u8 status;
2677         __le16 cookie;
2678         __le32 size;
2679         u8 v;
2680         #define CREQ_QUERY_FUNC_RESP_V                              0x1UL
2681         #define CREQ_QUERY_FUNC_RESP_RESERVED7_MASK                 0xfeUL
2682         #define CREQ_QUERY_FUNC_RESP_RESERVED7_SFT                  1
2683         u8 event;
2684         #define CREQ_QUERY_FUNC_RESP_EVENT_QUERY_FUNC              0x83UL
2685         __le16 reserved48[3];
2686 };
2687
2688 /* Query function command response side buffer structure (88 bytes) */
2689 struct creq_query_func_resp_sb {
2690         u8 opcode;
2691         #define CREQ_QUERY_FUNC_RESP_SB_OPCODE_QUERY_FUNC          0x83UL
2692         u8 status;
2693         __le16 cookie;
2694         __le16 flags;
2695         u8 resp_size;
2696         u8 reserved8;
2697         __le64 max_mr_size;
2698         __le32 max_qp;
2699         __le16 max_qp_wr;
2700         __le16 dev_cap_flags;
2701         #define CREQ_QUERY_FUNC_RESP_SB_DEV_CAP_FLAGS_RESIZE_QP   0x1UL
2702         __le32 max_cq;
2703         __le32 max_cqe;
2704         __le32 max_pd;
2705         u8 max_sge;
2706         u8 max_srq_sge;
2707         u8 max_qp_rd_atom;
2708         u8 max_qp_init_rd_atom;
2709         __le32 max_mr;
2710         __le32 max_mw;
2711         __le32 max_raw_eth_qp;
2712         __le32 max_ah;
2713         __le32 max_fmr;
2714         __le32 max_srq_wr;
2715         __le32 max_pkeys;
2716         __le32 max_inline_data;
2717         u8 max_map_per_fmr;
2718         u8 l2_db_space_size;
2719         __le16 max_srq;
2720         __le32 max_gid;
2721         __le32 tqm_alloc_reqs[12];
2722 };
2723
2724 /* Set resources command response (16 bytes) */
2725 struct creq_set_func_resources_resp {
2726         u8 type;
2727         #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_MASK              0x3fUL
2728         #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_SFT               0
2729         #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_QP_EVENT         0x38UL
2730         #define CREQ_SET_FUNC_RESOURCES_RESP_RESERVED2_MASK         0xc0UL
2731         #define CREQ_SET_FUNC_RESOURCES_RESP_RESERVED2_SFT          6
2732         u8 status;
2733         __le16 cookie;
2734         __le32 reserved32;
2735         u8 v;
2736         #define CREQ_SET_FUNC_RESOURCES_RESP_V                      0x1UL
2737         #define CREQ_SET_FUNC_RESOURCES_RESP_RESERVED7_MASK         0xfeUL
2738         #define CREQ_SET_FUNC_RESOURCES_RESP_RESERVED7_SFT          1
2739         u8 event;
2740         #define CREQ_SET_FUNC_RESOURCES_RESP_EVENT_SET_FUNC_RESOURCES 0x84UL
2741         __le16 reserved48[3];
2742 };
2743
2744 /* Map TC to COS response (16 bytes) */
2745 struct creq_map_tc_to_cos_resp {
2746         u8 type;
2747         #define CREQ_MAP_TC_TO_COS_RESP_TYPE_MASK                   0x3fUL
2748         #define CREQ_MAP_TC_TO_COS_RESP_TYPE_SFT                    0
2749         #define CREQ_MAP_TC_TO_COS_RESP_TYPE_QP_EVENT              0x38UL
2750         #define CREQ_MAP_TC_TO_COS_RESP_RESERVED2_MASK              0xc0UL
2751         #define CREQ_MAP_TC_TO_COS_RESP_RESERVED2_SFT               6
2752         u8 status;
2753         __le16 cookie;
2754         __le32 reserved32;
2755         u8 v;
2756         #define CREQ_MAP_TC_TO_COS_RESP_V                           0x1UL
2757         #define CREQ_MAP_TC_TO_COS_RESP_RESERVED7_MASK              0xfeUL
2758         #define CREQ_MAP_TC_TO_COS_RESP_RESERVED7_SFT               1
2759         u8 event;
2760         #define CREQ_MAP_TC_TO_COS_RESP_EVENT_MAP_TC_TO_COS       0x8aUL
2761         __le16 reserved48[3];
2762 };
2763
2764 /* Query version response (16 bytes) */
2765 struct creq_query_version_resp {
2766         u8 type;
2767         #define CREQ_QUERY_VERSION_RESP_TYPE_MASK                   0x3fUL
2768         #define CREQ_QUERY_VERSION_RESP_TYPE_SFT                    0
2769         #define CREQ_QUERY_VERSION_RESP_TYPE_QP_EVENT              0x38UL
2770         #define CREQ_QUERY_VERSION_RESP_RESERVED2_MASK              0xc0UL
2771         #define CREQ_QUERY_VERSION_RESP_RESERVED2_SFT               6
2772         u8 status;
2773         __le16 cookie;
2774         u8 fw_maj;
2775         u8 fw_minor;
2776         u8 fw_bld;
2777         u8 fw_rsvd;
2778         u8 v;
2779         #define CREQ_QUERY_VERSION_RESP_V                           0x1UL
2780         #define CREQ_QUERY_VERSION_RESP_RESERVED7_MASK              0xfeUL
2781         #define CREQ_QUERY_VERSION_RESP_RESERVED7_SFT               1
2782         u8 event;
2783         #define CREQ_QUERY_VERSION_RESP_EVENT_QUERY_VERSION       0x8bUL
2784         __le16 reserved16;
2785         u8 intf_maj;
2786         u8 intf_minor;
2787         u8 intf_bld;
2788         u8 intf_rsvd;
2789 };
2790
2791 /* Modify congestion control command response (16 bytes) */
2792 struct creq_modify_cc_resp {
2793         u8 type;
2794         #define CREQ_MODIFY_CC_RESP_TYPE_MASK                       0x3fUL
2795         #define CREQ_MODIFY_CC_RESP_TYPE_SFT                        0
2796         #define CREQ_MODIFY_CC_RESP_TYPE_QP_EVENT                  0x38UL
2797         #define CREQ_MODIFY_CC_RESP_RESERVED2_MASK                  0xc0UL
2798         #define CREQ_MODIFY_CC_RESP_RESERVED2_SFT                   6
2799         u8 status;
2800         __le16 cookie;
2801         __le32 reserved32;
2802         u8 v;
2803         #define CREQ_MODIFY_CC_RESP_V                               0x1UL
2804         #define CREQ_MODIFY_CC_RESP_RESERVED7_MASK                  0xfeUL
2805         #define CREQ_MODIFY_CC_RESP_RESERVED7_SFT                   1
2806         u8 event;
2807         #define CREQ_MODIFY_CC_RESP_EVENT_MODIFY_CC                0x8cUL
2808         __le16 reserved48[3];
2809 };
2810
2811 /* Query congestion control command response (16 bytes) */
2812 struct creq_query_cc_resp {
2813         u8 type;
2814         #define CREQ_QUERY_CC_RESP_TYPE_MASK                        0x3fUL
2815         #define CREQ_QUERY_CC_RESP_TYPE_SFT                         0
2816         #define CREQ_QUERY_CC_RESP_TYPE_QP_EVENT                   0x38UL
2817         #define CREQ_QUERY_CC_RESP_RESERVED2_MASK                   0xc0UL
2818         #define CREQ_QUERY_CC_RESP_RESERVED2_SFT                    6
2819         u8 status;
2820         __le16 cookie;
2821         __le32 size;
2822         u8 v;
2823         #define CREQ_QUERY_CC_RESP_V                                0x1UL
2824         #define CREQ_QUERY_CC_RESP_RESERVED7_MASK                   0xfeUL
2825         #define CREQ_QUERY_CC_RESP_RESERVED7_SFT                    1
2826         u8 event;
2827         #define CREQ_QUERY_CC_RESP_EVENT_QUERY_CC                  0x8dUL
2828         __le16 reserved48[3];
2829 };
2830
2831 /* Query congestion control command response side buffer structure (32 bytes) */
2832 struct creq_query_cc_resp_sb {
2833         u8 opcode;
2834         #define CREQ_QUERY_CC_RESP_SB_OPCODE_QUERY_CC              0x8dUL
2835         u8 status;
2836         __le16 cookie;
2837         __le16 flags;
2838         u8 resp_size;
2839         u8 reserved8;
2840         u8 enable_cc;
2841         #define CREQ_QUERY_CC_RESP_SB_ENABLE_CC             0x1UL
2842         u8 g;
2843         #define CREQ_QUERY_CC_RESP_SB_G_MASK                        0x7UL
2844         #define CREQ_QUERY_CC_RESP_SB_G_SFT                         0
2845         u8 num_phases_per_state;
2846         __le16 init_cr;
2847         u8 unused_2;
2848         __le16 unused_3;
2849         u8 unused_4;
2850         __le16 init_tr;
2851         u8 tos_dscp_tos_ecn;
2852         #define CREQ_QUERY_CC_RESP_SB_TOS_ECN_MASK                  0x3UL
2853         #define CREQ_QUERY_CC_RESP_SB_TOS_ECN_SFT                   0
2854         #define CREQ_QUERY_CC_RESP_SB_TOS_DSCP_MASK                 0xfcUL
2855         #define CREQ_QUERY_CC_RESP_SB_TOS_DSCP_SFT                  2
2856         __le64 reserved64;
2857         __le64 reserved64_1;
2858 };
2859
2860 /* creq_query_roce_stats_resp (size:128b/16B) */
2861 struct creq_query_roce_stats_resp {
2862         u8      type;
2863         #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_MASK    0x3fUL
2864         #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_SFT     0
2865         #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_QP_EVENT  0x38UL
2866         #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_LAST    \
2867                                 CREQ_QUERY_ROCE_STATS_RESP_TYPE_QP_EVENT
2868         u8      status;
2869         __le16  cookie;
2870         __le32  size;
2871         u8      v;
2872         #define CREQ_QUERY_ROCE_STATS_RESP_V     0x1UL
2873         u8      event;
2874         #define CREQ_QUERY_ROCE_STATS_RESP_EVENT_QUERY_ROCE_STATS 0x8eUL
2875         #define CREQ_QUERY_ROCE_STATS_RESP_EVENT_LAST   \
2876                         CREQ_QUERY_ROCE_STATS_RESP_EVENT_QUERY_ROCE_STATS
2877         u8      reserved48[6];
2878 };
2879
2880 /* creq_query_roce_stats_resp_sb (size:2624b/328B) */
2881 struct creq_query_roce_stats_resp_sb {
2882         u8      opcode;
2883         #define CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_QUERY_ROCE_STATS 0x8eUL
2884         #define CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_LAST \
2885                         CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_QUERY_ROCE_STATS
2886         u8      status;
2887         __le16  cookie;
2888         __le16  flags;
2889         u8      resp_size;
2890         u8      rsvd;
2891         __le32  num_counters;
2892         __le32  rsvd1;
2893         __le64  to_retransmits;
2894         __le64  seq_err_naks_rcvd;
2895         __le64  max_retry_exceeded;
2896         __le64  rnr_naks_rcvd;
2897         __le64  missing_resp;
2898         __le64  unrecoverable_err;
2899         __le64  bad_resp_err;
2900         __le64  local_qp_op_err;
2901         __le64  local_protection_err;
2902         __le64  mem_mgmt_op_err;
2903         __le64  remote_invalid_req_err;
2904         __le64  remote_access_err;
2905         __le64  remote_op_err;
2906         __le64  dup_req;
2907         __le64  res_exceed_max;
2908         __le64  res_length_mismatch;
2909         __le64  res_exceeds_wqe;
2910         __le64  res_opcode_err;
2911         __le64  res_rx_invalid_rkey;
2912         __le64  res_rx_domain_err;
2913         __le64  res_rx_no_perm;
2914         __le64  res_rx_range_err;
2915         __le64  res_tx_invalid_rkey;
2916         __le64  res_tx_domain_err;
2917         __le64  res_tx_no_perm;
2918         __le64  res_tx_range_err;
2919         __le64  res_irrq_oflow;
2920         __le64  res_unsup_opcode;
2921         __le64  res_unaligned_atomic;
2922         __le64  res_rem_inv_err;
2923         __le64  res_mem_error;
2924         __le64  res_srq_err;
2925         __le64  res_cmp_err;
2926         __le64  res_invalid_dup_rkey;
2927         __le64  res_wqe_format_err;
2928         __le64  res_cq_load_err;
2929         __le64  res_srq_load_err;
2930         __le64  res_tx_pci_err;
2931         __le64  res_rx_pci_err;
2932 };
2933
2934 /* QP error notification event (16 bytes) */
2935 struct creq_qp_error_notification {
2936         u8 type;
2937         #define CREQ_QP_ERROR_NOTIFICATION_TYPE_MASK                0x3fUL
2938         #define CREQ_QP_ERROR_NOTIFICATION_TYPE_SFT                 0
2939         #define CREQ_QP_ERROR_NOTIFICATION_TYPE_QP_EVENT           0x38UL
2940         #define CREQ_QP_ERROR_NOTIFICATION_RESERVED2_MASK           0xc0UL
2941         #define CREQ_QP_ERROR_NOTIFICATION_RESERVED2_SFT            6
2942         u8 status;
2943         u8 req_slow_path_state;
2944         u8 req_err_state_reason;
2945         __le32 xid;
2946         u8 v;
2947         #define CREQ_QP_ERROR_NOTIFICATION_V                        0x1UL
2948         #define CREQ_QP_ERROR_NOTIFICATION_RESERVED7_MASK           0xfeUL
2949         #define CREQ_QP_ERROR_NOTIFICATION_RESERVED7_SFT            1
2950         u8 event;
2951         #define CREQ_QP_ERROR_NOTIFICATION_EVENT_QP_ERROR_NOTIFICATION 0xc0UL
2952         u8 res_slow_path_state;
2953         u8 res_err_state_reason;
2954         __le16 sq_cons_idx;
2955         __le16 rq_cons_idx;
2956 };
2957
2958 /* RoCE Slowpath HSI Specification 1.6.0 */
2959 #define ROCE_SP_HSI_VERSION_MAJOR       1
2960 #define ROCE_SP_HSI_VERSION_MINOR       6
2961 #define ROCE_SP_HSI_VERSION_UPDATE      0
2962
2963 #define ROCE_SP_HSI_VERSION_STR "1.6.0"
2964 /*
2965  * Following is the signature for ROCE_SP_HSI message field that indicates not
2966  * applicable (All F's). Need to cast it the size of the field if needed.
2967  */
2968 #define ROCE_SP_HSI_NA_SIGNATURE        ((__le32)(-1))
2969 #endif /* __BNXT_RE_HSI_H__ */