drivers/infiniband/hw/cxgb3/cxio_hal.c

   1 /*
   2  * Copyright (c) 2006 Chelsio, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #include <asm/delay.h>
  33
  34 #include <linux/mutex.h>
  35 #include <linux/netdevice.h>
  36 #include <linux/sched.h>
  37 #include <linux/spinlock.h>
  38 #include <linux/pci.h>
  39 #include <linux/dma-mapping.h>
  40 #include <linux/slab.h>
  41 #include <net/net_namespace.h>
  42
  43 #include "cxio_resource.h"
  44 #include "cxio_hal.h"
  45 #include "cxgb3_offload.h"
  46 #include "sge_defs.h"
  47
  48 static LIST_HEAD(rdev_list);
  49 static cxio_hal_ev_callback_func_t cxio_ev_cb = NULL;
  50
  51 static struct cxio_rdev *cxio_hal_find_rdev_by_name(char *dev_name)
  52 {
  53         struct cxio_rdev *rdev;
  54
  55         list_for_each_entry(rdev, &rdev_list, entry)
  56                 if (!strcmp(rdev->dev_name, dev_name))
  57                         return rdev;
  58         return NULL;
  59 }
  60
  61 static struct cxio_rdev *cxio_hal_find_rdev_by_t3cdev(struct t3cdev *tdev)
  62 {
  63         struct cxio_rdev *rdev;
  64
  65         list_for_each_entry(rdev, &rdev_list, entry)
  66                 if (rdev->t3cdev_p == tdev)
  67                         return rdev;
  68         return NULL;
  69 }
  70
  71 int cxio_hal_cq_op(struct cxio_rdev *rdev_p, struct t3_cq *cq,
  72                    enum t3_cq_opcode op, u32 credit)
  73 {
  74         int ret;
  75         struct t3_cqe *cqe;
  76         u32 rptr;
  77
  78         struct rdma_cq_op setup;
  79         setup.id = cq->cqid;
  80         setup.credits = (op == CQ_CREDIT_UPDATE) ? credit : 0;
  81         setup.op = op;
  82         ret = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_OP, &setup);
  83
  84         if ((ret < 0) || (op == CQ_CREDIT_UPDATE))
  85                 return ret;
  86
  87         /*
  88          * If the rearm returned an index other than our current index,
  89          * then there might be CQE's in flight (being DMA'd).  We must wait
  90          * here for them to complete or the consumer can miss a notification.
  91          */
  92         if (Q_PTR2IDX((cq->rptr), cq->size_log2) != ret) {
  93                 int i=0;
  94
  95                 rptr = cq->rptr;
  96
  97                 /*
  98                  * Keep the generation correct by bumping rptr until it
  99                  * matches the index returned by the rearm - 1.
 100                  */
 101                 while (Q_PTR2IDX((rptr+1), cq->size_log2) != ret)
 102                         rptr++;
 103
 104                 /*
 105                  * Now rptr is the index for the (last) cqe that was
 106                  * in-flight at the time the HW rearmed the CQ.  We
 107                  * spin until that CQE is valid.
 108                  */
 109                 cqe = cq->queue + Q_PTR2IDX(rptr, cq->size_log2);
 110                 while (!CQ_VLD_ENTRY(rptr, cq->size_log2, cqe)) {
 111                         udelay(1);
 112                         if (i++ > 1000000) {
 113                                 pr_err("%s: stalled rnic\n", rdev_p->dev_name);
 114                                 return -EIO;
 115                         }
 116                 }
 117
 118                 return 1;
 119         }
 120
 121         return 0;
 122 }
 123
 124 static int cxio_hal_clear_cq_ctx(struct cxio_rdev *rdev_p, u32 cqid)
 125 {
 126         struct rdma_cq_setup setup;
 127         setup.id = cqid;
 128         setup.base_addr = 0;    /* NULL address */
 129         setup.size = 0;         /* disaable the CQ */
 130         setup.credits = 0;
 131         setup.credit_thres = 0;
 132         setup.ovfl_mode = 0;
 133         return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
 134 }
 135
 136 static int cxio_hal_clear_qp_ctx(struct cxio_rdev *rdev_p, u32 qpid)
 137 {
 138         u64 sge_cmd;
 139         struct t3_modify_qp_wr *wqe;
 140         struct sk_buff *skb = alloc_skb(sizeof(*wqe), GFP_KERNEL);
 141         if (!skb) {
 142                 pr_debug("%s alloc_skb failed\n", __func__);
 143                 return -ENOMEM;
 144         }
 145         wqe = skb_put_zero(skb, sizeof(*wqe));
 146         build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_QP_MOD,
 147                        T3_COMPLETION_FLAG | T3_NOTIFY_FLAG, 0, qpid, 7,
 148                        T3_SOPEOP);
 149         wqe->flags = cpu_to_be32(MODQP_WRITE_EC);
 150         sge_cmd = qpid << 8 | 3;
 151         wqe->sge_cmd = cpu_to_be64(sge_cmd);
 152         skb->priority = CPL_PRIORITY_CONTROL;
 153         return iwch_cxgb3_ofld_send(rdev_p->t3cdev_p, skb);
 154 }
 155
 156 int cxio_create_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq, int kernel)
 157 {
 158         struct rdma_cq_setup setup;
 159         int size = (1UL << (cq->size_log2)) * sizeof(struct t3_cqe);
 160
 161         size += 1; /* one extra page for storing cq-in-err state */
 162         cq->cqid = cxio_hal_get_cqid(rdev_p->rscp);
 163         if (!cq->cqid)
 164                 return -ENOMEM;
 165         if (kernel) {
 166                 cq->sw_queue = kzalloc(size, GFP_KERNEL);
 167                 if (!cq->sw_queue)
 168                         return -ENOMEM;
 169         }
 170         cq->queue = dma_alloc_coherent(&(rdev_p->rnic_info.pdev->dev), size,
 171                                              &(cq->dma_addr), GFP_KERNEL);
 172         if (!cq->queue) {
 173                 kfree(cq->sw_queue);
 174                 return -ENOMEM;
 175         }
 176         dma_unmap_addr_set(cq, mapping, cq->dma_addr);
 177         memset(cq->queue, 0, size);
 178         setup.id = cq->cqid;
 179         setup.base_addr = (u64) (cq->dma_addr);
 180         setup.size = 1UL << cq->size_log2;
 181         setup.credits = 65535;
 182         setup.credit_thres = 1;
 183         if (rdev_p->t3cdev_p->type != T3A)
 184                 setup.ovfl_mode = 0;
 185         else
 186                 setup.ovfl_mode = 1;
 187         return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
 188 }
 189
 190 #ifdef notyet
 191 int cxio_resize_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq)
 192 {
 193         struct rdma_cq_setup setup;
 194         setup.id = cq->cqid;
 195         setup.base_addr = (u64) (cq->dma_addr);
 196         setup.size = 1UL << cq->size_log2;
 197         setup.credits = setup.size;
 198         setup.credit_thres = setup.size;        /* TBD: overflow recovery */
 199         setup.ovfl_mode = 1;
 200         return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
 201 }
 202 #endif
 203
 204 static u32 get_qpid(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
 205 {
 206         struct cxio_qpid_list *entry;
 207         u32 qpid;
 208         int i;
 209
 210         mutex_lock(&uctx->lock);
 211         if (!list_empty(&uctx->qpids)) {
 212                 entry = list_entry(uctx->qpids.next, struct cxio_qpid_list,
 213                                    entry);
 214                 list_del(&entry->entry);
 215                 qpid = entry->qpid;
 216                 kfree(entry);
 217         } else {
 218                 qpid = cxio_hal_get_qpid(rdev_p->rscp);
 219                 if (!qpid)
 220                         goto out;
 221                 for (i = qpid+1; i & rdev_p->qpmask; i++) {
 222                         entry = kmalloc(sizeof *entry, GFP_KERNEL);
 223                         if (!entry)
 224                                 break;
 225                         entry->qpid = i;
 226                         list_add_tail(&entry->entry, &uctx->qpids);
 227                 }
 228         }
 229 out:
 230         mutex_unlock(&uctx->lock);
 231         pr_debug("%s qpid 0x%x\n", __func__, qpid);
 232         return qpid;
 233 }
 234
 235 static void put_qpid(struct cxio_rdev *rdev_p, u32 qpid,
 236                      struct cxio_ucontext *uctx)
 237 {
 238         struct cxio_qpid_list *entry;
 239
 240         entry = kmalloc(sizeof *entry, GFP_KERNEL);
 241         if (!entry)
 242                 return;
 243         pr_debug("%s qpid 0x%x\n", __func__, qpid);
 244         entry->qpid = qpid;
 245         mutex_lock(&uctx->lock);
 246         list_add_tail(&entry->entry, &uctx->qpids);
 247         mutex_unlock(&uctx->lock);
 248 }
 249
 250 void cxio_release_ucontext(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
 251 {
 252         struct list_head *pos, *nxt;
 253         struct cxio_qpid_list *entry;
 254
 255         mutex_lock(&uctx->lock);
 256         list_for_each_safe(pos, nxt, &uctx->qpids) {
 257                 entry = list_entry(pos, struct cxio_qpid_list, entry);
 258                 list_del_init(&entry->entry);
 259                 if (!(entry->qpid & rdev_p->qpmask))
 260                         cxio_hal_put_qpid(rdev_p->rscp, entry->qpid);
 261                 kfree(entry);
 262         }
 263         mutex_unlock(&uctx->lock);
 264 }
 265
 266 void cxio_init_ucontext(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
 267 {
 268         INIT_LIST_HEAD(&uctx->qpids);
 269         mutex_init(&uctx->lock);
 270 }
 271
 272 int cxio_create_qp(struct cxio_rdev *rdev_p, u32 kernel_domain,
 273                    struct t3_wq *wq, struct cxio_ucontext *uctx)
 274 {
 275         int depth = 1UL << wq->size_log2;
 276         int rqsize = 1UL << wq->rq_size_log2;
 277
 278         wq->qpid = get_qpid(rdev_p, uctx);
 279         if (!wq->qpid)
 280                 return -ENOMEM;
 281
 282         wq->rq = kcalloc(depth, sizeof(struct t3_swrq), GFP_KERNEL);
 283         if (!wq->rq)
 284                 goto err1;
 285
 286         wq->rq_addr = cxio_hal_rqtpool_alloc(rdev_p, rqsize);
 287         if (!wq->rq_addr)
 288                 goto err2;
 289
 290         wq->sq = kcalloc(depth, sizeof(struct t3_swsq), GFP_KERNEL);
 291         if (!wq->sq)
 292                 goto err3;
 293
 294         wq->queue = dma_alloc_coherent(&(rdev_p->rnic_info.pdev->dev),
 295                                              depth * sizeof(union t3_wr),
 296                                              &(wq->dma_addr), GFP_KERNEL);
 297         if (!wq->queue)
 298                 goto err4;
 299
 300         memset(wq->queue, 0, depth * sizeof(union t3_wr));
 301         dma_unmap_addr_set(wq, mapping, wq->dma_addr);
 302         wq->doorbell = (void __iomem *)rdev_p->rnic_info.kdb_addr;
 303         if (!kernel_domain)
 304                 wq->udb = (u64)rdev_p->rnic_info.udbell_physbase +
 305                                         (wq->qpid << rdev_p->qpshift);
 306         wq->rdev = rdev_p;
 307         pr_debug("%s qpid 0x%x doorbell 0x%p udb 0x%llx\n",
 308                  __func__, wq->qpid, wq->doorbell, (unsigned long long)wq->udb);
 309         return 0;
 310 err4:
 311         kfree(wq->sq);
 312 err3:
 313         cxio_hal_rqtpool_free(rdev_p, wq->rq_addr, rqsize);
 314 err2:
 315         kfree(wq->rq);
 316 err1:
 317         put_qpid(rdev_p, wq->qpid, uctx);
 318         return -ENOMEM;
 319 }
 320
 321 int cxio_destroy_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq)
 322 {
 323         int err;
 324         err = cxio_hal_clear_cq_ctx(rdev_p, cq->cqid);
 325         kfree(cq->sw_queue);
 326         dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
 327                           (1UL << (cq->size_log2))
 328                           * sizeof(struct t3_cqe) + 1, cq->queue,
 329                           dma_unmap_addr(cq, mapping));
 330         cxio_hal_put_cqid(rdev_p->rscp, cq->cqid);
 331         return err;
 332 }
 333
 334 int cxio_destroy_qp(struct cxio_rdev *rdev_p, struct t3_wq *wq,
 335                     struct cxio_ucontext *uctx)
 336 {
 337         dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
 338                           (1UL << (wq->size_log2))
 339                           * sizeof(union t3_wr), wq->queue,
 340                           dma_unmap_addr(wq, mapping));
 341         kfree(wq->sq);
 342         cxio_hal_rqtpool_free(rdev_p, wq->rq_addr, (1UL << wq->rq_size_log2));
 343         kfree(wq->rq);
 344         put_qpid(rdev_p, wq->qpid, uctx);
 345         return 0;
 346 }
 347
 348 static void insert_recv_cqe(struct t3_wq *wq, struct t3_cq *cq)
 349 {
 350         struct t3_cqe cqe;
 351
 352         pr_debug("%s wq %p cq %p sw_rptr 0x%x sw_wptr 0x%x\n", __func__,
 353                  wq, cq, cq->sw_rptr, cq->sw_wptr);
 354         memset(&cqe, 0, sizeof(cqe));
 355         cqe.header = cpu_to_be32(V_CQE_STATUS(TPT_ERR_SWFLUSH) |
 356                                  V_CQE_OPCODE(T3_SEND) |
 357                                  V_CQE_TYPE(0) |
 358                                  V_CQE_SWCQE(1) |
 359                                  V_CQE_QPID(wq->qpid) |
 360                                  V_CQE_GENBIT(Q_GENBIT(cq->sw_wptr,
 361                                                        cq->size_log2)));
 362         *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2)) = cqe;
 363         cq->sw_wptr++;
 364 }
 365
 366 int cxio_flush_rq(struct t3_wq *wq, struct t3_cq *cq, int count)
 367 {
 368         u32 ptr;
 369         int flushed = 0;
 370
 371         pr_debug("%s wq %p cq %p\n", __func__, wq, cq);
 372
 373         /* flush RQ */
 374         pr_debug("%s rq_rptr %u rq_wptr %u skip count %u\n", __func__,
 375                  wq->rq_rptr, wq->rq_wptr, count);
 376         ptr = wq->rq_rptr + count;
 377         while (ptr++ != wq->rq_wptr) {
 378                 insert_recv_cqe(wq, cq);
 379                 flushed++;
 380         }
 381         return flushed;
 382 }
 383
 384 static void insert_sq_cqe(struct t3_wq *wq, struct t3_cq *cq,
 385                           struct t3_swsq *sqp)
 386 {
 387         struct t3_cqe cqe;
 388
 389         pr_debug("%s wq %p cq %p sw_rptr 0x%x sw_wptr 0x%x\n", __func__,
 390                  wq, cq, cq->sw_rptr, cq->sw_wptr);
 391         memset(&cqe, 0, sizeof(cqe));
 392         cqe.header = cpu_to_be32(V_CQE_STATUS(TPT_ERR_SWFLUSH) |
 393                                  V_CQE_OPCODE(sqp->opcode) |
 394                                  V_CQE_TYPE(1) |
 395                                  V_CQE_SWCQE(1) |
 396                                  V_CQE_QPID(wq->qpid) |
 397                                  V_CQE_GENBIT(Q_GENBIT(cq->sw_wptr,
 398                                                        cq->size_log2)));
 399         cqe.u.scqe.wrid_hi = sqp->sq_wptr;
 400
 401         *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2)) = cqe;
 402         cq->sw_wptr++;
 403 }
 404
 405 int cxio_flush_sq(struct t3_wq *wq, struct t3_cq *cq, int count)
 406 {
 407         __u32 ptr = wq->sq_rptr + count;
 408         int flushed = 0;
 409         struct t3_swsq *sqp = wq->sq + Q_PTR2IDX(ptr, wq->sq_size_log2);
 410
 411         while (ptr != wq->sq_wptr) {
 412                 sqp->signaled = 0;
 413                 insert_sq_cqe(wq, cq, sqp);
 414                 ptr++;
 415                 sqp = wq->sq + Q_PTR2IDX(ptr, wq->sq_size_log2);
 416                 flushed++;
 417         }
 418         return flushed;
 419 }
 420
 421 /*
 422  * Move all CQEs from the HWCQ into the SWCQ.
 423  */
 424 void cxio_flush_hw_cq(struct t3_cq *cq)
 425 {
 426         struct t3_cqe *cqe, *swcqe;
 427
 428         pr_debug("%s cq %p cqid 0x%x\n", __func__, cq, cq->cqid);
 429         cqe = cxio_next_hw_cqe(cq);
 430         while (cqe) {
 431                 pr_debug("%s flushing hwcq rptr 0x%x to swcq wptr 0x%x\n",
 432                          __func__, cq->rptr, cq->sw_wptr);
 433                 swcqe = cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2);
 434                 *swcqe = *cqe;
 435                 swcqe->header |= cpu_to_be32(V_CQE_SWCQE(1));
 436                 cq->sw_wptr++;
 437                 cq->rptr++;
 438                 cqe = cxio_next_hw_cqe(cq);
 439         }
 440 }
 441
 442 static int cqe_completes_wr(struct t3_cqe *cqe, struct t3_wq *wq)
 443 {
 444         if (CQE_OPCODE(*cqe) == T3_TERMINATE)
 445                 return 0;
 446
 447         if ((CQE_OPCODE(*cqe) == T3_RDMA_WRITE) && RQ_TYPE(*cqe))
 448                 return 0;
 449
 450         if ((CQE_OPCODE(*cqe) == T3_READ_RESP) && SQ_TYPE(*cqe))
 451                 return 0;
 452
 453         if (CQE_SEND_OPCODE(*cqe) && RQ_TYPE(*cqe) &&
 454             Q_EMPTY(wq->rq_rptr, wq->rq_wptr))
 455                 return 0;
 456
 457         return 1;
 458 }
 459
 460 void cxio_count_scqes(struct t3_cq *cq, struct t3_wq *wq, int *count)
 461 {
 462         struct t3_cqe *cqe;
 463         u32 ptr;
 464
 465         *count = 0;
 466         ptr = cq->sw_rptr;
 467         while (!Q_EMPTY(ptr, cq->sw_wptr)) {
 468                 cqe = cq->sw_queue + (Q_PTR2IDX(ptr, cq->size_log2));
 469                 if ((SQ_TYPE(*cqe) ||
 470                      ((CQE_OPCODE(*cqe) == T3_READ_RESP) && wq->oldest_read)) &&
 471                     (CQE_QPID(*cqe) == wq->qpid))
 472                         (*count)++;
 473                 ptr++;
 474         }
 475         pr_debug("%s cq %p count %d\n", __func__, cq, *count);
 476 }
 477
 478 void cxio_count_rcqes(struct t3_cq *cq, struct t3_wq *wq, int *count)
 479 {
 480         struct t3_cqe *cqe;
 481         u32 ptr;
 482
 483         *count = 0;
 484         pr_debug("%s count zero %d\n", __func__, *count);
 485         ptr = cq->sw_rptr;
 486         while (!Q_EMPTY(ptr, cq->sw_wptr)) {
 487                 cqe = cq->sw_queue + (Q_PTR2IDX(ptr, cq->size_log2));
 488                 if (RQ_TYPE(*cqe) && (CQE_OPCODE(*cqe) != T3_READ_RESP) &&
 489                     (CQE_QPID(*cqe) == wq->qpid) && cqe_completes_wr(cqe, wq))
 490                         (*count)++;
 491                 ptr++;
 492         }
 493         pr_debug("%s cq %p count %d\n", __func__, cq, *count);
 494 }
 495
 496 static int cxio_hal_init_ctrl_cq(struct cxio_rdev *rdev_p)
 497 {
 498         struct rdma_cq_setup setup;
 499         setup.id = 0;
 500         setup.base_addr = 0;    /* NULL address */
 501         setup.size = 1;         /* enable the CQ */
 502         setup.credits = 0;
 503
 504         /* force SGE to redirect to RspQ and interrupt */
 505         setup.credit_thres = 0;
 506         setup.ovfl_mode = 1;
 507         return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
 508 }
 509
 510 static int cxio_hal_init_ctrl_qp(struct cxio_rdev *rdev_p)
 511 {
 512         int err;
 513         u64 sge_cmd, ctx0, ctx1;
 514         u64 base_addr;
 515         struct t3_modify_qp_wr *wqe;
 516         struct sk_buff *skb;
 517
 518         skb = alloc_skb(sizeof(*wqe), GFP_KERNEL);
 519         if (!skb) {
 520                 pr_debug("%s alloc_skb failed\n", __func__);
 521                 return -ENOMEM;
 522         }
 523         err = cxio_hal_init_ctrl_cq(rdev_p);
 524         if (err) {
 525                 pr_debug("%s err %d initializing ctrl_cq\n", __func__, err);
 526                 goto err;
 527         }
 528         rdev_p->ctrl_qp.workq = dma_alloc_coherent(
 529                                         &(rdev_p->rnic_info.pdev->dev),
 530                                         (1 << T3_CTRL_QP_SIZE_LOG2) *
 531                                         sizeof(union t3_wr),
 532                                         &(rdev_p->ctrl_qp.dma_addr),
 533                                         GFP_KERNEL);
 534         if (!rdev_p->ctrl_qp.workq) {
 535                 pr_debug("%s dma_alloc_coherent failed\n", __func__);
 536                 err = -ENOMEM;
 537                 goto err;
 538         }
 539         dma_unmap_addr_set(&rdev_p->ctrl_qp, mapping,
 540                            rdev_p->ctrl_qp.dma_addr);
 541         rdev_p->ctrl_qp.doorbell = (void __iomem *)rdev_p->rnic_info.kdb_addr;
 542         memset(rdev_p->ctrl_qp.workq, 0,
 543                (1 << T3_CTRL_QP_SIZE_LOG2) * sizeof(union t3_wr));
 544
 545         mutex_init(&rdev_p->ctrl_qp.lock);
 546         init_waitqueue_head(&rdev_p->ctrl_qp.waitq);
 547
 548         /* update HW Ctrl QP context */
 549         base_addr = rdev_p->ctrl_qp.dma_addr;
 550         base_addr >>= 12;
 551         ctx0 = (V_EC_SIZE((1 << T3_CTRL_QP_SIZE_LOG2)) |
 552                 V_EC_BASE_LO((u32) base_addr & 0xffff));
 553         ctx0 <<= 32;
 554         ctx0 |= V_EC_CREDITS(FW_WR_NUM);
 555         base_addr >>= 16;
 556         ctx1 = (u32) base_addr;
 557         base_addr >>= 32;
 558         ctx1 |= ((u64) (V_EC_BASE_HI((u32) base_addr & 0xf) | V_EC_RESPQ(0) |
 559                         V_EC_TYPE(0) | V_EC_GEN(1) |
 560                         V_EC_UP_TOKEN(T3_CTL_QP_TID) | F_EC_VALID)) << 32;
 561         wqe = skb_put_zero(skb, sizeof(*wqe));
 562         build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_QP_MOD, 0, 0,
 563                        T3_CTL_QP_TID, 7, T3_SOPEOP);
 564         wqe->flags = cpu_to_be32(MODQP_WRITE_EC);
 565         sge_cmd = (3ULL << 56) | FW_RI_SGEEC_START << 8 | 3;
 566         wqe->sge_cmd = cpu_to_be64(sge_cmd);
 567         wqe->ctx1 = cpu_to_be64(ctx1);
 568         wqe->ctx0 = cpu_to_be64(ctx0);
 569         pr_debug("CtrlQP dma_addr 0x%llx workq %p size %d\n",
 570                  (unsigned long long)rdev_p->ctrl_qp.dma_addr,
 571                  rdev_p->ctrl_qp.workq, 1 << T3_CTRL_QP_SIZE_LOG2);
 572         skb->priority = CPL_PRIORITY_CONTROL;
 573         return iwch_cxgb3_ofld_send(rdev_p->t3cdev_p, skb);
 574 err:
 575         kfree_skb(skb);
 576         return err;
 577 }
 578
 579 static int cxio_hal_destroy_ctrl_qp(struct cxio_rdev *rdev_p)
 580 {
 581         dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
 582                           (1UL << T3_CTRL_QP_SIZE_LOG2)
 583                           * sizeof(union t3_wr), rdev_p->ctrl_qp.workq,
 584                           dma_unmap_addr(&rdev_p->ctrl_qp, mapping));
 585         return cxio_hal_clear_qp_ctx(rdev_p, T3_CTRL_QP_ID);
 586 }
 587
 588 /* write len bytes of data into addr (32B aligned address)
 589  * If data is NULL, clear len byte of memory to zero.
 590  * caller acquires the ctrl_qp lock before the call
 591  */
 592 static int cxio_hal_ctrl_qp_write_mem(struct cxio_rdev *rdev_p, u32 addr,
 593                                       u32 len, void *data)
 594 {
 595         u32 i, nr_wqe, copy_len;
 596         u8 *copy_data;
 597         u8 wr_len, utx_len;     /* length in 8 byte flit */
 598         enum t3_wr_flags flag;
 599         __be64 *wqe;
 600         u64 utx_cmd;
 601         addr &= 0x7FFFFFF;
 602         nr_wqe = len % 96 ? len / 96 + 1 : len / 96;    /* 96B max per WQE */
 603         pr_debug("%s wptr 0x%x rptr 0x%x len %d, nr_wqe %d data %p addr 0x%0x\n",
 604                  __func__, rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, len,
 605                  nr_wqe, data, addr);
 606         utx_len = 3;            /* in 32B unit */
 607         for (i = 0; i < nr_wqe; i++) {
 608                 if (Q_FULL(rdev_p->ctrl_qp.rptr, rdev_p->ctrl_qp.wptr,
 609                            T3_CTRL_QP_SIZE_LOG2)) {
 610                         pr_debug("%s ctrl_qp full wtpr 0x%0x rptr 0x%0x, wait for more space i %d\n",
 611                                  __func__,
 612                                  rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, i);
 613                         if (wait_event_interruptible(rdev_p->ctrl_qp.waitq,
 614                                              !Q_FULL(rdev_p->ctrl_qp.rptr,
 615                                                      rdev_p->ctrl_qp.wptr,
 616                                                      T3_CTRL_QP_SIZE_LOG2))) {
 617                                 pr_debug("%s ctrl_qp workq interrupted\n",
 618                                          __func__);
 619                                 return -ERESTARTSYS;
 620                         }
 621                         pr_debug("%s ctrl_qp wakeup, continue posting work request i %d\n",
 622                                  __func__, i);
 623                 }
 624                 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr %
 625                                                 (1 << T3_CTRL_QP_SIZE_LOG2)));
 626                 flag = 0;
 627                 if (i == (nr_wqe - 1)) {
 628                         /* last WQE */
 629                         flag = T3_COMPLETION_FLAG;
 630                         if (len % 32)
 631                                 utx_len = len / 32 + 1;
 632                         else
 633                                 utx_len = len / 32;
 634                 }
 635
 636                 /*
 637                  * Force a CQE to return the credit to the workq in case
 638                  * we posted more than half the max QP size of WRs
 639                  */
 640                 if ((i != 0) &&
 641                     (i % (((1 << T3_CTRL_QP_SIZE_LOG2)) >> 1) == 0)) {
 642                         flag = T3_COMPLETION_FLAG;
 643                         pr_debug("%s force completion at i %d\n", __func__, i);
 644                 }
 645
 646                 /* build the utx mem command */
 647                 wqe += (sizeof(struct t3_bypass_wr) >> 3);
 648                 utx_cmd = (T3_UTX_MEM_WRITE << 28) | (addr + i * 3);
 649                 utx_cmd <<= 32;
 650                 utx_cmd |= (utx_len << 28) | ((utx_len << 2) + 1);
 651                 *wqe = cpu_to_be64(utx_cmd);
 652                 wqe++;
 653                 copy_data = (u8 *) data + i * 96;
 654                 copy_len = len > 96 ? 96 : len;
 655
 656                 /* clear memory content if data is NULL */
 657                 if (data)
 658                         memcpy(wqe, copy_data, copy_len);
 659                 else
 660                         memset(wqe, 0, copy_len);
 661                 if (copy_len % 32)
 662                         memset(((u8 *) wqe) + copy_len, 0,
 663                                32 - (copy_len % 32));
 664                 wr_len = ((sizeof(struct t3_bypass_wr)) >> 3) + 1 +
 665                          (utx_len << 2);
 666                 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr %
 667                               (1 << T3_CTRL_QP_SIZE_LOG2)));
 668
 669                 /* wptr in the WRID[31:0] */
 670                 ((union t3_wrid *)(wqe+1))->id0.low = rdev_p->ctrl_qp.wptr;
 671
 672                 /*
 673                  * This must be the last write with a memory barrier
 674                  * for the genbit
 675                  */
 676                 build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_BP, flag,
 677                                Q_GENBIT(rdev_p->ctrl_qp.wptr,
 678                                         T3_CTRL_QP_SIZE_LOG2), T3_CTRL_QP_ID,
 679                                wr_len, T3_SOPEOP);
 680                 if (flag == T3_COMPLETION_FLAG)
 681                         ring_doorbell(rdev_p->ctrl_qp.doorbell, T3_CTRL_QP_ID);
 682                 len -= 96;
 683                 rdev_p->ctrl_qp.wptr++;
 684         }
 685         return 0;
 686 }
 687
 688 /* IN: stag key, pdid, perm, zbva, to, len, page_size, pbl_size and pbl_addr
 689  * OUT: stag index
 690  * TBD: shared memory region support
 691  */
 692 static int __cxio_tpt_op(struct cxio_rdev *rdev_p, u32 reset_tpt_entry,
 693                          u32 *stag, u8 stag_state, u32 pdid,
 694                          enum tpt_mem_type type, enum tpt_mem_perm perm,
 695                          u32 zbva, u64 to, u32 len, u8 page_size,
 696                          u32 pbl_size, u32 pbl_addr)
 697 {
 698         int err;
 699         struct tpt_entry tpt;
 700         u32 stag_idx;
 701         u32 wptr;
 702
 703         if (cxio_fatal_error(rdev_p))
 704                 return -EIO;
 705
 706         stag_state = stag_state > 0;
 707         stag_idx = (*stag) >> 8;
 708
 709         if ((!reset_tpt_entry) && !(*stag != T3_STAG_UNSET)) {
 710                 stag_idx = cxio_hal_get_stag(rdev_p->rscp);
 711                 if (!stag_idx)
 712                         return -ENOMEM;
 713                 *stag = (stag_idx << 8) | ((*stag) & 0xFF);
 714         }
 715         pr_debug("%s stag_state 0x%0x type 0x%0x pdid 0x%0x, stag_idx 0x%x\n",
 716                  __func__, stag_state, type, pdid, stag_idx);
 717
 718         mutex_lock(&rdev_p->ctrl_qp.lock);
 719
 720         /* write TPT entry */
 721         if (reset_tpt_entry)
 722                 memset(&tpt, 0, sizeof(tpt));
 723         else {
 724                 tpt.valid_stag_pdid = cpu_to_be32(F_TPT_VALID |
 725                                 V_TPT_STAG_KEY((*stag) & M_TPT_STAG_KEY) |
 726                                 V_TPT_STAG_STATE(stag_state) |
 727                                 V_TPT_STAG_TYPE(type) | V_TPT_PDID(pdid));
 728                 BUG_ON(page_size >= 28);
 729                 tpt.flags_pagesize_qpid = cpu_to_be32(V_TPT_PERM(perm) |
 730                         ((perm & TPT_MW_BIND) ? F_TPT_MW_BIND_ENABLE : 0) |
 731                         V_TPT_ADDR_TYPE((zbva ? TPT_ZBTO : TPT_VATO)) |
 732                         V_TPT_PAGE_SIZE(page_size));
 733                 tpt.rsvd_pbl_addr = cpu_to_be32(V_TPT_PBL_ADDR(PBL_OFF(rdev_p, pbl_addr)>>3));
 734                 tpt.len = cpu_to_be32(len);
 735                 tpt.va_hi = cpu_to_be32((u32) (to >> 32));
 736                 tpt.va_low_or_fbo = cpu_to_be32((u32) (to & 0xFFFFFFFFULL));
 737                 tpt.rsvd_bind_cnt_or_pstag = 0;
 738                 tpt.rsvd_pbl_size = cpu_to_be32(V_TPT_PBL_SIZE(pbl_size >> 2));
 739         }
 740         err = cxio_hal_ctrl_qp_write_mem(rdev_p,
 741                                        stag_idx +
 742                                        (rdev_p->rnic_info.tpt_base >> 5),
 743                                        sizeof(tpt), &tpt);
 744
 745         /* release the stag index to free pool */
 746         if (reset_tpt_entry)
 747                 cxio_hal_put_stag(rdev_p->rscp, stag_idx);
 748
 749         wptr = rdev_p->ctrl_qp.wptr;
 750         mutex_unlock(&rdev_p->ctrl_qp.lock);
 751         if (!err)
 752                 if (wait_event_interruptible(rdev_p->ctrl_qp.waitq,
 753                                              SEQ32_GE(rdev_p->ctrl_qp.rptr,
 754                                                       wptr)))
 755                         return -ERESTARTSYS;
 756         return err;
 757 }
 758
 759 int cxio_write_pbl(struct cxio_rdev *rdev_p, __be64 *pbl,
 760                    u32 pbl_addr, u32 pbl_size)
 761 {
 762         u32 wptr;
 763         int err;
 764
 765         pr_debug("%s *pdb_addr 0x%x, pbl_base 0x%x, pbl_size %d\n",
 766                  __func__, pbl_addr, rdev_p->rnic_info.pbl_base,
 767                  pbl_size);
 768
 769         mutex_lock(&rdev_p->ctrl_qp.lock);
 770         err = cxio_hal_ctrl_qp_write_mem(rdev_p, pbl_addr >> 5, pbl_size << 3,
 771                                          pbl);
 772         wptr = rdev_p->ctrl_qp.wptr;
 773         mutex_unlock(&rdev_p->ctrl_qp.lock);
 774         if (err)
 775                 return err;
 776
 777         if (wait_event_interruptible(rdev_p->ctrl_qp.waitq,
 778                                      SEQ32_GE(rdev_p->ctrl_qp.rptr,
 779                                               wptr)))
 780                 return -ERESTARTSYS;
 781
 782         return 0;
 783 }
 784
 785 int cxio_register_phys_mem(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid,
 786                            enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len,
 787                            u8 page_size, u32 pbl_size, u32 pbl_addr)
 788 {
 789         *stag = T3_STAG_UNSET;
 790         return __cxio_tpt_op(rdev_p, 0, stag, 1, pdid, TPT_NON_SHARED_MR, perm,
 791                              zbva, to, len, page_size, pbl_size, pbl_addr);
 792 }
 793
 794 int cxio_reregister_phys_mem(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid,
 795                            enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len,
 796                            u8 page_size, u32 pbl_size, u32 pbl_addr)
 797 {
 798         return __cxio_tpt_op(rdev_p, 0, stag, 1, pdid, TPT_NON_SHARED_MR, perm,
 799                              zbva, to, len, page_size, pbl_size, pbl_addr);
 800 }
 801
 802 int cxio_dereg_mem(struct cxio_rdev *rdev_p, u32 stag, u32 pbl_size,
 803                    u32 pbl_addr)
 804 {
 805         return __cxio_tpt_op(rdev_p, 1, &stag, 0, 0, 0, 0, 0, 0ULL, 0, 0,
 806                              pbl_size, pbl_addr);
 807 }
 808
 809 int cxio_allocate_window(struct cxio_rdev *rdev_p, u32 * stag, u32 pdid)
 810 {
 811         *stag = T3_STAG_UNSET;
 812         return __cxio_tpt_op(rdev_p, 0, stag, 0, pdid, TPT_MW, 0, 0, 0ULL, 0, 0,
 813                              0, 0);
 814 }
 815
 816 int cxio_deallocate_window(struct cxio_rdev *rdev_p, u32 stag)
 817 {
 818         return __cxio_tpt_op(rdev_p, 1, &stag, 0, 0, 0, 0, 0, 0ULL, 0, 0,
 819                              0, 0);
 820 }
 821
 822 int cxio_allocate_stag(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid, u32 pbl_size, u32 pbl_addr)
 823 {
 824         *stag = T3_STAG_UNSET;
 825         return __cxio_tpt_op(rdev_p, 0, stag, 0, pdid, TPT_NON_SHARED_MR,
 826                              0, 0, 0ULL, 0, 0, pbl_size, pbl_addr);
 827 }
 828
 829 int cxio_rdma_init(struct cxio_rdev *rdev_p, struct t3_rdma_init_attr *attr)
 830 {
 831         struct t3_rdma_init_wr *wqe;
 832         struct sk_buff *skb = alloc_skb(sizeof(*wqe), GFP_ATOMIC);
 833         if (!skb)
 834                 return -ENOMEM;
 835         pr_debug("%s rdev_p %p\n", __func__, rdev_p);
 836         wqe = __skb_put(skb, sizeof(*wqe));
 837         wqe->wrh.op_seop_flags = cpu_to_be32(V_FW_RIWR_OP(T3_WR_INIT));
 838         wqe->wrh.gen_tid_len = cpu_to_be32(V_FW_RIWR_TID(attr->tid) |
 839                                            V_FW_RIWR_LEN(sizeof(*wqe) >> 3));
 840         wqe->wrid.id1 = 0;
 841         wqe->qpid = cpu_to_be32(attr->qpid);
 842         wqe->pdid = cpu_to_be32(attr->pdid);
 843         wqe->scqid = cpu_to_be32(attr->scqid);
 844         wqe->rcqid = cpu_to_be32(attr->rcqid);
 845         wqe->rq_addr = cpu_to_be32(attr->rq_addr - rdev_p->rnic_info.rqt_base);
 846         wqe->rq_size = cpu_to_be32(attr->rq_size);
 847         wqe->mpaattrs = attr->mpaattrs;
 848         wqe->qpcaps = attr->qpcaps;
 849         wqe->ulpdu_size = cpu_to_be16(attr->tcp_emss);
 850         wqe->rqe_count = cpu_to_be16(attr->rqe_count);
 851         wqe->flags_rtr_type = cpu_to_be16(attr->flags |
 852                                           V_RTR_TYPE(attr->rtr_type) |
 853                                           V_CHAN(attr->chan));
 854         wqe->ord = cpu_to_be32(attr->ord);
 855         wqe->ird = cpu_to_be32(attr->ird);
 856         wqe->qp_dma_addr = cpu_to_be64(attr->qp_dma_addr);
 857         wqe->qp_dma_size = cpu_to_be32(attr->qp_dma_size);
 858         wqe->irs = cpu_to_be32(attr->irs);
 859         skb->priority = 0;      /* 0=>ToeQ; 1=>CtrlQ */
 860         return iwch_cxgb3_ofld_send(rdev_p->t3cdev_p, skb);
 861 }
 862
 863 void cxio_register_ev_cb(cxio_hal_ev_callback_func_t ev_cb)
 864 {
 865         cxio_ev_cb = ev_cb;
 866 }
 867
 868 void cxio_unregister_ev_cb(cxio_hal_ev_callback_func_t ev_cb)
 869 {
 870         cxio_ev_cb = NULL;
 871 }
 872
 873 static int cxio_hal_ev_handler(struct t3cdev *t3cdev_p, struct sk_buff *skb)
 874 {
 875         static int cnt;
 876         struct cxio_rdev *rdev_p = NULL;
 877         struct respQ_msg_t *rsp_msg = (struct respQ_msg_t *) skb->data;
 878         pr_debug("%d: %s cq_id 0x%x cq_ptr 0x%x genbit %0x overflow %0x an %0x se %0x notify %0x cqbranch %0x creditth %0x\n",
 879                  cnt, __func__, RSPQ_CQID(rsp_msg), RSPQ_CQPTR(rsp_msg),
 880                  RSPQ_GENBIT(rsp_msg), RSPQ_OVERFLOW(rsp_msg), RSPQ_AN(rsp_msg),
 881                  RSPQ_SE(rsp_msg), RSPQ_NOTIFY(rsp_msg), RSPQ_CQBRANCH(rsp_msg),
 882                  RSPQ_CREDIT_THRESH(rsp_msg));
 883         pr_debug("CQE: QPID 0x%0x genbit %0x type 0x%0x status 0x%0x opcode %d len 0x%0x wrid_hi_stag 0x%x wrid_low_msn 0x%x\n",
 884                  CQE_QPID(rsp_msg->cqe), CQE_GENBIT(rsp_msg->cqe),
 885                  CQE_TYPE(rsp_msg->cqe), CQE_STATUS(rsp_msg->cqe),
 886                  CQE_OPCODE(rsp_msg->cqe), CQE_LEN(rsp_msg->cqe),
 887                  CQE_WRID_HI(rsp_msg->cqe), CQE_WRID_LOW(rsp_msg->cqe));
 888         rdev_p = (struct cxio_rdev *)t3cdev_p->ulp;
 889         if (!rdev_p) {
 890                 pr_debug("%s called by t3cdev %p with null ulp\n", __func__,
 891                          t3cdev_p);
 892                 return 0;
 893         }
 894         if (CQE_QPID(rsp_msg->cqe) == T3_CTRL_QP_ID) {
 895                 rdev_p->ctrl_qp.rptr = CQE_WRID_LOW(rsp_msg->cqe) + 1;
 896                 wake_up_interruptible(&rdev_p->ctrl_qp.waitq);
 897                 dev_kfree_skb_irq(skb);
 898         } else if (CQE_QPID(rsp_msg->cqe) == 0xfff8)
 899                 dev_kfree_skb_irq(skb);
 900         else if (cxio_ev_cb)
 901                 (*cxio_ev_cb) (rdev_p, skb);
 902         else
 903                 dev_kfree_skb_irq(skb);
 904         cnt++;
 905         return 0;
 906 }
 907
 908 /* Caller takes care of locking if needed */
 909 int cxio_rdev_open(struct cxio_rdev *rdev_p)
 910 {
 911         struct net_device *netdev_p = NULL;
 912         int err = 0;
 913         if (strlen(rdev_p->dev_name)) {
 914                 if (cxio_hal_find_rdev_by_name(rdev_p->dev_name)) {
 915                         return -EBUSY;
 916                 }
 917                 netdev_p = dev_get_by_name(&init_net, rdev_p->dev_name);
 918                 if (!netdev_p) {
 919                         return -EINVAL;
 920                 }
 921                 dev_put(netdev_p);
 922         } else if (rdev_p->t3cdev_p) {
 923                 if (cxio_hal_find_rdev_by_t3cdev(rdev_p->t3cdev_p)) {
 924                         return -EBUSY;
 925                 }
 926                 netdev_p = rdev_p->t3cdev_p->lldev;
 927                 strncpy(rdev_p->dev_name, rdev_p->t3cdev_p->name,
 928                         T3_MAX_DEV_NAME_LEN);
 929         } else {
 930                 pr_debug("%s t3cdev_p or dev_name must be set\n", __func__);
 931                 return -EINVAL;
 932         }
 933
 934         list_add_tail(&rdev_p->entry, &rdev_list);
 935
 936         pr_debug("%s opening rnic dev %s\n", __func__, rdev_p->dev_name);
 937         memset(&rdev_p->ctrl_qp, 0, sizeof(rdev_p->ctrl_qp));
 938         if (!rdev_p->t3cdev_p)
 939                 rdev_p->t3cdev_p = dev2t3cdev(netdev_p);
 940         rdev_p->t3cdev_p->ulp = (void *) rdev_p;
 941
 942         err = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, GET_EMBEDDED_INFO,
 943                                          &(rdev_p->fw_info));
 944         if (err) {
 945                 pr_err("%s t3cdev_p(%p)->ctl returned error %d\n",
 946                        __func__, rdev_p->t3cdev_p, err);
 947                 goto err1;
 948         }
 949         if (G_FW_VERSION_MAJOR(rdev_p->fw_info.fw_vers) != CXIO_FW_MAJ) {
 950                 pr_err("fatal firmware version mismatch: need version %u but adapter has version %u\n",
 951                        CXIO_FW_MAJ,
 952                        G_FW_VERSION_MAJOR(rdev_p->fw_info.fw_vers));
 953                 err = -EINVAL;
 954                 goto err1;
 955         }
 956
 957         err = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_GET_PARAMS,
 958                                          &(rdev_p->rnic_info));
 959         if (err) {
 960                 pr_err("%s t3cdev_p(%p)->ctl returned error %d\n",
 961                        __func__, rdev_p->t3cdev_p, err);
 962                 goto err1;
 963         }
 964         err = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, GET_PORTS,
 965                                     &(rdev_p->port_info));
 966         if (err) {
 967                 pr_err("%s t3cdev_p(%p)->ctl returned error %d\n",
 968                        __func__, rdev_p->t3cdev_p, err);
 969                 goto err1;
 970         }
 971
 972         /*
 973          * qpshift is the number of bits to shift the qpid left in order
 974          * to get the correct address of the doorbell for that qp.
 975          */
 976         cxio_init_ucontext(rdev_p, &rdev_p->uctx);
 977         rdev_p->qpshift = PAGE_SHIFT -
 978                           ilog2(65536 >>
 979                                     ilog2(rdev_p->rnic_info.udbell_len >>
 980                                               PAGE_SHIFT));
 981         rdev_p->qpnr = rdev_p->rnic_info.udbell_len >> PAGE_SHIFT;
 982         rdev_p->qpmask = (65536 >> ilog2(rdev_p->qpnr)) - 1;
 983         pr_debug("%s rnic %s info: tpt_base 0x%0x tpt_top 0x%0x num stags %d pbl_base 0x%0x pbl_top 0x%0x rqt_base 0x%0x, rqt_top 0x%0x\n",
 984                  __func__, rdev_p->dev_name, rdev_p->rnic_info.tpt_base,
 985                  rdev_p->rnic_info.tpt_top, cxio_num_stags(rdev_p),
 986                  rdev_p->rnic_info.pbl_base,
 987                  rdev_p->rnic_info.pbl_top, rdev_p->rnic_info.rqt_base,
 988                  rdev_p->rnic_info.rqt_top);
 989         pr_debug("udbell_len 0x%0x udbell_physbase 0x%lx kdb_addr %p qpshift %lu qpnr %d qpmask 0x%x\n",
 990                  rdev_p->rnic_info.udbell_len,
 991                  rdev_p->rnic_info.udbell_physbase, rdev_p->rnic_info.kdb_addr,
 992                  rdev_p->qpshift, rdev_p->qpnr, rdev_p->qpmask);
 993
 994         err = cxio_hal_init_ctrl_qp(rdev_p);
 995         if (err) {
 996                 pr_err("%s error %d initializing ctrl_qp\n", __func__, err);
 997                 goto err1;
 998         }
 999         err = cxio_hal_init_resource(rdev_p, cxio_num_stags(rdev_p), 0,
1000                                      0, T3_MAX_NUM_QP, T3_MAX_NUM_CQ,
1001                                      T3_MAX_NUM_PD);
1002         if (err) {
1003                 pr_err("%s error %d initializing hal resources\n",
1004                        __func__, err);
1005                 goto err2;
1006         }
1007         err = cxio_hal_pblpool_create(rdev_p);
1008         if (err) {
1009                 pr_err("%s error %d initializing pbl mem pool\n",
1010                        __func__, err);
1011                 goto err3;
1012         }
1013         err = cxio_hal_rqtpool_create(rdev_p);
1014         if (err) {
1015                 pr_err("%s error %d initializing rqt mem pool\n",
1016                        __func__, err);
1017                 goto err4;
1018         }
1019         return 0;
1020 err4:
1021         cxio_hal_pblpool_destroy(rdev_p);
1022 err3:
1023         cxio_hal_destroy_resource(rdev_p->rscp);
1024 err2:
1025         cxio_hal_destroy_ctrl_qp(rdev_p);
1026 err1:
1027         rdev_p->t3cdev_p->ulp = NULL;
1028         list_del(&rdev_p->entry);
1029         return err;
1030 }
1031
1032 void cxio_rdev_close(struct cxio_rdev *rdev_p)
1033 {
1034         if (rdev_p) {
1035                 cxio_hal_pblpool_destroy(rdev_p);
1036                 cxio_hal_rqtpool_destroy(rdev_p);
1037                 list_del(&rdev_p->entry);
1038                 cxio_hal_destroy_ctrl_qp(rdev_p);
1039                 cxio_hal_destroy_resource(rdev_p->rscp);
1040                 rdev_p->t3cdev_p->ulp = NULL;
1041         }
1042 }
1043
1044 int __init cxio_hal_init(void)
1045 {
1046         if (cxio_hal_init_rhdl_resource(T3_MAX_NUM_RI))
1047                 return -ENOMEM;
1048         t3_register_cpl_handler(CPL_ASYNC_NOTIF, cxio_hal_ev_handler);
1049         return 0;
1050 }
1051
1052 void __exit cxio_hal_exit(void)
1053 {
1054         struct cxio_rdev *rdev, *tmp;
1055
1056         t3_register_cpl_handler(CPL_ASYNC_NOTIF, NULL);
1057         list_for_each_entry_safe(rdev, tmp, &rdev_list, entry)
1058                 cxio_rdev_close(rdev);
1059         cxio_hal_destroy_rhdl_resource();
1060 }
1061
1062 static void flush_completed_wrs(struct t3_wq *wq, struct t3_cq *cq)
1063 {
1064         struct t3_swsq *sqp;
1065         __u32 ptr = wq->sq_rptr;
1066         int count = Q_COUNT(wq->sq_rptr, wq->sq_wptr);
1067
1068         sqp = wq->sq + Q_PTR2IDX(ptr, wq->sq_size_log2);
1069         while (count--)
1070                 if (!sqp->signaled) {
1071                         ptr++;
1072                         sqp = wq->sq + Q_PTR2IDX(ptr,  wq->sq_size_log2);
1073                 } else if (sqp->complete) {
1074
1075                         /*
1076                          * Insert this completed cqe into the swcq.
1077                          */
1078                         pr_debug("%s moving cqe into swcq sq idx %ld cq idx %ld\n",
1079                                  __func__, Q_PTR2IDX(ptr,  wq->sq_size_log2),
1080                                  Q_PTR2IDX(cq->sw_wptr, cq->size_log2));
1081                         sqp->cqe.header |= htonl(V_CQE_SWCQE(1));
1082                         *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2))
1083                                 = sqp->cqe;
1084                         cq->sw_wptr++;
1085                         sqp->signaled = 0;
1086                         break;
1087                 } else
1088                         break;
1089 }
1090
1091 static void create_read_req_cqe(struct t3_wq *wq, struct t3_cqe *hw_cqe,
1092                                 struct t3_cqe *read_cqe)
1093 {
1094         read_cqe->u.scqe.wrid_hi = wq->oldest_read->sq_wptr;
1095         read_cqe->len = wq->oldest_read->read_len;
1096         read_cqe->header = htonl(V_CQE_QPID(CQE_QPID(*hw_cqe)) |
1097                                  V_CQE_SWCQE(SW_CQE(*hw_cqe)) |
1098                                  V_CQE_OPCODE(T3_READ_REQ) |
1099                                  V_CQE_TYPE(1));
1100 }
1101
1102 /*
1103  * Return a ptr to the next read wr in the SWSQ or NULL.
1104  */
1105 static void advance_oldest_read(struct t3_wq *wq)
1106 {
1107
1108         u32 rptr = wq->oldest_read - wq->sq + 1;
1109         u32 wptr = Q_PTR2IDX(wq->sq_wptr, wq->sq_size_log2);
1110
1111         while (Q_PTR2IDX(rptr, wq->sq_size_log2) != wptr) {
1112                 wq->oldest_read = wq->sq + Q_PTR2IDX(rptr, wq->sq_size_log2);
1113
1114                 if (wq->oldest_read->opcode == T3_READ_REQ)
1115                         return;
1116                 rptr++;
1117         }
1118         wq->oldest_read = NULL;
1119 }
1120
1121 /*
1122  * cxio_poll_cq
1123  *
1124  * Caller must:
1125  *     check the validity of the first CQE,
1126  *     supply the wq assicated with the qpid.
1127  *
1128  * credit: cq credit to return to sge.
1129  * cqe_flushed: 1 iff the CQE is flushed.
1130  * cqe: copy of the polled CQE.
1131  *
1132  * return value:
1133  *     0       CQE returned,
1134  *    -1       CQE skipped, try again.
1135  */
1136 int cxio_poll_cq(struct t3_wq *wq, struct t3_cq *cq, struct t3_cqe *cqe,
1137                      u8 *cqe_flushed, u64 *cookie, u32 *credit)
1138 {
1139         int ret = 0;
1140         struct t3_cqe *hw_cqe, read_cqe;
1141
1142         *cqe_flushed = 0;
1143         *credit = 0;
1144         hw_cqe = cxio_next_cqe(cq);
1145
1146         pr_debug("%s CQE OOO %d qpid 0x%0x genbit %d type %d status 0x%0x opcode 0x%0x len 0x%0x wrid_hi_stag 0x%x wrid_low_msn 0x%x\n",
1147                  __func__, CQE_OOO(*hw_cqe), CQE_QPID(*hw_cqe),
1148                  CQE_GENBIT(*hw_cqe), CQE_TYPE(*hw_cqe), CQE_STATUS(*hw_cqe),
1149                  CQE_OPCODE(*hw_cqe), CQE_LEN(*hw_cqe), CQE_WRID_HI(*hw_cqe),
1150                  CQE_WRID_LOW(*hw_cqe));
1151
1152         /*
1153          * skip cqe's not affiliated with a QP.
1154          */
1155         if (wq == NULL) {
1156                 ret = -1;
1157                 goto skip_cqe;
1158         }
1159
1160         /*
1161          * Gotta tweak READ completions:
1162          *      1) the cqe doesn't contain the sq_wptr from the wr.
1163          *      2) opcode not reflected from the wr.
1164          *      3) read_len not reflected from the wr.
1165          *      4) cq_type is RQ_TYPE not SQ_TYPE.
1166          */
1167         if (RQ_TYPE(*hw_cqe) && (CQE_OPCODE(*hw_cqe) == T3_READ_RESP)) {
1168
1169                 /*
1170                  * If this is an unsolicited read response, then the read
1171                  * was generated by the kernel driver as part of peer-2-peer
1172                  * connection setup.  So ignore the completion.
1173                  */
1174                 if (!wq->oldest_read) {
1175                         if (CQE_STATUS(*hw_cqe))
1176                                 wq->error = 1;
1177                         ret = -1;
1178                         goto skip_cqe;
1179                 }
1180
1181                 /*
1182                  * Don't write to the HWCQ, so create a new read req CQE
1183                  * in local memory.
1184                  */
1185                 create_read_req_cqe(wq, hw_cqe, &read_cqe);
1186                 hw_cqe = &read_cqe;
1187                 advance_oldest_read(wq);
1188         }
1189
1190         /*
1191          * T3A: Discard TERMINATE CQEs.
1192          */
1193         if (CQE_OPCODE(*hw_cqe) == T3_TERMINATE) {
1194                 ret = -1;
1195                 wq->error = 1;
1196                 goto skip_cqe;
1197         }
1198
1199         if (CQE_STATUS(*hw_cqe) || wq->error) {
1200                 *cqe_flushed = wq->error;
1201                 wq->error = 1;
1202
1203                 /*
1204                  * T3A inserts errors into the CQE.  We cannot return
1205                  * these as work completions.
1206                  */
1207                 /* incoming write failures */
1208                 if ((CQE_OPCODE(*hw_cqe) == T3_RDMA_WRITE)
1209                      && RQ_TYPE(*hw_cqe)) {
1210                         ret = -1;
1211                         goto skip_cqe;
1212                 }
1213                 /* incoming read request failures */
1214                 if ((CQE_OPCODE(*hw_cqe) == T3_READ_RESP) && SQ_TYPE(*hw_cqe)) {
1215                         ret = -1;
1216                         goto skip_cqe;
1217                 }
1218
1219                 /* incoming SEND with no receive posted failures */
1220                 if (CQE_SEND_OPCODE(*hw_cqe) && RQ_TYPE(*hw_cqe) &&
1221                     Q_EMPTY(wq->rq_rptr, wq->rq_wptr)) {
1222                         ret = -1;
1223                         goto skip_cqe;
1224                 }
1225                 BUG_ON((*cqe_flushed == 0) && !SW_CQE(*hw_cqe));
1226                 goto proc_cqe;
1227         }
1228
1229         /*
1230          * RECV completion.
1231          */
1232         if (RQ_TYPE(*hw_cqe)) {
1233
1234                 /*
1235                  * HW only validates 4 bits of MSN.  So we must validate that
1236                  * the MSN in the SEND is the next expected MSN.  If its not,
1237                  * then we complete this with TPT_ERR_MSN and mark the wq in
1238                  * error.
1239                  */
1240
1241                 if (Q_EMPTY(wq->rq_rptr, wq->rq_wptr)) {
1242                         wq->error = 1;
1243                         ret = -1;
1244                         goto skip_cqe;
1245                 }
1246
1247                 if (unlikely((CQE_WRID_MSN(*hw_cqe) != (wq->rq_rptr + 1)))) {
1248                         wq->error = 1;
1249                         hw_cqe->header |= htonl(V_CQE_STATUS(TPT_ERR_MSN));
1250                         goto proc_cqe;
1251                 }
1252                 goto proc_cqe;
1253         }
1254
1255         /*
1256          * If we get here its a send completion.
1257          *
1258          * Handle out of order completion. These get stuffed
1259          * in the SW SQ. Then the SW SQ is walked to move any
1260          * now in-order completions into the SW CQ.  This handles
1261          * 2 cases:
1262          *      1) reaping unsignaled WRs when the first subsequent
1263          *         signaled WR is completed.
1264          *      2) out of order read completions.
1265          */
1266         if (!SW_CQE(*hw_cqe) && (CQE_WRID_SQ_WPTR(*hw_cqe) != wq->sq_rptr)) {
1267                 struct t3_swsq *sqp;
1268
1269                 pr_debug("%s out of order completion going in swsq at idx %ld\n",
1270                          __func__,
1271                          Q_PTR2IDX(CQE_WRID_SQ_WPTR(*hw_cqe),
1272                                    wq->sq_size_log2));
1273                 sqp = wq->sq +
1274                       Q_PTR2IDX(CQE_WRID_SQ_WPTR(*hw_cqe), wq->sq_size_log2);
1275                 sqp->cqe = *hw_cqe;
1276                 sqp->complete = 1;
1277                 ret = -1;
1278                 goto flush_wq;
1279         }
1280
1281 proc_cqe:
1282         *cqe = *hw_cqe;
1283
1284         /*
1285          * Reap the associated WR(s) that are freed up with this
1286          * completion.
1287          */
1288         if (SQ_TYPE(*hw_cqe)) {
1289                 wq->sq_rptr = CQE_WRID_SQ_WPTR(*hw_cqe);
1290                 pr_debug("%s completing sq idx %ld\n", __func__,
1291                          Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2));
1292                 *cookie = wq->sq[Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2)].wr_id;
1293                 wq->sq_rptr++;
1294         } else {
1295                 pr_debug("%s completing rq idx %ld\n", __func__,
1296                          Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2));
1297                 *cookie = wq->rq[Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2)].wr_id;
1298                 if (wq->rq[Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2)].pbl_addr)
1299                         cxio_hal_pblpool_free(wq->rdev,
1300                                 wq->rq[Q_PTR2IDX(wq->rq_rptr,
1301                                 wq->rq_size_log2)].pbl_addr, T3_STAG0_PBL_SIZE);
1302                 BUG_ON(Q_EMPTY(wq->rq_rptr, wq->rq_wptr));
1303                 wq->rq_rptr++;
1304         }
1305
1306 flush_wq:
1307         /*
1308          * Flush any completed cqes that are now in-order.
1309          */
1310         flush_completed_wrs(wq, cq);
1311
1312 skip_cqe:
1313         if (SW_CQE(*hw_cqe)) {
1314                 pr_debug("%s cq %p cqid 0x%x skip sw cqe sw_rptr 0x%x\n",
1315                          __func__, cq, cq->cqid, cq->sw_rptr);
1316                 ++cq->sw_rptr;
1317         } else {
1318                 pr_debug("%s cq %p cqid 0x%x skip hw cqe rptr 0x%x\n",
1319                          __func__, cq, cq->cqid, cq->rptr);
1320                 ++cq->rptr;
1321
1322                 /*
1323                  * T3A: compute credits.
1324                  */
1325                 if (((cq->rptr - cq->wptr) > (1 << (cq->size_log2 - 1)))
1326                     || ((cq->rptr - cq->wptr) >= 128)) {
1327                         *credit = cq->rptr - cq->wptr;
1328                         cq->wptr = cq->rptr;
1329                 }
1330         }
1331         return ret;
1332 }