2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 #include <linux/module.h>
33 #include <linux/moduleparam.h>
34 #include <linux/debugfs.h>
35 #include <linux/vmalloc.h>
36 #include <linux/math64.h>
38 #include <rdma/ib_verbs.h>
42 #define DRV_VERSION "0.1"
44 MODULE_AUTHOR("Steve Wise");
45 MODULE_DESCRIPTION("Chelsio T4/T5 RDMA Driver");
46 MODULE_LICENSE("Dual BSD/GPL");
48 static int allow_db_fc_on_t5;
49 module_param(allow_db_fc_on_t5, int, 0644);
50 MODULE_PARM_DESC(allow_db_fc_on_t5,
51 "Allow DB Flow Control on T5 (default = 0)");
53 static int allow_db_coalescing_on_t5;
54 module_param(allow_db_coalescing_on_t5, int, 0644);
55 MODULE_PARM_DESC(allow_db_coalescing_on_t5,
56 "Allow DB Coalescing on T5 (default = 0)");
59 module_param(c4iw_wr_log, int, 0444);
60 MODULE_PARM_DESC(c4iw_wr_log, "Enables logging of work request timing data.");
62 static int c4iw_wr_log_size_order = 12;
63 module_param(c4iw_wr_log_size_order, int, 0444);
64 MODULE_PARM_DESC(c4iw_wr_log_size_order,
65 "Number of entries (log2) in the work request timing log.");
67 static LIST_HEAD(uld_ctx_list);
68 static DEFINE_MUTEX(dev_mutex);
69 static struct workqueue_struct *reg_workq;
71 #define DB_FC_RESUME_SIZE 64
72 #define DB_FC_RESUME_DELAY 1
73 #define DB_FC_DRAIN_THRESH 0
75 static struct dentry *c4iw_debugfs_root;
77 struct c4iw_debugfs_data {
78 struct c4iw_dev *devp;
84 static int count_idrs(int id, void *p, void *data)
88 *countp = *countp + 1;
92 static ssize_t debugfs_read(struct file *file, char __user *buf, size_t count,
95 struct c4iw_debugfs_data *d = file->private_data;
97 return simple_read_from_buffer(buf, count, ppos, d->buf, d->pos);
100 void c4iw_log_wr_stats(struct t4_wq *wq, struct t4_cqe *cqe)
102 struct wr_log_entry le;
105 if (!wq->rdev->wr_log)
108 idx = (atomic_inc_return(&wq->rdev->wr_log_idx) - 1) &
109 (wq->rdev->wr_log_size - 1);
110 le.poll_sge_ts = cxgb4_read_sge_timestamp(wq->rdev->lldi.ports[0]);
111 le.poll_host_time = ktime_get();
113 le.cqe_sge_ts = CQE_TS(cqe);
116 le.opcode = CQE_OPCODE(cqe);
117 le.post_host_time = wq->sq.sw_sq[wq->sq.cidx].host_time;
118 le.post_sge_ts = wq->sq.sw_sq[wq->sq.cidx].sge_ts;
119 le.wr_id = CQE_WRID_SQ_IDX(cqe);
122 le.opcode = FW_RI_RECEIVE;
123 le.post_host_time = wq->rq.sw_rq[wq->rq.cidx].host_time;
124 le.post_sge_ts = wq->rq.sw_rq[wq->rq.cidx].sge_ts;
125 le.wr_id = CQE_WRID_MSN(cqe);
127 wq->rdev->wr_log[idx] = le;
130 static int wr_log_show(struct seq_file *seq, void *v)
132 struct c4iw_dev *dev = seq->private;
134 struct wr_log_entry *lep;
135 int prev_time_set = 0;
138 #define ts2ns(ts) div64_u64((ts) * dev->rdev.lldi.cclk_ps, 1000)
140 idx = atomic_read(&dev->rdev.wr_log_idx) &
141 (dev->rdev.wr_log_size - 1);
144 end = dev->rdev.wr_log_size - 1;
145 lep = &dev->rdev.wr_log[idx];
148 if (!prev_time_set) {
150 prev_time = lep->poll_host_time;
152 seq_printf(seq, "%04u: nsec %llu qid %u opcode "
153 "%u %s 0x%x host_wr_delta nsec %llu "
154 "post_sge_ts 0x%llx cqe_sge_ts 0x%llx "
155 "poll_sge_ts 0x%llx post_poll_delta_ns %llu "
156 "cqe_poll_delta_ns %llu\n",
158 ktime_to_ns(ktime_sub(lep->poll_host_time,
160 lep->qid, lep->opcode,
161 lep->opcode == FW_RI_RECEIVE ?
164 ktime_to_ns(ktime_sub(lep->poll_host_time,
165 lep->post_host_time)),
166 lep->post_sge_ts, lep->cqe_sge_ts,
168 ts2ns(lep->poll_sge_ts - lep->post_sge_ts),
169 ts2ns(lep->poll_sge_ts - lep->cqe_sge_ts));
170 prev_time = lep->poll_host_time;
173 if (idx > (dev->rdev.wr_log_size - 1))
175 lep = &dev->rdev.wr_log[idx];
181 static int wr_log_open(struct inode *inode, struct file *file)
183 return single_open(file, wr_log_show, inode->i_private);
186 static ssize_t wr_log_clear(struct file *file, const char __user *buf,
187 size_t count, loff_t *pos)
189 struct c4iw_dev *dev = ((struct seq_file *)file->private_data)->private;
192 if (dev->rdev.wr_log)
193 for (i = 0; i < dev->rdev.wr_log_size; i++)
194 dev->rdev.wr_log[i].valid = 0;
198 static const struct file_operations wr_log_debugfs_fops = {
199 .owner = THIS_MODULE,
201 .release = single_release,
204 .write = wr_log_clear,
207 static struct sockaddr_in zero_sin = {
208 .sin_family = AF_INET,
211 static struct sockaddr_in6 zero_sin6 = {
212 .sin6_family = AF_INET6,
215 static void set_ep_sin_addrs(struct c4iw_ep *ep,
216 struct sockaddr_in **lsin,
217 struct sockaddr_in **rsin,
218 struct sockaddr_in **m_lsin,
219 struct sockaddr_in **m_rsin)
221 struct iw_cm_id *id = ep->com.cm_id;
223 *m_lsin = (struct sockaddr_in *)&ep->com.local_addr;
224 *m_rsin = (struct sockaddr_in *)&ep->com.remote_addr;
226 *lsin = (struct sockaddr_in *)&id->local_addr;
227 *rsin = (struct sockaddr_in *)&id->remote_addr;
234 static void set_ep_sin6_addrs(struct c4iw_ep *ep,
235 struct sockaddr_in6 **lsin6,
236 struct sockaddr_in6 **rsin6,
237 struct sockaddr_in6 **m_lsin6,
238 struct sockaddr_in6 **m_rsin6)
240 struct iw_cm_id *id = ep->com.cm_id;
242 *m_lsin6 = (struct sockaddr_in6 *)&ep->com.local_addr;
243 *m_rsin6 = (struct sockaddr_in6 *)&ep->com.remote_addr;
245 *lsin6 = (struct sockaddr_in6 *)&id->local_addr;
246 *rsin6 = (struct sockaddr_in6 *)&id->remote_addr;
253 static int dump_qp(int id, void *p, void *data)
255 struct c4iw_qp *qp = p;
256 struct c4iw_debugfs_data *qpd = data;
260 if (id != qp->wq.sq.qid)
263 space = qpd->bufsize - qpd->pos - 1;
268 struct c4iw_ep *ep = qp->ep;
270 if (ep->com.local_addr.ss_family == AF_INET) {
271 struct sockaddr_in *lsin;
272 struct sockaddr_in *rsin;
273 struct sockaddr_in *m_lsin;
274 struct sockaddr_in *m_rsin;
276 set_ep_sin_addrs(ep, &lsin, &rsin, &m_lsin, &m_rsin);
277 cc = snprintf(qpd->buf + qpd->pos, space,
278 "rc qp sq id %u %s id %u state %u "
279 "onchip %u ep tid %u state %u "
280 "%pI4:%u/%u->%pI4:%u/%u\n",
281 qp->wq.sq.qid, qp->srq ? "srq" : "rq",
282 qp->srq ? qp->srq->idx : qp->wq.rq.qid,
284 qp->wq.sq.flags & T4_SQ_ONCHIP,
285 ep->hwtid, (int)ep->com.state,
286 &lsin->sin_addr, ntohs(lsin->sin_port),
287 ntohs(m_lsin->sin_port),
288 &rsin->sin_addr, ntohs(rsin->sin_port),
289 ntohs(m_rsin->sin_port));
291 struct sockaddr_in6 *lsin6;
292 struct sockaddr_in6 *rsin6;
293 struct sockaddr_in6 *m_lsin6;
294 struct sockaddr_in6 *m_rsin6;
296 set_ep_sin6_addrs(ep, &lsin6, &rsin6, &m_lsin6,
298 cc = snprintf(qpd->buf + qpd->pos, space,
299 "rc qp sq id %u rq id %u state %u "
300 "onchip %u ep tid %u state %u "
301 "%pI6:%u/%u->%pI6:%u/%u\n",
302 qp->wq.sq.qid, qp->wq.rq.qid,
304 qp->wq.sq.flags & T4_SQ_ONCHIP,
305 ep->hwtid, (int)ep->com.state,
307 ntohs(lsin6->sin6_port),
308 ntohs(m_lsin6->sin6_port),
310 ntohs(rsin6->sin6_port),
311 ntohs(m_rsin6->sin6_port));
314 cc = snprintf(qpd->buf + qpd->pos, space,
315 "qp sq id %u rq id %u state %u onchip %u\n",
316 qp->wq.sq.qid, qp->wq.rq.qid,
318 qp->wq.sq.flags & T4_SQ_ONCHIP);
324 static int qp_release(struct inode *inode, struct file *file)
326 struct c4iw_debugfs_data *qpd = file->private_data;
328 pr_info("%s null qpd?\n", __func__);
336 static int qp_open(struct inode *inode, struct file *file)
338 struct c4iw_debugfs_data *qpd;
341 qpd = kmalloc(sizeof *qpd, GFP_KERNEL);
345 qpd->devp = inode->i_private;
348 spin_lock_irq(&qpd->devp->lock);
349 idr_for_each(&qpd->devp->qpidr, count_idrs, &count);
350 spin_unlock_irq(&qpd->devp->lock);
352 qpd->bufsize = count * 180;
353 qpd->buf = vmalloc(qpd->bufsize);
359 spin_lock_irq(&qpd->devp->lock);
360 idr_for_each(&qpd->devp->qpidr, dump_qp, qpd);
361 spin_unlock_irq(&qpd->devp->lock);
363 qpd->buf[qpd->pos++] = 0;
364 file->private_data = qpd;
368 static const struct file_operations qp_debugfs_fops = {
369 .owner = THIS_MODULE,
371 .release = qp_release,
372 .read = debugfs_read,
373 .llseek = default_llseek,
376 static int dump_stag(int id, void *p, void *data)
378 struct c4iw_debugfs_data *stagd = data;
381 struct fw_ri_tpte tpte;
384 space = stagd->bufsize - stagd->pos - 1;
388 ret = cxgb4_read_tpte(stagd->devp->rdev.lldi.ports[0], (u32)id<<8,
391 dev_err(&stagd->devp->rdev.lldi.pdev->dev,
392 "%s cxgb4_read_tpte err %d\n", __func__, ret);
395 cc = snprintf(stagd->buf + stagd->pos, space,
396 "stag: idx 0x%x valid %d key 0x%x state %d pdid %d "
397 "perm 0x%x ps %d len 0x%llx va 0x%llx\n",
399 FW_RI_TPTE_VALID_G(ntohl(tpte.valid_to_pdid)),
400 FW_RI_TPTE_STAGKEY_G(ntohl(tpte.valid_to_pdid)),
401 FW_RI_TPTE_STAGSTATE_G(ntohl(tpte.valid_to_pdid)),
402 FW_RI_TPTE_PDID_G(ntohl(tpte.valid_to_pdid)),
403 FW_RI_TPTE_PERM_G(ntohl(tpte.locread_to_qpid)),
404 FW_RI_TPTE_PS_G(ntohl(tpte.locread_to_qpid)),
405 ((u64)ntohl(tpte.len_hi) << 32) | ntohl(tpte.len_lo),
406 ((u64)ntohl(tpte.va_hi) << 32) | ntohl(tpte.va_lo_fbo));
412 static int stag_release(struct inode *inode, struct file *file)
414 struct c4iw_debugfs_data *stagd = file->private_data;
416 pr_info("%s null stagd?\n", __func__);
424 static int stag_open(struct inode *inode, struct file *file)
426 struct c4iw_debugfs_data *stagd;
430 stagd = kmalloc(sizeof *stagd, GFP_KERNEL);
435 stagd->devp = inode->i_private;
438 spin_lock_irq(&stagd->devp->lock);
439 idr_for_each(&stagd->devp->mmidr, count_idrs, &count);
440 spin_unlock_irq(&stagd->devp->lock);
442 stagd->bufsize = count * 256;
443 stagd->buf = vmalloc(stagd->bufsize);
449 spin_lock_irq(&stagd->devp->lock);
450 idr_for_each(&stagd->devp->mmidr, dump_stag, stagd);
451 spin_unlock_irq(&stagd->devp->lock);
453 stagd->buf[stagd->pos++] = 0;
454 file->private_data = stagd;
462 static const struct file_operations stag_debugfs_fops = {
463 .owner = THIS_MODULE,
465 .release = stag_release,
466 .read = debugfs_read,
467 .llseek = default_llseek,
470 static char *db_state_str[] = {"NORMAL", "FLOW_CONTROL", "RECOVERY", "STOPPED"};
472 static int stats_show(struct seq_file *seq, void *v)
474 struct c4iw_dev *dev = seq->private;
476 seq_printf(seq, " Object: %10s %10s %10s %10s\n", "Total", "Current",
478 seq_printf(seq, " PDID: %10llu %10llu %10llu %10llu\n",
479 dev->rdev.stats.pd.total, dev->rdev.stats.pd.cur,
480 dev->rdev.stats.pd.max, dev->rdev.stats.pd.fail);
481 seq_printf(seq, " QID: %10llu %10llu %10llu %10llu\n",
482 dev->rdev.stats.qid.total, dev->rdev.stats.qid.cur,
483 dev->rdev.stats.qid.max, dev->rdev.stats.qid.fail);
484 seq_printf(seq, " SRQS: %10llu %10llu %10llu %10llu\n",
485 dev->rdev.stats.srqt.total, dev->rdev.stats.srqt.cur,
486 dev->rdev.stats.srqt.max, dev->rdev.stats.srqt.fail);
487 seq_printf(seq, " TPTMEM: %10llu %10llu %10llu %10llu\n",
488 dev->rdev.stats.stag.total, dev->rdev.stats.stag.cur,
489 dev->rdev.stats.stag.max, dev->rdev.stats.stag.fail);
490 seq_printf(seq, " PBLMEM: %10llu %10llu %10llu %10llu\n",
491 dev->rdev.stats.pbl.total, dev->rdev.stats.pbl.cur,
492 dev->rdev.stats.pbl.max, dev->rdev.stats.pbl.fail);
493 seq_printf(seq, " RQTMEM: %10llu %10llu %10llu %10llu\n",
494 dev->rdev.stats.rqt.total, dev->rdev.stats.rqt.cur,
495 dev->rdev.stats.rqt.max, dev->rdev.stats.rqt.fail);
496 seq_printf(seq, " OCQPMEM: %10llu %10llu %10llu %10llu\n",
497 dev->rdev.stats.ocqp.total, dev->rdev.stats.ocqp.cur,
498 dev->rdev.stats.ocqp.max, dev->rdev.stats.ocqp.fail);
499 seq_printf(seq, " DB FULL: %10llu\n", dev->rdev.stats.db_full);
500 seq_printf(seq, " DB EMPTY: %10llu\n", dev->rdev.stats.db_empty);
501 seq_printf(seq, " DB DROP: %10llu\n", dev->rdev.stats.db_drop);
502 seq_printf(seq, " DB State: %s Transitions %llu FC Interruptions %llu\n",
503 db_state_str[dev->db_state],
504 dev->rdev.stats.db_state_transitions,
505 dev->rdev.stats.db_fc_interruptions);
506 seq_printf(seq, "TCAM_FULL: %10llu\n", dev->rdev.stats.tcam_full);
507 seq_printf(seq, "ACT_OFLD_CONN_FAILS: %10llu\n",
508 dev->rdev.stats.act_ofld_conn_fails);
509 seq_printf(seq, "PAS_OFLD_CONN_FAILS: %10llu\n",
510 dev->rdev.stats.pas_ofld_conn_fails);
511 seq_printf(seq, "NEG_ADV_RCVD: %10llu\n", dev->rdev.stats.neg_adv);
512 seq_printf(seq, "AVAILABLE IRD: %10u\n", dev->avail_ird);
516 static int stats_open(struct inode *inode, struct file *file)
518 return single_open(file, stats_show, inode->i_private);
521 static ssize_t stats_clear(struct file *file, const char __user *buf,
522 size_t count, loff_t *pos)
524 struct c4iw_dev *dev = ((struct seq_file *)file->private_data)->private;
526 mutex_lock(&dev->rdev.stats.lock);
527 dev->rdev.stats.pd.max = 0;
528 dev->rdev.stats.pd.fail = 0;
529 dev->rdev.stats.qid.max = 0;
530 dev->rdev.stats.qid.fail = 0;
531 dev->rdev.stats.stag.max = 0;
532 dev->rdev.stats.stag.fail = 0;
533 dev->rdev.stats.pbl.max = 0;
534 dev->rdev.stats.pbl.fail = 0;
535 dev->rdev.stats.rqt.max = 0;
536 dev->rdev.stats.rqt.fail = 0;
537 dev->rdev.stats.rqt.max = 0;
538 dev->rdev.stats.rqt.fail = 0;
539 dev->rdev.stats.ocqp.max = 0;
540 dev->rdev.stats.ocqp.fail = 0;
541 dev->rdev.stats.db_full = 0;
542 dev->rdev.stats.db_empty = 0;
543 dev->rdev.stats.db_drop = 0;
544 dev->rdev.stats.db_state_transitions = 0;
545 dev->rdev.stats.tcam_full = 0;
546 dev->rdev.stats.act_ofld_conn_fails = 0;
547 dev->rdev.stats.pas_ofld_conn_fails = 0;
548 mutex_unlock(&dev->rdev.stats.lock);
552 static const struct file_operations stats_debugfs_fops = {
553 .owner = THIS_MODULE,
555 .release = single_release,
558 .write = stats_clear,
561 static int dump_ep(int id, void *p, void *data)
563 struct c4iw_ep *ep = p;
564 struct c4iw_debugfs_data *epd = data;
568 space = epd->bufsize - epd->pos - 1;
572 if (ep->com.local_addr.ss_family == AF_INET) {
573 struct sockaddr_in *lsin;
574 struct sockaddr_in *rsin;
575 struct sockaddr_in *m_lsin;
576 struct sockaddr_in *m_rsin;
578 set_ep_sin_addrs(ep, &lsin, &rsin, &m_lsin, &m_rsin);
579 cc = snprintf(epd->buf + epd->pos, space,
580 "ep %p cm_id %p qp %p state %d flags 0x%lx "
581 "history 0x%lx hwtid %d atid %d "
582 "conn_na %u abort_na %u "
583 "%pI4:%d/%d <-> %pI4:%d/%d\n",
584 ep, ep->com.cm_id, ep->com.qp,
585 (int)ep->com.state, ep->com.flags,
586 ep->com.history, ep->hwtid, ep->atid,
587 ep->stats.connect_neg_adv,
588 ep->stats.abort_neg_adv,
589 &lsin->sin_addr, ntohs(lsin->sin_port),
590 ntohs(m_lsin->sin_port),
591 &rsin->sin_addr, ntohs(rsin->sin_port),
592 ntohs(m_rsin->sin_port));
594 struct sockaddr_in6 *lsin6;
595 struct sockaddr_in6 *rsin6;
596 struct sockaddr_in6 *m_lsin6;
597 struct sockaddr_in6 *m_rsin6;
599 set_ep_sin6_addrs(ep, &lsin6, &rsin6, &m_lsin6, &m_rsin6);
600 cc = snprintf(epd->buf + epd->pos, space,
601 "ep %p cm_id %p qp %p state %d flags 0x%lx "
602 "history 0x%lx hwtid %d atid %d "
603 "conn_na %u abort_na %u "
604 "%pI6:%d/%d <-> %pI6:%d/%d\n",
605 ep, ep->com.cm_id, ep->com.qp,
606 (int)ep->com.state, ep->com.flags,
607 ep->com.history, ep->hwtid, ep->atid,
608 ep->stats.connect_neg_adv,
609 ep->stats.abort_neg_adv,
610 &lsin6->sin6_addr, ntohs(lsin6->sin6_port),
611 ntohs(m_lsin6->sin6_port),
612 &rsin6->sin6_addr, ntohs(rsin6->sin6_port),
613 ntohs(m_rsin6->sin6_port));
620 static int dump_listen_ep(int id, void *p, void *data)
622 struct c4iw_listen_ep *ep = p;
623 struct c4iw_debugfs_data *epd = data;
627 space = epd->bufsize - epd->pos - 1;
631 if (ep->com.local_addr.ss_family == AF_INET) {
632 struct sockaddr_in *lsin = (struct sockaddr_in *)
633 &ep->com.cm_id->local_addr;
634 struct sockaddr_in *m_lsin = (struct sockaddr_in *)
635 &ep->com.cm_id->m_local_addr;
637 cc = snprintf(epd->buf + epd->pos, space,
638 "ep %p cm_id %p state %d flags 0x%lx stid %d "
639 "backlog %d %pI4:%d/%d\n",
640 ep, ep->com.cm_id, (int)ep->com.state,
641 ep->com.flags, ep->stid, ep->backlog,
642 &lsin->sin_addr, ntohs(lsin->sin_port),
643 ntohs(m_lsin->sin_port));
645 struct sockaddr_in6 *lsin6 = (struct sockaddr_in6 *)
646 &ep->com.cm_id->local_addr;
647 struct sockaddr_in6 *m_lsin6 = (struct sockaddr_in6 *)
648 &ep->com.cm_id->m_local_addr;
650 cc = snprintf(epd->buf + epd->pos, space,
651 "ep %p cm_id %p state %d flags 0x%lx stid %d "
652 "backlog %d %pI6:%d/%d\n",
653 ep, ep->com.cm_id, (int)ep->com.state,
654 ep->com.flags, ep->stid, ep->backlog,
655 &lsin6->sin6_addr, ntohs(lsin6->sin6_port),
656 ntohs(m_lsin6->sin6_port));
663 static int ep_release(struct inode *inode, struct file *file)
665 struct c4iw_debugfs_data *epd = file->private_data;
667 pr_info("%s null qpd?\n", __func__);
675 static int ep_open(struct inode *inode, struct file *file)
677 struct c4iw_debugfs_data *epd;
681 epd = kmalloc(sizeof(*epd), GFP_KERNEL);
686 epd->devp = inode->i_private;
689 spin_lock_irq(&epd->devp->lock);
690 idr_for_each(&epd->devp->hwtid_idr, count_idrs, &count);
691 idr_for_each(&epd->devp->atid_idr, count_idrs, &count);
692 idr_for_each(&epd->devp->stid_idr, count_idrs, &count);
693 spin_unlock_irq(&epd->devp->lock);
695 epd->bufsize = count * 240;
696 epd->buf = vmalloc(epd->bufsize);
702 spin_lock_irq(&epd->devp->lock);
703 idr_for_each(&epd->devp->hwtid_idr, dump_ep, epd);
704 idr_for_each(&epd->devp->atid_idr, dump_ep, epd);
705 idr_for_each(&epd->devp->stid_idr, dump_listen_ep, epd);
706 spin_unlock_irq(&epd->devp->lock);
708 file->private_data = epd;
716 static const struct file_operations ep_debugfs_fops = {
717 .owner = THIS_MODULE,
719 .release = ep_release,
720 .read = debugfs_read,
723 static int setup_debugfs(struct c4iw_dev *devp)
725 if (!devp->debugfs_root)
728 debugfs_create_file_size("qps", S_IWUSR, devp->debugfs_root,
729 (void *)devp, &qp_debugfs_fops, 4096);
731 debugfs_create_file_size("stags", S_IWUSR, devp->debugfs_root,
732 (void *)devp, &stag_debugfs_fops, 4096);
734 debugfs_create_file_size("stats", S_IWUSR, devp->debugfs_root,
735 (void *)devp, &stats_debugfs_fops, 4096);
737 debugfs_create_file_size("eps", S_IWUSR, devp->debugfs_root,
738 (void *)devp, &ep_debugfs_fops, 4096);
741 debugfs_create_file_size("wr_log", S_IWUSR, devp->debugfs_root,
742 (void *)devp, &wr_log_debugfs_fops, 4096);
746 void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
747 struct c4iw_dev_ucontext *uctx)
749 struct list_head *pos, *nxt;
750 struct c4iw_qid_list *entry;
752 mutex_lock(&uctx->lock);
753 list_for_each_safe(pos, nxt, &uctx->qpids) {
754 entry = list_entry(pos, struct c4iw_qid_list, entry);
755 list_del_init(&entry->entry);
756 if (!(entry->qid & rdev->qpmask)) {
757 c4iw_put_resource(&rdev->resource.qid_table,
759 mutex_lock(&rdev->stats.lock);
760 rdev->stats.qid.cur -= rdev->qpmask + 1;
761 mutex_unlock(&rdev->stats.lock);
766 list_for_each_safe(pos, nxt, &uctx->cqids) {
767 entry = list_entry(pos, struct c4iw_qid_list, entry);
768 list_del_init(&entry->entry);
771 mutex_unlock(&uctx->lock);
774 void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
775 struct c4iw_dev_ucontext *uctx)
777 INIT_LIST_HEAD(&uctx->qpids);
778 INIT_LIST_HEAD(&uctx->cqids);
779 mutex_init(&uctx->lock);
782 /* Caller takes care of locking if needed */
783 static int c4iw_rdev_open(struct c4iw_rdev *rdev)
787 c4iw_init_dev_ucontext(rdev, &rdev->uctx);
790 * This implementation assumes udb_density == ucq_density! Eventually
791 * we might need to support this but for now fail the open. Also the
792 * cqid and qpid range must match for now.
794 if (rdev->lldi.udb_density != rdev->lldi.ucq_density) {
795 pr_err("%s: unsupported udb/ucq densities %u/%u\n",
796 pci_name(rdev->lldi.pdev), rdev->lldi.udb_density,
797 rdev->lldi.ucq_density);
800 if (rdev->lldi.vr->qp.start != rdev->lldi.vr->cq.start ||
801 rdev->lldi.vr->qp.size != rdev->lldi.vr->cq.size) {
802 pr_err("%s: unsupported qp and cq id ranges qp start %u size %u cq start %u size %u\n",
803 pci_name(rdev->lldi.pdev), rdev->lldi.vr->qp.start,
804 rdev->lldi.vr->qp.size, rdev->lldi.vr->cq.size,
805 rdev->lldi.vr->cq.size);
809 rdev->qpmask = rdev->lldi.udb_density - 1;
810 rdev->cqmask = rdev->lldi.ucq_density - 1;
811 pr_debug("dev %s stag start 0x%0x size 0x%0x num stags %d pbl start 0x%0x size 0x%0x rq start 0x%0x size 0x%0x qp qid start %u size %u cq qid start %u size %u srq size %u\n",
812 pci_name(rdev->lldi.pdev), rdev->lldi.vr->stag.start,
813 rdev->lldi.vr->stag.size, c4iw_num_stags(rdev),
814 rdev->lldi.vr->pbl.start,
815 rdev->lldi.vr->pbl.size, rdev->lldi.vr->rq.start,
816 rdev->lldi.vr->rq.size,
817 rdev->lldi.vr->qp.start,
818 rdev->lldi.vr->qp.size,
819 rdev->lldi.vr->cq.start,
820 rdev->lldi.vr->cq.size,
821 rdev->lldi.vr->srq.size);
822 pr_debug("udb %pR db_reg %p gts_reg %p qpmask 0x%x cqmask 0x%x\n",
823 &rdev->lldi.pdev->resource[2],
824 rdev->lldi.db_reg, rdev->lldi.gts_reg,
825 rdev->qpmask, rdev->cqmask);
827 if (c4iw_num_stags(rdev) == 0)
830 rdev->stats.pd.total = T4_MAX_NUM_PD;
831 rdev->stats.stag.total = rdev->lldi.vr->stag.size;
832 rdev->stats.pbl.total = rdev->lldi.vr->pbl.size;
833 rdev->stats.rqt.total = rdev->lldi.vr->rq.size;
834 rdev->stats.srqt.total = rdev->lldi.vr->srq.size;
835 rdev->stats.ocqp.total = rdev->lldi.vr->ocq.size;
836 rdev->stats.qid.total = rdev->lldi.vr->qp.size;
838 err = c4iw_init_resource(rdev, c4iw_num_stags(rdev),
839 T4_MAX_NUM_PD, rdev->lldi.vr->srq.size);
841 pr_err("error %d initializing resources\n", err);
844 err = c4iw_pblpool_create(rdev);
846 pr_err("error %d initializing pbl pool\n", err);
847 goto destroy_resource;
849 err = c4iw_rqtpool_create(rdev);
851 pr_err("error %d initializing rqt pool\n", err);
852 goto destroy_pblpool;
854 err = c4iw_ocqp_pool_create(rdev);
856 pr_err("error %d initializing ocqp pool\n", err);
857 goto destroy_rqtpool;
859 rdev->status_page = (struct t4_dev_status_page *)
860 __get_free_page(GFP_KERNEL);
861 if (!rdev->status_page) {
863 goto destroy_ocqp_pool;
865 rdev->status_page->qp_start = rdev->lldi.vr->qp.start;
866 rdev->status_page->qp_size = rdev->lldi.vr->qp.size;
867 rdev->status_page->cq_start = rdev->lldi.vr->cq.start;
868 rdev->status_page->cq_size = rdev->lldi.vr->cq.size;
869 rdev->status_page->write_cmpl_supported = rdev->lldi.write_cmpl_support;
872 rdev->wr_log = kcalloc(1 << c4iw_wr_log_size_order,
873 sizeof(*rdev->wr_log),
876 rdev->wr_log_size = 1 << c4iw_wr_log_size_order;
877 atomic_set(&rdev->wr_log_idx, 0);
881 rdev->free_workq = create_singlethread_workqueue("iw_cxgb4_free");
882 if (!rdev->free_workq) {
884 goto err_free_status_page_and_wr_log;
887 rdev->status_page->db_off = 0;
889 init_completion(&rdev->rqt_compl);
890 init_completion(&rdev->pbl_compl);
891 kref_init(&rdev->rqt_kref);
892 kref_init(&rdev->pbl_kref);
895 err_free_status_page_and_wr_log:
896 if (c4iw_wr_log && rdev->wr_log)
898 free_page((unsigned long)rdev->status_page);
900 c4iw_ocqp_pool_destroy(rdev);
902 c4iw_rqtpool_destroy(rdev);
904 c4iw_pblpool_destroy(rdev);
906 c4iw_destroy_resource(&rdev->resource);
910 static void c4iw_rdev_close(struct c4iw_rdev *rdev)
913 c4iw_release_dev_ucontext(rdev, &rdev->uctx);
914 free_page((unsigned long)rdev->status_page);
915 c4iw_pblpool_destroy(rdev);
916 c4iw_rqtpool_destroy(rdev);
917 wait_for_completion(&rdev->pbl_compl);
918 wait_for_completion(&rdev->rqt_compl);
919 c4iw_ocqp_pool_destroy(rdev);
920 destroy_workqueue(rdev->free_workq);
921 c4iw_destroy_resource(&rdev->resource);
924 void c4iw_dealloc(struct uld_ctx *ctx)
926 c4iw_rdev_close(&ctx->dev->rdev);
927 WARN_ON_ONCE(!idr_is_empty(&ctx->dev->cqidr));
928 idr_destroy(&ctx->dev->cqidr);
929 WARN_ON_ONCE(!idr_is_empty(&ctx->dev->qpidr));
930 idr_destroy(&ctx->dev->qpidr);
931 WARN_ON_ONCE(!idr_is_empty(&ctx->dev->mmidr));
932 idr_destroy(&ctx->dev->mmidr);
933 wait_event(ctx->dev->wait, idr_is_empty(&ctx->dev->hwtid_idr));
934 idr_destroy(&ctx->dev->hwtid_idr);
935 idr_destroy(&ctx->dev->stid_idr);
936 idr_destroy(&ctx->dev->atid_idr);
937 if (ctx->dev->rdev.bar2_kva)
938 iounmap(ctx->dev->rdev.bar2_kva);
939 if (ctx->dev->rdev.oc_mw_kva)
940 iounmap(ctx->dev->rdev.oc_mw_kva);
941 ib_dealloc_device(&ctx->dev->ibdev);
945 static void c4iw_remove(struct uld_ctx *ctx)
947 pr_debug("c4iw_dev %p\n", ctx->dev);
948 debugfs_remove_recursive(ctx->dev->debugfs_root);
949 c4iw_unregister_device(ctx->dev);
953 static int rdma_supported(const struct cxgb4_lld_info *infop)
955 return infop->vr->stag.size > 0 && infop->vr->pbl.size > 0 &&
956 infop->vr->rq.size > 0 && infop->vr->qp.size > 0 &&
957 infop->vr->cq.size > 0;
960 static struct c4iw_dev *c4iw_alloc(const struct cxgb4_lld_info *infop)
962 struct c4iw_dev *devp;
965 if (!rdma_supported(infop)) {
966 pr_info("%s: RDMA not supported on this device\n",
967 pci_name(infop->pdev));
968 return ERR_PTR(-ENOSYS);
970 if (!ocqp_supported(infop))
971 pr_info("%s: On-Chip Queues not supported on this device\n",
972 pci_name(infop->pdev));
974 devp = (struct c4iw_dev *)ib_alloc_device(sizeof(*devp));
976 pr_err("Cannot allocate ib device\n");
977 return ERR_PTR(-ENOMEM);
979 devp->rdev.lldi = *infop;
981 /* init various hw-queue params based on lld info */
982 pr_debug("Ing. padding boundary is %d, egrsstatuspagesize = %d\n",
983 devp->rdev.lldi.sge_ingpadboundary,
984 devp->rdev.lldi.sge_egrstatuspagesize);
986 devp->rdev.hw_queue.t4_eq_status_entries =
987 devp->rdev.lldi.sge_egrstatuspagesize / 64;
988 devp->rdev.hw_queue.t4_max_eq_size = 65520;
989 devp->rdev.hw_queue.t4_max_iq_size = 65520;
990 devp->rdev.hw_queue.t4_max_rq_size = 8192 -
991 devp->rdev.hw_queue.t4_eq_status_entries - 1;
992 devp->rdev.hw_queue.t4_max_sq_size =
993 devp->rdev.hw_queue.t4_max_eq_size -
994 devp->rdev.hw_queue.t4_eq_status_entries - 1;
995 devp->rdev.hw_queue.t4_max_qp_depth =
996 devp->rdev.hw_queue.t4_max_rq_size;
997 devp->rdev.hw_queue.t4_max_cq_depth =
998 devp->rdev.hw_queue.t4_max_iq_size - 2;
999 devp->rdev.hw_queue.t4_stat_len =
1000 devp->rdev.lldi.sge_egrstatuspagesize;
1003 * For T5/T6 devices, we map all of BAR2 with WC.
1004 * For T4 devices with onchip qp mem, we map only that part
1007 devp->rdev.bar2_pa = pci_resource_start(devp->rdev.lldi.pdev, 2);
1008 if (!is_t4(devp->rdev.lldi.adapter_type)) {
1009 devp->rdev.bar2_kva = ioremap_wc(devp->rdev.bar2_pa,
1010 pci_resource_len(devp->rdev.lldi.pdev, 2));
1011 if (!devp->rdev.bar2_kva) {
1012 pr_err("Unable to ioremap BAR2\n");
1013 ib_dealloc_device(&devp->ibdev);
1014 return ERR_PTR(-EINVAL);
1016 } else if (ocqp_supported(infop)) {
1017 devp->rdev.oc_mw_pa =
1018 pci_resource_start(devp->rdev.lldi.pdev, 2) +
1019 pci_resource_len(devp->rdev.lldi.pdev, 2) -
1020 roundup_pow_of_two(devp->rdev.lldi.vr->ocq.size);
1021 devp->rdev.oc_mw_kva = ioremap_wc(devp->rdev.oc_mw_pa,
1022 devp->rdev.lldi.vr->ocq.size);
1023 if (!devp->rdev.oc_mw_kva) {
1024 pr_err("Unable to ioremap onchip mem\n");
1025 ib_dealloc_device(&devp->ibdev);
1026 return ERR_PTR(-EINVAL);
1030 pr_debug("ocq memory: hw_start 0x%x size %u mw_pa 0x%lx mw_kva %p\n",
1031 devp->rdev.lldi.vr->ocq.start, devp->rdev.lldi.vr->ocq.size,
1032 devp->rdev.oc_mw_pa, devp->rdev.oc_mw_kva);
1034 ret = c4iw_rdev_open(&devp->rdev);
1036 pr_err("Unable to open CXIO rdev err %d\n", ret);
1037 ib_dealloc_device(&devp->ibdev);
1038 return ERR_PTR(ret);
1041 idr_init(&devp->cqidr);
1042 idr_init(&devp->qpidr);
1043 idr_init(&devp->mmidr);
1044 idr_init(&devp->hwtid_idr);
1045 idr_init(&devp->stid_idr);
1046 idr_init(&devp->atid_idr);
1047 spin_lock_init(&devp->lock);
1048 mutex_init(&devp->rdev.stats.lock);
1049 mutex_init(&devp->db_mutex);
1050 INIT_LIST_HEAD(&devp->db_fc_list);
1051 init_waitqueue_head(&devp->wait);
1052 devp->avail_ird = devp->rdev.lldi.max_ird_adapter;
1054 if (c4iw_debugfs_root) {
1055 devp->debugfs_root = debugfs_create_dir(
1056 pci_name(devp->rdev.lldi.pdev),
1058 setup_debugfs(devp);
1065 static void *c4iw_uld_add(const struct cxgb4_lld_info *infop)
1067 struct uld_ctx *ctx;
1068 static int vers_printed;
1071 if (!vers_printed++)
1072 pr_info("Chelsio T4/T5 RDMA Driver - version %s\n",
1075 ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
1077 ctx = ERR_PTR(-ENOMEM);
1082 pr_debug("found device %s nchan %u nrxq %u ntxq %u nports %u\n",
1083 pci_name(ctx->lldi.pdev),
1084 ctx->lldi.nchan, ctx->lldi.nrxq,
1085 ctx->lldi.ntxq, ctx->lldi.nports);
1087 mutex_lock(&dev_mutex);
1088 list_add_tail(&ctx->entry, &uld_ctx_list);
1089 mutex_unlock(&dev_mutex);
1091 for (i = 0; i < ctx->lldi.nrxq; i++)
1092 pr_debug("rxqid[%u] %u\n", i, ctx->lldi.rxq_ids[i]);
1097 static inline struct sk_buff *copy_gl_to_skb_pkt(const struct pkt_gl *gl,
1101 struct sk_buff *skb;
1104 * Allocate space for cpl_pass_accept_req which will be synthesized by
1105 * driver. Once the driver synthesizes the request the skb will go
1106 * through the regular cpl_pass_accept_req processing.
1107 * The math here assumes sizeof cpl_pass_accept_req >= sizeof
1110 skb = alloc_skb(gl->tot_len + sizeof(struct cpl_pass_accept_req) +
1111 sizeof(struct rss_header) - pktshift, GFP_ATOMIC);
1115 __skb_put(skb, gl->tot_len + sizeof(struct cpl_pass_accept_req) +
1116 sizeof(struct rss_header) - pktshift);
1119 * This skb will contain:
1120 * rss_header from the rspq descriptor (1 flit)
1121 * cpl_rx_pkt struct from the rspq descriptor (2 flits)
1122 * space for the difference between the size of an
1123 * rx_pkt and pass_accept_req cpl (1 flit)
1124 * the packet data from the gl
1126 skb_copy_to_linear_data(skb, rsp, sizeof(struct cpl_pass_accept_req) +
1127 sizeof(struct rss_header));
1128 skb_copy_to_linear_data_offset(skb, sizeof(struct rss_header) +
1129 sizeof(struct cpl_pass_accept_req),
1131 gl->tot_len - pktshift);
1135 static inline int recv_rx_pkt(struct c4iw_dev *dev, const struct pkt_gl *gl,
1138 unsigned int opcode = *(u8 *)rsp;
1139 struct sk_buff *skb;
1141 if (opcode != CPL_RX_PKT)
1144 skb = copy_gl_to_skb_pkt(gl , rsp, dev->rdev.lldi.sge_pktshift);
1148 if (c4iw_handlers[opcode] == NULL) {
1149 pr_info("%s no handler opcode 0x%x...\n", __func__, opcode);
1153 c4iw_handlers[opcode](dev, skb);
1159 static int c4iw_uld_rx_handler(void *handle, const __be64 *rsp,
1160 const struct pkt_gl *gl)
1162 struct uld_ctx *ctx = handle;
1163 struct c4iw_dev *dev = ctx->dev;
1164 struct sk_buff *skb;
1168 /* omit RSS and rsp_ctrl at end of descriptor */
1169 unsigned int len = 64 - sizeof(struct rsp_ctrl) - 8;
1171 skb = alloc_skb(256, GFP_ATOMIC);
1174 __skb_put(skb, len);
1175 skb_copy_to_linear_data(skb, &rsp[1], len);
1176 } else if (gl == CXGB4_MSG_AN) {
1177 const struct rsp_ctrl *rc = (void *)rsp;
1179 u32 qid = be32_to_cpu(rc->pldbuflen_qid);
1180 c4iw_ev_handler(dev, qid);
1182 } else if (unlikely(*(u8 *)rsp != *(u8 *)gl->va)) {
1183 if (recv_rx_pkt(dev, gl, rsp))
1186 pr_info("%s: unexpected FL contents at %p, RSS %#llx, FL %#llx, len %u\n",
1187 pci_name(ctx->lldi.pdev), gl->va,
1189 be64_to_cpu(*(__force __be64 *)gl->va),
1194 skb = cxgb4_pktgl_to_skb(gl, 128, 128);
1199 opcode = *(u8 *)rsp;
1200 if (c4iw_handlers[opcode]) {
1201 c4iw_handlers[opcode](dev, skb);
1203 pr_info("%s no handler opcode 0x%x...\n", __func__, opcode);
1212 static int c4iw_uld_state_change(void *handle, enum cxgb4_state new_state)
1214 struct uld_ctx *ctx = handle;
1216 pr_debug("new_state %u\n", new_state);
1217 switch (new_state) {
1218 case CXGB4_STATE_UP:
1219 pr_info("%s: Up\n", pci_name(ctx->lldi.pdev));
1221 ctx->dev = c4iw_alloc(&ctx->lldi);
1222 if (IS_ERR(ctx->dev)) {
1223 pr_err("%s: initialization failed: %ld\n",
1224 pci_name(ctx->lldi.pdev),
1230 INIT_WORK(&ctx->reg_work, c4iw_register_device);
1231 queue_work(reg_workq, &ctx->reg_work);
1234 case CXGB4_STATE_DOWN:
1235 pr_info("%s: Down\n", pci_name(ctx->lldi.pdev));
1239 case CXGB4_STATE_FATAL_ERROR:
1240 case CXGB4_STATE_START_RECOVERY:
1241 pr_info("%s: Fatal Error\n", pci_name(ctx->lldi.pdev));
1243 struct ib_event event;
1245 ctx->dev->rdev.flags |= T4_FATAL_ERROR;
1246 memset(&event, 0, sizeof event);
1247 event.event = IB_EVENT_DEVICE_FATAL;
1248 event.device = &ctx->dev->ibdev;
1249 ib_dispatch_event(&event);
1253 case CXGB4_STATE_DETACH:
1254 pr_info("%s: Detach\n", pci_name(ctx->lldi.pdev));
1262 static int disable_qp_db(int id, void *p, void *data)
1264 struct c4iw_qp *qp = p;
1266 t4_disable_wq_db(&qp->wq);
1270 static void stop_queues(struct uld_ctx *ctx)
1272 unsigned long flags;
1274 spin_lock_irqsave(&ctx->dev->lock, flags);
1275 ctx->dev->rdev.stats.db_state_transitions++;
1276 ctx->dev->db_state = STOPPED;
1277 if (ctx->dev->rdev.flags & T4_STATUS_PAGE_DISABLED)
1278 idr_for_each(&ctx->dev->qpidr, disable_qp_db, NULL);
1280 ctx->dev->rdev.status_page->db_off = 1;
1281 spin_unlock_irqrestore(&ctx->dev->lock, flags);
1284 static int enable_qp_db(int id, void *p, void *data)
1286 struct c4iw_qp *qp = p;
1288 t4_enable_wq_db(&qp->wq);
1292 static void resume_rc_qp(struct c4iw_qp *qp)
1294 spin_lock(&qp->lock);
1295 t4_ring_sq_db(&qp->wq, qp->wq.sq.wq_pidx_inc, NULL);
1296 qp->wq.sq.wq_pidx_inc = 0;
1297 t4_ring_rq_db(&qp->wq, qp->wq.rq.wq_pidx_inc, NULL);
1298 qp->wq.rq.wq_pidx_inc = 0;
1299 spin_unlock(&qp->lock);
1302 static void resume_a_chunk(struct uld_ctx *ctx)
1307 for (i = 0; i < DB_FC_RESUME_SIZE; i++) {
1308 qp = list_first_entry(&ctx->dev->db_fc_list, struct c4iw_qp,
1310 list_del_init(&qp->db_fc_entry);
1312 if (list_empty(&ctx->dev->db_fc_list))
1317 static void resume_queues(struct uld_ctx *ctx)
1319 spin_lock_irq(&ctx->dev->lock);
1320 if (ctx->dev->db_state != STOPPED)
1322 ctx->dev->db_state = FLOW_CONTROL;
1324 if (list_empty(&ctx->dev->db_fc_list)) {
1325 WARN_ON(ctx->dev->db_state != FLOW_CONTROL);
1326 ctx->dev->db_state = NORMAL;
1327 ctx->dev->rdev.stats.db_state_transitions++;
1328 if (ctx->dev->rdev.flags & T4_STATUS_PAGE_DISABLED) {
1329 idr_for_each(&ctx->dev->qpidr, enable_qp_db,
1332 ctx->dev->rdev.status_page->db_off = 0;
1336 if (cxgb4_dbfifo_count(ctx->dev->rdev.lldi.ports[0], 1)
1337 < (ctx->dev->rdev.lldi.dbfifo_int_thresh <<
1338 DB_FC_DRAIN_THRESH)) {
1339 resume_a_chunk(ctx);
1341 if (!list_empty(&ctx->dev->db_fc_list)) {
1342 spin_unlock_irq(&ctx->dev->lock);
1343 if (DB_FC_RESUME_DELAY) {
1344 set_current_state(TASK_UNINTERRUPTIBLE);
1345 schedule_timeout(DB_FC_RESUME_DELAY);
1347 spin_lock_irq(&ctx->dev->lock);
1348 if (ctx->dev->db_state != FLOW_CONTROL)
1354 if (ctx->dev->db_state != NORMAL)
1355 ctx->dev->rdev.stats.db_fc_interruptions++;
1356 spin_unlock_irq(&ctx->dev->lock);
1361 struct c4iw_qp **qps;
1364 static int add_and_ref_qp(int id, void *p, void *data)
1366 struct qp_list *qp_listp = data;
1367 struct c4iw_qp *qp = p;
1369 c4iw_qp_add_ref(&qp->ibqp);
1370 qp_listp->qps[qp_listp->idx++] = qp;
1374 static int count_qps(int id, void *p, void *data)
1376 unsigned *countp = data;
1381 static void deref_qps(struct qp_list *qp_list)
1385 for (idx = 0; idx < qp_list->idx; idx++)
1386 c4iw_qp_rem_ref(&qp_list->qps[idx]->ibqp);
1389 static void recover_lost_dbs(struct uld_ctx *ctx, struct qp_list *qp_list)
1394 for (idx = 0; idx < qp_list->idx; idx++) {
1395 struct c4iw_qp *qp = qp_list->qps[idx];
1397 spin_lock_irq(&qp->rhp->lock);
1398 spin_lock(&qp->lock);
1399 ret = cxgb4_sync_txq_pidx(qp->rhp->rdev.lldi.ports[0],
1401 t4_sq_host_wq_pidx(&qp->wq),
1402 t4_sq_wq_size(&qp->wq));
1404 pr_err("%s: Fatal error - DB overflow recovery failed - error syncing SQ qid %u\n",
1405 pci_name(ctx->lldi.pdev), qp->wq.sq.qid);
1406 spin_unlock(&qp->lock);
1407 spin_unlock_irq(&qp->rhp->lock);
1410 qp->wq.sq.wq_pidx_inc = 0;
1412 ret = cxgb4_sync_txq_pidx(qp->rhp->rdev.lldi.ports[0],
1414 t4_rq_host_wq_pidx(&qp->wq),
1415 t4_rq_wq_size(&qp->wq));
1418 pr_err("%s: Fatal error - DB overflow recovery failed - error syncing RQ qid %u\n",
1419 pci_name(ctx->lldi.pdev), qp->wq.rq.qid);
1420 spin_unlock(&qp->lock);
1421 spin_unlock_irq(&qp->rhp->lock);
1424 qp->wq.rq.wq_pidx_inc = 0;
1425 spin_unlock(&qp->lock);
1426 spin_unlock_irq(&qp->rhp->lock);
1428 /* Wait for the dbfifo to drain */
1429 while (cxgb4_dbfifo_count(qp->rhp->rdev.lldi.ports[0], 1) > 0) {
1430 set_current_state(TASK_UNINTERRUPTIBLE);
1431 schedule_timeout(usecs_to_jiffies(10));
1436 static void recover_queues(struct uld_ctx *ctx)
1439 struct qp_list qp_list;
1442 /* slow everybody down */
1443 set_current_state(TASK_UNINTERRUPTIBLE);
1444 schedule_timeout(usecs_to_jiffies(1000));
1446 /* flush the SGE contexts */
1447 ret = cxgb4_flush_eq_cache(ctx->dev->rdev.lldi.ports[0]);
1449 pr_err("%s: Fatal error - DB overflow recovery failed\n",
1450 pci_name(ctx->lldi.pdev));
1454 /* Count active queues so we can build a list of queues to recover */
1455 spin_lock_irq(&ctx->dev->lock);
1456 WARN_ON(ctx->dev->db_state != STOPPED);
1457 ctx->dev->db_state = RECOVERY;
1458 idr_for_each(&ctx->dev->qpidr, count_qps, &count);
1460 qp_list.qps = kcalloc(count, sizeof(*qp_list.qps), GFP_ATOMIC);
1462 spin_unlock_irq(&ctx->dev->lock);
1467 /* add and ref each qp so it doesn't get freed */
1468 idr_for_each(&ctx->dev->qpidr, add_and_ref_qp, &qp_list);
1470 spin_unlock_irq(&ctx->dev->lock);
1472 /* now traverse the list in a safe context to recover the db state*/
1473 recover_lost_dbs(ctx, &qp_list);
1475 /* we're almost done! deref the qps and clean up */
1476 deref_qps(&qp_list);
1479 spin_lock_irq(&ctx->dev->lock);
1480 WARN_ON(ctx->dev->db_state != RECOVERY);
1481 ctx->dev->db_state = STOPPED;
1482 spin_unlock_irq(&ctx->dev->lock);
1485 static int c4iw_uld_control(void *handle, enum cxgb4_control control, ...)
1487 struct uld_ctx *ctx = handle;
1490 case CXGB4_CONTROL_DB_FULL:
1492 ctx->dev->rdev.stats.db_full++;
1494 case CXGB4_CONTROL_DB_EMPTY:
1496 mutex_lock(&ctx->dev->rdev.stats.lock);
1497 ctx->dev->rdev.stats.db_empty++;
1498 mutex_unlock(&ctx->dev->rdev.stats.lock);
1500 case CXGB4_CONTROL_DB_DROP:
1501 recover_queues(ctx);
1502 mutex_lock(&ctx->dev->rdev.stats.lock);
1503 ctx->dev->rdev.stats.db_drop++;
1504 mutex_unlock(&ctx->dev->rdev.stats.lock);
1507 pr_warn("%s: unknown control cmd %u\n",
1508 pci_name(ctx->lldi.pdev), control);
1514 static struct cxgb4_uld_info c4iw_uld_info = {
1516 .nrxq = MAX_ULD_QSETS,
1517 .ntxq = MAX_ULD_QSETS,
1521 .add = c4iw_uld_add,
1522 .rx_handler = c4iw_uld_rx_handler,
1523 .state_change = c4iw_uld_state_change,
1524 .control = c4iw_uld_control,
1527 void _c4iw_free_wr_wait(struct kref *kref)
1529 struct c4iw_wr_wait *wr_waitp;
1531 wr_waitp = container_of(kref, struct c4iw_wr_wait, kref);
1532 pr_debug("Free wr_wait %p\n", wr_waitp);
1536 struct c4iw_wr_wait *c4iw_alloc_wr_wait(gfp_t gfp)
1538 struct c4iw_wr_wait *wr_waitp;
1540 wr_waitp = kzalloc(sizeof(*wr_waitp), gfp);
1542 kref_init(&wr_waitp->kref);
1543 pr_debug("wr_wait %p\n", wr_waitp);
1548 static int __init c4iw_init_module(void)
1552 err = c4iw_cm_init();
1556 c4iw_debugfs_root = debugfs_create_dir(DRV_NAME, NULL);
1557 if (!c4iw_debugfs_root)
1558 pr_warn("could not create debugfs entry, continuing\n");
1560 reg_workq = create_singlethread_workqueue("Register_iWARP_device");
1562 pr_err("Failed creating workqueue to register iwarp device\n");
1566 cxgb4_register_uld(CXGB4_ULD_RDMA, &c4iw_uld_info);
1571 static void __exit c4iw_exit_module(void)
1573 struct uld_ctx *ctx, *tmp;
1575 mutex_lock(&dev_mutex);
1576 list_for_each_entry_safe(ctx, tmp, &uld_ctx_list, entry) {
1581 mutex_unlock(&dev_mutex);
1582 flush_workqueue(reg_workq);
1583 destroy_workqueue(reg_workq);
1584 cxgb4_unregister_uld(CXGB4_ULD_RDMA);
1586 debugfs_remove_recursive(c4iw_debugfs_root);
1589 module_init(c4iw_init_module);
1590 module_exit(c4iw_exit_module);