2 * Copyright(c) 2015 - 2018 Intel Corporation.
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
24 * - Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
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34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48 #include <linux/spinlock.h>
49 #include <linux/seqlock.h>
50 #include <linux/netdevice.h>
51 #include <linux/moduleparam.h>
52 #include <linux/bitops.h>
53 #include <linux/timer.h>
54 #include <linux/vmalloc.h>
55 #include <linux/highmem.h>
64 /* must be a power of 2 >= 64 <= 32768 */
65 #define SDMA_DESCQ_CNT 2048
66 #define SDMA_DESC_INTR 64
67 #define INVALID_TAIL 0xffff
68 #define SDMA_PAD max_t(size_t, MAX_16B_PADDING, sizeof(u32))
70 static uint sdma_descq_cnt = SDMA_DESCQ_CNT;
71 module_param(sdma_descq_cnt, uint, S_IRUGO);
72 MODULE_PARM_DESC(sdma_descq_cnt, "Number of SDMA descq entries");
74 static uint sdma_idle_cnt = 250;
75 module_param(sdma_idle_cnt, uint, S_IRUGO);
76 MODULE_PARM_DESC(sdma_idle_cnt, "sdma interrupt idle delay (ns,default 250)");
79 module_param_named(num_sdma, mod_num_sdma, uint, S_IRUGO);
80 MODULE_PARM_DESC(num_sdma, "Set max number SDMA engines to use");
82 static uint sdma_desct_intr = SDMA_DESC_INTR;
83 module_param_named(desct_intr, sdma_desct_intr, uint, S_IRUGO | S_IWUSR);
84 MODULE_PARM_DESC(desct_intr, "Number of SDMA descriptor before interrupt");
86 #define SDMA_WAIT_BATCH_SIZE 20
87 /* max wait time for a SDMA engine to indicate it has halted */
88 #define SDMA_ERR_HALT_TIMEOUT 10 /* ms */
89 /* all SDMA engine errors that cause a halt */
91 #define SD(name) SEND_DMA_##name
92 #define ALL_SDMA_ENG_HALT_ERRS \
93 (SD(ENG_ERR_STATUS_SDMA_WRONG_DW_ERR_SMASK) \
94 | SD(ENG_ERR_STATUS_SDMA_GEN_MISMATCH_ERR_SMASK) \
95 | SD(ENG_ERR_STATUS_SDMA_TOO_LONG_ERR_SMASK) \
96 | SD(ENG_ERR_STATUS_SDMA_TAIL_OUT_OF_BOUNDS_ERR_SMASK) \
97 | SD(ENG_ERR_STATUS_SDMA_FIRST_DESC_ERR_SMASK) \
98 | SD(ENG_ERR_STATUS_SDMA_MEM_READ_ERR_SMASK) \
99 | SD(ENG_ERR_STATUS_SDMA_HALT_ERR_SMASK) \
100 | SD(ENG_ERR_STATUS_SDMA_LENGTH_MISMATCH_ERR_SMASK) \
101 | SD(ENG_ERR_STATUS_SDMA_PACKET_DESC_OVERFLOW_ERR_SMASK) \
102 | SD(ENG_ERR_STATUS_SDMA_HEADER_SELECT_ERR_SMASK) \
103 | SD(ENG_ERR_STATUS_SDMA_HEADER_ADDRESS_ERR_SMASK) \
104 | SD(ENG_ERR_STATUS_SDMA_HEADER_LENGTH_ERR_SMASK) \
105 | SD(ENG_ERR_STATUS_SDMA_TIMEOUT_ERR_SMASK) \
106 | SD(ENG_ERR_STATUS_SDMA_DESC_TABLE_UNC_ERR_SMASK) \
107 | SD(ENG_ERR_STATUS_SDMA_ASSEMBLY_UNC_ERR_SMASK) \
108 | SD(ENG_ERR_STATUS_SDMA_PACKET_TRACKING_UNC_ERR_SMASK) \
109 | SD(ENG_ERR_STATUS_SDMA_HEADER_STORAGE_UNC_ERR_SMASK) \
110 | SD(ENG_ERR_STATUS_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_SMASK))
112 /* sdma_sendctrl operations */
113 #define SDMA_SENDCTRL_OP_ENABLE BIT(0)
114 #define SDMA_SENDCTRL_OP_INTENABLE BIT(1)
115 #define SDMA_SENDCTRL_OP_HALT BIT(2)
116 #define SDMA_SENDCTRL_OP_CLEANUP BIT(3)
118 /* handle long defines */
119 #define SDMA_EGRESS_PACKET_OCCUPANCY_SMASK \
120 SEND_EGRESS_SEND_DMA_STATUS_SDMA_EGRESS_PACKET_OCCUPANCY_SMASK
121 #define SDMA_EGRESS_PACKET_OCCUPANCY_SHIFT \
122 SEND_EGRESS_SEND_DMA_STATUS_SDMA_EGRESS_PACKET_OCCUPANCY_SHIFT
124 static const char * const sdma_state_names[] = {
125 [sdma_state_s00_hw_down] = "s00_HwDown",
126 [sdma_state_s10_hw_start_up_halt_wait] = "s10_HwStartUpHaltWait",
127 [sdma_state_s15_hw_start_up_clean_wait] = "s15_HwStartUpCleanWait",
128 [sdma_state_s20_idle] = "s20_Idle",
129 [sdma_state_s30_sw_clean_up_wait] = "s30_SwCleanUpWait",
130 [sdma_state_s40_hw_clean_up_wait] = "s40_HwCleanUpWait",
131 [sdma_state_s50_hw_halt_wait] = "s50_HwHaltWait",
132 [sdma_state_s60_idle_halt_wait] = "s60_IdleHaltWait",
133 [sdma_state_s80_hw_freeze] = "s80_HwFreeze",
134 [sdma_state_s82_freeze_sw_clean] = "s82_FreezeSwClean",
135 [sdma_state_s99_running] = "s99_Running",
138 #ifdef CONFIG_SDMA_VERBOSITY
139 static const char * const sdma_event_names[] = {
140 [sdma_event_e00_go_hw_down] = "e00_GoHwDown",
141 [sdma_event_e10_go_hw_start] = "e10_GoHwStart",
142 [sdma_event_e15_hw_halt_done] = "e15_HwHaltDone",
143 [sdma_event_e25_hw_clean_up_done] = "e25_HwCleanUpDone",
144 [sdma_event_e30_go_running] = "e30_GoRunning",
145 [sdma_event_e40_sw_cleaned] = "e40_SwCleaned",
146 [sdma_event_e50_hw_cleaned] = "e50_HwCleaned",
147 [sdma_event_e60_hw_halted] = "e60_HwHalted",
148 [sdma_event_e70_go_idle] = "e70_GoIdle",
149 [sdma_event_e80_hw_freeze] = "e80_HwFreeze",
150 [sdma_event_e81_hw_frozen] = "e81_HwFrozen",
151 [sdma_event_e82_hw_unfreeze] = "e82_HwUnfreeze",
152 [sdma_event_e85_link_down] = "e85_LinkDown",
153 [sdma_event_e90_sw_halted] = "e90_SwHalted",
157 static const struct sdma_set_state_action sdma_action_table[] = {
158 [sdma_state_s00_hw_down] = {
159 .go_s99_running_tofalse = 1,
165 [sdma_state_s10_hw_start_up_halt_wait] = {
171 [sdma_state_s15_hw_start_up_clean_wait] = {
177 [sdma_state_s20_idle] = {
183 [sdma_state_s30_sw_clean_up_wait] = {
189 [sdma_state_s40_hw_clean_up_wait] = {
195 [sdma_state_s50_hw_halt_wait] = {
201 [sdma_state_s60_idle_halt_wait] = {
202 .go_s99_running_tofalse = 1,
208 [sdma_state_s80_hw_freeze] = {
214 [sdma_state_s82_freeze_sw_clean] = {
220 [sdma_state_s99_running] = {
225 .go_s99_running_totrue = 1,
229 #define SDMA_TAIL_UPDATE_THRESH 0x1F
231 /* declare all statics here rather than keep sorting */
232 static void sdma_complete(struct kref *);
233 static void sdma_finalput(struct sdma_state *);
234 static void sdma_get(struct sdma_state *);
235 static void sdma_hw_clean_up_task(unsigned long);
236 static void sdma_put(struct sdma_state *);
237 static void sdma_set_state(struct sdma_engine *, enum sdma_states);
238 static void sdma_start_hw_clean_up(struct sdma_engine *);
239 static void sdma_sw_clean_up_task(unsigned long);
240 static void sdma_sendctrl(struct sdma_engine *, unsigned);
241 static void init_sdma_regs(struct sdma_engine *, u32, uint);
242 static void sdma_process_event(
243 struct sdma_engine *sde,
244 enum sdma_events event);
245 static void __sdma_process_event(
246 struct sdma_engine *sde,
247 enum sdma_events event);
248 static void dump_sdma_state(struct sdma_engine *sde);
249 static void sdma_make_progress(struct sdma_engine *sde, u64 status);
250 static void sdma_desc_avail(struct sdma_engine *sde, uint avail);
251 static void sdma_flush_descq(struct sdma_engine *sde);
254 * sdma_state_name() - return state string from enum
257 static const char *sdma_state_name(enum sdma_states state)
259 return sdma_state_names[state];
262 static void sdma_get(struct sdma_state *ss)
267 static void sdma_complete(struct kref *kref)
269 struct sdma_state *ss =
270 container_of(kref, struct sdma_state, kref);
275 static void sdma_put(struct sdma_state *ss)
277 kref_put(&ss->kref, sdma_complete);
280 static void sdma_finalput(struct sdma_state *ss)
283 wait_for_completion(&ss->comp);
286 static inline void write_sde_csr(
287 struct sdma_engine *sde,
291 write_kctxt_csr(sde->dd, sde->this_idx, offset0, value);
294 static inline u64 read_sde_csr(
295 struct sdma_engine *sde,
298 return read_kctxt_csr(sde->dd, sde->this_idx, offset0);
302 * sdma_wait_for_packet_egress() - wait for the VL FIFO occupancy for
303 * sdma engine 'sde' to drop to 0.
305 static void sdma_wait_for_packet_egress(struct sdma_engine *sde,
308 u64 off = 8 * sde->this_idx;
309 struct hfi1_devdata *dd = sde->dd;
316 reg = read_csr(dd, off + SEND_EGRESS_SEND_DMA_STATUS);
318 reg &= SDMA_EGRESS_PACKET_OCCUPANCY_SMASK;
319 reg >>= SDMA_EGRESS_PACKET_OCCUPANCY_SHIFT;
322 /* counter is reest if accupancy count changes */
326 /* timed out - bounce the link */
327 dd_dev_err(dd, "%s: engine %u timeout waiting for packets to egress, remaining count %u, bouncing link\n",
328 __func__, sde->this_idx, (u32)reg);
329 queue_work(dd->pport->link_wq,
330 &dd->pport->link_bounce_work);
338 * sdma_wait() - wait for packet egress to complete for all SDMA engines,
339 * and pause for credit return.
341 void sdma_wait(struct hfi1_devdata *dd)
345 for (i = 0; i < dd->num_sdma; i++) {
346 struct sdma_engine *sde = &dd->per_sdma[i];
348 sdma_wait_for_packet_egress(sde, 0);
352 static inline void sdma_set_desc_cnt(struct sdma_engine *sde, unsigned cnt)
356 if (!(sde->dd->flags & HFI1_HAS_SDMA_TIMEOUT))
359 reg &= SD(DESC_CNT_CNT_MASK);
360 reg <<= SD(DESC_CNT_CNT_SHIFT);
361 write_sde_csr(sde, SD(DESC_CNT), reg);
364 static inline void complete_tx(struct sdma_engine *sde,
365 struct sdma_txreq *tx,
368 /* protect against complete modifying */
369 struct iowait *wait = tx->wait;
370 callback_t complete = tx->complete;
372 #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER
373 trace_hfi1_sdma_out_sn(sde, tx->sn);
374 if (WARN_ON_ONCE(sde->head_sn != tx->sn))
375 dd_dev_err(sde->dd, "expected %llu got %llu\n",
376 sde->head_sn, tx->sn);
379 __sdma_txclean(sde->dd, tx);
381 (*complete)(tx, res);
382 if (wait && iowait_sdma_dec(wait))
383 iowait_drain_wakeup(wait);
387 * Complete all the sdma requests with a SDMA_TXREQ_S_ABORTED status
389 * Depending on timing there can be txreqs in two places:
390 * - in the descq ring
391 * - in the flush list
393 * To avoid ordering issues the descq ring needs to be flushed
394 * first followed by the flush list.
396 * This routine is called from two places
397 * - From a work queue item
398 * - Directly from the state machine just before setting the
401 * Must be called with head_lock held
404 static void sdma_flush(struct sdma_engine *sde)
406 struct sdma_txreq *txp, *txp_next;
407 LIST_HEAD(flushlist);
410 /* flush from head to tail */
411 sdma_flush_descq(sde);
412 spin_lock_irqsave(&sde->flushlist_lock, flags);
413 /* copy flush list */
414 list_splice_init(&sde->flushlist, &flushlist);
415 spin_unlock_irqrestore(&sde->flushlist_lock, flags);
416 /* flush from flush list */
417 list_for_each_entry_safe(txp, txp_next, &flushlist, list)
418 complete_tx(sde, txp, SDMA_TXREQ_S_ABORTED);
422 * Fields a work request for flushing the descq ring
425 * If the engine has been brought to running during
426 * the scheduling delay, the flush is ignored, assuming
427 * that the process of bringing the engine to running
428 * would have done this flush prior to going to running.
431 static void sdma_field_flush(struct work_struct *work)
434 struct sdma_engine *sde =
435 container_of(work, struct sdma_engine, flush_worker);
437 write_seqlock_irqsave(&sde->head_lock, flags);
438 if (!__sdma_running(sde))
440 write_sequnlock_irqrestore(&sde->head_lock, flags);
443 static void sdma_err_halt_wait(struct work_struct *work)
445 struct sdma_engine *sde = container_of(work, struct sdma_engine,
448 unsigned long timeout;
450 timeout = jiffies + msecs_to_jiffies(SDMA_ERR_HALT_TIMEOUT);
452 statuscsr = read_sde_csr(sde, SD(STATUS));
453 statuscsr &= SD(STATUS_ENG_HALTED_SMASK);
456 if (time_after(jiffies, timeout)) {
458 "SDMA engine %d - timeout waiting for engine to halt\n",
461 * Continue anyway. This could happen if there was
462 * an uncorrectable error in the wrong spot.
466 usleep_range(80, 120);
469 sdma_process_event(sde, sdma_event_e15_hw_halt_done);
472 static void sdma_err_progress_check_schedule(struct sdma_engine *sde)
474 if (!is_bx(sde->dd) && HFI1_CAP_IS_KSET(SDMA_AHG)) {
476 struct hfi1_devdata *dd = sde->dd;
478 for (index = 0; index < dd->num_sdma; index++) {
479 struct sdma_engine *curr_sdma = &dd->per_sdma[index];
481 if (curr_sdma != sde)
482 curr_sdma->progress_check_head =
483 curr_sdma->descq_head;
486 "SDMA engine %d - check scheduled\n",
488 mod_timer(&sde->err_progress_check_timer, jiffies + 10);
492 static void sdma_err_progress_check(struct timer_list *t)
495 struct sdma_engine *sde = from_timer(sde, t, err_progress_check_timer);
497 dd_dev_err(sde->dd, "SDE progress check event\n");
498 for (index = 0; index < sde->dd->num_sdma; index++) {
499 struct sdma_engine *curr_sde = &sde->dd->per_sdma[index];
502 /* check progress on each engine except the current one */
506 * We must lock interrupts when acquiring sde->lock,
507 * to avoid a deadlock if interrupt triggers and spins on
508 * the same lock on same CPU
510 spin_lock_irqsave(&curr_sde->tail_lock, flags);
511 write_seqlock(&curr_sde->head_lock);
513 /* skip non-running queues */
514 if (curr_sde->state.current_state != sdma_state_s99_running) {
515 write_sequnlock(&curr_sde->head_lock);
516 spin_unlock_irqrestore(&curr_sde->tail_lock, flags);
520 if ((curr_sde->descq_head != curr_sde->descq_tail) &&
521 (curr_sde->descq_head ==
522 curr_sde->progress_check_head))
523 __sdma_process_event(curr_sde,
524 sdma_event_e90_sw_halted);
525 write_sequnlock(&curr_sde->head_lock);
526 spin_unlock_irqrestore(&curr_sde->tail_lock, flags);
528 schedule_work(&sde->err_halt_worker);
531 static void sdma_hw_clean_up_task(unsigned long opaque)
533 struct sdma_engine *sde = (struct sdma_engine *)opaque;
537 #ifdef CONFIG_SDMA_VERBOSITY
538 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n",
539 sde->this_idx, slashstrip(__FILE__), __LINE__,
542 statuscsr = read_sde_csr(sde, SD(STATUS));
543 statuscsr &= SD(STATUS_ENG_CLEANED_UP_SMASK);
549 sdma_process_event(sde, sdma_event_e25_hw_clean_up_done);
552 static inline struct sdma_txreq *get_txhead(struct sdma_engine *sde)
554 return sde->tx_ring[sde->tx_head & sde->sdma_mask];
558 * flush ring for recovery
560 static void sdma_flush_descq(struct sdma_engine *sde)
564 struct sdma_txreq *txp = get_txhead(sde);
566 /* The reason for some of the complexity of this code is that
567 * not all descriptors have corresponding txps. So, we have to
568 * be able to skip over descs until we wander into the range of
569 * the next txp on the list.
571 head = sde->descq_head & sde->sdma_mask;
572 tail = sde->descq_tail & sde->sdma_mask;
573 while (head != tail) {
574 /* advance head, wrap if needed */
575 head = ++sde->descq_head & sde->sdma_mask;
576 /* if now past this txp's descs, do the callback */
577 if (txp && txp->next_descq_idx == head) {
578 /* remove from list */
579 sde->tx_ring[sde->tx_head++ & sde->sdma_mask] = NULL;
580 complete_tx(sde, txp, SDMA_TXREQ_S_ABORTED);
581 trace_hfi1_sdma_progress(sde, head, tail, txp);
582 txp = get_txhead(sde);
587 sdma_desc_avail(sde, sdma_descq_freecnt(sde));
590 static void sdma_sw_clean_up_task(unsigned long opaque)
592 struct sdma_engine *sde = (struct sdma_engine *)opaque;
595 spin_lock_irqsave(&sde->tail_lock, flags);
596 write_seqlock(&sde->head_lock);
599 * At this point, the following should always be true:
600 * - We are halted, so no more descriptors are getting retired.
601 * - We are not running, so no one is submitting new work.
602 * - Only we can send the e40_sw_cleaned, so we can't start
603 * running again until we say so. So, the active list and
604 * descq are ours to play with.
608 * In the error clean up sequence, software clean must be called
609 * before the hardware clean so we can use the hardware head in
610 * the progress routine. A hardware clean or SPC unfreeze will
611 * reset the hardware head.
613 * Process all retired requests. The progress routine will use the
614 * latest physical hardware head - we are not running so speed does
617 sdma_make_progress(sde, 0);
622 * Reset our notion of head and tail.
623 * Note that the HW registers have been reset via an earlier
628 sde->desc_avail = sdma_descq_freecnt(sde);
631 __sdma_process_event(sde, sdma_event_e40_sw_cleaned);
633 write_sequnlock(&sde->head_lock);
634 spin_unlock_irqrestore(&sde->tail_lock, flags);
637 static void sdma_sw_tear_down(struct sdma_engine *sde)
639 struct sdma_state *ss = &sde->state;
641 /* Releasing this reference means the state machine has stopped. */
644 /* stop waiting for all unfreeze events to complete */
645 atomic_set(&sde->dd->sdma_unfreeze_count, -1);
646 wake_up_interruptible(&sde->dd->sdma_unfreeze_wq);
649 static void sdma_start_hw_clean_up(struct sdma_engine *sde)
651 tasklet_hi_schedule(&sde->sdma_hw_clean_up_task);
654 static void sdma_set_state(struct sdma_engine *sde,
655 enum sdma_states next_state)
657 struct sdma_state *ss = &sde->state;
658 const struct sdma_set_state_action *action = sdma_action_table;
661 trace_hfi1_sdma_state(
663 sdma_state_names[ss->current_state],
664 sdma_state_names[next_state]);
666 /* debugging bookkeeping */
667 ss->previous_state = ss->current_state;
668 ss->previous_op = ss->current_op;
669 ss->current_state = next_state;
671 if (ss->previous_state != sdma_state_s99_running &&
672 next_state == sdma_state_s99_running)
675 if (action[next_state].op_enable)
676 op |= SDMA_SENDCTRL_OP_ENABLE;
678 if (action[next_state].op_intenable)
679 op |= SDMA_SENDCTRL_OP_INTENABLE;
681 if (action[next_state].op_halt)
682 op |= SDMA_SENDCTRL_OP_HALT;
684 if (action[next_state].op_cleanup)
685 op |= SDMA_SENDCTRL_OP_CLEANUP;
687 if (action[next_state].go_s99_running_tofalse)
688 ss->go_s99_running = 0;
690 if (action[next_state].go_s99_running_totrue)
691 ss->go_s99_running = 1;
694 sdma_sendctrl(sde, ss->current_op);
698 * sdma_get_descq_cnt() - called when device probed
700 * Return a validated descq count.
702 * This is currently only used in the verbs initialization to build the tx
705 * This will probably be deleted in favor of a more scalable approach to
709 u16 sdma_get_descq_cnt(void)
711 u16 count = sdma_descq_cnt;
714 return SDMA_DESCQ_CNT;
715 /* count must be a power of 2 greater than 64 and less than
716 * 32768. Otherwise return default.
718 if (!is_power_of_2(count))
719 return SDMA_DESCQ_CNT;
720 if (count < 64 || count > 32768)
721 return SDMA_DESCQ_CNT;
726 * sdma_engine_get_vl() - return vl for a given sdma engine
729 * This function returns the vl mapped to a given engine, or an error if
730 * the mapping can't be found. The mapping fields are protected by RCU.
732 int sdma_engine_get_vl(struct sdma_engine *sde)
734 struct hfi1_devdata *dd = sde->dd;
735 struct sdma_vl_map *m;
738 if (sde->this_idx >= TXE_NUM_SDMA_ENGINES)
742 m = rcu_dereference(dd->sdma_map);
747 vl = m->engine_to_vl[sde->this_idx];
754 * sdma_select_engine_vl() - select sdma engine
756 * @selector: a spreading factor
760 * This function returns an engine based on the selector and a vl. The
761 * mapping fields are protected by RCU.
763 struct sdma_engine *sdma_select_engine_vl(
764 struct hfi1_devdata *dd,
768 struct sdma_vl_map *m;
769 struct sdma_map_elem *e;
770 struct sdma_engine *rval;
772 /* NOTE This should only happen if SC->VL changed after the initial
773 * checks on the QP/AH
774 * Default will return engine 0 below
782 m = rcu_dereference(dd->sdma_map);
785 return &dd->per_sdma[0];
787 e = m->map[vl & m->mask];
788 rval = e->sde[selector & e->mask];
792 rval = !rval ? &dd->per_sdma[0] : rval;
793 trace_hfi1_sdma_engine_select(dd, selector, vl, rval->this_idx);
798 * sdma_select_engine_sc() - select sdma engine
800 * @selector: a spreading factor
804 * This function returns an engine based on the selector and an sc.
806 struct sdma_engine *sdma_select_engine_sc(
807 struct hfi1_devdata *dd,
811 u8 vl = sc_to_vlt(dd, sc5);
813 return sdma_select_engine_vl(dd, selector, vl);
816 struct sdma_rht_map_elem {
819 struct sdma_engine *sde[0];
822 struct sdma_rht_node {
823 unsigned long cpu_id;
824 struct sdma_rht_map_elem *map[HFI1_MAX_VLS_SUPPORTED];
825 struct rhash_head node;
828 #define NR_CPUS_HINT 192
830 static const struct rhashtable_params sdma_rht_params = {
831 .nelem_hint = NR_CPUS_HINT,
832 .head_offset = offsetof(struct sdma_rht_node, node),
833 .key_offset = offsetof(struct sdma_rht_node, cpu_id),
834 .key_len = FIELD_SIZEOF(struct sdma_rht_node, cpu_id),
837 .automatic_shrinking = true,
841 * sdma_select_user_engine() - select sdma engine based on user setup
843 * @selector: a spreading factor
846 * This function returns an sdma engine for a user sdma request.
847 * User defined sdma engine affinity setting is honored when applicable,
848 * otherwise system default sdma engine mapping is used. To ensure correct
849 * ordering, the mapping from <selector, vl> to sde must remain unchanged.
851 struct sdma_engine *sdma_select_user_engine(struct hfi1_devdata *dd,
854 struct sdma_rht_node *rht_node;
855 struct sdma_engine *sde = NULL;
856 const struct cpumask *current_mask = ¤t->cpus_allowed;
857 unsigned long cpu_id;
860 * To ensure that always the same sdma engine(s) will be
861 * selected make sure the process is pinned to this CPU only.
863 if (cpumask_weight(current_mask) != 1)
866 cpu_id = smp_processor_id();
868 rht_node = rhashtable_lookup_fast(dd->sdma_rht, &cpu_id,
871 if (rht_node && rht_node->map[vl]) {
872 struct sdma_rht_map_elem *map = rht_node->map[vl];
874 sde = map->sde[selector & map->mask];
882 return sdma_select_engine_vl(dd, selector, vl);
885 static void sdma_populate_sde_map(struct sdma_rht_map_elem *map)
889 for (i = 0; i < roundup_pow_of_two(map->ctr ? : 1) - map->ctr; i++)
890 map->sde[map->ctr + i] = map->sde[i];
893 static void sdma_cleanup_sde_map(struct sdma_rht_map_elem *map,
894 struct sdma_engine *sde)
898 /* only need to check the first ctr entries for a match */
899 for (i = 0; i < map->ctr; i++) {
900 if (map->sde[i] == sde) {
901 memmove(&map->sde[i], &map->sde[i + 1],
902 (map->ctr - i - 1) * sizeof(map->sde[0]));
904 pow = roundup_pow_of_two(map->ctr ? : 1);
906 sdma_populate_sde_map(map);
913 * Prevents concurrent reads and writes of the sdma engine cpu_mask
915 static DEFINE_MUTEX(process_to_sde_mutex);
917 ssize_t sdma_set_cpu_to_sde_map(struct sdma_engine *sde, const char *buf,
920 struct hfi1_devdata *dd = sde->dd;
921 cpumask_var_t mask, new_mask;
924 struct sdma_rht_node *rht_node;
926 vl = sdma_engine_get_vl(sde);
927 if (unlikely(vl < 0 || vl >= ARRAY_SIZE(rht_node->map)))
930 ret = zalloc_cpumask_var(&mask, GFP_KERNEL);
934 ret = zalloc_cpumask_var(&new_mask, GFP_KERNEL);
936 free_cpumask_var(mask);
939 ret = cpulist_parse(buf, mask);
943 if (!cpumask_subset(mask, cpu_online_mask)) {
944 dd_dev_warn(sde->dd, "Invalid CPU mask\n");
949 sz = sizeof(struct sdma_rht_map_elem) +
950 (TXE_NUM_SDMA_ENGINES * sizeof(struct sdma_engine *));
952 mutex_lock(&process_to_sde_mutex);
954 for_each_cpu(cpu, mask) {
955 /* Check if we have this already mapped */
956 if (cpumask_test_cpu(cpu, &sde->cpu_mask)) {
957 cpumask_set_cpu(cpu, new_mask);
961 rht_node = rhashtable_lookup_fast(dd->sdma_rht, &cpu,
964 rht_node = kzalloc(sizeof(*rht_node), GFP_KERNEL);
970 rht_node->map[vl] = kzalloc(sz, GFP_KERNEL);
971 if (!rht_node->map[vl]) {
976 rht_node->cpu_id = cpu;
977 rht_node->map[vl]->mask = 0;
978 rht_node->map[vl]->ctr = 1;
979 rht_node->map[vl]->sde[0] = sde;
981 ret = rhashtable_insert_fast(dd->sdma_rht,
985 kfree(rht_node->map[vl]);
987 dd_dev_err(sde->dd, "Failed to set process to sde affinity for cpu %lu\n",
995 /* Add new user mappings */
996 if (!rht_node->map[vl])
997 rht_node->map[vl] = kzalloc(sz, GFP_KERNEL);
999 if (!rht_node->map[vl]) {
1004 rht_node->map[vl]->ctr++;
1005 ctr = rht_node->map[vl]->ctr;
1006 rht_node->map[vl]->sde[ctr - 1] = sde;
1007 pow = roundup_pow_of_two(ctr);
1008 rht_node->map[vl]->mask = pow - 1;
1010 /* Populate the sde map table */
1011 sdma_populate_sde_map(rht_node->map[vl]);
1013 cpumask_set_cpu(cpu, new_mask);
1016 /* Clean up old mappings */
1017 for_each_cpu(cpu, cpu_online_mask) {
1018 struct sdma_rht_node *rht_node;
1020 /* Don't cleanup sdes that are set in the new mask */
1021 if (cpumask_test_cpu(cpu, mask))
1024 rht_node = rhashtable_lookup_fast(dd->sdma_rht, &cpu,
1030 /* Remove mappings for old sde */
1031 for (i = 0; i < HFI1_MAX_VLS_SUPPORTED; i++)
1032 if (rht_node->map[i])
1033 sdma_cleanup_sde_map(rht_node->map[i],
1036 /* Free empty hash table entries */
1037 for (i = 0; i < HFI1_MAX_VLS_SUPPORTED; i++) {
1038 if (!rht_node->map[i])
1041 if (rht_node->map[i]->ctr) {
1048 ret = rhashtable_remove_fast(dd->sdma_rht,
1053 for (i = 0; i < HFI1_MAX_VLS_SUPPORTED; i++)
1054 kfree(rht_node->map[i]);
1061 cpumask_copy(&sde->cpu_mask, new_mask);
1063 mutex_unlock(&process_to_sde_mutex);
1065 free_cpumask_var(mask);
1066 free_cpumask_var(new_mask);
1067 return ret ? : strnlen(buf, PAGE_SIZE);
1070 ssize_t sdma_get_cpu_to_sde_map(struct sdma_engine *sde, char *buf)
1072 mutex_lock(&process_to_sde_mutex);
1073 if (cpumask_empty(&sde->cpu_mask))
1074 snprintf(buf, PAGE_SIZE, "%s\n", "empty");
1076 cpumap_print_to_pagebuf(true, buf, &sde->cpu_mask);
1077 mutex_unlock(&process_to_sde_mutex);
1078 return strnlen(buf, PAGE_SIZE);
1081 static void sdma_rht_free(void *ptr, void *arg)
1083 struct sdma_rht_node *rht_node = ptr;
1086 for (i = 0; i < HFI1_MAX_VLS_SUPPORTED; i++)
1087 kfree(rht_node->map[i]);
1093 * sdma_seqfile_dump_cpu_list() - debugfs dump the cpu to sdma mappings
1098 * This routine dumps the process to sde mappings per cpu
1100 void sdma_seqfile_dump_cpu_list(struct seq_file *s,
1101 struct hfi1_devdata *dd,
1102 unsigned long cpuid)
1104 struct sdma_rht_node *rht_node;
1107 rht_node = rhashtable_lookup_fast(dd->sdma_rht, &cpuid,
1112 seq_printf(s, "cpu%3lu: ", cpuid);
1113 for (i = 0; i < HFI1_MAX_VLS_SUPPORTED; i++) {
1114 if (!rht_node->map[i] || !rht_node->map[i]->ctr)
1117 seq_printf(s, " vl%d: [", i);
1119 for (j = 0; j < rht_node->map[i]->ctr; j++) {
1120 if (!rht_node->map[i]->sde[j])
1126 seq_printf(s, " sdma%2d",
1127 rht_node->map[i]->sde[j]->this_idx);
1136 * Free the indicated map struct
1138 static void sdma_map_free(struct sdma_vl_map *m)
1142 for (i = 0; m && i < m->actual_vls; i++)
1148 * Handle RCU callback
1150 static void sdma_map_rcu_callback(struct rcu_head *list)
1152 struct sdma_vl_map *m = container_of(list, struct sdma_vl_map, list);
1158 * sdma_map_init - called when # vls change
1160 * @port: port number
1161 * @num_vls: number of vls
1162 * @vl_engines: per vl engine mapping (optional)
1164 * This routine changes the mapping based on the number of vls.
1166 * vl_engines is used to specify a non-uniform vl/engine loading. NULL
1167 * implies auto computing the loading and giving each VLs a uniform
1168 * distribution of engines per VL.
1170 * The auto algorithm computes the sde_per_vl and the number of extra
1171 * engines. Any extra engines are added from the last VL on down.
1173 * rcu locking is used here to control access to the mapping fields.
1175 * If either the num_vls or num_sdma are non-power of 2, the array sizes
1176 * in the struct sdma_vl_map and the struct sdma_map_elem are rounded
1177 * up to the next highest power of 2 and the first entry is reused
1178 * in a round robin fashion.
1180 * If an error occurs the map change is not done and the mapping is
1184 int sdma_map_init(struct hfi1_devdata *dd, u8 port, u8 num_vls, u8 *vl_engines)
1187 int extra, sde_per_vl;
1189 u8 lvl_engines[OPA_MAX_VLS];
1190 struct sdma_vl_map *oldmap, *newmap;
1192 if (!(dd->flags & HFI1_HAS_SEND_DMA))
1196 /* truncate divide */
1197 sde_per_vl = dd->num_sdma / num_vls;
1199 extra = dd->num_sdma % num_vls;
1200 vl_engines = lvl_engines;
1201 /* add extras from last vl down */
1202 for (i = num_vls - 1; i >= 0; i--, extra--)
1203 vl_engines[i] = sde_per_vl + (extra > 0 ? 1 : 0);
1207 sizeof(struct sdma_vl_map) +
1208 roundup_pow_of_two(num_vls) *
1209 sizeof(struct sdma_map_elem *),
1213 newmap->actual_vls = num_vls;
1214 newmap->vls = roundup_pow_of_two(num_vls);
1215 newmap->mask = (1 << ilog2(newmap->vls)) - 1;
1216 /* initialize back-map */
1217 for (i = 0; i < TXE_NUM_SDMA_ENGINES; i++)
1218 newmap->engine_to_vl[i] = -1;
1219 for (i = 0; i < newmap->vls; i++) {
1220 /* save for wrap around */
1221 int first_engine = engine;
1223 if (i < newmap->actual_vls) {
1224 int sz = roundup_pow_of_two(vl_engines[i]);
1226 /* only allocate once */
1227 newmap->map[i] = kzalloc(
1228 sizeof(struct sdma_map_elem) +
1229 sz * sizeof(struct sdma_engine *),
1231 if (!newmap->map[i])
1233 newmap->map[i]->mask = (1 << ilog2(sz)) - 1;
1234 /* assign engines */
1235 for (j = 0; j < sz; j++) {
1236 newmap->map[i]->sde[j] =
1237 &dd->per_sdma[engine];
1238 if (++engine >= first_engine + vl_engines[i])
1239 /* wrap back to first engine */
1240 engine = first_engine;
1242 /* assign back-map */
1243 for (j = 0; j < vl_engines[i]; j++)
1244 newmap->engine_to_vl[first_engine + j] = i;
1246 /* just re-use entry without allocating */
1247 newmap->map[i] = newmap->map[i % num_vls];
1249 engine = first_engine + vl_engines[i];
1251 /* newmap in hand, save old map */
1252 spin_lock_irq(&dd->sde_map_lock);
1253 oldmap = rcu_dereference_protected(dd->sdma_map,
1254 lockdep_is_held(&dd->sde_map_lock));
1256 /* publish newmap */
1257 rcu_assign_pointer(dd->sdma_map, newmap);
1259 spin_unlock_irq(&dd->sde_map_lock);
1260 /* success, free any old map after grace period */
1262 call_rcu(&oldmap->list, sdma_map_rcu_callback);
1265 /* free any partial allocation */
1266 sdma_map_free(newmap);
1271 * sdma_clean() Clean up allocated memory
1272 * @dd: struct hfi1_devdata
1273 * @num_engines: num sdma engines
1275 * This routine can be called regardless of the success of
1278 void sdma_clean(struct hfi1_devdata *dd, size_t num_engines)
1281 struct sdma_engine *sde;
1283 if (dd->sdma_pad_dma) {
1284 dma_free_coherent(&dd->pcidev->dev, SDMA_PAD,
1285 (void *)dd->sdma_pad_dma,
1287 dd->sdma_pad_dma = NULL;
1288 dd->sdma_pad_phys = 0;
1290 if (dd->sdma_heads_dma) {
1291 dma_free_coherent(&dd->pcidev->dev, dd->sdma_heads_size,
1292 (void *)dd->sdma_heads_dma,
1293 dd->sdma_heads_phys);
1294 dd->sdma_heads_dma = NULL;
1295 dd->sdma_heads_phys = 0;
1297 for (i = 0; dd->per_sdma && i < num_engines; ++i) {
1298 sde = &dd->per_sdma[i];
1300 sde->head_dma = NULL;
1306 sde->descq_cnt * sizeof(u64[2]),
1311 sde->descq_phys = 0;
1313 kvfree(sde->tx_ring);
1314 sde->tx_ring = NULL;
1316 if (rcu_access_pointer(dd->sdma_map)) {
1317 spin_lock_irq(&dd->sde_map_lock);
1318 sdma_map_free(rcu_access_pointer(dd->sdma_map));
1319 RCU_INIT_POINTER(dd->sdma_map, NULL);
1320 spin_unlock_irq(&dd->sde_map_lock);
1323 kfree(dd->per_sdma);
1324 dd->per_sdma = NULL;
1327 rhashtable_free_and_destroy(dd->sdma_rht, sdma_rht_free, NULL);
1328 kfree(dd->sdma_rht);
1329 dd->sdma_rht = NULL;
1334 * sdma_init() - called when device probed
1336 * @port: port number (currently only zero)
1338 * Initializes each sde and its csrs.
1339 * Interrupts are not required to be enabled.
1342 * 0 - success, -errno on failure
1344 int sdma_init(struct hfi1_devdata *dd, u8 port)
1347 struct sdma_engine *sde;
1348 struct rhashtable *tmp_sdma_rht;
1351 struct hfi1_pportdata *ppd = dd->pport + port;
1352 u32 per_sdma_credits;
1353 uint idle_cnt = sdma_idle_cnt;
1354 size_t num_engines = chip_sdma_engines(dd);
1357 if (!HFI1_CAP_IS_KSET(SDMA)) {
1358 HFI1_CAP_CLEAR(SDMA_AHG);
1362 /* can't exceed chip support */
1363 mod_num_sdma <= chip_sdma_engines(dd) &&
1364 /* count must be >= vls */
1365 mod_num_sdma >= num_vls)
1366 num_engines = mod_num_sdma;
1368 dd_dev_info(dd, "SDMA mod_num_sdma: %u\n", mod_num_sdma);
1369 dd_dev_info(dd, "SDMA chip_sdma_engines: %u\n", chip_sdma_engines(dd));
1370 dd_dev_info(dd, "SDMA chip_sdma_mem_size: %u\n",
1371 chip_sdma_mem_size(dd));
1374 chip_sdma_mem_size(dd) / (num_engines * SDMA_BLOCK_SIZE);
1376 /* set up freeze waitqueue */
1377 init_waitqueue_head(&dd->sdma_unfreeze_wq);
1378 atomic_set(&dd->sdma_unfreeze_count, 0);
1380 descq_cnt = sdma_get_descq_cnt();
1381 dd_dev_info(dd, "SDMA engines %zu descq_cnt %u\n",
1382 num_engines, descq_cnt);
1384 /* alloc memory for array of send engines */
1385 dd->per_sdma = kcalloc_node(num_engines, sizeof(*dd->per_sdma),
1386 GFP_KERNEL, dd->node);
1390 idle_cnt = ns_to_cclock(dd, idle_cnt);
1393 SDMA_DESC1_HEAD_TO_HOST_FLAG;
1396 SDMA_DESC1_INT_REQ_FLAG;
1398 if (!sdma_desct_intr)
1399 sdma_desct_intr = SDMA_DESC_INTR;
1401 /* Allocate memory for SendDMA descriptor FIFOs */
1402 for (this_idx = 0; this_idx < num_engines; ++this_idx) {
1403 sde = &dd->per_sdma[this_idx];
1406 sde->this_idx = this_idx;
1407 sde->descq_cnt = descq_cnt;
1408 sde->desc_avail = sdma_descq_freecnt(sde);
1409 sde->sdma_shift = ilog2(descq_cnt);
1410 sde->sdma_mask = (1 << sde->sdma_shift) - 1;
1412 /* Create a mask specifically for each interrupt source */
1413 sde->int_mask = (u64)1 << (0 * TXE_NUM_SDMA_ENGINES +
1415 sde->progress_mask = (u64)1 << (1 * TXE_NUM_SDMA_ENGINES +
1417 sde->idle_mask = (u64)1 << (2 * TXE_NUM_SDMA_ENGINES +
1419 /* Create a combined mask to cover all 3 interrupt sources */
1420 sde->imask = sde->int_mask | sde->progress_mask |
1423 spin_lock_init(&sde->tail_lock);
1424 seqlock_init(&sde->head_lock);
1425 spin_lock_init(&sde->senddmactrl_lock);
1426 spin_lock_init(&sde->flushlist_lock);
1427 /* insure there is always a zero bit */
1428 sde->ahg_bits = 0xfffffffe00000000ULL;
1430 sdma_set_state(sde, sdma_state_s00_hw_down);
1432 /* set up reference counting */
1433 kref_init(&sde->state.kref);
1434 init_completion(&sde->state.comp);
1436 INIT_LIST_HEAD(&sde->flushlist);
1437 INIT_LIST_HEAD(&sde->dmawait);
1440 get_kctxt_csr_addr(dd, this_idx, SD(TAIL));
1442 tasklet_init(&sde->sdma_hw_clean_up_task, sdma_hw_clean_up_task,
1443 (unsigned long)sde);
1445 tasklet_init(&sde->sdma_sw_clean_up_task, sdma_sw_clean_up_task,
1446 (unsigned long)sde);
1447 INIT_WORK(&sde->err_halt_worker, sdma_err_halt_wait);
1448 INIT_WORK(&sde->flush_worker, sdma_field_flush);
1450 sde->progress_check_head = 0;
1452 timer_setup(&sde->err_progress_check_timer,
1453 sdma_err_progress_check, 0);
1455 sde->descq = dma_zalloc_coherent(
1457 descq_cnt * sizeof(u64[2]),
1464 kvzalloc_node(array_size(descq_cnt,
1465 sizeof(struct sdma_txreq *)),
1466 GFP_KERNEL, dd->node);
1471 dd->sdma_heads_size = L1_CACHE_BYTES * num_engines;
1472 /* Allocate memory for DMA of head registers to memory */
1473 dd->sdma_heads_dma = dma_zalloc_coherent(
1475 dd->sdma_heads_size,
1476 &dd->sdma_heads_phys,
1479 if (!dd->sdma_heads_dma) {
1480 dd_dev_err(dd, "failed to allocate SendDMA head memory\n");
1484 /* Allocate memory for pad */
1485 dd->sdma_pad_dma = dma_zalloc_coherent(
1491 if (!dd->sdma_pad_dma) {
1492 dd_dev_err(dd, "failed to allocate SendDMA pad memory\n");
1496 /* assign each engine to different cacheline and init registers */
1497 curr_head = (void *)dd->sdma_heads_dma;
1498 for (this_idx = 0; this_idx < num_engines; ++this_idx) {
1499 unsigned long phys_offset;
1501 sde = &dd->per_sdma[this_idx];
1503 sde->head_dma = curr_head;
1504 curr_head += L1_CACHE_BYTES;
1505 phys_offset = (unsigned long)sde->head_dma -
1506 (unsigned long)dd->sdma_heads_dma;
1507 sde->head_phys = dd->sdma_heads_phys + phys_offset;
1508 init_sdma_regs(sde, per_sdma_credits, idle_cnt);
1510 dd->flags |= HFI1_HAS_SEND_DMA;
1511 dd->flags |= idle_cnt ? HFI1_HAS_SDMA_TIMEOUT : 0;
1512 dd->num_sdma = num_engines;
1513 ret = sdma_map_init(dd, port, ppd->vls_operational, NULL);
1517 tmp_sdma_rht = kzalloc(sizeof(*tmp_sdma_rht), GFP_KERNEL);
1518 if (!tmp_sdma_rht) {
1523 ret = rhashtable_init(tmp_sdma_rht, &sdma_rht_params);
1525 kfree(tmp_sdma_rht);
1529 dd->sdma_rht = tmp_sdma_rht;
1531 dd_dev_info(dd, "SDMA num_sdma: %u\n", dd->num_sdma);
1535 sdma_clean(dd, num_engines);
1540 * sdma_all_running() - called when the link goes up
1543 * This routine moves all engines to the running state.
1545 void sdma_all_running(struct hfi1_devdata *dd)
1547 struct sdma_engine *sde;
1550 /* move all engines to running */
1551 for (i = 0; i < dd->num_sdma; ++i) {
1552 sde = &dd->per_sdma[i];
1553 sdma_process_event(sde, sdma_event_e30_go_running);
1558 * sdma_all_idle() - called when the link goes down
1561 * This routine moves all engines to the idle state.
1563 void sdma_all_idle(struct hfi1_devdata *dd)
1565 struct sdma_engine *sde;
1568 /* idle all engines */
1569 for (i = 0; i < dd->num_sdma; ++i) {
1570 sde = &dd->per_sdma[i];
1571 sdma_process_event(sde, sdma_event_e70_go_idle);
1576 * sdma_start() - called to kick off state processing for all engines
1579 * This routine is for kicking off the state processing for all required
1580 * sdma engines. Interrupts need to be working at this point.
1583 void sdma_start(struct hfi1_devdata *dd)
1586 struct sdma_engine *sde;
1588 /* kick off the engines state processing */
1589 for (i = 0; i < dd->num_sdma; ++i) {
1590 sde = &dd->per_sdma[i];
1591 sdma_process_event(sde, sdma_event_e10_go_hw_start);
1596 * sdma_exit() - used when module is removed
1599 void sdma_exit(struct hfi1_devdata *dd)
1602 struct sdma_engine *sde;
1604 for (this_idx = 0; dd->per_sdma && this_idx < dd->num_sdma;
1606 sde = &dd->per_sdma[this_idx];
1607 if (!list_empty(&sde->dmawait))
1608 dd_dev_err(dd, "sde %u: dmawait list not empty!\n",
1610 sdma_process_event(sde, sdma_event_e00_go_hw_down);
1612 del_timer_sync(&sde->err_progress_check_timer);
1615 * This waits for the state machine to exit so it is not
1616 * necessary to kill the sdma_sw_clean_up_task to make sure
1617 * it is not running.
1619 sdma_finalput(&sde->state);
1624 * unmap the indicated descriptor
1626 static inline void sdma_unmap_desc(
1627 struct hfi1_devdata *dd,
1628 struct sdma_desc *descp)
1630 switch (sdma_mapping_type(descp)) {
1631 case SDMA_MAP_SINGLE:
1634 sdma_mapping_addr(descp),
1635 sdma_mapping_len(descp),
1641 sdma_mapping_addr(descp),
1642 sdma_mapping_len(descp),
1649 * return the mode as indicated by the first
1650 * descriptor in the tx.
1652 static inline u8 ahg_mode(struct sdma_txreq *tx)
1654 return (tx->descp[0].qw[1] & SDMA_DESC1_HEADER_MODE_SMASK)
1655 >> SDMA_DESC1_HEADER_MODE_SHIFT;
1659 * __sdma_txclean() - clean tx of mappings, descp *kmalloc's
1660 * @dd: hfi1_devdata for unmapping
1661 * @tx: tx request to clean
1663 * This is used in the progress routine to clean the tx or
1664 * by the ULP to toss an in-process tx build.
1666 * The code can be called multiple times without issue.
1669 void __sdma_txclean(
1670 struct hfi1_devdata *dd,
1671 struct sdma_txreq *tx)
1676 u8 skip = 0, mode = ahg_mode(tx);
1679 sdma_unmap_desc(dd, &tx->descp[0]);
1680 /* determine number of AHG descriptors to skip */
1681 if (mode > SDMA_AHG_APPLY_UPDATE1)
1683 for (i = 1 + skip; i < tx->num_desc; i++)
1684 sdma_unmap_desc(dd, &tx->descp[i]);
1687 kfree(tx->coalesce_buf);
1688 tx->coalesce_buf = NULL;
1689 /* kmalloc'ed descp */
1690 if (unlikely(tx->desc_limit > ARRAY_SIZE(tx->descs))) {
1691 tx->desc_limit = ARRAY_SIZE(tx->descs);
1696 static inline u16 sdma_gethead(struct sdma_engine *sde)
1698 struct hfi1_devdata *dd = sde->dd;
1702 #ifdef CONFIG_SDMA_VERBOSITY
1703 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n",
1704 sde->this_idx, slashstrip(__FILE__), __LINE__, __func__);
1708 use_dmahead = HFI1_CAP_IS_KSET(USE_SDMA_HEAD) && __sdma_running(sde) &&
1709 (dd->flags & HFI1_HAS_SDMA_TIMEOUT);
1710 hwhead = use_dmahead ?
1711 (u16)le64_to_cpu(*sde->head_dma) :
1712 (u16)read_sde_csr(sde, SD(HEAD));
1714 if (unlikely(HFI1_CAP_IS_KSET(SDMA_HEAD_CHECK))) {
1720 swhead = sde->descq_head & sde->sdma_mask;
1721 /* this code is really bad for cache line trading */
1722 swtail = READ_ONCE(sde->descq_tail) & sde->sdma_mask;
1723 cnt = sde->descq_cnt;
1725 if (swhead < swtail)
1727 sane = (hwhead >= swhead) & (hwhead <= swtail);
1728 else if (swhead > swtail)
1729 /* wrapped around */
1730 sane = ((hwhead >= swhead) && (hwhead < cnt)) ||
1734 sane = (hwhead == swhead);
1736 if (unlikely(!sane)) {
1737 dd_dev_err(dd, "SDMA(%u) bad head (%s) hwhd=%hu swhd=%hu swtl=%hu cnt=%hu\n",
1739 use_dmahead ? "dma" : "kreg",
1740 hwhead, swhead, swtail, cnt);
1742 /* try one more time, using csr */
1746 /* proceed as if no progress */
1754 * This is called when there are send DMA descriptors that might be
1757 * This is called with head_lock held.
1759 static void sdma_desc_avail(struct sdma_engine *sde, uint avail)
1761 struct iowait *wait, *nw;
1762 struct iowait *waits[SDMA_WAIT_BATCH_SIZE];
1763 uint i, n = 0, seq, max_idx = 0;
1764 struct sdma_txreq *stx;
1765 struct hfi1_ibdev *dev = &sde->dd->verbs_dev;
1766 u8 max_starved_cnt = 0;
1768 #ifdef CONFIG_SDMA_VERBOSITY
1769 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx,
1770 slashstrip(__FILE__), __LINE__, __func__);
1771 dd_dev_err(sde->dd, "avail: %u\n", avail);
1775 seq = read_seqbegin(&dev->iowait_lock);
1776 if (!list_empty(&sde->dmawait)) {
1777 /* at least one item */
1778 write_seqlock(&dev->iowait_lock);
1779 /* Harvest waiters wanting DMA descriptors */
1780 list_for_each_entry_safe(
1789 if (n == ARRAY_SIZE(waits))
1791 if (!list_empty(&wait->tx_head)) {
1792 stx = list_first_entry(
1796 num_desc = stx->num_desc;
1798 if (num_desc > avail)
1801 /* Find the most starved wait memeber */
1802 iowait_starve_find_max(wait, &max_starved_cnt,
1804 list_del_init(&wait->list);
1807 write_sequnlock(&dev->iowait_lock);
1810 } while (read_seqretry(&dev->iowait_lock, seq));
1812 /* Schedule the most starved one first */
1814 waits[max_idx]->wakeup(waits[max_idx], SDMA_AVAIL_REASON);
1816 for (i = 0; i < n; i++)
1818 waits[i]->wakeup(waits[i], SDMA_AVAIL_REASON);
1821 /* head_lock must be held */
1822 static void sdma_make_progress(struct sdma_engine *sde, u64 status)
1824 struct sdma_txreq *txp = NULL;
1827 int idle_check_done = 0;
1829 hwhead = sdma_gethead(sde);
1831 /* The reason for some of the complexity of this code is that
1832 * not all descriptors have corresponding txps. So, we have to
1833 * be able to skip over descs until we wander into the range of
1834 * the next txp on the list.
1838 txp = get_txhead(sde);
1839 swhead = sde->descq_head & sde->sdma_mask;
1840 trace_hfi1_sdma_progress(sde, hwhead, swhead, txp);
1841 while (swhead != hwhead) {
1842 /* advance head, wrap if needed */
1843 swhead = ++sde->descq_head & sde->sdma_mask;
1845 /* if now past this txp's descs, do the callback */
1846 if (txp && txp->next_descq_idx == swhead) {
1847 /* remove from list */
1848 sde->tx_ring[sde->tx_head++ & sde->sdma_mask] = NULL;
1849 complete_tx(sde, txp, SDMA_TXREQ_S_OK);
1850 /* see if there is another txp */
1851 txp = get_txhead(sde);
1853 trace_hfi1_sdma_progress(sde, hwhead, swhead, txp);
1858 * The SDMA idle interrupt is not guaranteed to be ordered with respect
1859 * to updates to the the dma_head location in host memory. The head
1860 * value read might not be fully up to date. If there are pending
1861 * descriptors and the SDMA idle interrupt fired then read from the
1862 * CSR SDMA head instead to get the latest value from the hardware.
1863 * The hardware SDMA head should be read at most once in this invocation
1864 * of sdma_make_progress(..) which is ensured by idle_check_done flag
1866 if ((status & sde->idle_mask) && !idle_check_done) {
1869 swtail = READ_ONCE(sde->descq_tail) & sde->sdma_mask;
1870 if (swtail != hwhead) {
1871 hwhead = (u16)read_sde_csr(sde, SD(HEAD));
1872 idle_check_done = 1;
1877 sde->last_status = status;
1879 sdma_desc_avail(sde, sdma_descq_freecnt(sde));
1883 * sdma_engine_interrupt() - interrupt handler for engine
1885 * @status: sdma interrupt reason
1887 * Status is a mask of the 3 possible interrupts for this engine. It will
1888 * contain bits _only_ for this SDMA engine. It will contain at least one
1889 * bit, it may contain more.
1891 void sdma_engine_interrupt(struct sdma_engine *sde, u64 status)
1893 trace_hfi1_sdma_engine_interrupt(sde, status);
1894 write_seqlock(&sde->head_lock);
1895 sdma_set_desc_cnt(sde, sdma_desct_intr);
1896 if (status & sde->idle_mask)
1897 sde->idle_int_cnt++;
1898 else if (status & sde->progress_mask)
1899 sde->progress_int_cnt++;
1900 else if (status & sde->int_mask)
1901 sde->sdma_int_cnt++;
1902 sdma_make_progress(sde, status);
1903 write_sequnlock(&sde->head_lock);
1907 * sdma_engine_error() - error handler for engine
1909 * @status: sdma interrupt reason
1911 void sdma_engine_error(struct sdma_engine *sde, u64 status)
1913 unsigned long flags;
1915 #ifdef CONFIG_SDMA_VERBOSITY
1916 dd_dev_err(sde->dd, "CONFIG SDMA(%u) error status 0x%llx state %s\n",
1918 (unsigned long long)status,
1919 sdma_state_names[sde->state.current_state]);
1921 spin_lock_irqsave(&sde->tail_lock, flags);
1922 write_seqlock(&sde->head_lock);
1923 if (status & ALL_SDMA_ENG_HALT_ERRS)
1924 __sdma_process_event(sde, sdma_event_e60_hw_halted);
1925 if (status & ~SD(ENG_ERR_STATUS_SDMA_HALT_ERR_SMASK)) {
1927 "SDMA (%u) engine error: 0x%llx state %s\n",
1929 (unsigned long long)status,
1930 sdma_state_names[sde->state.current_state]);
1931 dump_sdma_state(sde);
1933 write_sequnlock(&sde->head_lock);
1934 spin_unlock_irqrestore(&sde->tail_lock, flags);
1937 static void sdma_sendctrl(struct sdma_engine *sde, unsigned op)
1939 u64 set_senddmactrl = 0;
1940 u64 clr_senddmactrl = 0;
1941 unsigned long flags;
1943 #ifdef CONFIG_SDMA_VERBOSITY
1944 dd_dev_err(sde->dd, "CONFIG SDMA(%u) senddmactrl E=%d I=%d H=%d C=%d\n",
1946 (op & SDMA_SENDCTRL_OP_ENABLE) ? 1 : 0,
1947 (op & SDMA_SENDCTRL_OP_INTENABLE) ? 1 : 0,
1948 (op & SDMA_SENDCTRL_OP_HALT) ? 1 : 0,
1949 (op & SDMA_SENDCTRL_OP_CLEANUP) ? 1 : 0);
1952 if (op & SDMA_SENDCTRL_OP_ENABLE)
1953 set_senddmactrl |= SD(CTRL_SDMA_ENABLE_SMASK);
1955 clr_senddmactrl |= SD(CTRL_SDMA_ENABLE_SMASK);
1957 if (op & SDMA_SENDCTRL_OP_INTENABLE)
1958 set_senddmactrl |= SD(CTRL_SDMA_INT_ENABLE_SMASK);
1960 clr_senddmactrl |= SD(CTRL_SDMA_INT_ENABLE_SMASK);
1962 if (op & SDMA_SENDCTRL_OP_HALT)
1963 set_senddmactrl |= SD(CTRL_SDMA_HALT_SMASK);
1965 clr_senddmactrl |= SD(CTRL_SDMA_HALT_SMASK);
1967 spin_lock_irqsave(&sde->senddmactrl_lock, flags);
1969 sde->p_senddmactrl |= set_senddmactrl;
1970 sde->p_senddmactrl &= ~clr_senddmactrl;
1972 if (op & SDMA_SENDCTRL_OP_CLEANUP)
1973 write_sde_csr(sde, SD(CTRL),
1974 sde->p_senddmactrl |
1975 SD(CTRL_SDMA_CLEANUP_SMASK));
1977 write_sde_csr(sde, SD(CTRL), sde->p_senddmactrl);
1979 spin_unlock_irqrestore(&sde->senddmactrl_lock, flags);
1981 #ifdef CONFIG_SDMA_VERBOSITY
1982 sdma_dumpstate(sde);
1986 static void sdma_setlengen(struct sdma_engine *sde)
1988 #ifdef CONFIG_SDMA_VERBOSITY
1989 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n",
1990 sde->this_idx, slashstrip(__FILE__), __LINE__, __func__);
1994 * Set SendDmaLenGen and clear-then-set the MSB of the generation
1995 * count to enable generation checking and load the internal
1996 * generation counter.
1998 write_sde_csr(sde, SD(LEN_GEN),
1999 (sde->descq_cnt / 64) << SD(LEN_GEN_LENGTH_SHIFT));
2000 write_sde_csr(sde, SD(LEN_GEN),
2001 ((sde->descq_cnt / 64) << SD(LEN_GEN_LENGTH_SHIFT)) |
2002 (4ULL << SD(LEN_GEN_GENERATION_SHIFT)));
2005 static inline void sdma_update_tail(struct sdma_engine *sde, u16 tail)
2007 /* Commit writes to memory and advance the tail on the chip */
2008 smp_wmb(); /* see get_txhead() */
2009 writeq(tail, sde->tail_csr);
2013 * This is called when changing to state s10_hw_start_up_halt_wait as
2014 * a result of send buffer errors or send DMA descriptor errors.
2016 static void sdma_hw_start_up(struct sdma_engine *sde)
2020 #ifdef CONFIG_SDMA_VERBOSITY
2021 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n",
2022 sde->this_idx, slashstrip(__FILE__), __LINE__, __func__);
2025 sdma_setlengen(sde);
2026 sdma_update_tail(sde, 0); /* Set SendDmaTail */
2029 reg = SD(ENG_ERR_CLEAR_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_MASK) <<
2030 SD(ENG_ERR_CLEAR_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_SHIFT);
2031 write_sde_csr(sde, SD(ENG_ERR_CLEAR), reg);
2035 * set_sdma_integrity
2037 * Set the SEND_DMA_CHECK_ENABLE register for send DMA engine 'sde'.
2039 static void set_sdma_integrity(struct sdma_engine *sde)
2041 struct hfi1_devdata *dd = sde->dd;
2043 write_sde_csr(sde, SD(CHECK_ENABLE),
2044 hfi1_pkt_base_sdma_integrity(dd));
2047 static void init_sdma_regs(
2048 struct sdma_engine *sde,
2053 #ifdef CONFIG_SDMA_VERBOSITY
2054 struct hfi1_devdata *dd = sde->dd;
2056 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n",
2057 sde->this_idx, slashstrip(__FILE__), __LINE__, __func__);
2060 write_sde_csr(sde, SD(BASE_ADDR), sde->descq_phys);
2061 sdma_setlengen(sde);
2062 sdma_update_tail(sde, 0); /* Set SendDmaTail */
2063 write_sde_csr(sde, SD(RELOAD_CNT), idle_cnt);
2064 write_sde_csr(sde, SD(DESC_CNT), 0);
2065 write_sde_csr(sde, SD(HEAD_ADDR), sde->head_phys);
2066 write_sde_csr(sde, SD(MEMORY),
2067 ((u64)credits << SD(MEMORY_SDMA_MEMORY_CNT_SHIFT)) |
2068 ((u64)(credits * sde->this_idx) <<
2069 SD(MEMORY_SDMA_MEMORY_INDEX_SHIFT)));
2070 write_sde_csr(sde, SD(ENG_ERR_MASK), ~0ull);
2071 set_sdma_integrity(sde);
2072 opmask = OPCODE_CHECK_MASK_DISABLED;
2073 opval = OPCODE_CHECK_VAL_DISABLED;
2074 write_sde_csr(sde, SD(CHECK_OPCODE),
2075 (opmask << SEND_CTXT_CHECK_OPCODE_MASK_SHIFT) |
2076 (opval << SEND_CTXT_CHECK_OPCODE_VALUE_SHIFT));
2079 #ifdef CONFIG_SDMA_VERBOSITY
2081 #define sdma_dumpstate_helper0(reg) do { \
2082 csr = read_csr(sde->dd, reg); \
2083 dd_dev_err(sde->dd, "%36s 0x%016llx\n", #reg, csr); \
2086 #define sdma_dumpstate_helper(reg) do { \
2087 csr = read_sde_csr(sde, reg); \
2088 dd_dev_err(sde->dd, "%36s[%02u] 0x%016llx\n", \
2089 #reg, sde->this_idx, csr); \
2092 #define sdma_dumpstate_helper2(reg) do { \
2093 csr = read_csr(sde->dd, reg + (8 * i)); \
2094 dd_dev_err(sde->dd, "%33s_%02u 0x%016llx\n", \
2098 void sdma_dumpstate(struct sdma_engine *sde)
2103 sdma_dumpstate_helper(SD(CTRL));
2104 sdma_dumpstate_helper(SD(STATUS));
2105 sdma_dumpstate_helper0(SD(ERR_STATUS));
2106 sdma_dumpstate_helper0(SD(ERR_MASK));
2107 sdma_dumpstate_helper(SD(ENG_ERR_STATUS));
2108 sdma_dumpstate_helper(SD(ENG_ERR_MASK));
2110 for (i = 0; i < CCE_NUM_INT_CSRS; ++i) {
2111 sdma_dumpstate_helper2(CCE_INT_STATUS);
2112 sdma_dumpstate_helper2(CCE_INT_MASK);
2113 sdma_dumpstate_helper2(CCE_INT_BLOCKED);
2116 sdma_dumpstate_helper(SD(TAIL));
2117 sdma_dumpstate_helper(SD(HEAD));
2118 sdma_dumpstate_helper(SD(PRIORITY_THLD));
2119 sdma_dumpstate_helper(SD(IDLE_CNT));
2120 sdma_dumpstate_helper(SD(RELOAD_CNT));
2121 sdma_dumpstate_helper(SD(DESC_CNT));
2122 sdma_dumpstate_helper(SD(DESC_FETCHED_CNT));
2123 sdma_dumpstate_helper(SD(MEMORY));
2124 sdma_dumpstate_helper0(SD(ENGINES));
2125 sdma_dumpstate_helper0(SD(MEM_SIZE));
2126 /* sdma_dumpstate_helper(SEND_EGRESS_SEND_DMA_STATUS); */
2127 sdma_dumpstate_helper(SD(BASE_ADDR));
2128 sdma_dumpstate_helper(SD(LEN_GEN));
2129 sdma_dumpstate_helper(SD(HEAD_ADDR));
2130 sdma_dumpstate_helper(SD(CHECK_ENABLE));
2131 sdma_dumpstate_helper(SD(CHECK_VL));
2132 sdma_dumpstate_helper(SD(CHECK_JOB_KEY));
2133 sdma_dumpstate_helper(SD(CHECK_PARTITION_KEY));
2134 sdma_dumpstate_helper(SD(CHECK_SLID));
2135 sdma_dumpstate_helper(SD(CHECK_OPCODE));
2139 static void dump_sdma_state(struct sdma_engine *sde)
2141 struct hw_sdma_desc *descqp;
2146 u16 head, tail, cnt;
2148 head = sde->descq_head & sde->sdma_mask;
2149 tail = sde->descq_tail & sde->sdma_mask;
2150 cnt = sdma_descq_freecnt(sde);
2153 "SDMA (%u) descq_head: %u descq_tail: %u freecnt: %u FLE %d\n",
2154 sde->this_idx, head, tail, cnt,
2155 !list_empty(&sde->flushlist));
2157 /* print info for each entry in the descriptor queue */
2158 while (head != tail) {
2159 char flags[6] = { 'x', 'x', 'x', 'x', 0 };
2161 descqp = &sde->descq[head];
2162 desc[0] = le64_to_cpu(descqp->qw[0]);
2163 desc[1] = le64_to_cpu(descqp->qw[1]);
2164 flags[0] = (desc[1] & SDMA_DESC1_INT_REQ_FLAG) ? 'I' : '-';
2165 flags[1] = (desc[1] & SDMA_DESC1_HEAD_TO_HOST_FLAG) ?
2167 flags[2] = (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG) ? 'F' : '-';
2168 flags[3] = (desc[0] & SDMA_DESC0_LAST_DESC_FLAG) ? 'L' : '-';
2169 addr = (desc[0] >> SDMA_DESC0_PHY_ADDR_SHIFT)
2170 & SDMA_DESC0_PHY_ADDR_MASK;
2171 gen = (desc[1] >> SDMA_DESC1_GENERATION_SHIFT)
2172 & SDMA_DESC1_GENERATION_MASK;
2173 len = (desc[0] >> SDMA_DESC0_BYTE_COUNT_SHIFT)
2174 & SDMA_DESC0_BYTE_COUNT_MASK;
2176 "SDMA sdmadesc[%u]: flags:%s addr:0x%016llx gen:%u len:%u bytes\n",
2177 head, flags, addr, gen, len);
2179 "\tdesc0:0x%016llx desc1 0x%016llx\n",
2181 if (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG)
2183 "\taidx: %u amode: %u alen: %u\n",
2185 SDMA_DESC1_HEADER_INDEX_SMASK) >>
2186 SDMA_DESC1_HEADER_INDEX_SHIFT),
2188 SDMA_DESC1_HEADER_MODE_SMASK) >>
2189 SDMA_DESC1_HEADER_MODE_SHIFT),
2191 SDMA_DESC1_HEADER_DWS_SMASK) >>
2192 SDMA_DESC1_HEADER_DWS_SHIFT));
2194 head &= sde->sdma_mask;
2199 "SDE %u CPU %d STE %s C 0x%llx S 0x%016llx E 0x%llx T(HW) 0x%llx T(SW) 0x%x H(HW) 0x%llx H(SW) 0x%x H(D) 0x%llx DM 0x%llx GL 0x%llx R 0x%llx LIS 0x%llx AHGI 0x%llx TXT %u TXH %u DT %u DH %u FLNE %d DQF %u SLC 0x%llx\n"
2201 * sdma_seqfile_dump_sde() - debugfs dump of sde
2203 * @sde: send dma engine to dump
2205 * This routine dumps the sde to the indicated seq file.
2207 void sdma_seqfile_dump_sde(struct seq_file *s, struct sdma_engine *sde)
2210 struct hw_sdma_desc *descqp;
2216 head = sde->descq_head & sde->sdma_mask;
2217 tail = READ_ONCE(sde->descq_tail) & sde->sdma_mask;
2218 seq_printf(s, SDE_FMT, sde->this_idx,
2220 sdma_state_name(sde->state.current_state),
2221 (unsigned long long)read_sde_csr(sde, SD(CTRL)),
2222 (unsigned long long)read_sde_csr(sde, SD(STATUS)),
2223 (unsigned long long)read_sde_csr(sde, SD(ENG_ERR_STATUS)),
2224 (unsigned long long)read_sde_csr(sde, SD(TAIL)), tail,
2225 (unsigned long long)read_sde_csr(sde, SD(HEAD)), head,
2226 (unsigned long long)le64_to_cpu(*sde->head_dma),
2227 (unsigned long long)read_sde_csr(sde, SD(MEMORY)),
2228 (unsigned long long)read_sde_csr(sde, SD(LEN_GEN)),
2229 (unsigned long long)read_sde_csr(sde, SD(RELOAD_CNT)),
2230 (unsigned long long)sde->last_status,
2231 (unsigned long long)sde->ahg_bits,
2236 !list_empty(&sde->flushlist),
2237 sde->descq_full_count,
2238 (unsigned long long)read_sde_csr(sde, SEND_DMA_CHECK_SLID));
2240 /* print info for each entry in the descriptor queue */
2241 while (head != tail) {
2242 char flags[6] = { 'x', 'x', 'x', 'x', 0 };
2244 descqp = &sde->descq[head];
2245 desc[0] = le64_to_cpu(descqp->qw[0]);
2246 desc[1] = le64_to_cpu(descqp->qw[1]);
2247 flags[0] = (desc[1] & SDMA_DESC1_INT_REQ_FLAG) ? 'I' : '-';
2248 flags[1] = (desc[1] & SDMA_DESC1_HEAD_TO_HOST_FLAG) ?
2250 flags[2] = (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG) ? 'F' : '-';
2251 flags[3] = (desc[0] & SDMA_DESC0_LAST_DESC_FLAG) ? 'L' : '-';
2252 addr = (desc[0] >> SDMA_DESC0_PHY_ADDR_SHIFT)
2253 & SDMA_DESC0_PHY_ADDR_MASK;
2254 gen = (desc[1] >> SDMA_DESC1_GENERATION_SHIFT)
2255 & SDMA_DESC1_GENERATION_MASK;
2256 len = (desc[0] >> SDMA_DESC0_BYTE_COUNT_SHIFT)
2257 & SDMA_DESC0_BYTE_COUNT_MASK;
2259 "\tdesc[%u]: flags:%s addr:0x%016llx gen:%u len:%u bytes\n",
2260 head, flags, addr, gen, len);
2261 if (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG)
2262 seq_printf(s, "\t\tahgidx: %u ahgmode: %u\n",
2264 SDMA_DESC1_HEADER_INDEX_SMASK) >>
2265 SDMA_DESC1_HEADER_INDEX_SHIFT),
2267 SDMA_DESC1_HEADER_MODE_SMASK) >>
2268 SDMA_DESC1_HEADER_MODE_SHIFT));
2269 head = (head + 1) & sde->sdma_mask;
2274 * add the generation number into
2275 * the qw1 and return
2277 static inline u64 add_gen(struct sdma_engine *sde, u64 qw1)
2279 u8 generation = (sde->descq_tail >> sde->sdma_shift) & 3;
2281 qw1 &= ~SDMA_DESC1_GENERATION_SMASK;
2282 qw1 |= ((u64)generation & SDMA_DESC1_GENERATION_MASK)
2283 << SDMA_DESC1_GENERATION_SHIFT;
2288 * This routine submits the indicated tx
2290 * Space has already been guaranteed and
2291 * tail side of ring is locked.
2293 * The hardware tail update is done
2294 * in the caller and that is facilitated
2295 * by returning the new tail.
2297 * There is special case logic for ahg
2298 * to not add the generation number for
2299 * up to 2 descriptors that follow the
2303 static inline u16 submit_tx(struct sdma_engine *sde, struct sdma_txreq *tx)
2307 struct sdma_desc *descp = tx->descp;
2308 u8 skip = 0, mode = ahg_mode(tx);
2310 tail = sde->descq_tail & sde->sdma_mask;
2311 sde->descq[tail].qw[0] = cpu_to_le64(descp->qw[0]);
2312 sde->descq[tail].qw[1] = cpu_to_le64(add_gen(sde, descp->qw[1]));
2313 trace_hfi1_sdma_descriptor(sde, descp->qw[0], descp->qw[1],
2314 tail, &sde->descq[tail]);
2315 tail = ++sde->descq_tail & sde->sdma_mask;
2317 if (mode > SDMA_AHG_APPLY_UPDATE1)
2319 for (i = 1; i < tx->num_desc; i++, descp++) {
2322 sde->descq[tail].qw[0] = cpu_to_le64(descp->qw[0]);
2324 /* edits don't have generation */
2328 /* replace generation with real one for non-edits */
2329 qw1 = add_gen(sde, descp->qw[1]);
2331 sde->descq[tail].qw[1] = cpu_to_le64(qw1);
2332 trace_hfi1_sdma_descriptor(sde, descp->qw[0], qw1,
2333 tail, &sde->descq[tail]);
2334 tail = ++sde->descq_tail & sde->sdma_mask;
2336 tx->next_descq_idx = tail;
2337 #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER
2338 tx->sn = sde->tail_sn++;
2339 trace_hfi1_sdma_in_sn(sde, tx->sn);
2340 WARN_ON_ONCE(sde->tx_ring[sde->tx_tail & sde->sdma_mask]);
2342 sde->tx_ring[sde->tx_tail++ & sde->sdma_mask] = tx;
2343 sde->desc_avail -= tx->num_desc;
2348 * Check for progress
2350 static int sdma_check_progress(
2351 struct sdma_engine *sde,
2352 struct iowait *wait,
2353 struct sdma_txreq *tx,
2358 sde->desc_avail = sdma_descq_freecnt(sde);
2359 if (tx->num_desc <= sde->desc_avail)
2361 /* pulse the head_lock */
2362 if (wait && wait->sleep) {
2365 seq = raw_seqcount_begin(
2366 (const seqcount_t *)&sde->head_lock.seqcount);
2367 ret = wait->sleep(sde, wait, tx, seq, pkts_sent);
2369 sde->desc_avail = sdma_descq_freecnt(sde);
2377 * sdma_send_txreq() - submit a tx req to ring
2378 * @sde: sdma engine to use
2379 * @wait: wait structure to use when full (may be NULL)
2380 * @tx: sdma_txreq to submit
2381 * @pkts_sent: has any packet been sent yet?
2383 * The call submits the tx into the ring. If a iowait structure is non-NULL
2384 * the packet will be queued to the list in wait.
2387 * 0 - Success, -EINVAL - sdma_txreq incomplete, -EBUSY - no space in
2388 * ring (wait == NULL)
2389 * -EIOCBQUEUED - tx queued to iowait, -ECOMM bad sdma state
2391 int sdma_send_txreq(struct sdma_engine *sde,
2392 struct iowait *wait,
2393 struct sdma_txreq *tx,
2398 unsigned long flags;
2400 /* user should have supplied entire packet */
2401 if (unlikely(tx->tlen))
2404 spin_lock_irqsave(&sde->tail_lock, flags);
2406 if (unlikely(!__sdma_running(sde)))
2408 if (unlikely(tx->num_desc > sde->desc_avail))
2410 tail = submit_tx(sde, tx);
2412 iowait_sdma_inc(wait);
2413 sdma_update_tail(sde, tail);
2415 spin_unlock_irqrestore(&sde->tail_lock, flags);
2419 iowait_sdma_inc(wait);
2420 tx->next_descq_idx = 0;
2421 #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER
2422 tx->sn = sde->tail_sn++;
2423 trace_hfi1_sdma_in_sn(sde, tx->sn);
2425 spin_lock(&sde->flushlist_lock);
2426 list_add_tail(&tx->list, &sde->flushlist);
2427 spin_unlock(&sde->flushlist_lock);
2430 wait->count += tx->num_desc;
2432 queue_work_on(sde->cpu, system_highpri_wq, &sde->flush_worker);
2436 ret = sdma_check_progress(sde, wait, tx, pkts_sent);
2437 if (ret == -EAGAIN) {
2441 sde->descq_full_count++;
2446 * sdma_send_txlist() - submit a list of tx req to ring
2447 * @sde: sdma engine to use
2448 * @wait: wait structure to use when full (may be NULL)
2449 * @tx_list: list of sdma_txreqs to submit
2450 * @count: pointer to a u32 which, after return will contain the total number of
2451 * sdma_txreqs removed from the tx_list. This will include sdma_txreqs
2452 * whose SDMA descriptors are submitted to the ring and the sdma_txreqs
2453 * which are added to SDMA engine flush list if the SDMA engine state is
2456 * The call submits the list into the ring.
2458 * If the iowait structure is non-NULL and not equal to the iowait list
2459 * the unprocessed part of the list will be appended to the list in wait.
2461 * In all cases, the tx_list will be updated so the head of the tx_list is
2462 * the list of descriptors that have yet to be transmitted.
2464 * The intent of this call is to provide a more efficient
2465 * way of submitting multiple packets to SDMA while holding the tail
2470 * -EINVAL - sdma_txreq incomplete, -EBUSY - no space in ring (wait == NULL)
2471 * -EIOCBQUEUED - tx queued to iowait, -ECOMM bad sdma state
2473 int sdma_send_txlist(struct sdma_engine *sde, struct iowait *wait,
2474 struct list_head *tx_list, u32 *count_out)
2476 struct sdma_txreq *tx, *tx_next;
2478 unsigned long flags;
2479 u16 tail = INVALID_TAIL;
2480 u32 submit_count = 0, flush_count = 0, total_count;
2482 spin_lock_irqsave(&sde->tail_lock, flags);
2484 list_for_each_entry_safe(tx, tx_next, tx_list, list) {
2486 if (unlikely(!__sdma_running(sde)))
2488 if (unlikely(tx->num_desc > sde->desc_avail))
2490 if (unlikely(tx->tlen)) {
2494 list_del_init(&tx->list);
2495 tail = submit_tx(sde, tx);
2497 if (tail != INVALID_TAIL &&
2498 (submit_count & SDMA_TAIL_UPDATE_THRESH) == 0) {
2499 sdma_update_tail(sde, tail);
2500 tail = INVALID_TAIL;
2504 total_count = submit_count + flush_count;
2506 iowait_sdma_add(wait, total_count);
2507 iowait_starve_clear(submit_count > 0, wait);
2509 if (tail != INVALID_TAIL)
2510 sdma_update_tail(sde, tail);
2511 spin_unlock_irqrestore(&sde->tail_lock, flags);
2512 *count_out = total_count;
2515 spin_lock(&sde->flushlist_lock);
2516 list_for_each_entry_safe(tx, tx_next, tx_list, list) {
2518 list_del_init(&tx->list);
2519 tx->next_descq_idx = 0;
2520 #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER
2521 tx->sn = sde->tail_sn++;
2522 trace_hfi1_sdma_in_sn(sde, tx->sn);
2524 list_add_tail(&tx->list, &sde->flushlist);
2528 wait->count += tx->num_desc;
2531 spin_unlock(&sde->flushlist_lock);
2532 queue_work_on(sde->cpu, system_highpri_wq, &sde->flush_worker);
2536 ret = sdma_check_progress(sde, wait, tx, submit_count > 0);
2537 if (ret == -EAGAIN) {
2541 sde->descq_full_count++;
2545 static void sdma_process_event(struct sdma_engine *sde, enum sdma_events event)
2547 unsigned long flags;
2549 spin_lock_irqsave(&sde->tail_lock, flags);
2550 write_seqlock(&sde->head_lock);
2552 __sdma_process_event(sde, event);
2554 if (sde->state.current_state == sdma_state_s99_running)
2555 sdma_desc_avail(sde, sdma_descq_freecnt(sde));
2557 write_sequnlock(&sde->head_lock);
2558 spin_unlock_irqrestore(&sde->tail_lock, flags);
2561 static void __sdma_process_event(struct sdma_engine *sde,
2562 enum sdma_events event)
2564 struct sdma_state *ss = &sde->state;
2565 int need_progress = 0;
2567 /* CONFIG SDMA temporary */
2568 #ifdef CONFIG_SDMA_VERBOSITY
2569 dd_dev_err(sde->dd, "CONFIG SDMA(%u) [%s] %s\n", sde->this_idx,
2570 sdma_state_names[ss->current_state],
2571 sdma_event_names[event]);
2574 switch (ss->current_state) {
2575 case sdma_state_s00_hw_down:
2577 case sdma_event_e00_go_hw_down:
2579 case sdma_event_e30_go_running:
2581 * If down, but running requested (usually result
2582 * of link up, then we need to start up.
2583 * This can happen when hw down is requested while
2584 * bringing the link up with traffic active on
2587 ss->go_s99_running = 1;
2588 /* fall through -- and start dma engine */
2589 case sdma_event_e10_go_hw_start:
2590 /* This reference means the state machine is started */
2591 sdma_get(&sde->state);
2593 sdma_state_s10_hw_start_up_halt_wait);
2595 case sdma_event_e15_hw_halt_done:
2597 case sdma_event_e25_hw_clean_up_done:
2599 case sdma_event_e40_sw_cleaned:
2600 sdma_sw_tear_down(sde);
2602 case sdma_event_e50_hw_cleaned:
2604 case sdma_event_e60_hw_halted:
2606 case sdma_event_e70_go_idle:
2608 case sdma_event_e80_hw_freeze:
2610 case sdma_event_e81_hw_frozen:
2612 case sdma_event_e82_hw_unfreeze:
2614 case sdma_event_e85_link_down:
2616 case sdma_event_e90_sw_halted:
2621 case sdma_state_s10_hw_start_up_halt_wait:
2623 case sdma_event_e00_go_hw_down:
2624 sdma_set_state(sde, sdma_state_s00_hw_down);
2625 sdma_sw_tear_down(sde);
2627 case sdma_event_e10_go_hw_start:
2629 case sdma_event_e15_hw_halt_done:
2631 sdma_state_s15_hw_start_up_clean_wait);
2632 sdma_start_hw_clean_up(sde);
2634 case sdma_event_e25_hw_clean_up_done:
2636 case sdma_event_e30_go_running:
2637 ss->go_s99_running = 1;
2639 case sdma_event_e40_sw_cleaned:
2641 case sdma_event_e50_hw_cleaned:
2643 case sdma_event_e60_hw_halted:
2644 schedule_work(&sde->err_halt_worker);
2646 case sdma_event_e70_go_idle:
2647 ss->go_s99_running = 0;
2649 case sdma_event_e80_hw_freeze:
2651 case sdma_event_e81_hw_frozen:
2653 case sdma_event_e82_hw_unfreeze:
2655 case sdma_event_e85_link_down:
2657 case sdma_event_e90_sw_halted:
2662 case sdma_state_s15_hw_start_up_clean_wait:
2664 case sdma_event_e00_go_hw_down:
2665 sdma_set_state(sde, sdma_state_s00_hw_down);
2666 sdma_sw_tear_down(sde);
2668 case sdma_event_e10_go_hw_start:
2670 case sdma_event_e15_hw_halt_done:
2672 case sdma_event_e25_hw_clean_up_done:
2673 sdma_hw_start_up(sde);
2674 sdma_set_state(sde, ss->go_s99_running ?
2675 sdma_state_s99_running :
2676 sdma_state_s20_idle);
2678 case sdma_event_e30_go_running:
2679 ss->go_s99_running = 1;
2681 case sdma_event_e40_sw_cleaned:
2683 case sdma_event_e50_hw_cleaned:
2685 case sdma_event_e60_hw_halted:
2687 case sdma_event_e70_go_idle:
2688 ss->go_s99_running = 0;
2690 case sdma_event_e80_hw_freeze:
2692 case sdma_event_e81_hw_frozen:
2694 case sdma_event_e82_hw_unfreeze:
2696 case sdma_event_e85_link_down:
2698 case sdma_event_e90_sw_halted:
2703 case sdma_state_s20_idle:
2705 case sdma_event_e00_go_hw_down:
2706 sdma_set_state(sde, sdma_state_s00_hw_down);
2707 sdma_sw_tear_down(sde);
2709 case sdma_event_e10_go_hw_start:
2711 case sdma_event_e15_hw_halt_done:
2713 case sdma_event_e25_hw_clean_up_done:
2715 case sdma_event_e30_go_running:
2716 sdma_set_state(sde, sdma_state_s99_running);
2717 ss->go_s99_running = 1;
2719 case sdma_event_e40_sw_cleaned:
2721 case sdma_event_e50_hw_cleaned:
2723 case sdma_event_e60_hw_halted:
2724 sdma_set_state(sde, sdma_state_s50_hw_halt_wait);
2725 schedule_work(&sde->err_halt_worker);
2727 case sdma_event_e70_go_idle:
2729 case sdma_event_e85_link_down:
2731 case sdma_event_e80_hw_freeze:
2732 sdma_set_state(sde, sdma_state_s80_hw_freeze);
2733 atomic_dec(&sde->dd->sdma_unfreeze_count);
2734 wake_up_interruptible(&sde->dd->sdma_unfreeze_wq);
2736 case sdma_event_e81_hw_frozen:
2738 case sdma_event_e82_hw_unfreeze:
2740 case sdma_event_e90_sw_halted:
2745 case sdma_state_s30_sw_clean_up_wait:
2747 case sdma_event_e00_go_hw_down:
2748 sdma_set_state(sde, sdma_state_s00_hw_down);
2750 case sdma_event_e10_go_hw_start:
2752 case sdma_event_e15_hw_halt_done:
2754 case sdma_event_e25_hw_clean_up_done:
2756 case sdma_event_e30_go_running:
2757 ss->go_s99_running = 1;
2759 case sdma_event_e40_sw_cleaned:
2760 sdma_set_state(sde, sdma_state_s40_hw_clean_up_wait);
2761 sdma_start_hw_clean_up(sde);
2763 case sdma_event_e50_hw_cleaned:
2765 case sdma_event_e60_hw_halted:
2767 case sdma_event_e70_go_idle:
2768 ss->go_s99_running = 0;
2770 case sdma_event_e80_hw_freeze:
2772 case sdma_event_e81_hw_frozen:
2774 case sdma_event_e82_hw_unfreeze:
2776 case sdma_event_e85_link_down:
2777 ss->go_s99_running = 0;
2779 case sdma_event_e90_sw_halted:
2784 case sdma_state_s40_hw_clean_up_wait:
2786 case sdma_event_e00_go_hw_down:
2787 sdma_set_state(sde, sdma_state_s00_hw_down);
2788 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
2790 case sdma_event_e10_go_hw_start:
2792 case sdma_event_e15_hw_halt_done:
2794 case sdma_event_e25_hw_clean_up_done:
2795 sdma_hw_start_up(sde);
2796 sdma_set_state(sde, ss->go_s99_running ?
2797 sdma_state_s99_running :
2798 sdma_state_s20_idle);
2800 case sdma_event_e30_go_running:
2801 ss->go_s99_running = 1;
2803 case sdma_event_e40_sw_cleaned:
2805 case sdma_event_e50_hw_cleaned:
2807 case sdma_event_e60_hw_halted:
2809 case sdma_event_e70_go_idle:
2810 ss->go_s99_running = 0;
2812 case sdma_event_e80_hw_freeze:
2814 case sdma_event_e81_hw_frozen:
2816 case sdma_event_e82_hw_unfreeze:
2818 case sdma_event_e85_link_down:
2819 ss->go_s99_running = 0;
2821 case sdma_event_e90_sw_halted:
2826 case sdma_state_s50_hw_halt_wait:
2828 case sdma_event_e00_go_hw_down:
2829 sdma_set_state(sde, sdma_state_s00_hw_down);
2830 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
2832 case sdma_event_e10_go_hw_start:
2834 case sdma_event_e15_hw_halt_done:
2835 sdma_set_state(sde, sdma_state_s30_sw_clean_up_wait);
2836 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
2838 case sdma_event_e25_hw_clean_up_done:
2840 case sdma_event_e30_go_running:
2841 ss->go_s99_running = 1;
2843 case sdma_event_e40_sw_cleaned:
2845 case sdma_event_e50_hw_cleaned:
2847 case sdma_event_e60_hw_halted:
2848 schedule_work(&sde->err_halt_worker);
2850 case sdma_event_e70_go_idle:
2851 ss->go_s99_running = 0;
2853 case sdma_event_e80_hw_freeze:
2855 case sdma_event_e81_hw_frozen:
2857 case sdma_event_e82_hw_unfreeze:
2859 case sdma_event_e85_link_down:
2860 ss->go_s99_running = 0;
2862 case sdma_event_e90_sw_halted:
2867 case sdma_state_s60_idle_halt_wait:
2869 case sdma_event_e00_go_hw_down:
2870 sdma_set_state(sde, sdma_state_s00_hw_down);
2871 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
2873 case sdma_event_e10_go_hw_start:
2875 case sdma_event_e15_hw_halt_done:
2876 sdma_set_state(sde, sdma_state_s30_sw_clean_up_wait);
2877 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
2879 case sdma_event_e25_hw_clean_up_done:
2881 case sdma_event_e30_go_running:
2882 ss->go_s99_running = 1;
2884 case sdma_event_e40_sw_cleaned:
2886 case sdma_event_e50_hw_cleaned:
2888 case sdma_event_e60_hw_halted:
2889 schedule_work(&sde->err_halt_worker);
2891 case sdma_event_e70_go_idle:
2892 ss->go_s99_running = 0;
2894 case sdma_event_e80_hw_freeze:
2896 case sdma_event_e81_hw_frozen:
2898 case sdma_event_e82_hw_unfreeze:
2900 case sdma_event_e85_link_down:
2902 case sdma_event_e90_sw_halted:
2907 case sdma_state_s80_hw_freeze:
2909 case sdma_event_e00_go_hw_down:
2910 sdma_set_state(sde, sdma_state_s00_hw_down);
2911 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
2913 case sdma_event_e10_go_hw_start:
2915 case sdma_event_e15_hw_halt_done:
2917 case sdma_event_e25_hw_clean_up_done:
2919 case sdma_event_e30_go_running:
2920 ss->go_s99_running = 1;
2922 case sdma_event_e40_sw_cleaned:
2924 case sdma_event_e50_hw_cleaned:
2926 case sdma_event_e60_hw_halted:
2928 case sdma_event_e70_go_idle:
2929 ss->go_s99_running = 0;
2931 case sdma_event_e80_hw_freeze:
2933 case sdma_event_e81_hw_frozen:
2934 sdma_set_state(sde, sdma_state_s82_freeze_sw_clean);
2935 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
2937 case sdma_event_e82_hw_unfreeze:
2939 case sdma_event_e85_link_down:
2941 case sdma_event_e90_sw_halted:
2946 case sdma_state_s82_freeze_sw_clean:
2948 case sdma_event_e00_go_hw_down:
2949 sdma_set_state(sde, sdma_state_s00_hw_down);
2950 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
2952 case sdma_event_e10_go_hw_start:
2954 case sdma_event_e15_hw_halt_done:
2956 case sdma_event_e25_hw_clean_up_done:
2958 case sdma_event_e30_go_running:
2959 ss->go_s99_running = 1;
2961 case sdma_event_e40_sw_cleaned:
2962 /* notify caller this engine is done cleaning */
2963 atomic_dec(&sde->dd->sdma_unfreeze_count);
2964 wake_up_interruptible(&sde->dd->sdma_unfreeze_wq);
2966 case sdma_event_e50_hw_cleaned:
2968 case sdma_event_e60_hw_halted:
2970 case sdma_event_e70_go_idle:
2971 ss->go_s99_running = 0;
2973 case sdma_event_e80_hw_freeze:
2975 case sdma_event_e81_hw_frozen:
2977 case sdma_event_e82_hw_unfreeze:
2978 sdma_hw_start_up(sde);
2979 sdma_set_state(sde, ss->go_s99_running ?
2980 sdma_state_s99_running :
2981 sdma_state_s20_idle);
2983 case sdma_event_e85_link_down:
2985 case sdma_event_e90_sw_halted:
2990 case sdma_state_s99_running:
2992 case sdma_event_e00_go_hw_down:
2993 sdma_set_state(sde, sdma_state_s00_hw_down);
2994 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
2996 case sdma_event_e10_go_hw_start:
2998 case sdma_event_e15_hw_halt_done:
3000 case sdma_event_e25_hw_clean_up_done:
3002 case sdma_event_e30_go_running:
3004 case sdma_event_e40_sw_cleaned:
3006 case sdma_event_e50_hw_cleaned:
3008 case sdma_event_e60_hw_halted:
3010 sdma_err_progress_check_schedule(sde);
3012 case sdma_event_e90_sw_halted:
3014 * SW initiated halt does not perform engines
3017 sdma_set_state(sde, sdma_state_s50_hw_halt_wait);
3018 schedule_work(&sde->err_halt_worker);
3020 case sdma_event_e70_go_idle:
3021 sdma_set_state(sde, sdma_state_s60_idle_halt_wait);
3023 case sdma_event_e85_link_down:
3024 ss->go_s99_running = 0;
3026 case sdma_event_e80_hw_freeze:
3027 sdma_set_state(sde, sdma_state_s80_hw_freeze);
3028 atomic_dec(&sde->dd->sdma_unfreeze_count);
3029 wake_up_interruptible(&sde->dd->sdma_unfreeze_wq);
3031 case sdma_event_e81_hw_frozen:
3033 case sdma_event_e82_hw_unfreeze:
3039 ss->last_event = event;
3041 sdma_make_progress(sde, 0);
3045 * _extend_sdma_tx_descs() - helper to extend txreq
3047 * This is called once the initial nominal allocation
3048 * of descriptors in the sdma_txreq is exhausted.
3050 * The code will bump the allocation up to the max
3051 * of MAX_DESC (64) descriptors. There doesn't seem
3052 * much point in an interim step. The last descriptor
3053 * is reserved for coalesce buffer in order to support
3054 * cases where input packet has >MAX_DESC iovecs.
3057 static int _extend_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx)
3060 struct sdma_desc *descp;
3062 /* Handle last descriptor */
3063 if (unlikely((tx->num_desc == (MAX_DESC - 1)))) {
3064 /* if tlen is 0, it is for padding, release last descriptor */
3066 tx->desc_limit = MAX_DESC;
3067 } else if (!tx->coalesce_buf) {
3068 /* allocate coalesce buffer with space for padding */
3069 tx->coalesce_buf = kmalloc(tx->tlen + sizeof(u32),
3071 if (!tx->coalesce_buf)
3073 tx->coalesce_idx = 0;
3078 if (unlikely(tx->num_desc == MAX_DESC))
3081 descp = kmalloc_array(MAX_DESC, sizeof(struct sdma_desc), GFP_ATOMIC);
3086 /* reserve last descriptor for coalescing */
3087 tx->desc_limit = MAX_DESC - 1;
3088 /* copy ones already built */
3089 for (i = 0; i < tx->num_desc; i++)
3090 tx->descp[i] = tx->descs[i];
3093 __sdma_txclean(dd, tx);
3098 * ext_coal_sdma_tx_descs() - extend or coalesce sdma tx descriptors
3100 * This is called once the initial nominal allocation of descriptors
3101 * in the sdma_txreq is exhausted.
3103 * This function calls _extend_sdma_tx_descs to extend or allocate
3104 * coalesce buffer. If there is a allocated coalesce buffer, it will
3105 * copy the input packet data into the coalesce buffer. It also adds
3106 * coalesce buffer descriptor once when whole packet is received.
3110 * 0 - coalescing, don't populate descriptor
3111 * 1 - continue with populating descriptor
3113 int ext_coal_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx,
3114 int type, void *kvaddr, struct page *page,
3115 unsigned long offset, u16 len)
3120 rval = _extend_sdma_tx_descs(dd, tx);
3122 __sdma_txclean(dd, tx);
3126 /* If coalesce buffer is allocated, copy data into it */
3127 if (tx->coalesce_buf) {
3128 if (type == SDMA_MAP_NONE) {
3129 __sdma_txclean(dd, tx);
3133 if (type == SDMA_MAP_PAGE) {
3134 kvaddr = kmap(page);
3136 } else if (WARN_ON(!kvaddr)) {
3137 __sdma_txclean(dd, tx);
3141 memcpy(tx->coalesce_buf + tx->coalesce_idx, kvaddr, len);
3142 tx->coalesce_idx += len;
3143 if (type == SDMA_MAP_PAGE)
3146 /* If there is more data, return */
3147 if (tx->tlen - tx->coalesce_idx)
3150 /* Whole packet is received; add any padding */
3151 pad_len = tx->packet_len & (sizeof(u32) - 1);
3153 pad_len = sizeof(u32) - pad_len;
3154 memset(tx->coalesce_buf + tx->coalesce_idx, 0, pad_len);
3155 /* padding is taken care of for coalescing case */
3156 tx->packet_len += pad_len;
3157 tx->tlen += pad_len;
3160 /* dma map the coalesce buffer */
3161 addr = dma_map_single(&dd->pcidev->dev,
3166 if (unlikely(dma_mapping_error(&dd->pcidev->dev, addr))) {
3167 __sdma_txclean(dd, tx);
3171 /* Add descriptor for coalesce buffer */
3172 tx->desc_limit = MAX_DESC;
3173 return _sdma_txadd_daddr(dd, SDMA_MAP_SINGLE, tx,
3180 /* Update sdes when the lmc changes */
3181 void sdma_update_lmc(struct hfi1_devdata *dd, u64 mask, u32 lid)
3183 struct sdma_engine *sde;
3187 sreg = ((mask & SD(CHECK_SLID_MASK_MASK)) <<
3188 SD(CHECK_SLID_MASK_SHIFT)) |
3189 (((lid & mask) & SD(CHECK_SLID_VALUE_MASK)) <<
3190 SD(CHECK_SLID_VALUE_SHIFT));
3192 for (i = 0; i < dd->num_sdma; i++) {
3193 hfi1_cdbg(LINKVERB, "SendDmaEngine[%d].SLID_CHECK = 0x%x",
3195 sde = &dd->per_sdma[i];
3196 write_sde_csr(sde, SD(CHECK_SLID), sreg);
3200 /* tx not dword sized - pad */
3201 int _pad_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx)
3206 if ((unlikely(tx->num_desc == tx->desc_limit))) {
3207 rval = _extend_sdma_tx_descs(dd, tx);
3209 __sdma_txclean(dd, tx);
3213 /* finish the one just added */
3218 sizeof(u32) - (tx->packet_len & (sizeof(u32) - 1)));
3219 _sdma_close_tx(dd, tx);
3224 * Add ahg to the sdma_txreq
3226 * The logic will consume up to 3
3227 * descriptors at the beginning of
3230 void _sdma_txreq_ahgadd(
3231 struct sdma_txreq *tx,
3237 u32 i, shift = 0, desc = 0;
3240 WARN_ON_ONCE(num_ahg > 9 || (ahg_hlen & 3) || ahg_hlen == 4);
3243 mode = SDMA_AHG_APPLY_UPDATE1;
3244 else if (num_ahg <= 5)
3245 mode = SDMA_AHG_APPLY_UPDATE2;
3247 mode = SDMA_AHG_APPLY_UPDATE3;
3249 /* initialize to consumed descriptors to zero */
3251 case SDMA_AHG_APPLY_UPDATE3:
3253 tx->descs[2].qw[0] = 0;
3254 tx->descs[2].qw[1] = 0;
3256 case SDMA_AHG_APPLY_UPDATE2:
3258 tx->descs[1].qw[0] = 0;
3259 tx->descs[1].qw[1] = 0;
3263 tx->descs[0].qw[1] |=
3264 (((u64)ahg_entry & SDMA_DESC1_HEADER_INDEX_MASK)
3265 << SDMA_DESC1_HEADER_INDEX_SHIFT) |
3266 (((u64)ahg_hlen & SDMA_DESC1_HEADER_DWS_MASK)
3267 << SDMA_DESC1_HEADER_DWS_SHIFT) |
3268 (((u64)mode & SDMA_DESC1_HEADER_MODE_MASK)
3269 << SDMA_DESC1_HEADER_MODE_SHIFT) |
3270 (((u64)ahg[0] & SDMA_DESC1_HEADER_UPDATE1_MASK)
3271 << SDMA_DESC1_HEADER_UPDATE1_SHIFT);
3272 for (i = 0; i < (num_ahg - 1); i++) {
3273 if (!shift && !(i & 2))
3275 tx->descs[desc].qw[!!(i & 2)] |=
3278 shift = (shift + 32) & 63;
3283 * sdma_ahg_alloc - allocate an AHG entry
3284 * @sde: engine to allocate from
3287 * 0-31 when successful, -EOPNOTSUPP if AHG is not enabled,
3288 * -ENOSPC if an entry is not available
3290 int sdma_ahg_alloc(struct sdma_engine *sde)
3296 trace_hfi1_ahg_allocate(sde, -EINVAL);
3300 nr = ffz(READ_ONCE(sde->ahg_bits));
3302 trace_hfi1_ahg_allocate(sde, -ENOSPC);
3305 oldbit = test_and_set_bit(nr, &sde->ahg_bits);
3310 trace_hfi1_ahg_allocate(sde, nr);
3315 * sdma_ahg_free - free an AHG entry
3316 * @sde: engine to return AHG entry
3317 * @ahg_index: index to free
3319 * This routine frees the indicate AHG entry.
3321 void sdma_ahg_free(struct sdma_engine *sde, int ahg_index)
3325 trace_hfi1_ahg_deallocate(sde, ahg_index);
3326 if (ahg_index < 0 || ahg_index > 31)
3328 clear_bit(ahg_index, &sde->ahg_bits);
3332 * SPC freeze handling for SDMA engines. Called when the driver knows
3333 * the SPC is going into a freeze but before the freeze is fully
3334 * settled. Generally an error interrupt.
3336 * This event will pull the engine out of running so no more entries can be
3337 * added to the engine's queue.
3339 void sdma_freeze_notify(struct hfi1_devdata *dd, int link_down)
3342 enum sdma_events event = link_down ? sdma_event_e85_link_down :
3343 sdma_event_e80_hw_freeze;
3345 /* set up the wait but do not wait here */
3346 atomic_set(&dd->sdma_unfreeze_count, dd->num_sdma);
3348 /* tell all engines to stop running and wait */
3349 for (i = 0; i < dd->num_sdma; i++)
3350 sdma_process_event(&dd->per_sdma[i], event);
3352 /* sdma_freeze() will wait for all engines to have stopped */
3356 * SPC freeze handling for SDMA engines. Called when the driver knows
3357 * the SPC is fully frozen.
3359 void sdma_freeze(struct hfi1_devdata *dd)
3365 * Make sure all engines have moved out of the running state before
3368 ret = wait_event_interruptible(dd->sdma_unfreeze_wq,
3369 atomic_read(&dd->sdma_unfreeze_count) <=
3371 /* interrupted or count is negative, then unloading - just exit */
3372 if (ret || atomic_read(&dd->sdma_unfreeze_count) < 0)
3375 /* set up the count for the next wait */
3376 atomic_set(&dd->sdma_unfreeze_count, dd->num_sdma);
3378 /* tell all engines that the SPC is frozen, they can start cleaning */
3379 for (i = 0; i < dd->num_sdma; i++)
3380 sdma_process_event(&dd->per_sdma[i], sdma_event_e81_hw_frozen);
3383 * Wait for everyone to finish software clean before exiting. The
3384 * software clean will read engine CSRs, so must be completed before
3385 * the next step, which will clear the engine CSRs.
3387 (void)wait_event_interruptible(dd->sdma_unfreeze_wq,
3388 atomic_read(&dd->sdma_unfreeze_count) <= 0);
3389 /* no need to check results - done no matter what */
3393 * SPC freeze handling for the SDMA engines. Called after the SPC is unfrozen.
3395 * The SPC freeze acts like a SDMA halt and a hardware clean combined. All
3396 * that is left is a software clean. We could do it after the SPC is fully
3397 * frozen, but then we'd have to add another state to wait for the unfreeze.
3398 * Instead, just defer the software clean until the unfreeze step.
3400 void sdma_unfreeze(struct hfi1_devdata *dd)
3404 /* tell all engines start freeze clean up */
3405 for (i = 0; i < dd->num_sdma; i++)
3406 sdma_process_event(&dd->per_sdma[i],
3407 sdma_event_e82_hw_unfreeze);
3411 * _sdma_engine_progress_schedule() - schedule progress on engine
3412 * @sde: sdma_engine to schedule progress
3415 void _sdma_engine_progress_schedule(
3416 struct sdma_engine *sde)
3418 trace_hfi1_sdma_engine_progress(sde, sde->progress_mask);
3419 /* assume we have selected a good cpu */
3421 CCE_INT_FORCE + (8 * (IS_SDMA_START / 64)),
3422 sde->progress_mask);