1 #ifndef _HFI1_USER_SDMA_H
2 #define _HFI1_USER_SDMA_H
4 * Copyright(c) 2015 - 2017 Intel Corporation.
6 * This file is provided under a dual BSD/GPLv2 license. When using or
7 * redistributing this file, you may do so under either license.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions
26 * - Redistributions of source code must retain the above copyright
27 * notice, this list of conditions and the following disclaimer.
28 * - Redistributions in binary form must reproduce the above copyright
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36 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
37 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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49 #include <linux/device.h>
50 #include <linux/wait.h>
54 #include "user_exp_rcv.h"
56 /* The maximum number of Data io vectors per message/request */
57 #define MAX_VECTORS_PER_REQ 8
59 * Maximum number of packet to send from each message/request
60 * before moving to the next one.
62 #define MAX_PKTS_PER_QUEUE 16
64 #define num_pages(x) (1 + ((((x) - 1) & PAGE_MASK) >> PAGE_SHIFT))
66 #define req_opcode(x) \
67 (((x) >> HFI1_SDMA_REQ_OPCODE_SHIFT) & HFI1_SDMA_REQ_OPCODE_MASK)
68 #define req_version(x) \
69 (((x) >> HFI1_SDMA_REQ_VERSION_SHIFT) & HFI1_SDMA_REQ_OPCODE_MASK)
70 #define req_iovcnt(x) \
71 (((x) >> HFI1_SDMA_REQ_IOVCNT_SHIFT) & HFI1_SDMA_REQ_IOVCNT_MASK)
73 /* Number of BTH.PSN bits used for sequence number in expected rcvs */
74 #define BTH_SEQ_MASK 0x7ffull
76 #define AHG_KDETH_INTR_SHIFT 12
77 #define AHG_KDETH_SH_SHIFT 13
78 #define AHG_KDETH_ARRAY_SIZE 9
80 #define PBC2LRH(x) ((((x) & 0xfff) << 2) - 4)
81 #define LRH2PBC(x) ((((x) >> 2) + 1) & 0xfff)
83 #define AHG_HEADER_SET(arr, idx, dw, bit, width, value) \
85 if ((idx) < ARRAY_SIZE((arr))) \
86 (arr)[(idx++)] = sdma_build_ahg_descriptor( \
87 (__force u16)(value), (dw), (bit), \
93 /* Tx request flag bits */
94 #define TXREQ_FLAGS_REQ_ACK BIT(0) /* Set the ACK bit in the header */
95 #define TXREQ_FLAGS_REQ_DISABLE_SH BIT(1) /* Disable header suppression */
97 enum pkt_q_sdma_state {
103 * Maximum retry attempts to submit a TX request
104 * before putting the process to sleep.
106 #define MAX_DEFER_RETRY_COUNT 1
108 #define SDMA_IOWAIT_TIMEOUT 1000 /* in milliseconds */
110 #define SDMA_DBG(req, fmt, ...) \
111 hfi1_cdbg(SDMA, "[%u:%u:%u:%u] " fmt, (req)->pq->dd->unit, \
112 (req)->pq->ctxt, (req)->pq->subctxt, (req)->info.comp_idx, \
115 extern uint extended_psn;
117 struct hfi1_user_sdma_pkt_q {
123 struct hfi1_devdata *dd;
124 struct kmem_cache *txreq_cache;
125 struct user_sdma_request *reqs;
126 unsigned long *req_in_use;
128 enum pkt_q_sdma_state state;
129 wait_queue_head_t wait;
130 unsigned long unpinned;
131 struct mmu_rb_handler *handler;
133 struct mm_struct *mm;
136 struct hfi1_user_sdma_comp_q {
138 struct hfi1_sdma_comp_entry *comps;
141 struct sdma_mmu_node {
142 struct mmu_rb_node rb;
143 struct hfi1_user_sdma_pkt_q *pq;
149 struct user_sdma_iovec {
150 struct list_head list;
152 /* number of pages in this vector */
154 /* array of pinned pages for this vector */
157 * offset into the virtual address space of the vector at
158 * which we last left off.
161 struct sdma_mmu_node *node;
164 /* evict operation argument */
166 u32 cleared; /* count evicted so far */
167 u32 target; /* target count to evict */
170 struct user_sdma_request {
171 /* This is the original header from user space */
172 struct hfi1_pkt_header hdr;
174 /* Read mostly fields */
175 struct hfi1_user_sdma_pkt_q *pq ____cacheline_aligned_in_smp;
176 struct hfi1_user_sdma_comp_q *cq;
178 * Pointer to the SDMA engine for this request.
179 * Since different request could be on different VLs,
180 * each request will need it's own engine pointer.
182 struct sdma_engine *sde;
183 struct sdma_req_info info;
184 /* TID array values copied from the tid_iov vector */
186 /* total length of the data in the request */
188 /* number of elements copied to the tids array */
191 * We copy the iovs for this request (based on
192 * info.iovcnt). These are only the data vectors
197 /* Writeable fields shared with interrupt */
198 u64 seqcomp ____cacheline_aligned_in_smp;
201 /* Send side fields */
202 struct list_head txps ____cacheline_aligned_in_smp;
205 * KDETH.OFFSET (TID) field
206 * The offset can cover multiple packets, depending on the
207 * size of the TID entry.
211 * KDETH.Offset (Eager) field
212 * We need to remember the initial value so the headers
213 * can be updated properly.
217 /* TID index copied from the tid_iov vector */
219 /* progress index moving along the iovs array */
223 struct user_sdma_iovec iovs[MAX_VECTORS_PER_REQ];
224 } ____cacheline_aligned_in_smp;
227 * A single txreq could span up to 3 physical pages when the MTU
228 * is sufficiently large (> 4K). Each of the IOV pointers also
229 * needs it's own set of flags so the vector has been handled
230 * independently of each other.
232 struct user_sdma_txreq {
233 /* Packet header for the txreq */
234 struct hfi1_pkt_header hdr;
235 struct sdma_txreq txreq;
236 struct list_head list;
237 struct user_sdma_request *req;
242 int hfi1_user_sdma_alloc_queues(struct hfi1_ctxtdata *uctxt,
243 struct hfi1_filedata *fd);
244 int hfi1_user_sdma_free_queues(struct hfi1_filedata *fd,
245 struct hfi1_ctxtdata *uctxt);
246 int hfi1_user_sdma_process_request(struct hfi1_filedata *fd,
247 struct iovec *iovec, unsigned long dim,
248 unsigned long *count);
250 #endif /* _HFI1_USER_SDMA_H */