drivers/infiniband/hw/hns/hns_roce_hw_v1.c

   1 /*
   2  * Copyright (c) 2016 Hisilicon Limited.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/platform_device.h>
  34 #include <linux/acpi.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/of.h>
  37 #include <rdma/ib_umem.h>
  38 #include "hns_roce_common.h"
  39 #include "hns_roce_device.h"
  40 #include "hns_roce_cmd.h"
  41 #include "hns_roce_hem.h"
  42 #include "hns_roce_hw_v1.h"
  43
  44 static void set_data_seg(struct hns_roce_wqe_data_seg *dseg, struct ib_sge *sg)
  45 {
  46         dseg->lkey = cpu_to_le32(sg->lkey);
  47         dseg->addr = cpu_to_le64(sg->addr);
  48         dseg->len  = cpu_to_le32(sg->length);
  49 }
  50
  51 static void set_raddr_seg(struct hns_roce_wqe_raddr_seg *rseg, u64 remote_addr,
  52                           u32 rkey)
  53 {
  54         rseg->raddr = cpu_to_le64(remote_addr);
  55         rseg->rkey  = cpu_to_le32(rkey);
  56         rseg->len   = 0;
  57 }
  58
  59 int hns_roce_v1_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
  60                           struct ib_send_wr **bad_wr)
  61 {
  62         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
  63         struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
  64         struct hns_roce_ud_send_wqe *ud_sq_wqe = NULL;
  65         struct hns_roce_wqe_ctrl_seg *ctrl = NULL;
  66         struct hns_roce_wqe_data_seg *dseg = NULL;
  67         struct hns_roce_qp *qp = to_hr_qp(ibqp);
  68         struct device *dev = &hr_dev->pdev->dev;
  69         struct hns_roce_sq_db sq_db;
  70         int ps_opcode = 0, i = 0;
  71         unsigned long flags = 0;
  72         void *wqe = NULL;
  73         u32 doorbell[2];
  74         int nreq = 0;
  75         u32 ind = 0;
  76         int ret = 0;
  77         u8 *smac;
  78         int loopback;
  79
  80         if (unlikely(ibqp->qp_type != IB_QPT_GSI &&
  81                 ibqp->qp_type != IB_QPT_RC)) {
  82                 dev_err(dev, "un-supported QP type\n");
  83                 *bad_wr = NULL;
  84                 return -EOPNOTSUPP;
  85         }
  86
  87         spin_lock_irqsave(&qp->sq.lock, flags);
  88         ind = qp->sq_next_wqe;
  89         for (nreq = 0; wr; ++nreq, wr = wr->next) {
  90                 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
  91                         ret = -ENOMEM;
  92                         *bad_wr = wr;
  93                         goto out;
  94                 }
  95
  96                 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
  97                         dev_err(dev, "num_sge=%d > qp->sq.max_gs=%d\n",
  98                                 wr->num_sge, qp->sq.max_gs);
  99                         ret = -EINVAL;
 100                         *bad_wr = wr;
 101                         goto out;
 102                 }
 103
 104                 wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
 105                 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] =
 106                                                                       wr->wr_id;
 107
 108                 /* Corresponding to the RC and RD type wqe process separately */
 109                 if (ibqp->qp_type == IB_QPT_GSI) {
 110                         ud_sq_wqe = wqe;
 111                         roce_set_field(ud_sq_wqe->dmac_h,
 112                                        UD_SEND_WQE_U32_4_DMAC_0_M,
 113                                        UD_SEND_WQE_U32_4_DMAC_0_S,
 114                                        ah->av.mac[0]);
 115                         roce_set_field(ud_sq_wqe->dmac_h,
 116                                        UD_SEND_WQE_U32_4_DMAC_1_M,
 117                                        UD_SEND_WQE_U32_4_DMAC_1_S,
 118                                        ah->av.mac[1]);
 119                         roce_set_field(ud_sq_wqe->dmac_h,
 120                                        UD_SEND_WQE_U32_4_DMAC_2_M,
 121                                        UD_SEND_WQE_U32_4_DMAC_2_S,
 122                                        ah->av.mac[2]);
 123                         roce_set_field(ud_sq_wqe->dmac_h,
 124                                        UD_SEND_WQE_U32_4_DMAC_3_M,
 125                                        UD_SEND_WQE_U32_4_DMAC_3_S,
 126                                        ah->av.mac[3]);
 127
 128                         roce_set_field(ud_sq_wqe->u32_8,
 129                                        UD_SEND_WQE_U32_8_DMAC_4_M,
 130                                        UD_SEND_WQE_U32_8_DMAC_4_S,
 131                                        ah->av.mac[4]);
 132                         roce_set_field(ud_sq_wqe->u32_8,
 133                                        UD_SEND_WQE_U32_8_DMAC_5_M,
 134                                        UD_SEND_WQE_U32_8_DMAC_5_S,
 135                                        ah->av.mac[5]);
 136
 137                         smac = (u8 *)hr_dev->dev_addr[qp->port];
 138                         loopback = ether_addr_equal_unaligned(ah->av.mac,
 139                                                               smac) ? 1 : 0;
 140                         roce_set_bit(ud_sq_wqe->u32_8,
 141                                      UD_SEND_WQE_U32_8_LOOPBACK_INDICATOR_S,
 142                                      loopback);
 143
 144                         roce_set_field(ud_sq_wqe->u32_8,
 145                                        UD_SEND_WQE_U32_8_OPERATION_TYPE_M,
 146                                        UD_SEND_WQE_U32_8_OPERATION_TYPE_S,
 147                                        HNS_ROCE_WQE_OPCODE_SEND);
 148                         roce_set_field(ud_sq_wqe->u32_8,
 149                                        UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_M,
 150                                        UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_S,
 151                                        2);
 152                         roce_set_bit(ud_sq_wqe->u32_8,
 153                                 UD_SEND_WQE_U32_8_SEND_GL_ROUTING_HDR_FLAG_S,
 154                                 1);
 155
 156                         ud_sq_wqe->u32_8 |= (wr->send_flags & IB_SEND_SIGNALED ?
 157                                 cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
 158                                 (wr->send_flags & IB_SEND_SOLICITED ?
 159                                 cpu_to_le32(HNS_ROCE_WQE_SE) : 0) |
 160                                 ((wr->opcode == IB_WR_SEND_WITH_IMM) ?
 161                                 cpu_to_le32(HNS_ROCE_WQE_IMM) : 0);
 162
 163                         roce_set_field(ud_sq_wqe->u32_16,
 164                                        UD_SEND_WQE_U32_16_DEST_QP_M,
 165                                        UD_SEND_WQE_U32_16_DEST_QP_S,
 166                                        ud_wr(wr)->remote_qpn);
 167                         roce_set_field(ud_sq_wqe->u32_16,
 168                                        UD_SEND_WQE_U32_16_MAX_STATIC_RATE_M,
 169                                        UD_SEND_WQE_U32_16_MAX_STATIC_RATE_S,
 170                                        ah->av.stat_rate);
 171
 172                         roce_set_field(ud_sq_wqe->u32_36,
 173                                        UD_SEND_WQE_U32_36_FLOW_LABEL_M,
 174                                        UD_SEND_WQE_U32_36_FLOW_LABEL_S, 0);
 175                         roce_set_field(ud_sq_wqe->u32_36,
 176                                        UD_SEND_WQE_U32_36_PRIORITY_M,
 177                                        UD_SEND_WQE_U32_36_PRIORITY_S,
 178                                        ah->av.sl_tclass_flowlabel >>
 179                                        HNS_ROCE_SL_SHIFT);
 180                         roce_set_field(ud_sq_wqe->u32_36,
 181                                        UD_SEND_WQE_U32_36_SGID_INDEX_M,
 182                                        UD_SEND_WQE_U32_36_SGID_INDEX_S,
 183                                        hns_get_gid_index(hr_dev, qp->phy_port,
 184                                                          ah->av.gid_index));
 185
 186                         roce_set_field(ud_sq_wqe->u32_40,
 187                                        UD_SEND_WQE_U32_40_HOP_LIMIT_M,
 188                                        UD_SEND_WQE_U32_40_HOP_LIMIT_S,
 189                                        ah->av.hop_limit);
 190                         roce_set_field(ud_sq_wqe->u32_40,
 191                                        UD_SEND_WQE_U32_40_TRAFFIC_CLASS_M,
 192                                        UD_SEND_WQE_U32_40_TRAFFIC_CLASS_S, 0);
 193
 194                         memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0], GID_LEN);
 195
 196                         ud_sq_wqe->va0_l = (u32)wr->sg_list[0].addr;
 197                         ud_sq_wqe->va0_h = (wr->sg_list[0].addr) >> 32;
 198                         ud_sq_wqe->l_key0 = wr->sg_list[0].lkey;
 199
 200                         ud_sq_wqe->va1_l = (u32)wr->sg_list[1].addr;
 201                         ud_sq_wqe->va1_h = (wr->sg_list[1].addr) >> 32;
 202                         ud_sq_wqe->l_key1 = wr->sg_list[1].lkey;
 203                         ind++;
 204                 } else if (ibqp->qp_type == IB_QPT_RC) {
 205                         ctrl = wqe;
 206                         memset(ctrl, 0, sizeof(struct hns_roce_wqe_ctrl_seg));
 207                         for (i = 0; i < wr->num_sge; i++)
 208                                 ctrl->msg_length += wr->sg_list[i].length;
 209
 210                         ctrl->sgl_pa_h = 0;
 211                         ctrl->flag = 0;
 212                         ctrl->imm_data = send_ieth(wr);
 213
 214                         /*Ctrl field, ctrl set type: sig, solic, imm, fence */
 215                         /* SO wait for conforming application scenarios */
 216                         ctrl->flag |= (wr->send_flags & IB_SEND_SIGNALED ?
 217                                       cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
 218                                       (wr->send_flags & IB_SEND_SOLICITED ?
 219                                       cpu_to_le32(HNS_ROCE_WQE_SE) : 0) |
 220                                       ((wr->opcode == IB_WR_SEND_WITH_IMM ||
 221                                       wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) ?
 222                                       cpu_to_le32(HNS_ROCE_WQE_IMM) : 0) |
 223                                       (wr->send_flags & IB_SEND_FENCE ?
 224                                       (cpu_to_le32(HNS_ROCE_WQE_FENCE)) : 0);
 225
 226                         wqe += sizeof(struct hns_roce_wqe_ctrl_seg);
 227
 228                         switch (wr->opcode) {
 229                         case IB_WR_RDMA_READ:
 230                                 ps_opcode = HNS_ROCE_WQE_OPCODE_RDMA_READ;
 231                                 set_raddr_seg(wqe,  rdma_wr(wr)->remote_addr,
 232                                                rdma_wr(wr)->rkey);
 233                                 break;
 234                         case IB_WR_RDMA_WRITE:
 235                         case IB_WR_RDMA_WRITE_WITH_IMM:
 236                                 ps_opcode = HNS_ROCE_WQE_OPCODE_RDMA_WRITE;
 237                                 set_raddr_seg(wqe,  rdma_wr(wr)->remote_addr,
 238                                               rdma_wr(wr)->rkey);
 239                                 break;
 240                         case IB_WR_SEND:
 241                         case IB_WR_SEND_WITH_INV:
 242                         case IB_WR_SEND_WITH_IMM:
 243                                 ps_opcode = HNS_ROCE_WQE_OPCODE_SEND;
 244                                 break;
 245                         case IB_WR_LOCAL_INV:
 246                         case IB_WR_ATOMIC_CMP_AND_SWP:
 247                         case IB_WR_ATOMIC_FETCH_AND_ADD:
 248                         case IB_WR_LSO:
 249                         default:
 250                                 ps_opcode = HNS_ROCE_WQE_OPCODE_MASK;
 251                                 break;
 252                         }
 253                         ctrl->flag |= cpu_to_le32(ps_opcode);
 254                         wqe += sizeof(struct hns_roce_wqe_raddr_seg);
 255
 256                         dseg = wqe;
 257                         if (wr->send_flags & IB_SEND_INLINE && wr->num_sge) {
 258                                 if (ctrl->msg_length >
 259                                         hr_dev->caps.max_sq_inline) {
 260                                         ret = -EINVAL;
 261                                         *bad_wr = wr;
 262                                         dev_err(dev, "inline len(1-%d)=%d, illegal",
 263                                                 ctrl->msg_length,
 264                                                 hr_dev->caps.max_sq_inline);
 265                                         goto out;
 266                                 }
 267                                 for (i = 0; i < wr->num_sge; i++) {
 268                                         memcpy(wqe, ((void *) (uintptr_t)
 269                                                wr->sg_list[i].addr),
 270                                                wr->sg_list[i].length);
 271                                         wqe += wr->sg_list[i].length;
 272                                 }
 273                                 ctrl->flag |= HNS_ROCE_WQE_INLINE;
 274                         } else {
 275                                 /*sqe num is two */
 276                                 for (i = 0; i < wr->num_sge; i++)
 277                                         set_data_seg(dseg + i, wr->sg_list + i);
 278
 279                                 ctrl->flag |= cpu_to_le32(wr->num_sge <<
 280                                               HNS_ROCE_WQE_SGE_NUM_BIT);
 281                         }
 282                         ind++;
 283                 }
 284         }
 285
 286 out:
 287         /* Set DB return */
 288         if (likely(nreq)) {
 289                 qp->sq.head += nreq;
 290                 /* Memory barrier */
 291                 wmb();
 292
 293                 sq_db.u32_4 = 0;
 294                 sq_db.u32_8 = 0;
 295                 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SQ_HEAD_M,
 296                                SQ_DOORBELL_U32_4_SQ_HEAD_S,
 297                               (qp->sq.head & ((qp->sq.wqe_cnt << 1) - 1)));
 298                 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SL_M,
 299                                SQ_DOORBELL_U32_4_SL_S, qp->sl);
 300                 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_PORT_M,
 301                                SQ_DOORBELL_U32_4_PORT_S, qp->phy_port);
 302                 roce_set_field(sq_db.u32_8, SQ_DOORBELL_U32_8_QPN_M,
 303                                SQ_DOORBELL_U32_8_QPN_S, qp->doorbell_qpn);
 304                 roce_set_bit(sq_db.u32_8, SQ_DOORBELL_HW_SYNC_S, 1);
 305
 306                 doorbell[0] = sq_db.u32_4;
 307                 doorbell[1] = sq_db.u32_8;
 308
 309                 hns_roce_write64_k(doorbell, qp->sq.db_reg_l);
 310                 qp->sq_next_wqe = ind;
 311         }
 312
 313         spin_unlock_irqrestore(&qp->sq.lock, flags);
 314
 315         return ret;
 316 }
 317
 318 int hns_roce_v1_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
 319                           struct ib_recv_wr **bad_wr)
 320 {
 321         int ret = 0;
 322         int nreq = 0;
 323         int ind = 0;
 324         int i = 0;
 325         u32 reg_val = 0;
 326         unsigned long flags = 0;
 327         struct hns_roce_rq_wqe_ctrl *ctrl = NULL;
 328         struct hns_roce_wqe_data_seg *scat = NULL;
 329         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
 330         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
 331         struct device *dev = &hr_dev->pdev->dev;
 332         struct hns_roce_rq_db rq_db;
 333         uint32_t doorbell[2] = {0};
 334
 335         spin_lock_irqsave(&hr_qp->rq.lock, flags);
 336         ind = hr_qp->rq.head & (hr_qp->rq.wqe_cnt - 1);
 337
 338         for (nreq = 0; wr; ++nreq, wr = wr->next) {
 339                 if (hns_roce_wq_overflow(&hr_qp->rq, nreq,
 340                         hr_qp->ibqp.recv_cq)) {
 341                         ret = -ENOMEM;
 342                         *bad_wr = wr;
 343                         goto out;
 344                 }
 345
 346                 if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) {
 347                         dev_err(dev, "rq:num_sge=%d > qp->sq.max_gs=%d\n",
 348                                 wr->num_sge, hr_qp->rq.max_gs);
 349                         ret = -EINVAL;
 350                         *bad_wr = wr;
 351                         goto out;
 352                 }
 353
 354                 ctrl = get_recv_wqe(hr_qp, ind);
 355
 356                 roce_set_field(ctrl->rwqe_byte_12,
 357                                RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_M,
 358                                RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_S,
 359                                wr->num_sge);
 360
 361                 scat = (struct hns_roce_wqe_data_seg *)(ctrl + 1);
 362
 363                 for (i = 0; i < wr->num_sge; i++)
 364                         set_data_seg(scat + i, wr->sg_list + i);
 365
 366                 hr_qp->rq.wrid[ind] = wr->wr_id;
 367
 368                 ind = (ind + 1) & (hr_qp->rq.wqe_cnt - 1);
 369         }
 370
 371 out:
 372         if (likely(nreq)) {
 373                 hr_qp->rq.head += nreq;
 374                 /* Memory barrier */
 375                 wmb();
 376
 377                 if (ibqp->qp_type == IB_QPT_GSI) {
 378                         /* SW update GSI rq header */
 379                         reg_val = roce_read(to_hr_dev(ibqp->device),
 380                                             ROCEE_QP1C_CFG3_0_REG +
 381                                             QP1C_CFGN_OFFSET * hr_qp->phy_port);
 382                         roce_set_field(reg_val,
 383                                        ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_M,
 384                                        ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_S,
 385                                        hr_qp->rq.head);
 386                         roce_write(to_hr_dev(ibqp->device),
 387                                    ROCEE_QP1C_CFG3_0_REG +
 388                                    QP1C_CFGN_OFFSET * hr_qp->phy_port, reg_val);
 389                 } else {
 390                         rq_db.u32_4 = 0;
 391                         rq_db.u32_8 = 0;
 392
 393                         roce_set_field(rq_db.u32_4, RQ_DOORBELL_U32_4_RQ_HEAD_M,
 394                                        RQ_DOORBELL_U32_4_RQ_HEAD_S,
 395                                        hr_qp->rq.head);
 396                         roce_set_field(rq_db.u32_8, RQ_DOORBELL_U32_8_QPN_M,
 397                                        RQ_DOORBELL_U32_8_QPN_S, hr_qp->qpn);
 398                         roce_set_field(rq_db.u32_8, RQ_DOORBELL_U32_8_CMD_M,
 399                                        RQ_DOORBELL_U32_8_CMD_S, 1);
 400                         roce_set_bit(rq_db.u32_8, RQ_DOORBELL_U32_8_HW_SYNC_S,
 401                                      1);
 402
 403                         doorbell[0] = rq_db.u32_4;
 404                         doorbell[1] = rq_db.u32_8;
 405
 406                         hns_roce_write64_k(doorbell, hr_qp->rq.db_reg_l);
 407                 }
 408         }
 409         spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
 410
 411         return ret;
 412 }
 413
 414 static void hns_roce_set_db_event_mode(struct hns_roce_dev *hr_dev,
 415                                        int sdb_mode, int odb_mode)
 416 {
 417         u32 val;
 418
 419         val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
 420         roce_set_bit(val, ROCEE_GLB_CFG_ROCEE_DB_SQ_MODE_S, sdb_mode);
 421         roce_set_bit(val, ROCEE_GLB_CFG_ROCEE_DB_OTH_MODE_S, odb_mode);
 422         roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
 423 }
 424
 425 static void hns_roce_set_db_ext_mode(struct hns_roce_dev *hr_dev, u32 sdb_mode,
 426                                      u32 odb_mode)
 427 {
 428         u32 val;
 429
 430         /* Configure SDB/ODB extend mode */
 431         val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
 432         roce_set_bit(val, ROCEE_GLB_CFG_SQ_EXT_DB_MODE_S, sdb_mode);
 433         roce_set_bit(val, ROCEE_GLB_CFG_OTH_EXT_DB_MODE_S, odb_mode);
 434         roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
 435 }
 436
 437 static void hns_roce_set_sdb(struct hns_roce_dev *hr_dev, u32 sdb_alept,
 438                              u32 sdb_alful)
 439 {
 440         u32 val;
 441
 442         /* Configure SDB */
 443         val = roce_read(hr_dev, ROCEE_DB_SQ_WL_REG);
 444         roce_set_field(val, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_M,
 445                        ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_S, sdb_alful);
 446         roce_set_field(val, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_M,
 447                        ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_S, sdb_alept);
 448         roce_write(hr_dev, ROCEE_DB_SQ_WL_REG, val);
 449 }
 450
 451 static void hns_roce_set_odb(struct hns_roce_dev *hr_dev, u32 odb_alept,
 452                              u32 odb_alful)
 453 {
 454         u32 val;
 455
 456         /* Configure ODB */
 457         val = roce_read(hr_dev, ROCEE_DB_OTHERS_WL_REG);
 458         roce_set_field(val, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_M,
 459                        ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_S, odb_alful);
 460         roce_set_field(val, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_M,
 461                        ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_S, odb_alept);
 462         roce_write(hr_dev, ROCEE_DB_OTHERS_WL_REG, val);
 463 }
 464
 465 static void hns_roce_set_sdb_ext(struct hns_roce_dev *hr_dev, u32 ext_sdb_alept,
 466                                  u32 ext_sdb_alful)
 467 {
 468         struct device *dev = &hr_dev->pdev->dev;
 469         struct hns_roce_v1_priv *priv;
 470         struct hns_roce_db_table *db;
 471         dma_addr_t sdb_dma_addr;
 472         u32 val;
 473
 474         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
 475         db = &priv->db_table;
 476
 477         /* Configure extend SDB threshold */
 478         roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_EMPTY_REG, ext_sdb_alept);
 479         roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_REG, ext_sdb_alful);
 480
 481         /* Configure extend SDB base addr */
 482         sdb_dma_addr = db->ext_db->sdb_buf_list->map;
 483         roce_write(hr_dev, ROCEE_EXT_DB_SQ_REG, (u32)(sdb_dma_addr >> 12));
 484
 485         /* Configure extend SDB depth */
 486         val = roce_read(hr_dev, ROCEE_EXT_DB_SQ_H_REG);
 487         roce_set_field(val, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_M,
 488                        ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_S,
 489                        db->ext_db->esdb_dep);
 490         /*
 491          * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
 492          * using 4K page, and shift more 32 because of
 493          * caculating the high 32 bit value evaluated to hardware.
 494          */
 495         roce_set_field(val, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_M,
 496                        ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_S, sdb_dma_addr >> 44);
 497         roce_write(hr_dev, ROCEE_EXT_DB_SQ_H_REG, val);
 498
 499         dev_dbg(dev, "ext SDB depth: 0x%x\n", db->ext_db->esdb_dep);
 500         dev_dbg(dev, "ext SDB threshold: epmty: 0x%x, ful: 0x%x\n",
 501                 ext_sdb_alept, ext_sdb_alful);
 502 }
 503
 504 static void hns_roce_set_odb_ext(struct hns_roce_dev *hr_dev, u32 ext_odb_alept,
 505                                  u32 ext_odb_alful)
 506 {
 507         struct device *dev = &hr_dev->pdev->dev;
 508         struct hns_roce_v1_priv *priv;
 509         struct hns_roce_db_table *db;
 510         dma_addr_t odb_dma_addr;
 511         u32 val;
 512
 513         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
 514         db = &priv->db_table;
 515
 516         /* Configure extend ODB threshold */
 517         roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_EMPTY_REG, ext_odb_alept);
 518         roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_REG, ext_odb_alful);
 519
 520         /* Configure extend ODB base addr */
 521         odb_dma_addr = db->ext_db->odb_buf_list->map;
 522         roce_write(hr_dev, ROCEE_EXT_DB_OTH_REG, (u32)(odb_dma_addr >> 12));
 523
 524         /* Configure extend ODB depth */
 525         val = roce_read(hr_dev, ROCEE_EXT_DB_OTH_H_REG);
 526         roce_set_field(val, ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_M,
 527                        ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_S,
 528                        db->ext_db->eodb_dep);
 529         roce_set_field(val, ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_M,
 530                        ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_S,
 531                        db->ext_db->eodb_dep);
 532         roce_write(hr_dev, ROCEE_EXT_DB_OTH_H_REG, val);
 533
 534         dev_dbg(dev, "ext ODB depth: 0x%x\n", db->ext_db->eodb_dep);
 535         dev_dbg(dev, "ext ODB threshold: empty: 0x%x, ful: 0x%x\n",
 536                 ext_odb_alept, ext_odb_alful);
 537 }
 538
 539 static int hns_roce_db_ext_init(struct hns_roce_dev *hr_dev, u32 sdb_ext_mod,
 540                                 u32 odb_ext_mod)
 541 {
 542         struct device *dev = &hr_dev->pdev->dev;
 543         struct hns_roce_v1_priv *priv;
 544         struct hns_roce_db_table *db;
 545         dma_addr_t sdb_dma_addr;
 546         dma_addr_t odb_dma_addr;
 547         int ret = 0;
 548
 549         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
 550         db = &priv->db_table;
 551
 552         db->ext_db = kmalloc(sizeof(*db->ext_db), GFP_KERNEL);
 553         if (!db->ext_db)
 554                 return -ENOMEM;
 555
 556         if (sdb_ext_mod) {
 557                 db->ext_db->sdb_buf_list = kmalloc(
 558                                 sizeof(*db->ext_db->sdb_buf_list), GFP_KERNEL);
 559                 if (!db->ext_db->sdb_buf_list) {
 560                         ret = -ENOMEM;
 561                         goto ext_sdb_buf_fail_out;
 562                 }
 563
 564                 db->ext_db->sdb_buf_list->buf = dma_alloc_coherent(dev,
 565                                                      HNS_ROCE_V1_EXT_SDB_SIZE,
 566                                                      &sdb_dma_addr, GFP_KERNEL);
 567                 if (!db->ext_db->sdb_buf_list->buf) {
 568                         ret = -ENOMEM;
 569                         goto alloc_sq_db_buf_fail;
 570                 }
 571                 db->ext_db->sdb_buf_list->map = sdb_dma_addr;
 572
 573                 db->ext_db->esdb_dep = ilog2(HNS_ROCE_V1_EXT_SDB_DEPTH);
 574                 hns_roce_set_sdb_ext(hr_dev, HNS_ROCE_V1_EXT_SDB_ALEPT,
 575                                      HNS_ROCE_V1_EXT_SDB_ALFUL);
 576         } else
 577                 hns_roce_set_sdb(hr_dev, HNS_ROCE_V1_SDB_ALEPT,
 578                                  HNS_ROCE_V1_SDB_ALFUL);
 579
 580         if (odb_ext_mod) {
 581                 db->ext_db->odb_buf_list = kmalloc(
 582                                 sizeof(*db->ext_db->odb_buf_list), GFP_KERNEL);
 583                 if (!db->ext_db->odb_buf_list) {
 584                         ret = -ENOMEM;
 585                         goto ext_odb_buf_fail_out;
 586                 }
 587
 588                 db->ext_db->odb_buf_list->buf = dma_alloc_coherent(dev,
 589                                                      HNS_ROCE_V1_EXT_ODB_SIZE,
 590                                                      &odb_dma_addr, GFP_KERNEL);
 591                 if (!db->ext_db->odb_buf_list->buf) {
 592                         ret = -ENOMEM;
 593                         goto alloc_otr_db_buf_fail;
 594                 }
 595                 db->ext_db->odb_buf_list->map = odb_dma_addr;
 596
 597                 db->ext_db->eodb_dep = ilog2(HNS_ROCE_V1_EXT_ODB_DEPTH);
 598                 hns_roce_set_odb_ext(hr_dev, HNS_ROCE_V1_EXT_ODB_ALEPT,
 599                                      HNS_ROCE_V1_EXT_ODB_ALFUL);
 600         } else
 601                 hns_roce_set_odb(hr_dev, HNS_ROCE_V1_ODB_ALEPT,
 602                                  HNS_ROCE_V1_ODB_ALFUL);
 603
 604         hns_roce_set_db_ext_mode(hr_dev, sdb_ext_mod, odb_ext_mod);
 605
 606         return 0;
 607
 608 alloc_otr_db_buf_fail:
 609         kfree(db->ext_db->odb_buf_list);
 610
 611 ext_odb_buf_fail_out:
 612         if (sdb_ext_mod) {
 613                 dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
 614                                   db->ext_db->sdb_buf_list->buf,
 615                                   db->ext_db->sdb_buf_list->map);
 616         }
 617
 618 alloc_sq_db_buf_fail:
 619         if (sdb_ext_mod)
 620                 kfree(db->ext_db->sdb_buf_list);
 621
 622 ext_sdb_buf_fail_out:
 623         kfree(db->ext_db);
 624         return ret;
 625 }
 626
 627 static struct hns_roce_qp *hns_roce_v1_create_lp_qp(struct hns_roce_dev *hr_dev,
 628                                                     struct ib_pd *pd)
 629 {
 630         struct device *dev = &hr_dev->pdev->dev;
 631         struct ib_qp_init_attr init_attr;
 632         struct ib_qp *qp;
 633
 634         memset(&init_attr, 0, sizeof(struct ib_qp_init_attr));
 635         init_attr.qp_type               = IB_QPT_RC;
 636         init_attr.sq_sig_type           = IB_SIGNAL_ALL_WR;
 637         init_attr.cap.max_recv_wr       = HNS_ROCE_MIN_WQE_NUM;
 638         init_attr.cap.max_send_wr       = HNS_ROCE_MIN_WQE_NUM;
 639
 640         qp = hns_roce_create_qp(pd, &init_attr, NULL);
 641         if (IS_ERR(qp)) {
 642                 dev_err(dev, "Create loop qp for mr free failed!");
 643                 return NULL;
 644         }
 645
 646         return to_hr_qp(qp);
 647 }
 648
 649 static int hns_roce_v1_rsv_lp_qp(struct hns_roce_dev *hr_dev)
 650 {
 651         struct hns_roce_caps *caps = &hr_dev->caps;
 652         struct device *dev = &hr_dev->pdev->dev;
 653         struct ib_cq_init_attr cq_init_attr;
 654         struct hns_roce_free_mr *free_mr;
 655         struct ib_qp_attr attr = { 0 };
 656         struct hns_roce_v1_priv *priv;
 657         struct hns_roce_qp *hr_qp;
 658         struct ib_cq *cq;
 659         struct ib_pd *pd;
 660         union ib_gid dgid;
 661         u64 subnet_prefix;
 662         int attr_mask = 0;
 663         int i, j;
 664         int ret;
 665         u8 queue_en[HNS_ROCE_V1_RESV_QP] = { 0 };
 666         u8 phy_port;
 667         u8 port = 0;
 668         u8 sl;
 669
 670         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
 671         free_mr = &priv->free_mr;
 672
 673         /* Reserved cq for loop qp */
 674         cq_init_attr.cqe                = HNS_ROCE_MIN_WQE_NUM * 2;
 675         cq_init_attr.comp_vector        = 0;
 676         cq = hns_roce_ib_create_cq(&hr_dev->ib_dev, &cq_init_attr, NULL, NULL);
 677         if (IS_ERR(cq)) {
 678                 dev_err(dev, "Create cq for reseved loop qp failed!");
 679                 return -ENOMEM;
 680         }
 681         free_mr->mr_free_cq = to_hr_cq(cq);
 682         free_mr->mr_free_cq->ib_cq.device               = &hr_dev->ib_dev;
 683         free_mr->mr_free_cq->ib_cq.uobject              = NULL;
 684         free_mr->mr_free_cq->ib_cq.comp_handler         = NULL;
 685         free_mr->mr_free_cq->ib_cq.event_handler        = NULL;
 686         free_mr->mr_free_cq->ib_cq.cq_context           = NULL;
 687         atomic_set(&free_mr->mr_free_cq->ib_cq.usecnt, 0);
 688
 689         pd = hns_roce_alloc_pd(&hr_dev->ib_dev, NULL, NULL);
 690         if (IS_ERR(pd)) {
 691                 dev_err(dev, "Create pd for reseved loop qp failed!");
 692                 ret = -ENOMEM;
 693                 goto alloc_pd_failed;
 694         }
 695         free_mr->mr_free_pd = to_hr_pd(pd);
 696         free_mr->mr_free_pd->ibpd.device  = &hr_dev->ib_dev;
 697         free_mr->mr_free_pd->ibpd.uobject = NULL;
 698         atomic_set(&free_mr->mr_free_pd->ibpd.usecnt, 0);
 699
 700         attr.qp_access_flags    = IB_ACCESS_REMOTE_WRITE;
 701         attr.pkey_index         = 0;
 702         attr.min_rnr_timer      = 0;
 703         /* Disable read ability */
 704         attr.max_dest_rd_atomic = 0;
 705         attr.max_rd_atomic      = 0;
 706         /* Use arbitrary values as rq_psn and sq_psn */
 707         attr.rq_psn             = 0x0808;
 708         attr.sq_psn             = 0x0808;
 709         attr.retry_cnt          = 7;
 710         attr.rnr_retry          = 7;
 711         attr.timeout            = 0x12;
 712         attr.path_mtu           = IB_MTU_256;
 713         attr.ah_attr.type       = RDMA_AH_ATTR_TYPE_ROCE;
 714         rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0);
 715         rdma_ah_set_static_rate(&attr.ah_attr, 3);
 716
 717         subnet_prefix = cpu_to_be64(0xfe80000000000000LL);
 718         for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
 719                 phy_port = (i >= HNS_ROCE_MAX_PORTS) ? (i - 2) :
 720                                 (i % HNS_ROCE_MAX_PORTS);
 721                 sl = i / HNS_ROCE_MAX_PORTS;
 722
 723                 for (j = 0; j < caps->num_ports; j++) {
 724                         if (hr_dev->iboe.phy_port[j] == phy_port) {
 725                                 queue_en[i] = 1;
 726                                 port = j;
 727                                 break;
 728                         }
 729                 }
 730
 731                 if (!queue_en[i])
 732                         continue;
 733
 734                 free_mr->mr_free_qp[i] = hns_roce_v1_create_lp_qp(hr_dev, pd);
 735                 if (!free_mr->mr_free_qp[i]) {
 736                         dev_err(dev, "Create loop qp failed!\n");
 737                         goto create_lp_qp_failed;
 738                 }
 739                 hr_qp = free_mr->mr_free_qp[i];
 740
 741                 hr_qp->port             = port;
 742                 hr_qp->phy_port         = phy_port;
 743                 hr_qp->ibqp.qp_type     = IB_QPT_RC;
 744                 hr_qp->ibqp.device      = &hr_dev->ib_dev;
 745                 hr_qp->ibqp.uobject     = NULL;
 746                 atomic_set(&hr_qp->ibqp.usecnt, 0);
 747                 hr_qp->ibqp.pd          = pd;
 748                 hr_qp->ibqp.recv_cq     = cq;
 749                 hr_qp->ibqp.send_cq     = cq;
 750
 751                 rdma_ah_set_port_num(&attr.ah_attr, port + 1);
 752                 rdma_ah_set_sl(&attr.ah_attr, sl);
 753                 attr.port_num           = port + 1;
 754
 755                 attr.dest_qp_num        = hr_qp->qpn;
 756                 memcpy(rdma_ah_retrieve_dmac(&attr.ah_attr),
 757                        hr_dev->dev_addr[port],
 758                        MAC_ADDR_OCTET_NUM);
 759
 760                 memcpy(&dgid.raw, &subnet_prefix, sizeof(u64));
 761                 memcpy(&dgid.raw[8], hr_dev->dev_addr[port], 3);
 762                 memcpy(&dgid.raw[13], hr_dev->dev_addr[port] + 3, 3);
 763                 dgid.raw[11] = 0xff;
 764                 dgid.raw[12] = 0xfe;
 765                 dgid.raw[8] ^= 2;
 766                 rdma_ah_set_dgid_raw(&attr.ah_attr, dgid.raw);
 767
 768                 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
 769                                             IB_QPS_RESET, IB_QPS_INIT);
 770                 if (ret) {
 771                         dev_err(dev, "modify qp failed(%d)!\n", ret);
 772                         goto create_lp_qp_failed;
 773                 }
 774
 775                 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
 776                                             IB_QPS_INIT, IB_QPS_RTR);
 777                 if (ret) {
 778                         dev_err(dev, "modify qp failed(%d)!\n", ret);
 779                         goto create_lp_qp_failed;
 780                 }
 781
 782                 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
 783                                             IB_QPS_RTR, IB_QPS_RTS);
 784                 if (ret) {
 785                         dev_err(dev, "modify qp failed(%d)!\n", ret);
 786                         goto create_lp_qp_failed;
 787                 }
 788         }
 789
 790         return 0;
 791
 792 create_lp_qp_failed:
 793         for (i -= 1; i >= 0; i--) {
 794                 hr_qp = free_mr->mr_free_qp[i];
 795                 if (hns_roce_v1_destroy_qp(&hr_qp->ibqp))
 796                         dev_err(dev, "Destroy qp %d for mr free failed!\n", i);
 797         }
 798
 799         if (hns_roce_dealloc_pd(pd))
 800                 dev_err(dev, "Destroy pd for create_lp_qp failed!\n");
 801
 802 alloc_pd_failed:
 803         if (hns_roce_ib_destroy_cq(cq))
 804                 dev_err(dev, "Destroy cq for create_lp_qp failed!\n");
 805
 806         return -EINVAL;
 807 }
 808
 809 static void hns_roce_v1_release_lp_qp(struct hns_roce_dev *hr_dev)
 810 {
 811         struct device *dev = &hr_dev->pdev->dev;
 812         struct hns_roce_free_mr *free_mr;
 813         struct hns_roce_v1_priv *priv;
 814         struct hns_roce_qp *hr_qp;
 815         int ret;
 816         int i;
 817
 818         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
 819         free_mr = &priv->free_mr;
 820
 821         for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
 822                 hr_qp = free_mr->mr_free_qp[i];
 823                 if (!hr_qp)
 824                         continue;
 825
 826                 ret = hns_roce_v1_destroy_qp(&hr_qp->ibqp);
 827                 if (ret)
 828                         dev_err(dev, "Destroy qp %d for mr free failed(%d)!\n",
 829                                 i, ret);
 830         }
 831
 832         ret = hns_roce_ib_destroy_cq(&free_mr->mr_free_cq->ib_cq);
 833         if (ret)
 834                 dev_err(dev, "Destroy cq for mr_free failed(%d)!\n", ret);
 835
 836         ret = hns_roce_dealloc_pd(&free_mr->mr_free_pd->ibpd);
 837         if (ret)
 838                 dev_err(dev, "Destroy pd for mr_free failed(%d)!\n", ret);
 839 }
 840
 841 static int hns_roce_db_init(struct hns_roce_dev *hr_dev)
 842 {
 843         struct device *dev = &hr_dev->pdev->dev;
 844         struct hns_roce_v1_priv *priv;
 845         struct hns_roce_db_table *db;
 846         u32 sdb_ext_mod;
 847         u32 odb_ext_mod;
 848         u32 sdb_evt_mod;
 849         u32 odb_evt_mod;
 850         int ret = 0;
 851
 852         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
 853         db = &priv->db_table;
 854
 855         memset(db, 0, sizeof(*db));
 856
 857         /* Default DB mode */
 858         sdb_ext_mod = HNS_ROCE_SDB_EXTEND_MODE;
 859         odb_ext_mod = HNS_ROCE_ODB_EXTEND_MODE;
 860         sdb_evt_mod = HNS_ROCE_SDB_NORMAL_MODE;
 861         odb_evt_mod = HNS_ROCE_ODB_POLL_MODE;
 862
 863         db->sdb_ext_mod = sdb_ext_mod;
 864         db->odb_ext_mod = odb_ext_mod;
 865
 866         /* Init extend DB */
 867         ret = hns_roce_db_ext_init(hr_dev, sdb_ext_mod, odb_ext_mod);
 868         if (ret) {
 869                 dev_err(dev, "Failed in extend DB configuration.\n");
 870                 return ret;
 871         }
 872
 873         hns_roce_set_db_event_mode(hr_dev, sdb_evt_mod, odb_evt_mod);
 874
 875         return 0;
 876 }
 877
 878 void hns_roce_v1_recreate_lp_qp_work_fn(struct work_struct *work)
 879 {
 880         struct hns_roce_recreate_lp_qp_work *lp_qp_work;
 881         struct hns_roce_dev *hr_dev;
 882
 883         lp_qp_work = container_of(work, struct hns_roce_recreate_lp_qp_work,
 884                                   work);
 885         hr_dev = to_hr_dev(lp_qp_work->ib_dev);
 886
 887         hns_roce_v1_release_lp_qp(hr_dev);
 888
 889         if (hns_roce_v1_rsv_lp_qp(hr_dev))
 890                 dev_err(&hr_dev->pdev->dev, "create reserver qp failed\n");
 891
 892         if (lp_qp_work->comp_flag)
 893                 complete(lp_qp_work->comp);
 894
 895         kfree(lp_qp_work);
 896 }
 897
 898 static int hns_roce_v1_recreate_lp_qp(struct hns_roce_dev *hr_dev)
 899 {
 900         struct device *dev = &hr_dev->pdev->dev;
 901         struct hns_roce_recreate_lp_qp_work *lp_qp_work;
 902         struct hns_roce_free_mr *free_mr;
 903         struct hns_roce_v1_priv *priv;
 904         struct completion comp;
 905         unsigned long end =
 906           msecs_to_jiffies(HNS_ROCE_V1_RECREATE_LP_QP_TIMEOUT_MSECS) + jiffies;
 907
 908         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
 909         free_mr = &priv->free_mr;
 910
 911         lp_qp_work = kzalloc(sizeof(struct hns_roce_recreate_lp_qp_work),
 912                              GFP_KERNEL);
 913
 914         INIT_WORK(&(lp_qp_work->work), hns_roce_v1_recreate_lp_qp_work_fn);
 915
 916         lp_qp_work->ib_dev = &(hr_dev->ib_dev);
 917         lp_qp_work->comp = &comp;
 918         lp_qp_work->comp_flag = 1;
 919
 920         init_completion(lp_qp_work->comp);
 921
 922         queue_work(free_mr->free_mr_wq, &(lp_qp_work->work));
 923
 924         while (time_before_eq(jiffies, end)) {
 925                 if (try_wait_for_completion(&comp))
 926                         return 0;
 927                 msleep(HNS_ROCE_V1_RECREATE_LP_QP_WAIT_VALUE);
 928         }
 929
 930         lp_qp_work->comp_flag = 0;
 931         if (try_wait_for_completion(&comp))
 932                 return 0;
 933
 934         dev_warn(dev, "recreate lp qp failed 20s timeout and return failed!\n");
 935         return -ETIMEDOUT;
 936 }
 937
 938 static int hns_roce_v1_send_lp_wqe(struct hns_roce_qp *hr_qp)
 939 {
 940         struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device);
 941         struct device *dev = &hr_dev->pdev->dev;
 942         struct ib_send_wr send_wr, *bad_wr;
 943         int ret;
 944
 945         memset(&send_wr, 0, sizeof(send_wr));
 946         send_wr.next    = NULL;
 947         send_wr.num_sge = 0;
 948         send_wr.send_flags = 0;
 949         send_wr.sg_list = NULL;
 950         send_wr.wr_id   = (unsigned long long)&send_wr;
 951         send_wr.opcode  = IB_WR_RDMA_WRITE;
 952
 953         ret = hns_roce_v1_post_send(&hr_qp->ibqp, &send_wr, &bad_wr);
 954         if (ret) {
 955                 dev_err(dev, "Post write wqe for mr free failed(%d)!", ret);
 956                 return ret;
 957         }
 958
 959         return 0;
 960 }
 961
 962 static void hns_roce_v1_mr_free_work_fn(struct work_struct *work)
 963 {
 964         struct hns_roce_mr_free_work *mr_work;
 965         struct ib_wc wc[HNS_ROCE_V1_RESV_QP];
 966         struct hns_roce_free_mr *free_mr;
 967         struct hns_roce_cq *mr_free_cq;
 968         struct hns_roce_v1_priv *priv;
 969         struct hns_roce_dev *hr_dev;
 970         struct hns_roce_mr *hr_mr;
 971         struct hns_roce_qp *hr_qp;
 972         struct device *dev;
 973         unsigned long end =
 974                 msecs_to_jiffies(HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS) + jiffies;
 975         int i;
 976         int ret;
 977         int ne = 0;
 978
 979         mr_work = container_of(work, struct hns_roce_mr_free_work, work);
 980         hr_mr = (struct hns_roce_mr *)mr_work->mr;
 981         hr_dev = to_hr_dev(mr_work->ib_dev);
 982         dev = &hr_dev->pdev->dev;
 983
 984         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
 985         free_mr = &priv->free_mr;
 986         mr_free_cq = free_mr->mr_free_cq;
 987
 988         for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
 989                 hr_qp = free_mr->mr_free_qp[i];
 990                 if (!hr_qp)
 991                         continue;
 992                 ne++;
 993
 994                 ret = hns_roce_v1_send_lp_wqe(hr_qp);
 995                 if (ret) {
 996                         dev_err(dev,
 997                              "Send wqe (qp:0x%lx) for mr free failed(%d)!\n",
 998                              hr_qp->qpn, ret);
 999                         goto free_work;
1000                 }
1001         }
1002
1003         if (!ne) {
1004                 dev_err(dev, "Reseved loop qp is absent!\n");
1005                 goto free_work;
1006         }
1007
1008         do {
1009                 ret = hns_roce_v1_poll_cq(&mr_free_cq->ib_cq, ne, wc);
1010                 if (ret < 0) {
1011                         dev_err(dev,
1012                            "(qp:0x%lx) starts, Poll cqe failed(%d) for mr 0x%x free! Remain %d cqe\n",
1013                            hr_qp->qpn, ret, hr_mr->key, ne);
1014                         goto free_work;
1015                 }
1016                 ne -= ret;
1017                 usleep_range(HNS_ROCE_V1_FREE_MR_WAIT_VALUE * 1000,
1018                              (1 + HNS_ROCE_V1_FREE_MR_WAIT_VALUE) * 1000);
1019         } while (ne && time_before_eq(jiffies, end));
1020
1021         if (ne != 0)
1022                 dev_err(dev,
1023                         "Poll cqe for mr 0x%x free timeout! Remain %d cqe\n",
1024                         hr_mr->key, ne);
1025
1026 free_work:
1027         if (mr_work->comp_flag)
1028                 complete(mr_work->comp);
1029         kfree(mr_work);
1030 }
1031
1032 int hns_roce_v1_dereg_mr(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr)
1033 {
1034         struct device *dev = &hr_dev->pdev->dev;
1035         struct hns_roce_mr_free_work *mr_work;
1036         struct hns_roce_free_mr *free_mr;
1037         struct hns_roce_v1_priv *priv;
1038         struct completion comp;
1039         unsigned long end =
1040                 msecs_to_jiffies(HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS) + jiffies;
1041         unsigned long start = jiffies;
1042         int npages;
1043         int ret = 0;
1044
1045         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1046         free_mr = &priv->free_mr;
1047
1048         if (mr->enabled) {
1049                 if (hns_roce_hw2sw_mpt(hr_dev, NULL, key_to_hw_index(mr->key)
1050                                        & (hr_dev->caps.num_mtpts - 1)))
1051                         dev_warn(dev, "HW2SW_MPT failed!\n");
1052         }
1053
1054         mr_work = kzalloc(sizeof(*mr_work), GFP_KERNEL);
1055         if (!mr_work) {
1056                 ret = -ENOMEM;
1057                 goto free_mr;
1058         }
1059
1060         INIT_WORK(&(mr_work->work), hns_roce_v1_mr_free_work_fn);
1061
1062         mr_work->ib_dev = &(hr_dev->ib_dev);
1063         mr_work->comp = &comp;
1064         mr_work->comp_flag = 1;
1065         mr_work->mr = (void *)mr;
1066         init_completion(mr_work->comp);
1067
1068         queue_work(free_mr->free_mr_wq, &(mr_work->work));
1069
1070         while (time_before_eq(jiffies, end)) {
1071                 if (try_wait_for_completion(&comp))
1072                         goto free_mr;
1073                 msleep(HNS_ROCE_V1_FREE_MR_WAIT_VALUE);
1074         }
1075
1076         mr_work->comp_flag = 0;
1077         if (try_wait_for_completion(&comp))
1078                 goto free_mr;
1079
1080         dev_warn(dev, "Free mr work 0x%x over 50s and failed!\n", mr->key);
1081         ret = -ETIMEDOUT;
1082
1083 free_mr:
1084         dev_dbg(dev, "Free mr 0x%x use 0x%x us.\n",
1085                 mr->key, jiffies_to_usecs(jiffies) - jiffies_to_usecs(start));
1086
1087         if (mr->size != ~0ULL) {
1088                 npages = ib_umem_page_count(mr->umem);
1089                 dma_free_coherent(dev, npages * 8, mr->pbl_buf,
1090                                   mr->pbl_dma_addr);
1091         }
1092
1093         hns_roce_bitmap_free(&hr_dev->mr_table.mtpt_bitmap,
1094                              key_to_hw_index(mr->key), 0);
1095
1096         if (mr->umem)
1097                 ib_umem_release(mr->umem);
1098
1099         kfree(mr);
1100
1101         return ret;
1102 }
1103
1104 static void hns_roce_db_free(struct hns_roce_dev *hr_dev)
1105 {
1106         struct device *dev = &hr_dev->pdev->dev;
1107         struct hns_roce_v1_priv *priv;
1108         struct hns_roce_db_table *db;
1109
1110         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1111         db = &priv->db_table;
1112
1113         if (db->sdb_ext_mod) {
1114                 dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
1115                                   db->ext_db->sdb_buf_list->buf,
1116                                   db->ext_db->sdb_buf_list->map);
1117                 kfree(db->ext_db->sdb_buf_list);
1118         }
1119
1120         if (db->odb_ext_mod) {
1121                 dma_free_coherent(dev, HNS_ROCE_V1_EXT_ODB_SIZE,
1122                                   db->ext_db->odb_buf_list->buf,
1123                                   db->ext_db->odb_buf_list->map);
1124                 kfree(db->ext_db->odb_buf_list);
1125         }
1126
1127         kfree(db->ext_db);
1128 }
1129
1130 static int hns_roce_raq_init(struct hns_roce_dev *hr_dev)
1131 {
1132         int ret;
1133         int raq_shift = 0;
1134         dma_addr_t addr;
1135         u32 val;
1136         struct hns_roce_v1_priv *priv;
1137         struct hns_roce_raq_table *raq;
1138         struct device *dev = &hr_dev->pdev->dev;
1139
1140         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1141         raq = &priv->raq_table;
1142
1143         raq->e_raq_buf = kzalloc(sizeof(*(raq->e_raq_buf)), GFP_KERNEL);
1144         if (!raq->e_raq_buf)
1145                 return -ENOMEM;
1146
1147         raq->e_raq_buf->buf = dma_alloc_coherent(dev, HNS_ROCE_V1_RAQ_SIZE,
1148                                                  &addr, GFP_KERNEL);
1149         if (!raq->e_raq_buf->buf) {
1150                 ret = -ENOMEM;
1151                 goto err_dma_alloc_raq;
1152         }
1153         raq->e_raq_buf->map = addr;
1154
1155         /* Configure raq extended address. 48bit 4K align*/
1156         roce_write(hr_dev, ROCEE_EXT_RAQ_REG, raq->e_raq_buf->map >> 12);
1157
1158         /* Configure raq_shift */
1159         raq_shift = ilog2(HNS_ROCE_V1_RAQ_SIZE / HNS_ROCE_V1_RAQ_ENTRY);
1160         val = roce_read(hr_dev, ROCEE_EXT_RAQ_H_REG);
1161         roce_set_field(val, ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_M,
1162                        ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_S, raq_shift);
1163         /*
1164          * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
1165          * using 4K page, and shift more 32 because of
1166          * caculating the high 32 bit value evaluated to hardware.
1167          */
1168         roce_set_field(val, ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_M,
1169                        ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_S,
1170                        raq->e_raq_buf->map >> 44);
1171         roce_write(hr_dev, ROCEE_EXT_RAQ_H_REG, val);
1172         dev_dbg(dev, "Configure raq_shift 0x%x.\n", val);
1173
1174         /* Configure raq threshold */
1175         val = roce_read(hr_dev, ROCEE_RAQ_WL_REG);
1176         roce_set_field(val, ROCEE_RAQ_WL_ROCEE_RAQ_WL_M,
1177                        ROCEE_RAQ_WL_ROCEE_RAQ_WL_S,
1178                        HNS_ROCE_V1_EXT_RAQ_WF);
1179         roce_write(hr_dev, ROCEE_RAQ_WL_REG, val);
1180         dev_dbg(dev, "Configure raq_wl 0x%x.\n", val);
1181
1182         /* Enable extend raq */
1183         val = roce_read(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG);
1184         roce_set_field(val,
1185                        ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_M,
1186                        ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_S,
1187                        POL_TIME_INTERVAL_VAL);
1188         roce_set_bit(val, ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_EXT_RAQ_MODE, 1);
1189         roce_set_field(val,
1190                        ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_M,
1191                        ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_S,
1192                        2);
1193         roce_set_bit(val,
1194                      ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_EN_S, 1);
1195         roce_write(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG, val);
1196         dev_dbg(dev, "Configure WrmsPolTimeInterval 0x%x.\n", val);
1197
1198         /* Enable raq drop */
1199         val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1200         roce_set_bit(val, ROCEE_GLB_CFG_TRP_RAQ_DROP_EN_S, 1);
1201         roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1202         dev_dbg(dev, "Configure GlbCfg = 0x%x.\n", val);
1203
1204         return 0;
1205
1206 err_dma_alloc_raq:
1207         kfree(raq->e_raq_buf);
1208         return ret;
1209 }
1210
1211 static void hns_roce_raq_free(struct hns_roce_dev *hr_dev)
1212 {
1213         struct device *dev = &hr_dev->pdev->dev;
1214         struct hns_roce_v1_priv *priv;
1215         struct hns_roce_raq_table *raq;
1216
1217         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1218         raq = &priv->raq_table;
1219
1220         dma_free_coherent(dev, HNS_ROCE_V1_RAQ_SIZE, raq->e_raq_buf->buf,
1221                           raq->e_raq_buf->map);
1222         kfree(raq->e_raq_buf);
1223 }
1224
1225 static void hns_roce_port_enable(struct hns_roce_dev *hr_dev, int enable_flag)
1226 {
1227         u32 val;
1228
1229         if (enable_flag) {
1230                 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1231                  /* Open all ports */
1232                 roce_set_field(val, ROCEE_GLB_CFG_ROCEE_PORT_ST_M,
1233                                ROCEE_GLB_CFG_ROCEE_PORT_ST_S,
1234                                ALL_PORT_VAL_OPEN);
1235                 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1236         } else {
1237                 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1238                 /* Close all ports */
1239                 roce_set_field(val, ROCEE_GLB_CFG_ROCEE_PORT_ST_M,
1240                                ROCEE_GLB_CFG_ROCEE_PORT_ST_S, 0x0);
1241                 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1242         }
1243 }
1244
1245 static int hns_roce_bt_init(struct hns_roce_dev *hr_dev)
1246 {
1247         struct device *dev = &hr_dev->pdev->dev;
1248         struct hns_roce_v1_priv *priv;
1249         int ret;
1250
1251         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1252
1253         priv->bt_table.qpc_buf.buf = dma_alloc_coherent(dev,
1254                 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.qpc_buf.map,
1255                 GFP_KERNEL);
1256         if (!priv->bt_table.qpc_buf.buf)
1257                 return -ENOMEM;
1258
1259         priv->bt_table.mtpt_buf.buf = dma_alloc_coherent(dev,
1260                 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.mtpt_buf.map,
1261                 GFP_KERNEL);
1262         if (!priv->bt_table.mtpt_buf.buf) {
1263                 ret = -ENOMEM;
1264                 goto err_failed_alloc_mtpt_buf;
1265         }
1266
1267         priv->bt_table.cqc_buf.buf = dma_alloc_coherent(dev,
1268                 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.cqc_buf.map,
1269                 GFP_KERNEL);
1270         if (!priv->bt_table.cqc_buf.buf) {
1271                 ret = -ENOMEM;
1272                 goto err_failed_alloc_cqc_buf;
1273         }
1274
1275         return 0;
1276
1277 err_failed_alloc_cqc_buf:
1278         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1279                 priv->bt_table.mtpt_buf.buf, priv->bt_table.mtpt_buf.map);
1280
1281 err_failed_alloc_mtpt_buf:
1282         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1283                 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map);
1284
1285         return ret;
1286 }
1287
1288 static void hns_roce_bt_free(struct hns_roce_dev *hr_dev)
1289 {
1290         struct device *dev = &hr_dev->pdev->dev;
1291         struct hns_roce_v1_priv *priv;
1292
1293         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1294
1295         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1296                 priv->bt_table.cqc_buf.buf, priv->bt_table.cqc_buf.map);
1297
1298         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1299                 priv->bt_table.mtpt_buf.buf, priv->bt_table.mtpt_buf.map);
1300
1301         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1302                 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map);
1303 }
1304
1305 static int hns_roce_tptr_init(struct hns_roce_dev *hr_dev)
1306 {
1307         struct device *dev = &hr_dev->pdev->dev;
1308         struct hns_roce_buf_list *tptr_buf;
1309         struct hns_roce_v1_priv *priv;
1310
1311         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1312         tptr_buf = &priv->tptr_table.tptr_buf;
1313
1314         /*
1315          * This buffer will be used for CQ's tptr(tail pointer), also
1316          * named ci(customer index). Every CQ will use 2 bytes to save
1317          * cqe ci in hip06. Hardware will read this area to get new ci
1318          * when the queue is almost full.
1319          */
1320         tptr_buf->buf = dma_alloc_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1321                                            &tptr_buf->map, GFP_KERNEL);
1322         if (!tptr_buf->buf)
1323                 return -ENOMEM;
1324
1325         hr_dev->tptr_dma_addr = tptr_buf->map;
1326         hr_dev->tptr_size = HNS_ROCE_V1_TPTR_BUF_SIZE;
1327
1328         return 0;
1329 }
1330
1331 static void hns_roce_tptr_free(struct hns_roce_dev *hr_dev)
1332 {
1333         struct device *dev = &hr_dev->pdev->dev;
1334         struct hns_roce_buf_list *tptr_buf;
1335         struct hns_roce_v1_priv *priv;
1336
1337         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1338         tptr_buf = &priv->tptr_table.tptr_buf;
1339
1340         dma_free_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1341                           tptr_buf->buf, tptr_buf->map);
1342 }
1343
1344 static int hns_roce_free_mr_init(struct hns_roce_dev *hr_dev)
1345 {
1346         struct device *dev = &hr_dev->pdev->dev;
1347         struct hns_roce_free_mr *free_mr;
1348         struct hns_roce_v1_priv *priv;
1349         int ret = 0;
1350
1351         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1352         free_mr = &priv->free_mr;
1353
1354         free_mr->free_mr_wq = create_singlethread_workqueue("hns_roce_free_mr");
1355         if (!free_mr->free_mr_wq) {
1356                 dev_err(dev, "Create free mr workqueue failed!\n");
1357                 return -ENOMEM;
1358         }
1359
1360         ret = hns_roce_v1_rsv_lp_qp(hr_dev);
1361         if (ret) {
1362                 dev_err(dev, "Reserved loop qp failed(%d)!\n", ret);
1363                 flush_workqueue(free_mr->free_mr_wq);
1364                 destroy_workqueue(free_mr->free_mr_wq);
1365         }
1366
1367         return ret;
1368 }
1369
1370 static void hns_roce_free_mr_free(struct hns_roce_dev *hr_dev)
1371 {
1372         struct hns_roce_free_mr *free_mr;
1373         struct hns_roce_v1_priv *priv;
1374
1375         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1376         free_mr = &priv->free_mr;
1377
1378         flush_workqueue(free_mr->free_mr_wq);
1379         destroy_workqueue(free_mr->free_mr_wq);
1380
1381         hns_roce_v1_release_lp_qp(hr_dev);
1382 }
1383
1384 /**
1385  * hns_roce_v1_reset - reset RoCE
1386  * @hr_dev: RoCE device struct pointer
1387  * @enable: true -- drop reset, false -- reset
1388  * return 0 - success , negative --fail
1389  */
1390 int hns_roce_v1_reset(struct hns_roce_dev *hr_dev, bool dereset)
1391 {
1392         struct device_node *dsaf_node;
1393         struct device *dev = &hr_dev->pdev->dev;
1394         struct device_node *np = dev->of_node;
1395         struct fwnode_handle *fwnode;
1396         int ret;
1397
1398         /* check if this is DT/ACPI case */
1399         if (dev_of_node(dev)) {
1400                 dsaf_node = of_parse_phandle(np, "dsaf-handle", 0);
1401                 if (!dsaf_node) {
1402                         dev_err(dev, "could not find dsaf-handle\n");
1403                         return -EINVAL;
1404                 }
1405                 fwnode = &dsaf_node->fwnode;
1406         } else if (is_acpi_device_node(dev->fwnode)) {
1407                 struct acpi_reference_args args;
1408
1409                 ret = acpi_node_get_property_reference(dev->fwnode,
1410                                                        "dsaf-handle", 0, &args);
1411                 if (ret) {
1412                         dev_err(dev, "could not find dsaf-handle\n");
1413                         return ret;
1414                 }
1415                 fwnode = acpi_fwnode_handle(args.adev);
1416         } else {
1417                 dev_err(dev, "cannot read data from DT or ACPI\n");
1418                 return -ENXIO;
1419         }
1420
1421         ret = hns_dsaf_roce_reset(fwnode, false);
1422         if (ret)
1423                 return ret;
1424
1425         if (dereset) {
1426                 msleep(SLEEP_TIME_INTERVAL);
1427                 ret = hns_dsaf_roce_reset(fwnode, true);
1428         }
1429
1430         return ret;
1431 }
1432
1433 static int hns_roce_des_qp_init(struct hns_roce_dev *hr_dev)
1434 {
1435         struct device *dev = &hr_dev->pdev->dev;
1436         struct hns_roce_v1_priv *priv;
1437         struct hns_roce_des_qp *des_qp;
1438
1439         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1440         des_qp = &priv->des_qp;
1441
1442         des_qp->requeue_flag = 1;
1443         des_qp->qp_wq = create_singlethread_workqueue("hns_roce_destroy_qp");
1444         if (!des_qp->qp_wq) {
1445                 dev_err(dev, "Create destroy qp workqueue failed!\n");
1446                 return -ENOMEM;
1447         }
1448
1449         return 0;
1450 }
1451
1452 static void hns_roce_des_qp_free(struct hns_roce_dev *hr_dev)
1453 {
1454         struct hns_roce_v1_priv *priv;
1455         struct hns_roce_des_qp *des_qp;
1456
1457         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1458         des_qp = &priv->des_qp;
1459
1460         des_qp->requeue_flag = 0;
1461         flush_workqueue(des_qp->qp_wq);
1462         destroy_workqueue(des_qp->qp_wq);
1463 }
1464
1465 void hns_roce_v1_profile(struct hns_roce_dev *hr_dev)
1466 {
1467         int i = 0;
1468         struct hns_roce_caps *caps = &hr_dev->caps;
1469
1470         hr_dev->vendor_id = le32_to_cpu(roce_read(hr_dev, ROCEE_VENDOR_ID_REG));
1471         hr_dev->vendor_part_id = le32_to_cpu(roce_read(hr_dev,
1472                                              ROCEE_VENDOR_PART_ID_REG));
1473         hr_dev->sys_image_guid = le32_to_cpu(roce_read(hr_dev,
1474                                              ROCEE_SYS_IMAGE_GUID_L_REG)) |
1475                                 ((u64)le32_to_cpu(roce_read(hr_dev,
1476                                             ROCEE_SYS_IMAGE_GUID_H_REG)) << 32);
1477         hr_dev->hw_rev          = HNS_ROCE_HW_VER1;
1478
1479         caps->num_qps           = HNS_ROCE_V1_MAX_QP_NUM;
1480         caps->max_wqes          = HNS_ROCE_V1_MAX_WQE_NUM;
1481         caps->num_cqs           = HNS_ROCE_V1_MAX_CQ_NUM;
1482         caps->max_cqes          = HNS_ROCE_V1_MAX_CQE_NUM;
1483         caps->max_sq_sg         = HNS_ROCE_V1_SG_NUM;
1484         caps->max_rq_sg         = HNS_ROCE_V1_SG_NUM;
1485         caps->max_sq_inline     = HNS_ROCE_V1_INLINE_SIZE;
1486         caps->num_uars          = HNS_ROCE_V1_UAR_NUM;
1487         caps->phy_num_uars      = HNS_ROCE_V1_PHY_UAR_NUM;
1488         caps->num_aeq_vectors   = HNS_ROCE_AEQE_VEC_NUM;
1489         caps->num_comp_vectors  = HNS_ROCE_COMP_VEC_NUM;
1490         caps->num_other_vectors = HNS_ROCE_AEQE_OF_VEC_NUM;
1491         caps->num_mtpts         = HNS_ROCE_V1_MAX_MTPT_NUM;
1492         caps->num_mtt_segs      = HNS_ROCE_V1_MAX_MTT_SEGS;
1493         caps->num_pds           = HNS_ROCE_V1_MAX_PD_NUM;
1494         caps->max_qp_init_rdma  = HNS_ROCE_V1_MAX_QP_INIT_RDMA;
1495         caps->max_qp_dest_rdma  = HNS_ROCE_V1_MAX_QP_DEST_RDMA;
1496         caps->max_sq_desc_sz    = HNS_ROCE_V1_MAX_SQ_DESC_SZ;
1497         caps->max_rq_desc_sz    = HNS_ROCE_V1_MAX_RQ_DESC_SZ;
1498         caps->qpc_entry_sz      = HNS_ROCE_V1_QPC_ENTRY_SIZE;
1499         caps->irrl_entry_sz     = HNS_ROCE_V1_IRRL_ENTRY_SIZE;
1500         caps->cqc_entry_sz      = HNS_ROCE_V1_CQC_ENTRY_SIZE;
1501         caps->mtpt_entry_sz     = HNS_ROCE_V1_MTPT_ENTRY_SIZE;
1502         caps->mtt_entry_sz      = HNS_ROCE_V1_MTT_ENTRY_SIZE;
1503         caps->cq_entry_sz       = HNS_ROCE_V1_CQE_ENTRY_SIZE;
1504         caps->page_size_cap     = HNS_ROCE_V1_PAGE_SIZE_SUPPORT;
1505         caps->reserved_lkey     = 0;
1506         caps->reserved_pds      = 0;
1507         caps->reserved_mrws     = 1;
1508         caps->reserved_uars     = 0;
1509         caps->reserved_cqs      = 0;
1510
1511         for (i = 0; i < caps->num_ports; i++)
1512                 caps->pkey_table_len[i] = 1;
1513
1514         for (i = 0; i < caps->num_ports; i++) {
1515                 /* Six ports shared 16 GID in v1 engine */
1516                 if (i >= (HNS_ROCE_V1_GID_NUM % caps->num_ports))
1517                         caps->gid_table_len[i] = HNS_ROCE_V1_GID_NUM /
1518                                                  caps->num_ports;
1519                 else
1520                         caps->gid_table_len[i] = HNS_ROCE_V1_GID_NUM /
1521                                                  caps->num_ports + 1;
1522         }
1523
1524         for (i = 0; i < caps->num_comp_vectors; i++)
1525                 caps->ceqe_depth[i] = HNS_ROCE_V1_NUM_COMP_EQE;
1526
1527         caps->aeqe_depth = HNS_ROCE_V1_NUM_ASYNC_EQE;
1528         caps->local_ca_ack_delay = le32_to_cpu(roce_read(hr_dev,
1529                                                          ROCEE_ACK_DELAY_REG));
1530         caps->max_mtu = IB_MTU_2048;
1531 }
1532
1533 int hns_roce_v1_init(struct hns_roce_dev *hr_dev)
1534 {
1535         int ret;
1536         u32 val;
1537         struct device *dev = &hr_dev->pdev->dev;
1538
1539         /* DMAE user config */
1540         val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG1_REG);
1541         roce_set_field(val, ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_M,
1542                        ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_S, 0xf);
1543         roce_set_field(val, ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_M,
1544                        ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_S,
1545                        1 << PAGES_SHIFT_16);
1546         roce_write(hr_dev, ROCEE_DMAE_USER_CFG1_REG, val);
1547
1548         val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG2_REG);
1549         roce_set_field(val, ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_M,
1550                        ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_S, 0xf);
1551         roce_set_field(val, ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_M,
1552                        ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_S,
1553                        1 << PAGES_SHIFT_16);
1554
1555         ret = hns_roce_db_init(hr_dev);
1556         if (ret) {
1557                 dev_err(dev, "doorbell init failed!\n");
1558                 return ret;
1559         }
1560
1561         ret = hns_roce_raq_init(hr_dev);
1562         if (ret) {
1563                 dev_err(dev, "raq init failed!\n");
1564                 goto error_failed_raq_init;
1565         }
1566
1567         ret = hns_roce_bt_init(hr_dev);
1568         if (ret) {
1569                 dev_err(dev, "bt init failed!\n");
1570                 goto error_failed_bt_init;
1571         }
1572
1573         ret = hns_roce_tptr_init(hr_dev);
1574         if (ret) {
1575                 dev_err(dev, "tptr init failed!\n");
1576                 goto error_failed_tptr_init;
1577         }
1578
1579         ret = hns_roce_des_qp_init(hr_dev);
1580         if (ret) {
1581                 dev_err(dev, "des qp init failed!\n");
1582                 goto error_failed_des_qp_init;
1583         }
1584
1585         ret = hns_roce_free_mr_init(hr_dev);
1586         if (ret) {
1587                 dev_err(dev, "free mr init failed!\n");
1588                 goto error_failed_free_mr_init;
1589         }
1590
1591         hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_UP);
1592
1593         return 0;
1594
1595 error_failed_free_mr_init:
1596         hns_roce_des_qp_free(hr_dev);
1597
1598 error_failed_des_qp_init:
1599         hns_roce_tptr_free(hr_dev);
1600
1601 error_failed_tptr_init:
1602         hns_roce_bt_free(hr_dev);
1603
1604 error_failed_bt_init:
1605         hns_roce_raq_free(hr_dev);
1606
1607 error_failed_raq_init:
1608         hns_roce_db_free(hr_dev);
1609         return ret;
1610 }
1611
1612 void hns_roce_v1_exit(struct hns_roce_dev *hr_dev)
1613 {
1614         hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_DOWN);
1615         hns_roce_free_mr_free(hr_dev);
1616         hns_roce_des_qp_free(hr_dev);
1617         hns_roce_tptr_free(hr_dev);
1618         hns_roce_bt_free(hr_dev);
1619         hns_roce_raq_free(hr_dev);
1620         hns_roce_db_free(hr_dev);
1621 }
1622
1623 void hns_roce_v1_set_gid(struct hns_roce_dev *hr_dev, u8 port, int gid_index,
1624                          union ib_gid *gid)
1625 {
1626         u32 *p = NULL;
1627         u8 gid_idx = 0;
1628
1629         gid_idx = hns_get_gid_index(hr_dev, port, gid_index);
1630
1631         p = (u32 *)&gid->raw[0];
1632         roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_L_0_REG +
1633                        (HNS_ROCE_V1_GID_NUM * gid_idx));
1634
1635         p = (u32 *)&gid->raw[4];
1636         roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_ML_0_REG +
1637                        (HNS_ROCE_V1_GID_NUM * gid_idx));
1638
1639         p = (u32 *)&gid->raw[8];
1640         roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_MH_0_REG +
1641                        (HNS_ROCE_V1_GID_NUM * gid_idx));
1642
1643         p = (u32 *)&gid->raw[0xc];
1644         roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_H_0_REG +
1645                        (HNS_ROCE_V1_GID_NUM * gid_idx));
1646 }
1647
1648 void hns_roce_v1_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr)
1649 {
1650         u32 reg_smac_l;
1651         u16 reg_smac_h;
1652         u16 *p_h;
1653         u32 *p;
1654         u32 val;
1655
1656         /*
1657          * When mac changed, loopback may fail
1658          * because of smac not equal to dmac.
1659          * We Need to release and create reserved qp again.
1660          */
1661         if (hr_dev->hw->dereg_mr && hns_roce_v1_recreate_lp_qp(hr_dev))
1662                 dev_warn(&hr_dev->pdev->dev, "recreate lp qp timeout!\n");
1663
1664         p = (u32 *)(&addr[0]);
1665         reg_smac_l = *p;
1666         roce_raw_write(reg_smac_l, hr_dev->reg_base + ROCEE_SMAC_L_0_REG +
1667                        PHY_PORT_OFFSET * phy_port);
1668
1669         val = roce_read(hr_dev,
1670                         ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET);
1671         p_h = (u16 *)(&addr[4]);
1672         reg_smac_h  = *p_h;
1673         roce_set_field(val, ROCEE_SMAC_H_ROCEE_SMAC_H_M,
1674                        ROCEE_SMAC_H_ROCEE_SMAC_H_S, reg_smac_h);
1675         roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET,
1676                    val);
1677 }
1678
1679 void hns_roce_v1_set_mtu(struct hns_roce_dev *hr_dev, u8 phy_port,
1680                          enum ib_mtu mtu)
1681 {
1682         u32 val;
1683
1684         val = roce_read(hr_dev,
1685                         ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET);
1686         roce_set_field(val, ROCEE_SMAC_H_ROCEE_PORT_MTU_M,
1687                        ROCEE_SMAC_H_ROCEE_PORT_MTU_S, mtu);
1688         roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET,
1689                    val);
1690 }
1691
1692 int hns_roce_v1_write_mtpt(void *mb_buf, struct hns_roce_mr *mr,
1693                            unsigned long mtpt_idx)
1694 {
1695         struct hns_roce_v1_mpt_entry *mpt_entry;
1696         struct scatterlist *sg;
1697         u64 *pages;
1698         int entry;
1699         int i;
1700
1701         /* MPT filled into mailbox buf */
1702         mpt_entry = (struct hns_roce_v1_mpt_entry *)mb_buf;
1703         memset(mpt_entry, 0, sizeof(*mpt_entry));
1704
1705         roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_KEY_STATE_M,
1706                        MPT_BYTE_4_KEY_STATE_S, KEY_VALID);
1707         roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_KEY_M,
1708                        MPT_BYTE_4_KEY_S, mr->key);
1709         roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_PAGE_SIZE_M,
1710                        MPT_BYTE_4_PAGE_SIZE_S, MR_SIZE_4K);
1711         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_MW_TYPE_S, 0);
1712         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_MW_BIND_ENABLE_S,
1713                      (mr->access & IB_ACCESS_MW_BIND ? 1 : 0));
1714         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_OWN_S, 0);
1715         roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_MEMORY_LOCATION_TYPE_M,
1716                        MPT_BYTE_4_MEMORY_LOCATION_TYPE_S, mr->type);
1717         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_ATOMIC_S, 0);
1718         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_LOCAL_WRITE_S,
1719                      (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
1720         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_WRITE_S,
1721                      (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
1722         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_READ_S,
1723                      (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0));
1724         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_INVAL_ENABLE_S,
1725                      0);
1726         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_ADDRESS_TYPE_S, 0);
1727
1728         roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
1729                        MPT_BYTE_12_PBL_ADDR_H_S, 0);
1730         roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_MW_BIND_COUNTER_M,
1731                        MPT_BYTE_12_MW_BIND_COUNTER_S, 0);
1732
1733         mpt_entry->virt_addr_l = (u32)mr->iova;
1734         mpt_entry->virt_addr_h = (u32)(mr->iova >> 32);
1735         mpt_entry->length = (u32)mr->size;
1736
1737         roce_set_field(mpt_entry->mpt_byte_28, MPT_BYTE_28_PD_M,
1738                        MPT_BYTE_28_PD_S, mr->pd);
1739         roce_set_field(mpt_entry->mpt_byte_28, MPT_BYTE_28_L_KEY_IDX_L_M,
1740                        MPT_BYTE_28_L_KEY_IDX_L_S, mtpt_idx);
1741         roce_set_field(mpt_entry->mpt_byte_64, MPT_BYTE_64_L_KEY_IDX_H_M,
1742                        MPT_BYTE_64_L_KEY_IDX_H_S, mtpt_idx >> MTPT_IDX_SHIFT);
1743
1744         /* DMA memory register */
1745         if (mr->type == MR_TYPE_DMA)
1746                 return 0;
1747
1748         pages = (u64 *) __get_free_page(GFP_KERNEL);
1749         if (!pages)
1750                 return -ENOMEM;
1751
1752         i = 0;
1753         for_each_sg(mr->umem->sg_head.sgl, sg, mr->umem->nmap, entry) {
1754                 pages[i] = ((u64)sg_dma_address(sg)) >> 12;
1755
1756                 /* Directly record to MTPT table firstly 7 entry */
1757                 if (i >= HNS_ROCE_MAX_INNER_MTPT_NUM)
1758                         break;
1759                 i++;
1760         }
1761
1762         /* Register user mr */
1763         for (i = 0; i < HNS_ROCE_MAX_INNER_MTPT_NUM; i++) {
1764                 switch (i) {
1765                 case 0:
1766                         mpt_entry->pa0_l = cpu_to_le32((u32)(pages[i]));
1767                         roce_set_field(mpt_entry->mpt_byte_36,
1768                                 MPT_BYTE_36_PA0_H_M,
1769                                 MPT_BYTE_36_PA0_H_S,
1770                                 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_32)));
1771                         break;
1772                 case 1:
1773                         roce_set_field(mpt_entry->mpt_byte_36,
1774                                        MPT_BYTE_36_PA1_L_M,
1775                                        MPT_BYTE_36_PA1_L_S,
1776                                        cpu_to_le32((u32)(pages[i])));
1777                         roce_set_field(mpt_entry->mpt_byte_40,
1778                                 MPT_BYTE_40_PA1_H_M,
1779                                 MPT_BYTE_40_PA1_H_S,
1780                                 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_24)));
1781                         break;
1782                 case 2:
1783                         roce_set_field(mpt_entry->mpt_byte_40,
1784                                        MPT_BYTE_40_PA2_L_M,
1785                                        MPT_BYTE_40_PA2_L_S,
1786                                        cpu_to_le32((u32)(pages[i])));
1787                         roce_set_field(mpt_entry->mpt_byte_44,
1788                                 MPT_BYTE_44_PA2_H_M,
1789                                 MPT_BYTE_44_PA2_H_S,
1790                                 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_16)));
1791                         break;
1792                 case 3:
1793                         roce_set_field(mpt_entry->mpt_byte_44,
1794                                        MPT_BYTE_44_PA3_L_M,
1795                                        MPT_BYTE_44_PA3_L_S,
1796                                        cpu_to_le32((u32)(pages[i])));
1797                         roce_set_field(mpt_entry->mpt_byte_48,
1798                                 MPT_BYTE_48_PA3_H_M,
1799                                 MPT_BYTE_48_PA3_H_S,
1800                                 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_8)));
1801                         break;
1802                 case 4:
1803                         mpt_entry->pa4_l = cpu_to_le32((u32)(pages[i]));
1804                         roce_set_field(mpt_entry->mpt_byte_56,
1805                                 MPT_BYTE_56_PA4_H_M,
1806                                 MPT_BYTE_56_PA4_H_S,
1807                                 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_32)));
1808                         break;
1809                 case 5:
1810                         roce_set_field(mpt_entry->mpt_byte_56,
1811                                        MPT_BYTE_56_PA5_L_M,
1812                                        MPT_BYTE_56_PA5_L_S,
1813                                        cpu_to_le32((u32)(pages[i])));
1814                         roce_set_field(mpt_entry->mpt_byte_60,
1815                                 MPT_BYTE_60_PA5_H_M,
1816                                 MPT_BYTE_60_PA5_H_S,
1817                                 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_24)));
1818                         break;
1819                 case 6:
1820                         roce_set_field(mpt_entry->mpt_byte_60,
1821                                        MPT_BYTE_60_PA6_L_M,
1822                                        MPT_BYTE_60_PA6_L_S,
1823                                        cpu_to_le32((u32)(pages[i])));
1824                         roce_set_field(mpt_entry->mpt_byte_64,
1825                                 MPT_BYTE_64_PA6_H_M,
1826                                 MPT_BYTE_64_PA6_H_S,
1827                                 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_16)));
1828                         break;
1829                 default:
1830                         break;
1831                 }
1832         }
1833
1834         free_page((unsigned long) pages);
1835
1836         mpt_entry->pbl_addr_l = (u32)(mr->pbl_dma_addr);
1837
1838         roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
1839                        MPT_BYTE_12_PBL_ADDR_H_S,
1840                        ((u32)(mr->pbl_dma_addr >> 32)));
1841
1842         return 0;
1843 }
1844
1845 static void *get_cqe(struct hns_roce_cq *hr_cq, int n)
1846 {
1847         return hns_roce_buf_offset(&hr_cq->hr_buf.hr_buf,
1848                                    n * HNS_ROCE_V1_CQE_ENTRY_SIZE);
1849 }
1850
1851 static void *get_sw_cqe(struct hns_roce_cq *hr_cq, int n)
1852 {
1853         struct hns_roce_cqe *hr_cqe = get_cqe(hr_cq, n & hr_cq->ib_cq.cqe);
1854
1855         /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
1856         return (roce_get_bit(hr_cqe->cqe_byte_4, CQE_BYTE_4_OWNER_S) ^
1857                 !!(n & (hr_cq->ib_cq.cqe + 1))) ? hr_cqe : NULL;
1858 }
1859
1860 static struct hns_roce_cqe *next_cqe_sw(struct hns_roce_cq *hr_cq)
1861 {
1862         return get_sw_cqe(hr_cq, hr_cq->cons_index);
1863 }
1864
1865 void hns_roce_v1_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index)
1866 {
1867         u32 doorbell[2];
1868
1869         doorbell[0] = cons_index & ((hr_cq->cq_depth << 1) - 1);
1870         doorbell[1] = 0;
1871         roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
1872         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
1873                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3);
1874         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M,
1875                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 0);
1876         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M,
1877                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S, hr_cq->cqn);
1878
1879         hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
1880 }
1881
1882 static void __hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
1883                                    struct hns_roce_srq *srq)
1884 {
1885         struct hns_roce_cqe *cqe, *dest;
1886         u32 prod_index;
1887         int nfreed = 0;
1888         u8 owner_bit;
1889
1890         for (prod_index = hr_cq->cons_index; get_sw_cqe(hr_cq, prod_index);
1891              ++prod_index) {
1892                 if (prod_index == hr_cq->cons_index + hr_cq->ib_cq.cqe)
1893                         break;
1894         }
1895
1896         /*
1897          * Now backwards through the CQ, removing CQ entries
1898          * that match our QP by overwriting them with next entries.
1899          */
1900         while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
1901                 cqe = get_cqe(hr_cq, prod_index & hr_cq->ib_cq.cqe);
1902                 if ((roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
1903                                      CQE_BYTE_16_LOCAL_QPN_S) &
1904                                      HNS_ROCE_CQE_QPN_MASK) == qpn) {
1905                         /* In v1 engine, not support SRQ */
1906                         ++nfreed;
1907                 } else if (nfreed) {
1908                         dest = get_cqe(hr_cq, (prod_index + nfreed) &
1909                                        hr_cq->ib_cq.cqe);
1910                         owner_bit = roce_get_bit(dest->cqe_byte_4,
1911                                                  CQE_BYTE_4_OWNER_S);
1912                         memcpy(dest, cqe, sizeof(*cqe));
1913                         roce_set_bit(dest->cqe_byte_4, CQE_BYTE_4_OWNER_S,
1914                                      owner_bit);
1915                 }
1916         }
1917
1918         if (nfreed) {
1919                 hr_cq->cons_index += nfreed;
1920                 /*
1921                  * Make sure update of buffer contents is done before
1922                  * updating consumer index.
1923                  */
1924                 wmb();
1925
1926                 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
1927         }
1928 }
1929
1930 static void hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
1931                                  struct hns_roce_srq *srq)
1932 {
1933         spin_lock_irq(&hr_cq->lock);
1934         __hns_roce_v1_cq_clean(hr_cq, qpn, srq);
1935         spin_unlock_irq(&hr_cq->lock);
1936 }
1937
1938 void hns_roce_v1_write_cqc(struct hns_roce_dev *hr_dev,
1939                            struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts,
1940                            dma_addr_t dma_handle, int nent, u32 vector)
1941 {
1942         struct hns_roce_cq_context *cq_context = NULL;
1943         struct hns_roce_buf_list *tptr_buf;
1944         struct hns_roce_v1_priv *priv;
1945         dma_addr_t tptr_dma_addr;
1946         int offset;
1947
1948         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1949         tptr_buf = &priv->tptr_table.tptr_buf;
1950
1951         cq_context = mb_buf;
1952         memset(cq_context, 0, sizeof(*cq_context));
1953
1954         /* Get the tptr for this CQ. */
1955         offset = hr_cq->cqn * HNS_ROCE_V1_TPTR_ENTRY_SIZE;
1956         tptr_dma_addr = tptr_buf->map + offset;
1957         hr_cq->tptr_addr = (u16 *)(tptr_buf->buf + offset);
1958
1959         /* Register cq_context members */
1960         roce_set_field(cq_context->cqc_byte_4,
1961                        CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_M,
1962                        CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_S, CQ_STATE_VALID);
1963         roce_set_field(cq_context->cqc_byte_4, CQ_CONTEXT_CQC_BYTE_4_CQN_M,
1964                        CQ_CONTEXT_CQC_BYTE_4_CQN_S, hr_cq->cqn);
1965         cq_context->cqc_byte_4 = cpu_to_le32(cq_context->cqc_byte_4);
1966
1967         cq_context->cq_bt_l = (u32)dma_handle;
1968         cq_context->cq_bt_l = cpu_to_le32(cq_context->cq_bt_l);
1969
1970         roce_set_field(cq_context->cqc_byte_12,
1971                        CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_M,
1972                        CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_S,
1973                        ((u64)dma_handle >> 32));
1974         roce_set_field(cq_context->cqc_byte_12,
1975                        CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_M,
1976                        CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_S,
1977                        ilog2((unsigned int)nent));
1978         roce_set_field(cq_context->cqc_byte_12, CQ_CONTEXT_CQC_BYTE_12_CEQN_M,
1979                        CQ_CONTEXT_CQC_BYTE_12_CEQN_S, vector);
1980         cq_context->cqc_byte_12 = cpu_to_le32(cq_context->cqc_byte_12);
1981
1982         cq_context->cur_cqe_ba0_l = (u32)(mtts[0]);
1983         cq_context->cur_cqe_ba0_l = cpu_to_le32(cq_context->cur_cqe_ba0_l);
1984
1985         roce_set_field(cq_context->cqc_byte_20,
1986                        CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_M,
1987                        CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_S,
1988                        cpu_to_le32((mtts[0]) >> 32));
1989         /* Dedicated hardware, directly set 0 */
1990         roce_set_field(cq_context->cqc_byte_20,
1991                        CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_M,
1992                        CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_S, 0);
1993         /**
1994          * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
1995          * using 4K page, and shift more 32 because of
1996          * caculating the high 32 bit value evaluated to hardware.
1997          */
1998         roce_set_field(cq_context->cqc_byte_20,
1999                        CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_M,
2000                        CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_S,
2001                        tptr_dma_addr >> 44);
2002         cq_context->cqc_byte_20 = cpu_to_le32(cq_context->cqc_byte_20);
2003
2004         cq_context->cqe_tptr_addr_l = (u32)(tptr_dma_addr >> 12);
2005
2006         roce_set_field(cq_context->cqc_byte_32,
2007                        CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_M,
2008                        CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_S, 0);
2009         roce_set_bit(cq_context->cqc_byte_32,
2010                      CQ_CONTEXT_CQC_BYTE_32_SE_FLAG_S, 0);
2011         roce_set_bit(cq_context->cqc_byte_32,
2012                      CQ_CONTEXT_CQC_BYTE_32_CE_FLAG_S, 0);
2013         roce_set_bit(cq_context->cqc_byte_32,
2014                      CQ_CONTEXT_CQC_BYTE_32_NOTIFICATION_FLAG_S, 0);
2015         roce_set_bit(cq_context->cqc_byte_32,
2016                      CQ_CQNTEXT_CQC_BYTE_32_TYPE_OF_COMPLETION_NOTIFICATION_S,
2017                      0);
2018         /* The initial value of cq's ci is 0 */
2019         roce_set_field(cq_context->cqc_byte_32,
2020                        CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_M,
2021                        CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_S, 0);
2022         cq_context->cqc_byte_32 = cpu_to_le32(cq_context->cqc_byte_32);
2023 }
2024
2025 int hns_roce_v1_req_notify_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
2026 {
2027         struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2028         u32 notification_flag;
2029         u32 doorbell[2];
2030
2031         notification_flag = (flags & IB_CQ_SOLICITED_MASK) ==
2032                             IB_CQ_SOLICITED ? CQ_DB_REQ_NOT : CQ_DB_REQ_NOT_SOL;
2033         /*
2034          * flags = 0; Notification Flag = 1, next
2035          * flags = 1; Notification Flag = 0, solocited
2036          */
2037         doorbell[0] = hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1);
2038         roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
2039         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
2040                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3);
2041         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M,
2042                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 1);
2043         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M,
2044                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S,
2045                        hr_cq->cqn | notification_flag);
2046
2047         hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
2048
2049         return 0;
2050 }
2051
2052 static int hns_roce_v1_poll_one(struct hns_roce_cq *hr_cq,
2053                                 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
2054 {
2055         int qpn;
2056         int is_send;
2057         u16 wqe_ctr;
2058         u32 status;
2059         u32 opcode;
2060         struct hns_roce_cqe *cqe;
2061         struct hns_roce_qp *hr_qp;
2062         struct hns_roce_wq *wq;
2063         struct hns_roce_wqe_ctrl_seg *sq_wqe;
2064         struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
2065         struct device *dev = &hr_dev->pdev->dev;
2066
2067         /* Find cqe according consumer index */
2068         cqe = next_cqe_sw(hr_cq);
2069         if (!cqe)
2070                 return -EAGAIN;
2071
2072         ++hr_cq->cons_index;
2073         /* Memory barrier */
2074         rmb();
2075         /* 0->SQ, 1->RQ */
2076         is_send  = !(roce_get_bit(cqe->cqe_byte_4, CQE_BYTE_4_SQ_RQ_FLAG_S));
2077
2078         /* Local_qpn in UD cqe is always 1, so it needs to compute new qpn */
2079         if (roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2080                            CQE_BYTE_16_LOCAL_QPN_S) <= 1) {
2081                 qpn = roce_get_field(cqe->cqe_byte_20, CQE_BYTE_20_PORT_NUM_M,
2082                                      CQE_BYTE_20_PORT_NUM_S) +
2083                       roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2084                                      CQE_BYTE_16_LOCAL_QPN_S) *
2085                                      HNS_ROCE_MAX_PORTS;
2086         } else {
2087                 qpn = roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2088                                      CQE_BYTE_16_LOCAL_QPN_S);
2089         }
2090
2091         if (!*cur_qp || (qpn & HNS_ROCE_CQE_QPN_MASK) != (*cur_qp)->qpn) {
2092                 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
2093                 if (unlikely(!hr_qp)) {
2094                         dev_err(dev, "CQ %06lx with entry for unknown QPN %06x\n",
2095                                 hr_cq->cqn, (qpn & HNS_ROCE_CQE_QPN_MASK));
2096                         return -EINVAL;
2097                 }
2098
2099                 *cur_qp = hr_qp;
2100         }
2101
2102         wc->qp = &(*cur_qp)->ibqp;
2103         wc->vendor_err = 0;
2104
2105         status = roce_get_field(cqe->cqe_byte_4,
2106                                 CQE_BYTE_4_STATUS_OF_THE_OPERATION_M,
2107                                 CQE_BYTE_4_STATUS_OF_THE_OPERATION_S) &
2108                                 HNS_ROCE_CQE_STATUS_MASK;
2109         switch (status) {
2110         case HNS_ROCE_CQE_SUCCESS:
2111                 wc->status = IB_WC_SUCCESS;
2112                 break;
2113         case HNS_ROCE_CQE_SYNDROME_LOCAL_LENGTH_ERR:
2114                 wc->status = IB_WC_LOC_LEN_ERR;
2115                 break;
2116         case HNS_ROCE_CQE_SYNDROME_LOCAL_QP_OP_ERR:
2117                 wc->status = IB_WC_LOC_QP_OP_ERR;
2118                 break;
2119         case HNS_ROCE_CQE_SYNDROME_LOCAL_PROT_ERR:
2120                 wc->status = IB_WC_LOC_PROT_ERR;
2121                 break;
2122         case HNS_ROCE_CQE_SYNDROME_WR_FLUSH_ERR:
2123                 wc->status = IB_WC_WR_FLUSH_ERR;
2124                 break;
2125         case HNS_ROCE_CQE_SYNDROME_MEM_MANAGE_OPERATE_ERR:
2126                 wc->status = IB_WC_MW_BIND_ERR;
2127                 break;
2128         case HNS_ROCE_CQE_SYNDROME_BAD_RESP_ERR:
2129                 wc->status = IB_WC_BAD_RESP_ERR;
2130                 break;
2131         case HNS_ROCE_CQE_SYNDROME_LOCAL_ACCESS_ERR:
2132                 wc->status = IB_WC_LOC_ACCESS_ERR;
2133                 break;
2134         case HNS_ROCE_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
2135                 wc->status = IB_WC_REM_INV_REQ_ERR;
2136                 break;
2137         case HNS_ROCE_CQE_SYNDROME_REMOTE_ACCESS_ERR:
2138                 wc->status = IB_WC_REM_ACCESS_ERR;
2139                 break;
2140         case HNS_ROCE_CQE_SYNDROME_REMOTE_OP_ERR:
2141                 wc->status = IB_WC_REM_OP_ERR;
2142                 break;
2143         case HNS_ROCE_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
2144                 wc->status = IB_WC_RETRY_EXC_ERR;
2145                 break;
2146         case HNS_ROCE_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
2147                 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
2148                 break;
2149         default:
2150                 wc->status = IB_WC_GENERAL_ERR;
2151                 break;
2152         }
2153
2154         /* CQE status error, directly return */
2155         if (wc->status != IB_WC_SUCCESS)
2156                 return 0;
2157
2158         if (is_send) {
2159                 /* SQ conrespond to CQE */
2160                 sq_wqe = get_send_wqe(*cur_qp, roce_get_field(cqe->cqe_byte_4,
2161                                                 CQE_BYTE_4_WQE_INDEX_M,
2162                                                 CQE_BYTE_4_WQE_INDEX_S)&
2163                                                 ((*cur_qp)->sq.wqe_cnt-1));
2164                 switch (sq_wqe->flag & HNS_ROCE_WQE_OPCODE_MASK) {
2165                 case HNS_ROCE_WQE_OPCODE_SEND:
2166                         wc->opcode = IB_WC_SEND;
2167                         break;
2168                 case HNS_ROCE_WQE_OPCODE_RDMA_READ:
2169                         wc->opcode = IB_WC_RDMA_READ;
2170                         wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2171                         break;
2172                 case HNS_ROCE_WQE_OPCODE_RDMA_WRITE:
2173                         wc->opcode = IB_WC_RDMA_WRITE;
2174                         break;
2175                 case HNS_ROCE_WQE_OPCODE_LOCAL_INV:
2176                         wc->opcode = IB_WC_LOCAL_INV;
2177                         break;
2178                 case HNS_ROCE_WQE_OPCODE_UD_SEND:
2179                         wc->opcode = IB_WC_SEND;
2180                         break;
2181                 default:
2182                         wc->status = IB_WC_GENERAL_ERR;
2183                         break;
2184                 }
2185                 wc->wc_flags = (sq_wqe->flag & HNS_ROCE_WQE_IMM ?
2186                                 IB_WC_WITH_IMM : 0);
2187
2188                 wq = &(*cur_qp)->sq;
2189                 if ((*cur_qp)->sq_signal_bits) {
2190                         /*
2191                          * If sg_signal_bit is 1,
2192                          * firstly tail pointer updated to wqe
2193                          * which current cqe correspond to
2194                          */
2195                         wqe_ctr = (u16)roce_get_field(cqe->cqe_byte_4,
2196                                                       CQE_BYTE_4_WQE_INDEX_M,
2197                                                       CQE_BYTE_4_WQE_INDEX_S);
2198                         wq->tail += (wqe_ctr - (u16)wq->tail) &
2199                                     (wq->wqe_cnt - 1);
2200                 }
2201                 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2202                 ++wq->tail;
2203         } else {
2204                 /* RQ conrespond to CQE */
2205                 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2206                 opcode = roce_get_field(cqe->cqe_byte_4,
2207                                         CQE_BYTE_4_OPERATION_TYPE_M,
2208                                         CQE_BYTE_4_OPERATION_TYPE_S) &
2209                                         HNS_ROCE_CQE_OPCODE_MASK;
2210                 switch (opcode) {
2211                 case HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE:
2212                         wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
2213                         wc->wc_flags = IB_WC_WITH_IMM;
2214                         wc->ex.imm_data = le32_to_cpu(cqe->immediate_data);
2215                         break;
2216                 case HNS_ROCE_OPCODE_SEND_DATA_RECEIVE:
2217                         if (roce_get_bit(cqe->cqe_byte_4,
2218                                          CQE_BYTE_4_IMM_INDICATOR_S)) {
2219                                 wc->opcode = IB_WC_RECV;
2220                                 wc->wc_flags = IB_WC_WITH_IMM;
2221                                 wc->ex.imm_data = le32_to_cpu(
2222                                                   cqe->immediate_data);
2223                         } else {
2224                                 wc->opcode = IB_WC_RECV;
2225                                 wc->wc_flags = 0;
2226                         }
2227                         break;
2228                 default:
2229                         wc->status = IB_WC_GENERAL_ERR;
2230                         break;
2231                 }
2232
2233                 /* Update tail pointer, record wr_id */
2234                 wq = &(*cur_qp)->rq;
2235                 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2236                 ++wq->tail;
2237                 wc->sl = (u8)roce_get_field(cqe->cqe_byte_20, CQE_BYTE_20_SL_M,
2238                                             CQE_BYTE_20_SL_S);
2239                 wc->src_qp = (u8)roce_get_field(cqe->cqe_byte_20,
2240                                                 CQE_BYTE_20_REMOTE_QPN_M,
2241                                                 CQE_BYTE_20_REMOTE_QPN_S);
2242                 wc->wc_flags |= (roce_get_bit(cqe->cqe_byte_20,
2243                                               CQE_BYTE_20_GRH_PRESENT_S) ?
2244                                               IB_WC_GRH : 0);
2245                 wc->pkey_index = (u16)roce_get_field(cqe->cqe_byte_28,
2246                                                      CQE_BYTE_28_P_KEY_IDX_M,
2247                                                      CQE_BYTE_28_P_KEY_IDX_S);
2248         }
2249
2250         return 0;
2251 }
2252
2253 int hns_roce_v1_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
2254 {
2255         struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2256         struct hns_roce_qp *cur_qp = NULL;
2257         unsigned long flags;
2258         int npolled;
2259         int ret = 0;
2260
2261         spin_lock_irqsave(&hr_cq->lock, flags);
2262
2263         for (npolled = 0; npolled < num_entries; ++npolled) {
2264                 ret = hns_roce_v1_poll_one(hr_cq, &cur_qp, wc + npolled);
2265                 if (ret)
2266                         break;
2267         }
2268
2269         if (npolled) {
2270                 *hr_cq->tptr_addr = hr_cq->cons_index &
2271                         ((hr_cq->cq_depth << 1) - 1);
2272
2273                 /* Memroy barrier */
2274                 wmb();
2275                 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
2276         }
2277
2278         spin_unlock_irqrestore(&hr_cq->lock, flags);
2279
2280         if (ret == 0 || ret == -EAGAIN)
2281                 return npolled;
2282         else
2283                 return ret;
2284 }
2285
2286 int hns_roce_v1_clear_hem(struct hns_roce_dev *hr_dev,
2287                 struct hns_roce_hem_table *table, int obj)
2288 {
2289         struct device *dev = &hr_dev->pdev->dev;
2290         struct hns_roce_v1_priv *priv;
2291         unsigned long end = 0, flags = 0;
2292         uint32_t bt_cmd_val[2] = {0};
2293         void __iomem *bt_cmd;
2294         u64 bt_ba = 0;
2295
2296         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
2297
2298         switch (table->type) {
2299         case HEM_TYPE_QPC:
2300                 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2301                         ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_QPC);
2302                 bt_ba = priv->bt_table.qpc_buf.map >> 12;
2303                 break;
2304         case HEM_TYPE_MTPT:
2305                 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2306                         ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_MTPT);
2307                 bt_ba = priv->bt_table.mtpt_buf.map >> 12;
2308                 break;
2309         case HEM_TYPE_CQC:
2310                 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2311                         ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_CQC);
2312                 bt_ba = priv->bt_table.cqc_buf.map >> 12;
2313                 break;
2314         case HEM_TYPE_SRQC:
2315                 dev_dbg(dev, "HEM_TYPE_SRQC not support.\n");
2316                 return -EINVAL;
2317         default:
2318                 return 0;
2319         }
2320         roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M,
2321                 ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S, obj);
2322         roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_S, 0);
2323         roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_HW_SYNS_S, 1);
2324
2325         spin_lock_irqsave(&hr_dev->bt_cmd_lock, flags);
2326
2327         bt_cmd = hr_dev->reg_base + ROCEE_BT_CMD_H_REG;
2328
2329         end = msecs_to_jiffies(HW_SYNC_TIMEOUT_MSECS) + jiffies;
2330         while (1) {
2331                 if (readl(bt_cmd) >> BT_CMD_SYNC_SHIFT) {
2332                         if (!(time_before(jiffies, end))) {
2333                                 dev_err(dev, "Write bt_cmd err,hw_sync is not zero.\n");
2334                                 spin_unlock_irqrestore(&hr_dev->bt_cmd_lock,
2335                                         flags);
2336                                 return -EBUSY;
2337                         }
2338                 } else {
2339                         break;
2340                 }
2341                 msleep(HW_SYNC_SLEEP_TIME_INTERVAL);
2342         }
2343
2344         bt_cmd_val[0] = (uint32_t)bt_ba;
2345         roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M,
2346                 ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S, bt_ba >> 32);
2347         hns_roce_write64_k(bt_cmd_val, hr_dev->reg_base + ROCEE_BT_CMD_L_REG);
2348
2349         spin_unlock_irqrestore(&hr_dev->bt_cmd_lock, flags);
2350
2351         return 0;
2352 }
2353
2354 static int hns_roce_v1_qp_modify(struct hns_roce_dev *hr_dev,
2355                                  struct hns_roce_mtt *mtt,
2356                                  enum hns_roce_qp_state cur_state,
2357                                  enum hns_roce_qp_state new_state,
2358                                  struct hns_roce_qp_context *context,
2359                                  struct hns_roce_qp *hr_qp)
2360 {
2361         static const u16
2362         op[HNS_ROCE_QP_NUM_STATE][HNS_ROCE_QP_NUM_STATE] = {
2363                 [HNS_ROCE_QP_STATE_RST] = {
2364                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2365                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2366                 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP,
2367                 },
2368                 [HNS_ROCE_QP_STATE_INIT] = {
2369                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2370                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2371                 /* Note: In v1 engine, HW doesn't support RST2INIT.
2372                  * We use RST2INIT cmd instead of INIT2INIT.
2373                  */
2374                 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP,
2375                 [HNS_ROCE_QP_STATE_RTR] = HNS_ROCE_CMD_INIT2RTR_QP,
2376                 },
2377                 [HNS_ROCE_QP_STATE_RTR] = {
2378                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2379                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2380                 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTR2RTS_QP,
2381                 },
2382                 [HNS_ROCE_QP_STATE_RTS] = {
2383                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2384                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2385                 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTS2RTS_QP,
2386                 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_RTS2SQD_QP,
2387                 },
2388                 [HNS_ROCE_QP_STATE_SQD] = {
2389                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2390                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2391                 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_SQD2RTS_QP,
2392                 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_SQD2SQD_QP,
2393                 },
2394                 [HNS_ROCE_QP_STATE_ERR] = {
2395                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2396                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2397                 }
2398         };
2399
2400         struct hns_roce_cmd_mailbox *mailbox;
2401         struct device *dev = &hr_dev->pdev->dev;
2402         int ret = 0;
2403
2404         if (cur_state >= HNS_ROCE_QP_NUM_STATE ||
2405             new_state >= HNS_ROCE_QP_NUM_STATE ||
2406             !op[cur_state][new_state]) {
2407                 dev_err(dev, "[modify_qp]not support state %d to %d\n",
2408                         cur_state, new_state);
2409                 return -EINVAL;
2410         }
2411
2412         if (op[cur_state][new_state] == HNS_ROCE_CMD_2RST_QP)
2413                 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
2414                                          HNS_ROCE_CMD_2RST_QP,
2415                                          HNS_ROCE_CMD_TIMEOUT_MSECS);
2416
2417         if (op[cur_state][new_state] == HNS_ROCE_CMD_2ERR_QP)
2418                 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
2419                                          HNS_ROCE_CMD_2ERR_QP,
2420                                          HNS_ROCE_CMD_TIMEOUT_MSECS);
2421
2422         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
2423         if (IS_ERR(mailbox))
2424                 return PTR_ERR(mailbox);
2425
2426         memcpy(mailbox->buf, context, sizeof(*context));
2427
2428         ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0,
2429                                 op[cur_state][new_state],
2430                                 HNS_ROCE_CMD_TIMEOUT_MSECS);
2431
2432         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
2433         return ret;
2434 }
2435
2436 static int hns_roce_v1_m_sqp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2437                              int attr_mask, enum ib_qp_state cur_state,
2438                              enum ib_qp_state new_state)
2439 {
2440         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2441         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2442         struct hns_roce_sqp_context *context;
2443         struct device *dev = &hr_dev->pdev->dev;
2444         dma_addr_t dma_handle = 0;
2445         int rq_pa_start;
2446         u32 reg_val;
2447         u64 *mtts;
2448         u32 *addr;
2449
2450         context = kzalloc(sizeof(*context), GFP_KERNEL);
2451         if (!context)
2452                 return -ENOMEM;
2453
2454         /* Search QP buf's MTTs */
2455         mtts = hns_roce_table_find(&hr_dev->mr_table.mtt_table,
2456                                    hr_qp->mtt.first_seg, &dma_handle);
2457         if (!mtts) {
2458                 dev_err(dev, "qp buf pa find failed\n");
2459                 goto out;
2460         }
2461
2462         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2463                 roce_set_field(context->qp1c_bytes_4,
2464                                QP1C_BYTES_4_SQ_WQE_SHIFT_M,
2465                                QP1C_BYTES_4_SQ_WQE_SHIFT_S,
2466                                ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2467                 roce_set_field(context->qp1c_bytes_4,
2468                                QP1C_BYTES_4_RQ_WQE_SHIFT_M,
2469                                QP1C_BYTES_4_RQ_WQE_SHIFT_S,
2470                                ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2471                 roce_set_field(context->qp1c_bytes_4, QP1C_BYTES_4_PD_M,
2472                                QP1C_BYTES_4_PD_S, to_hr_pd(ibqp->pd)->pdn);
2473
2474                 context->sq_rq_bt_l = (u32)(dma_handle);
2475                 roce_set_field(context->qp1c_bytes_12,
2476                                QP1C_BYTES_12_SQ_RQ_BT_H_M,
2477                                QP1C_BYTES_12_SQ_RQ_BT_H_S,
2478                                ((u32)(dma_handle >> 32)));
2479
2480                 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_HEAD_M,
2481                                QP1C_BYTES_16_RQ_HEAD_S, hr_qp->rq.head);
2482                 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_PORT_NUM_M,
2483                                QP1C_BYTES_16_PORT_NUM_S, hr_qp->phy_port);
2484                 roce_set_bit(context->qp1c_bytes_16,
2485                              QP1C_BYTES_16_SIGNALING_TYPE_S,
2486                              hr_qp->sq_signal_bits);
2487                 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_BA_FLG_S,
2488                              1);
2489                 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_SQ_BA_FLG_S,
2490                              1);
2491                 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_QP1_ERR_S,
2492                              0);
2493
2494                 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_SQ_HEAD_M,
2495                                QP1C_BYTES_20_SQ_HEAD_S, hr_qp->sq.head);
2496                 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_PKEY_IDX_M,
2497                                QP1C_BYTES_20_PKEY_IDX_S, attr->pkey_index);
2498
2499                 rq_pa_start = (u32)hr_qp->rq.offset / PAGE_SIZE;
2500                 context->cur_rq_wqe_ba_l = (u32)(mtts[rq_pa_start]);
2501
2502                 roce_set_field(context->qp1c_bytes_28,
2503                                QP1C_BYTES_28_CUR_RQ_WQE_BA_H_M,
2504                                QP1C_BYTES_28_CUR_RQ_WQE_BA_H_S,
2505                                (mtts[rq_pa_start]) >> 32);
2506                 roce_set_field(context->qp1c_bytes_28,
2507                                QP1C_BYTES_28_RQ_CUR_IDX_M,
2508                                QP1C_BYTES_28_RQ_CUR_IDX_S, 0);
2509
2510                 roce_set_field(context->qp1c_bytes_32,
2511                                QP1C_BYTES_32_RX_CQ_NUM_M,
2512                                QP1C_BYTES_32_RX_CQ_NUM_S,
2513                                to_hr_cq(ibqp->recv_cq)->cqn);
2514                 roce_set_field(context->qp1c_bytes_32,
2515                                QP1C_BYTES_32_TX_CQ_NUM_M,
2516                                QP1C_BYTES_32_TX_CQ_NUM_S,
2517                                to_hr_cq(ibqp->send_cq)->cqn);
2518
2519                 context->cur_sq_wqe_ba_l  = (u32)mtts[0];
2520
2521                 roce_set_field(context->qp1c_bytes_40,
2522                                QP1C_BYTES_40_CUR_SQ_WQE_BA_H_M,
2523                                QP1C_BYTES_40_CUR_SQ_WQE_BA_H_S,
2524                                (mtts[0]) >> 32);
2525                 roce_set_field(context->qp1c_bytes_40,
2526                                QP1C_BYTES_40_SQ_CUR_IDX_M,
2527                                QP1C_BYTES_40_SQ_CUR_IDX_S, 0);
2528
2529                 /* Copy context to QP1C register */
2530                 addr = (u32 *)(hr_dev->reg_base + ROCEE_QP1C_CFG0_0_REG +
2531                         hr_qp->phy_port * sizeof(*context));
2532
2533                 writel(context->qp1c_bytes_4, addr);
2534                 writel(context->sq_rq_bt_l, addr + 1);
2535                 writel(context->qp1c_bytes_12, addr + 2);
2536                 writel(context->qp1c_bytes_16, addr + 3);
2537                 writel(context->qp1c_bytes_20, addr + 4);
2538                 writel(context->cur_rq_wqe_ba_l, addr + 5);
2539                 writel(context->qp1c_bytes_28, addr + 6);
2540                 writel(context->qp1c_bytes_32, addr + 7);
2541                 writel(context->cur_sq_wqe_ba_l, addr + 8);
2542                 writel(context->qp1c_bytes_40, addr + 9);
2543         }
2544
2545         /* Modify QP1C status */
2546         reg_val = roce_read(hr_dev, ROCEE_QP1C_CFG0_0_REG +
2547                             hr_qp->phy_port * sizeof(*context));
2548         roce_set_field(reg_val, ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_M,
2549                        ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_S, new_state);
2550         roce_write(hr_dev, ROCEE_QP1C_CFG0_0_REG +
2551                     hr_qp->phy_port * sizeof(*context), reg_val);
2552
2553         hr_qp->state = new_state;
2554         if (new_state == IB_QPS_RESET) {
2555                 hns_roce_v1_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
2556                                      ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
2557                 if (ibqp->send_cq != ibqp->recv_cq)
2558                         hns_roce_v1_cq_clean(to_hr_cq(ibqp->send_cq),
2559                                              hr_qp->qpn, NULL);
2560
2561                 hr_qp->rq.head = 0;
2562                 hr_qp->rq.tail = 0;
2563                 hr_qp->sq.head = 0;
2564                 hr_qp->sq.tail = 0;
2565                 hr_qp->sq_next_wqe = 0;
2566         }
2567
2568         kfree(context);
2569         return 0;
2570
2571 out:
2572         kfree(context);
2573         return -EINVAL;
2574 }
2575
2576 static int hns_roce_v1_m_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2577                             int attr_mask, enum ib_qp_state cur_state,
2578                             enum ib_qp_state new_state)
2579 {
2580         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2581         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2582         struct device *dev = &hr_dev->pdev->dev;
2583         struct hns_roce_qp_context *context;
2584         const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
2585         dma_addr_t dma_handle_2 = 0;
2586         dma_addr_t dma_handle = 0;
2587         uint32_t doorbell[2] = {0};
2588         int rq_pa_start = 0;
2589         u64 *mtts_2 = NULL;
2590         int ret = -EINVAL;
2591         u64 *mtts = NULL;
2592         int port;
2593         u8 port_num;
2594         u8 *dmac;
2595         u8 *smac;
2596
2597         context = kzalloc(sizeof(*context), GFP_KERNEL);
2598         if (!context)
2599                 return -ENOMEM;
2600
2601         /* Search qp buf's mtts */
2602         mtts = hns_roce_table_find(&hr_dev->mr_table.mtt_table,
2603                                    hr_qp->mtt.first_seg, &dma_handle);
2604         if (mtts == NULL) {
2605                 dev_err(dev, "qp buf pa find failed\n");
2606                 goto out;
2607         }
2608
2609         /* Search IRRL's mtts */
2610         mtts_2 = hns_roce_table_find(&hr_dev->qp_table.irrl_table, hr_qp->qpn,
2611                                      &dma_handle_2);
2612         if (mtts_2 == NULL) {
2613                 dev_err(dev, "qp irrl_table find failed\n");
2614                 goto out;
2615         }
2616
2617         /*
2618          * Reset to init
2619          *      Mandatory param:
2620          *      IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS
2621          *      Optional param: NA
2622          */
2623         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2624                 roce_set_field(context->qpc_bytes_4,
2625                                QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
2626                                QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S,
2627                                to_hr_qp_type(hr_qp->ibqp.qp_type));
2628
2629                 roce_set_bit(context->qpc_bytes_4,
2630                              QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S, 0);
2631                 roce_set_bit(context->qpc_bytes_4,
2632                              QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2633                              !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ));
2634                 roce_set_bit(context->qpc_bytes_4,
2635                              QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2636                              !!(attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
2637                              );
2638                 roce_set_bit(context->qpc_bytes_4,
2639                              QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S,
2640                              !!(attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC)
2641                              );
2642                 roce_set_bit(context->qpc_bytes_4,
2643                              QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S, 1);
2644                 roce_set_field(context->qpc_bytes_4,
2645                                QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M,
2646                                QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S,
2647                                ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2648                 roce_set_field(context->qpc_bytes_4,
2649                                QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M,
2650                                QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S,
2651                                ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2652                 roce_set_field(context->qpc_bytes_4,
2653                                QP_CONTEXT_QPC_BYTES_4_PD_M,
2654                                QP_CONTEXT_QPC_BYTES_4_PD_S,
2655                                to_hr_pd(ibqp->pd)->pdn);
2656                 hr_qp->access_flags = attr->qp_access_flags;
2657                 roce_set_field(context->qpc_bytes_8,
2658                                QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M,
2659                                QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S,
2660                                to_hr_cq(ibqp->send_cq)->cqn);
2661                 roce_set_field(context->qpc_bytes_8,
2662                                QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M,
2663                                QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S,
2664                                to_hr_cq(ibqp->recv_cq)->cqn);
2665
2666                 if (ibqp->srq)
2667                         roce_set_field(context->qpc_bytes_12,
2668                                        QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M,
2669                                        QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S,
2670                                        to_hr_srq(ibqp->srq)->srqn);
2671
2672                 roce_set_field(context->qpc_bytes_12,
2673                                QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2674                                QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2675                                attr->pkey_index);
2676                 hr_qp->pkey_index = attr->pkey_index;
2677                 roce_set_field(context->qpc_bytes_16,
2678                                QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
2679                                QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
2680
2681         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
2682                 roce_set_field(context->qpc_bytes_4,
2683                                QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
2684                                QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S,
2685                                to_hr_qp_type(hr_qp->ibqp.qp_type));
2686                 roce_set_bit(context->qpc_bytes_4,
2687                              QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S, 0);
2688                 if (attr_mask & IB_QP_ACCESS_FLAGS) {
2689                         roce_set_bit(context->qpc_bytes_4,
2690                                      QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2691                                      !!(attr->qp_access_flags &
2692                                      IB_ACCESS_REMOTE_READ));
2693                         roce_set_bit(context->qpc_bytes_4,
2694                                      QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2695                                      !!(attr->qp_access_flags &
2696                                      IB_ACCESS_REMOTE_WRITE));
2697                 } else {
2698                         roce_set_bit(context->qpc_bytes_4,
2699                                      QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2700                                      !!(hr_qp->access_flags &
2701                                      IB_ACCESS_REMOTE_READ));
2702                         roce_set_bit(context->qpc_bytes_4,
2703                                      QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2704                                      !!(hr_qp->access_flags &
2705                                      IB_ACCESS_REMOTE_WRITE));
2706                 }
2707
2708                 roce_set_bit(context->qpc_bytes_4,
2709                              QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S, 1);
2710                 roce_set_field(context->qpc_bytes_4,
2711                                QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M,
2712                                QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S,
2713                                ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2714                 roce_set_field(context->qpc_bytes_4,
2715                                QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M,
2716                                QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S,
2717                                ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2718                 roce_set_field(context->qpc_bytes_4,
2719                                QP_CONTEXT_QPC_BYTES_4_PD_M,
2720                                QP_CONTEXT_QPC_BYTES_4_PD_S,
2721                                to_hr_pd(ibqp->pd)->pdn);
2722
2723                 roce_set_field(context->qpc_bytes_8,
2724                                QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M,
2725                                QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S,
2726                                to_hr_cq(ibqp->send_cq)->cqn);
2727                 roce_set_field(context->qpc_bytes_8,
2728                                QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M,
2729                                QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S,
2730                                to_hr_cq(ibqp->recv_cq)->cqn);
2731
2732                 if (ibqp->srq)
2733                         roce_set_field(context->qpc_bytes_12,
2734                                        QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M,
2735                                        QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S,
2736                                        to_hr_srq(ibqp->srq)->srqn);
2737                 if (attr_mask & IB_QP_PKEY_INDEX)
2738                         roce_set_field(context->qpc_bytes_12,
2739                                        QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2740                                        QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2741                                        attr->pkey_index);
2742                 else
2743                         roce_set_field(context->qpc_bytes_12,
2744                                        QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2745                                        QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2746                                        hr_qp->pkey_index);
2747
2748                 roce_set_field(context->qpc_bytes_16,
2749                                QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
2750                                QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
2751         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
2752                 if ((attr_mask & IB_QP_ALT_PATH) ||
2753                     (attr_mask & IB_QP_ACCESS_FLAGS) ||
2754                     (attr_mask & IB_QP_PKEY_INDEX) ||
2755                     (attr_mask & IB_QP_QKEY)) {
2756                         dev_err(dev, "INIT2RTR attr_mask error\n");
2757                         goto out;
2758                 }
2759
2760                 dmac = (u8 *)attr->ah_attr.roce.dmac;
2761
2762                 context->sq_rq_bt_l = (u32)(dma_handle);
2763                 roce_set_field(context->qpc_bytes_24,
2764                                QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_M,
2765                                QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_S,
2766                                ((u32)(dma_handle >> 32)));
2767                 roce_set_bit(context->qpc_bytes_24,
2768                              QP_CONTEXT_QPC_BYTE_24_REMOTE_ENABLE_E2E_CREDITS_S,
2769                              1);
2770                 roce_set_field(context->qpc_bytes_24,
2771                                QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M,
2772                                QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S,
2773                                attr->min_rnr_timer);
2774                 context->irrl_ba_l = (u32)(dma_handle_2);
2775                 roce_set_field(context->qpc_bytes_32,
2776                                QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M,
2777                                QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_S,
2778                                ((u32)(dma_handle_2 >> 32)) &
2779                                 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M);
2780                 roce_set_field(context->qpc_bytes_32,
2781                                QP_CONTEXT_QPC_BYTES_32_MIG_STATE_M,
2782                                QP_CONTEXT_QPC_BYTES_32_MIG_STATE_S, 0);
2783                 roce_set_bit(context->qpc_bytes_32,
2784                              QP_CONTEXT_QPC_BYTE_32_LOCAL_ENABLE_E2E_CREDITS_S,
2785                              1);
2786                 roce_set_bit(context->qpc_bytes_32,
2787                              QP_CONTEXT_QPC_BYTE_32_SIGNALING_TYPE_S,
2788                              hr_qp->sq_signal_bits);
2789
2790                 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) :
2791                         hr_qp->port;
2792                 smac = (u8 *)hr_dev->dev_addr[port];
2793                 /* when dmac equals smac or loop_idc is 1, it should loopback */
2794                 if (ether_addr_equal_unaligned(dmac, smac) ||
2795                     hr_dev->loop_idc == 0x1)
2796                         roce_set_bit(context->qpc_bytes_32,
2797                               QP_CONTEXT_QPC_BYTE_32_LOOPBACK_INDICATOR_S, 1);
2798
2799                 roce_set_bit(context->qpc_bytes_32,
2800                              QP_CONTEXT_QPC_BYTE_32_GLOBAL_HEADER_S,
2801                              rdma_ah_get_ah_flags(&attr->ah_attr));
2802                 roce_set_field(context->qpc_bytes_32,
2803                                QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M,
2804                                QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S,
2805                                ilog2((unsigned int)attr->max_dest_rd_atomic));
2806
2807                 roce_set_field(context->qpc_bytes_36,
2808                                QP_CONTEXT_QPC_BYTES_36_DEST_QP_M,
2809                                QP_CONTEXT_QPC_BYTES_36_DEST_QP_S,
2810                                attr->dest_qp_num);
2811
2812                 /* Configure GID index */
2813                 port_num = rdma_ah_get_port_num(&attr->ah_attr);
2814                 roce_set_field(context->qpc_bytes_36,
2815                                QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M,
2816                                QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S,
2817                                 hns_get_gid_index(hr_dev,
2818                                                   port_num - 1,
2819                                                   grh->sgid_index));
2820
2821                 memcpy(&(context->dmac_l), dmac, 4);
2822
2823                 roce_set_field(context->qpc_bytes_44,
2824                                QP_CONTEXT_QPC_BYTES_44_DMAC_H_M,
2825                                QP_CONTEXT_QPC_BYTES_44_DMAC_H_S,
2826                                *((u16 *)(&dmac[4])));
2827                 roce_set_field(context->qpc_bytes_44,
2828                                QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_M,
2829                                QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_S,
2830                                rdma_ah_get_static_rate(&attr->ah_attr));
2831                 roce_set_field(context->qpc_bytes_44,
2832                                QP_CONTEXT_QPC_BYTES_44_HOPLMT_M,
2833                                QP_CONTEXT_QPC_BYTES_44_HOPLMT_S,
2834                                grh->hop_limit);
2835
2836                 roce_set_field(context->qpc_bytes_48,
2837                                QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M,
2838                                QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S,
2839                                grh->flow_label);
2840                 roce_set_field(context->qpc_bytes_48,
2841                                QP_CONTEXT_QPC_BYTES_48_TCLASS_M,
2842                                QP_CONTEXT_QPC_BYTES_48_TCLASS_S,
2843                                grh->traffic_class);
2844                 roce_set_field(context->qpc_bytes_48,
2845                                QP_CONTEXT_QPC_BYTES_48_MTU_M,
2846                                QP_CONTEXT_QPC_BYTES_48_MTU_S, attr->path_mtu);
2847
2848                 memcpy(context->dgid, grh->dgid.raw,
2849                        sizeof(grh->dgid.raw));
2850
2851                 dev_dbg(dev, "dmac:%x :%lx\n", context->dmac_l,
2852                         roce_get_field(context->qpc_bytes_44,
2853                                        QP_CONTEXT_QPC_BYTES_44_DMAC_H_M,
2854                                        QP_CONTEXT_QPC_BYTES_44_DMAC_H_S));
2855
2856                 roce_set_field(context->qpc_bytes_68,
2857                                QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_M,
2858                                QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_S,
2859                                hr_qp->rq.head);
2860                 roce_set_field(context->qpc_bytes_68,
2861                                QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_M,
2862                                QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_S, 0);
2863
2864                 rq_pa_start = (u32)hr_qp->rq.offset / PAGE_SIZE;
2865                 context->cur_rq_wqe_ba_l = (u32)(mtts[rq_pa_start]);
2866
2867                 roce_set_field(context->qpc_bytes_76,
2868                         QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_M,
2869                         QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_S,
2870                         mtts[rq_pa_start] >> 32);
2871                 roce_set_field(context->qpc_bytes_76,
2872                                QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_M,
2873                                QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_S, 0);
2874
2875                 context->rx_rnr_time = 0;
2876
2877                 roce_set_field(context->qpc_bytes_84,
2878                                QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_M,
2879                                QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_S,
2880                                attr->rq_psn - 1);
2881                 roce_set_field(context->qpc_bytes_84,
2882                                QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_M,
2883                                QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_S, 0);
2884
2885                 roce_set_field(context->qpc_bytes_88,
2886                                QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M,
2887                                QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S,
2888                                attr->rq_psn);
2889                 roce_set_bit(context->qpc_bytes_88,
2890                              QP_CONTEXT_QPC_BYTES_88_RX_REQ_PSN_ERR_FLAG_S, 0);
2891                 roce_set_bit(context->qpc_bytes_88,
2892                              QP_CONTEXT_QPC_BYTES_88_RX_LAST_OPCODE_FLG_S, 0);
2893                 roce_set_field(context->qpc_bytes_88,
2894                         QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_M,
2895                         QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_S,
2896                         0);
2897                 roce_set_field(context->qpc_bytes_88,
2898                                QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_M,
2899                                QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_S,
2900                                0);
2901
2902                 context->dma_length = 0;
2903                 context->r_key = 0;
2904                 context->va_l = 0;
2905                 context->va_h = 0;
2906
2907                 roce_set_field(context->qpc_bytes_108,
2908                                QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_M,
2909                                QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_S, 0);
2910                 roce_set_bit(context->qpc_bytes_108,
2911                              QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_FLG_S, 0);
2912                 roce_set_bit(context->qpc_bytes_108,
2913                              QP_CONTEXT_QPC_BYTES_108_TRRL_TDB_PSN_FLG_S, 0);
2914
2915                 roce_set_field(context->qpc_bytes_112,
2916                                QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_M,
2917                                QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_S, 0);
2918                 roce_set_field(context->qpc_bytes_112,
2919                                QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_M,
2920                                QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_S, 0);
2921
2922                 /* For chip resp ack */
2923                 roce_set_field(context->qpc_bytes_156,
2924                                QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
2925                                QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S,
2926                                hr_qp->phy_port);
2927                 roce_set_field(context->qpc_bytes_156,
2928                                QP_CONTEXT_QPC_BYTES_156_SL_M,
2929                                QP_CONTEXT_QPC_BYTES_156_SL_S,
2930                                rdma_ah_get_sl(&attr->ah_attr));
2931                 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
2932         } else if (cur_state == IB_QPS_RTR &&
2933                 new_state == IB_QPS_RTS) {
2934                 /* If exist optional param, return error */
2935                 if ((attr_mask & IB_QP_ALT_PATH) ||
2936                     (attr_mask & IB_QP_ACCESS_FLAGS) ||
2937                     (attr_mask & IB_QP_QKEY) ||
2938                     (attr_mask & IB_QP_PATH_MIG_STATE) ||
2939                     (attr_mask & IB_QP_CUR_STATE) ||
2940                     (attr_mask & IB_QP_MIN_RNR_TIMER)) {
2941                         dev_err(dev, "RTR2RTS attr_mask error\n");
2942                         goto out;
2943                 }
2944
2945                 context->rx_cur_sq_wqe_ba_l = (u32)(mtts[0]);
2946
2947                 roce_set_field(context->qpc_bytes_120,
2948                                QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_M,
2949                                QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_S,
2950                                (mtts[0]) >> 32);
2951
2952                 roce_set_field(context->qpc_bytes_124,
2953                                QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_M,
2954                                QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_S, 0);
2955                 roce_set_field(context->qpc_bytes_124,
2956                                QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_M,
2957                                QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_S, 0);
2958
2959                 roce_set_field(context->qpc_bytes_128,
2960                                QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_M,
2961                                QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_S,
2962                                attr->sq_psn);
2963                 roce_set_bit(context->qpc_bytes_128,
2964                              QP_CONTEXT_QPC_BYTES_128_RX_ACK_PSN_ERR_FLG_S, 0);
2965                 roce_set_field(context->qpc_bytes_128,
2966                              QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_M,
2967                              QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_S,
2968                              0);
2969                 roce_set_bit(context->qpc_bytes_128,
2970                              QP_CONTEXT_QPC_BYTES_128_IRRL_PSN_VLD_FLG_S, 0);
2971
2972                 roce_set_field(context->qpc_bytes_132,
2973                                QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_M,
2974                                QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_S, 0);
2975                 roce_set_field(context->qpc_bytes_132,
2976                                QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_M,
2977                                QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_S, 0);
2978
2979                 roce_set_field(context->qpc_bytes_136,
2980                                QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_M,
2981                                QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_S,
2982                                attr->sq_psn);
2983                 roce_set_field(context->qpc_bytes_136,
2984                                QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_M,
2985                                QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_S,
2986                                attr->sq_psn);
2987
2988                 roce_set_field(context->qpc_bytes_140,
2989                                QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_M,
2990                                QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_S,
2991                                (attr->sq_psn >> SQ_PSN_SHIFT));
2992                 roce_set_field(context->qpc_bytes_140,
2993                                QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_M,
2994                                QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_S, 0);
2995                 roce_set_bit(context->qpc_bytes_140,
2996                              QP_CONTEXT_QPC_BYTES_140_RNR_RETRY_FLG_S, 0);
2997
2998                 roce_set_field(context->qpc_bytes_148,
2999                                QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_M,
3000                                QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_S, 0);
3001                 roce_set_field(context->qpc_bytes_148,
3002                                QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
3003                                QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S,
3004                                attr->retry_cnt);
3005                 roce_set_field(context->qpc_bytes_148,
3006                                QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_M,
3007                                QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_S,
3008                                attr->rnr_retry);
3009                 roce_set_field(context->qpc_bytes_148,
3010                                QP_CONTEXT_QPC_BYTES_148_LSN_M,
3011                                QP_CONTEXT_QPC_BYTES_148_LSN_S, 0x100);
3012
3013                 context->rnr_retry = 0;
3014
3015                 roce_set_field(context->qpc_bytes_156,
3016                                QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_M,
3017                                QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_S,
3018                                attr->retry_cnt);
3019                 if (attr->timeout < 0x12) {
3020                         dev_info(dev, "ack timeout value(0x%x) must bigger than 0x12.\n",
3021                                  attr->timeout);
3022                         roce_set_field(context->qpc_bytes_156,
3023                                        QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3024                                        QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S,
3025                                        0x12);
3026                 } else {
3027                         roce_set_field(context->qpc_bytes_156,
3028                                        QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3029                                        QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S,
3030                                        attr->timeout);
3031                 }
3032                 roce_set_field(context->qpc_bytes_156,
3033                                QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_M,
3034                                QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_S,
3035                                attr->rnr_retry);
3036                 roce_set_field(context->qpc_bytes_156,
3037                                QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
3038                                QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S,
3039                                hr_qp->phy_port);
3040                 roce_set_field(context->qpc_bytes_156,
3041                                QP_CONTEXT_QPC_BYTES_156_SL_M,
3042                                QP_CONTEXT_QPC_BYTES_156_SL_S,
3043                                rdma_ah_get_sl(&attr->ah_attr));
3044                 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
3045                 roce_set_field(context->qpc_bytes_156,
3046                                QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
3047                                QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S,
3048                                ilog2((unsigned int)attr->max_rd_atomic));
3049                 roce_set_field(context->qpc_bytes_156,
3050                                QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_M,
3051                                QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_S, 0);
3052                 context->pkt_use_len = 0;
3053
3054                 roce_set_field(context->qpc_bytes_164,
3055                                QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M,
3056                                QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S, attr->sq_psn);
3057                 roce_set_field(context->qpc_bytes_164,
3058                                QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_M,
3059                                QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_S, 0);
3060
3061                 roce_set_field(context->qpc_bytes_168,
3062                                QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_M,
3063                                QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_S,
3064                                attr->sq_psn);
3065                 roce_set_field(context->qpc_bytes_168,
3066                                QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_M,
3067                                QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_S, 0);
3068                 roce_set_field(context->qpc_bytes_168,
3069                                QP_CONTEXT_QPC_BYTES_168_DB_TYPE_M,
3070                                QP_CONTEXT_QPC_BYTES_168_DB_TYPE_S, 0);
3071                 roce_set_bit(context->qpc_bytes_168,
3072                              QP_CONTEXT_QPC_BYTES_168_MSG_LP_IND_S, 0);
3073                 roce_set_bit(context->qpc_bytes_168,
3074                              QP_CONTEXT_QPC_BYTES_168_CSDB_LP_IND_S, 0);
3075                 roce_set_bit(context->qpc_bytes_168,
3076                              QP_CONTEXT_QPC_BYTES_168_QP_ERR_FLG_S, 0);
3077                 context->sge_use_len = 0;
3078
3079                 roce_set_field(context->qpc_bytes_176,
3080                                QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_M,
3081                                QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_S, 0);
3082                 roce_set_field(context->qpc_bytes_176,
3083                                QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_M,
3084                                QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_S,
3085                                0);
3086                 roce_set_field(context->qpc_bytes_180,
3087                                QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_M,
3088                                QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_S, 0);
3089                 roce_set_field(context->qpc_bytes_180,
3090                                QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_M,
3091                                QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_S, 0);
3092
3093                 context->tx_cur_sq_wqe_ba_l = (u32)(mtts[0]);
3094
3095                 roce_set_field(context->qpc_bytes_188,
3096                                QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_M,
3097                                QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_S,
3098                                (mtts[0]) >> 32);
3099                 roce_set_bit(context->qpc_bytes_188,
3100                              QP_CONTEXT_QPC_BYTES_188_PKT_RETRY_FLG_S, 0);
3101                 roce_set_field(context->qpc_bytes_188,
3102                                QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_M,
3103                                QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_S,
3104                                0);
3105         } else if (!((cur_state == IB_QPS_INIT && new_state == IB_QPS_RESET) ||
3106                    (cur_state == IB_QPS_INIT && new_state == IB_QPS_ERR) ||
3107                    (cur_state == IB_QPS_RTR && new_state == IB_QPS_RESET) ||
3108                    (cur_state == IB_QPS_RTR && new_state == IB_QPS_ERR) ||
3109                    (cur_state == IB_QPS_RTS && new_state == IB_QPS_RESET) ||
3110                    (cur_state == IB_QPS_RTS && new_state == IB_QPS_ERR) ||
3111                    (cur_state == IB_QPS_ERR && new_state == IB_QPS_RESET) ||
3112                    (cur_state == IB_QPS_ERR && new_state == IB_QPS_ERR))) {
3113                 dev_err(dev, "not support this status migration\n");
3114                 goto out;
3115         }
3116
3117         /* Every status migrate must change state */
3118         roce_set_field(context->qpc_bytes_144,
3119                        QP_CONTEXT_QPC_BYTES_144_QP_STATE_M,
3120                        QP_CONTEXT_QPC_BYTES_144_QP_STATE_S, new_state);
3121
3122         /* SW pass context to HW */
3123         ret = hns_roce_v1_qp_modify(hr_dev, &hr_qp->mtt,
3124                                     to_hns_roce_state(cur_state),
3125                                     to_hns_roce_state(new_state), context,
3126                                     hr_qp);
3127         if (ret) {
3128                 dev_err(dev, "hns_roce_qp_modify failed\n");
3129                 goto out;
3130         }
3131
3132         /*
3133          * Use rst2init to instead of init2init with drv,
3134          * need to hw to flash RQ HEAD by DB again
3135          */
3136         if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3137                 /* Memory barrier */
3138                 wmb();
3139
3140                 roce_set_field(doorbell[0], RQ_DOORBELL_U32_4_RQ_HEAD_M,
3141                                RQ_DOORBELL_U32_4_RQ_HEAD_S, hr_qp->rq.head);
3142                 roce_set_field(doorbell[1], RQ_DOORBELL_U32_8_QPN_M,
3143                                RQ_DOORBELL_U32_8_QPN_S, hr_qp->qpn);
3144                 roce_set_field(doorbell[1], RQ_DOORBELL_U32_8_CMD_M,
3145                                RQ_DOORBELL_U32_8_CMD_S, 1);
3146                 roce_set_bit(doorbell[1], RQ_DOORBELL_U32_8_HW_SYNC_S, 1);
3147
3148                 if (ibqp->uobject) {
3149                         hr_qp->rq.db_reg_l = hr_dev->reg_base +
3150                                      ROCEE_DB_OTHERS_L_0_REG +
3151                                      DB_REG_OFFSET * hr_dev->priv_uar.index;
3152                 }
3153
3154                 hns_roce_write64_k(doorbell, hr_qp->rq.db_reg_l);
3155         }
3156
3157         hr_qp->state = new_state;
3158
3159         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3160                 hr_qp->resp_depth = attr->max_dest_rd_atomic;
3161         if (attr_mask & IB_QP_PORT) {
3162                 hr_qp->port = attr->port_num - 1;
3163                 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
3164         }
3165
3166         if (new_state == IB_QPS_RESET && !ibqp->uobject) {
3167                 hns_roce_v1_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
3168                                      ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
3169                 if (ibqp->send_cq != ibqp->recv_cq)
3170                         hns_roce_v1_cq_clean(to_hr_cq(ibqp->send_cq),
3171                                              hr_qp->qpn, NULL);
3172
3173                 hr_qp->rq.head = 0;
3174                 hr_qp->rq.tail = 0;
3175                 hr_qp->sq.head = 0;
3176                 hr_qp->sq.tail = 0;
3177                 hr_qp->sq_next_wqe = 0;
3178         }
3179 out:
3180         kfree(context);
3181         return ret;
3182 }
3183
3184 int hns_roce_v1_modify_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
3185                           int attr_mask, enum ib_qp_state cur_state,
3186                           enum ib_qp_state new_state)
3187 {
3188
3189         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
3190                 return hns_roce_v1_m_sqp(ibqp, attr, attr_mask, cur_state,
3191                                          new_state);
3192         else
3193                 return hns_roce_v1_m_qp(ibqp, attr, attr_mask, cur_state,
3194                                         new_state);
3195 }
3196
3197 static enum ib_qp_state to_ib_qp_state(enum hns_roce_qp_state state)
3198 {
3199         switch (state) {
3200         case HNS_ROCE_QP_STATE_RST:
3201                 return IB_QPS_RESET;
3202         case HNS_ROCE_QP_STATE_INIT:
3203                 return IB_QPS_INIT;
3204         case HNS_ROCE_QP_STATE_RTR:
3205                 return IB_QPS_RTR;
3206         case HNS_ROCE_QP_STATE_RTS:
3207                 return IB_QPS_RTS;
3208         case HNS_ROCE_QP_STATE_SQD:
3209                 return IB_QPS_SQD;
3210         case HNS_ROCE_QP_STATE_ERR:
3211                 return IB_QPS_ERR;
3212         default:
3213                 return IB_QPS_ERR;
3214         }
3215 }
3216
3217 static int hns_roce_v1_query_qpc(struct hns_roce_dev *hr_dev,
3218                                  struct hns_roce_qp *hr_qp,
3219                                  struct hns_roce_qp_context *hr_context)
3220 {
3221         struct hns_roce_cmd_mailbox *mailbox;
3222         int ret;
3223
3224         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3225         if (IS_ERR(mailbox))
3226                 return PTR_ERR(mailbox);
3227
3228         ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0,
3229                                 HNS_ROCE_CMD_QUERY_QP,
3230                                 HNS_ROCE_CMD_TIMEOUT_MSECS);
3231         if (!ret)
3232                 memcpy(hr_context, mailbox->buf, sizeof(*hr_context));
3233         else
3234                 dev_err(&hr_dev->pdev->dev, "QUERY QP cmd process error\n");
3235
3236         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3237
3238         return ret;
3239 }
3240
3241 static int hns_roce_v1_q_sqp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3242                              int qp_attr_mask,
3243                              struct ib_qp_init_attr *qp_init_attr)
3244 {
3245         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3246         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3247         struct hns_roce_sqp_context context;
3248         u32 addr;
3249
3250         mutex_lock(&hr_qp->mutex);
3251
3252         if (hr_qp->state == IB_QPS_RESET) {
3253                 qp_attr->qp_state = IB_QPS_RESET;
3254                 goto done;
3255         }
3256
3257         addr = ROCEE_QP1C_CFG0_0_REG +
3258                 hr_qp->port * sizeof(struct hns_roce_sqp_context);
3259         context.qp1c_bytes_4 = roce_read(hr_dev, addr);
3260         context.sq_rq_bt_l = roce_read(hr_dev, addr + 1);
3261         context.qp1c_bytes_12 = roce_read(hr_dev, addr + 2);
3262         context.qp1c_bytes_16 = roce_read(hr_dev, addr + 3);
3263         context.qp1c_bytes_20 = roce_read(hr_dev, addr + 4);
3264         context.cur_rq_wqe_ba_l = roce_read(hr_dev, addr + 5);
3265         context.qp1c_bytes_28 = roce_read(hr_dev, addr + 6);
3266         context.qp1c_bytes_32 = roce_read(hr_dev, addr + 7);
3267         context.cur_sq_wqe_ba_l = roce_read(hr_dev, addr + 8);
3268         context.qp1c_bytes_40 = roce_read(hr_dev, addr + 9);
3269
3270         hr_qp->state = roce_get_field(context.qp1c_bytes_4,
3271                                       QP1C_BYTES_4_QP_STATE_M,
3272                                       QP1C_BYTES_4_QP_STATE_S);
3273         qp_attr->qp_state       = hr_qp->state;
3274         qp_attr->path_mtu       = IB_MTU_256;
3275         qp_attr->path_mig_state = IB_MIG_ARMED;
3276         qp_attr->qkey           = QKEY_VAL;
3277         qp_attr->rq_psn         = 0;
3278         qp_attr->sq_psn         = 0;
3279         qp_attr->dest_qp_num    = 1;
3280         qp_attr->qp_access_flags = 6;
3281
3282         qp_attr->pkey_index = roce_get_field(context.qp1c_bytes_20,
3283                                              QP1C_BYTES_20_PKEY_IDX_M,
3284                                              QP1C_BYTES_20_PKEY_IDX_S);
3285         qp_attr->port_num = hr_qp->port + 1;
3286         qp_attr->sq_draining = 0;
3287         qp_attr->max_rd_atomic = 0;
3288         qp_attr->max_dest_rd_atomic = 0;
3289         qp_attr->min_rnr_timer = 0;
3290         qp_attr->timeout = 0;
3291         qp_attr->retry_cnt = 0;
3292         qp_attr->rnr_retry = 0;
3293         qp_attr->alt_timeout = 0;
3294
3295 done:
3296         qp_attr->cur_qp_state = qp_attr->qp_state;
3297         qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3298         qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3299         qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3300         qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3301         qp_attr->cap.max_inline_data = 0;
3302         qp_init_attr->cap = qp_attr->cap;
3303         qp_init_attr->create_flags = 0;
3304
3305         mutex_unlock(&hr_qp->mutex);
3306
3307         return 0;
3308 }
3309
3310 static int hns_roce_v1_q_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3311                             int qp_attr_mask,
3312                             struct ib_qp_init_attr *qp_init_attr)
3313 {
3314         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3315         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3316         struct device *dev = &hr_dev->pdev->dev;
3317         struct hns_roce_qp_context *context;
3318         int tmp_qp_state = 0;
3319         int ret = 0;
3320         int state;
3321
3322         context = kzalloc(sizeof(*context), GFP_KERNEL);
3323         if (!context)
3324                 return -ENOMEM;
3325
3326         memset(qp_attr, 0, sizeof(*qp_attr));
3327         memset(qp_init_attr, 0, sizeof(*qp_init_attr));
3328
3329         mutex_lock(&hr_qp->mutex);
3330
3331         if (hr_qp->state == IB_QPS_RESET) {
3332                 qp_attr->qp_state = IB_QPS_RESET;
3333                 goto done;
3334         }
3335
3336         ret = hns_roce_v1_query_qpc(hr_dev, hr_qp, context);
3337         if (ret) {
3338                 dev_err(dev, "query qpc error\n");
3339                 ret = -EINVAL;
3340                 goto out;
3341         }
3342
3343         state = roce_get_field(context->qpc_bytes_144,
3344                                QP_CONTEXT_QPC_BYTES_144_QP_STATE_M,
3345                                QP_CONTEXT_QPC_BYTES_144_QP_STATE_S);
3346         tmp_qp_state = (int)to_ib_qp_state((enum hns_roce_qp_state)state);
3347         if (tmp_qp_state == -1) {
3348                 dev_err(dev, "to_ib_qp_state error\n");
3349                 ret = -EINVAL;
3350                 goto out;
3351         }
3352         hr_qp->state = (u8)tmp_qp_state;
3353         qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
3354         qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context->qpc_bytes_48,
3355                                                QP_CONTEXT_QPC_BYTES_48_MTU_M,
3356                                                QP_CONTEXT_QPC_BYTES_48_MTU_S);
3357         qp_attr->path_mig_state = IB_MIG_ARMED;
3358         if (hr_qp->ibqp.qp_type == IB_QPT_UD)
3359                 qp_attr->qkey = QKEY_VAL;
3360
3361         qp_attr->rq_psn = roce_get_field(context->qpc_bytes_88,
3362                                          QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M,
3363                                          QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S);
3364         qp_attr->sq_psn = (u32)roce_get_field(context->qpc_bytes_164,
3365                                              QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M,
3366                                              QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S);
3367         qp_attr->dest_qp_num = (u8)roce_get_field(context->qpc_bytes_36,
3368                                         QP_CONTEXT_QPC_BYTES_36_DEST_QP_M,
3369                                         QP_CONTEXT_QPC_BYTES_36_DEST_QP_S);
3370         qp_attr->qp_access_flags = ((roce_get_bit(context->qpc_bytes_4,
3371                         QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S)) << 2) |
3372                                    ((roce_get_bit(context->qpc_bytes_4,
3373                         QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S)) << 1) |
3374                                    ((roce_get_bit(context->qpc_bytes_4,
3375                         QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S)) << 3);
3376
3377         if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
3378             hr_qp->ibqp.qp_type == IB_QPT_UC) {
3379                 struct ib_global_route *grh =
3380                         rdma_ah_retrieve_grh(&qp_attr->ah_attr);
3381
3382                 rdma_ah_set_sl(&qp_attr->ah_attr,
3383                                roce_get_field(context->qpc_bytes_156,
3384                                               QP_CONTEXT_QPC_BYTES_156_SL_M,
3385                                               QP_CONTEXT_QPC_BYTES_156_SL_S));
3386                 rdma_ah_set_ah_flags(&qp_attr->ah_attr, IB_AH_GRH);
3387                 grh->flow_label =
3388                         roce_get_field(context->qpc_bytes_48,
3389                                        QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M,
3390                                        QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S);
3391                 grh->sgid_index =
3392                         roce_get_field(context->qpc_bytes_36,
3393                                        QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M,
3394                                        QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S);
3395                 grh->hop_limit =
3396                         roce_get_field(context->qpc_bytes_44,
3397                                        QP_CONTEXT_QPC_BYTES_44_HOPLMT_M,
3398                                        QP_CONTEXT_QPC_BYTES_44_HOPLMT_S);
3399                 grh->traffic_class =
3400                         roce_get_field(context->qpc_bytes_48,
3401                                        QP_CONTEXT_QPC_BYTES_48_TCLASS_M,
3402                                        QP_CONTEXT_QPC_BYTES_48_TCLASS_S);
3403
3404                 memcpy(grh->dgid.raw, context->dgid,
3405                        sizeof(grh->dgid.raw));
3406         }
3407
3408         qp_attr->pkey_index = roce_get_field(context->qpc_bytes_12,
3409                               QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
3410                               QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S);
3411         qp_attr->port_num = hr_qp->port + 1;
3412         qp_attr->sq_draining = 0;
3413         qp_attr->max_rd_atomic = roce_get_field(context->qpc_bytes_156,
3414                                  QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
3415                                  QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S);
3416         qp_attr->max_dest_rd_atomic = roce_get_field(context->qpc_bytes_32,
3417                                  QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M,
3418                                  QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S);
3419         qp_attr->min_rnr_timer = (u8)(roce_get_field(context->qpc_bytes_24,
3420                         QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M,
3421                         QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S));
3422         qp_attr->timeout = (u8)(roce_get_field(context->qpc_bytes_156,
3423                             QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3424                             QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S));
3425         qp_attr->retry_cnt = roce_get_field(context->qpc_bytes_148,
3426                              QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
3427                              QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S);
3428         qp_attr->rnr_retry = context->rnr_retry;
3429
3430 done:
3431         qp_attr->cur_qp_state = qp_attr->qp_state;
3432         qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3433         qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3434
3435         if (!ibqp->uobject) {
3436                 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3437                 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3438         } else {
3439                 qp_attr->cap.max_send_wr = 0;
3440                 qp_attr->cap.max_send_sge = 0;
3441         }
3442
3443         qp_init_attr->cap = qp_attr->cap;
3444
3445 out:
3446         mutex_unlock(&hr_qp->mutex);
3447         kfree(context);
3448         return ret;
3449 }
3450
3451 int hns_roce_v1_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3452                          int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
3453 {
3454         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3455
3456         return hr_qp->doorbell_qpn <= 1 ?
3457                 hns_roce_v1_q_sqp(ibqp, qp_attr, qp_attr_mask, qp_init_attr) :
3458                 hns_roce_v1_q_qp(ibqp, qp_attr, qp_attr_mask, qp_init_attr);
3459 }
3460
3461 static int check_qp_db_process_status(struct hns_roce_dev *hr_dev,
3462                                       struct hns_roce_qp *hr_qp,
3463                                       u32 sdb_issue_ptr,
3464                                       u32 *sdb_inv_cnt,
3465                                       u32 *wait_stage)
3466 {
3467         struct device *dev = &hr_dev->pdev->dev;
3468         u32 sdb_retry_cnt, old_retry;
3469         u32 sdb_send_ptr, old_send;
3470         u32 success_flags = 0;
3471         u32 cur_cnt, old_cnt;
3472         unsigned long end;
3473         u32 send_ptr;
3474         u32 inv_cnt;
3475         u32 tsp_st;
3476
3477         if (*wait_stage > HNS_ROCE_V1_DB_STAGE2 ||
3478             *wait_stage < HNS_ROCE_V1_DB_STAGE1) {
3479                 dev_err(dev, "QP(0x%lx) db status wait stage(%d) error!\n",
3480                         hr_qp->qpn, *wait_stage);
3481                 return -EINVAL;
3482         }
3483
3484         /* Calculate the total timeout for the entire verification process */
3485         end = msecs_to_jiffies(HNS_ROCE_V1_CHECK_DB_TIMEOUT_MSECS) + jiffies;
3486
3487         if (*wait_stage == HNS_ROCE_V1_DB_STAGE1) {
3488                 /* Query db process status, until hw process completely */
3489                 sdb_send_ptr = roce_read(hr_dev, ROCEE_SDB_SEND_PTR_REG);
3490                 while (roce_hw_index_cmp_lt(sdb_send_ptr, sdb_issue_ptr,
3491                                             ROCEE_SDB_PTR_CMP_BITS)) {
3492                         if (!time_before(jiffies, end)) {
3493                                 dev_dbg(dev, "QP(0x%lx) db process stage1 timeout. issue 0x%x send 0x%x.\n",
3494                                         hr_qp->qpn, sdb_issue_ptr,
3495                                         sdb_send_ptr);
3496                                 return 0;
3497                         }
3498
3499                         msleep(HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS);
3500                         sdb_send_ptr = roce_read(hr_dev,
3501                                                  ROCEE_SDB_SEND_PTR_REG);
3502                 }
3503
3504                 if (roce_get_field(sdb_issue_ptr,
3505                                    ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_M,
3506                                    ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_S) ==
3507                     roce_get_field(sdb_send_ptr,
3508                                    ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3509                                    ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S)) {
3510                         old_send = roce_read(hr_dev, ROCEE_SDB_SEND_PTR_REG);
3511                         old_retry = roce_read(hr_dev, ROCEE_SDB_RETRY_CNT_REG);
3512
3513                         do {
3514                                 tsp_st = roce_read(hr_dev, ROCEE_TSP_BP_ST_REG);
3515                                 if (roce_get_bit(tsp_st,
3516                                         ROCEE_TSP_BP_ST_QH_FIFO_ENTRY_S) == 1) {
3517                                         *wait_stage = HNS_ROCE_V1_DB_WAIT_OK;
3518                                         return 0;
3519                                 }
3520
3521                                 if (!time_before(jiffies, end)) {
3522                                         dev_dbg(dev, "QP(0x%lx) db process stage1 timeout when send ptr equals issue ptr.\n"
3523                                                      "issue 0x%x send 0x%x.\n",
3524                                                 hr_qp->qpn, sdb_issue_ptr,
3525                                                 sdb_send_ptr);
3526                                         return 0;
3527                                 }
3528
3529                                 msleep(HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS);
3530
3531                                 sdb_send_ptr = roce_read(hr_dev,
3532                                                         ROCEE_SDB_SEND_PTR_REG);
3533                                 sdb_retry_cnt = roce_read(hr_dev,
3534                                                        ROCEE_SDB_RETRY_CNT_REG);
3535                                 cur_cnt = roce_get_field(sdb_send_ptr,
3536                                         ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3537                                         ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
3538                                         roce_get_field(sdb_retry_cnt,
3539                                         ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3540                                         ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3541                                 if (!roce_get_bit(tsp_st,
3542                                         ROCEE_CNT_CLR_CE_CNT_CLR_CE_S)) {
3543                                         old_cnt = roce_get_field(old_send,
3544                                         ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3545                                         ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
3546                                         roce_get_field(old_retry,
3547                                         ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3548                                         ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3549                                         if (cur_cnt - old_cnt > SDB_ST_CMP_VAL)
3550                                                 success_flags = 1;
3551                                 } else {
3552                                         old_cnt = roce_get_field(old_send,
3553                                         ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3554                                         ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S);
3555                                         if (cur_cnt - old_cnt >
3556                                             SDB_ST_CMP_VAL) {
3557                                                 success_flags = 1;
3558                                         } else {
3559                                                 send_ptr =
3560                                                         roce_get_field(old_send,
3561                                             ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3562                                             ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
3563                                             roce_get_field(sdb_retry_cnt,
3564                                             ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3565                                             ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3566                                             roce_set_field(old_send,
3567                                             ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3568                                             ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S,
3569                                                 send_ptr);
3570                                         }
3571                                 }
3572                         } while (!success_flags);
3573                 }
3574
3575                 *wait_stage = HNS_ROCE_V1_DB_STAGE2;
3576
3577                 /* Get list pointer */
3578                 *sdb_inv_cnt = roce_read(hr_dev, ROCEE_SDB_INV_CNT_REG);
3579                 dev_dbg(dev, "QP(0x%lx) db process stage2. inv cnt = 0x%x.\n",
3580                         hr_qp->qpn, *sdb_inv_cnt);
3581         }
3582
3583         if (*wait_stage == HNS_ROCE_V1_DB_STAGE2) {
3584                 /* Query db's list status, until hw reversal */
3585                 inv_cnt = roce_read(hr_dev, ROCEE_SDB_INV_CNT_REG);
3586                 while (roce_hw_index_cmp_lt(inv_cnt,
3587                                             *sdb_inv_cnt + SDB_INV_CNT_OFFSET,
3588                                             ROCEE_SDB_CNT_CMP_BITS)) {
3589                         if (!time_before(jiffies, end)) {
3590                                 dev_dbg(dev, "QP(0x%lx) db process stage2 timeout. inv cnt 0x%x.\n",
3591                                         hr_qp->qpn, inv_cnt);
3592                                 return 0;
3593                         }
3594
3595                         msleep(HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS);
3596                         inv_cnt = roce_read(hr_dev, ROCEE_SDB_INV_CNT_REG);
3597                 }
3598
3599                 *wait_stage = HNS_ROCE_V1_DB_WAIT_OK;
3600         }
3601
3602         return 0;
3603 }
3604
3605 static int check_qp_reset_state(struct hns_roce_dev *hr_dev,
3606                                 struct hns_roce_qp *hr_qp,
3607                                 struct hns_roce_qp_work *qp_work_entry,
3608                                 int *is_timeout)
3609 {
3610         struct device *dev = &hr_dev->pdev->dev;
3611         u32 sdb_issue_ptr;
3612         int ret;
3613
3614         if (hr_qp->state != IB_QPS_RESET) {
3615                 /* Set qp to ERR, waiting for hw complete processing all dbs */
3616                 ret = hns_roce_v1_modify_qp(&hr_qp->ibqp, NULL, 0, hr_qp->state,
3617                                             IB_QPS_ERR);
3618                 if (ret) {
3619                         dev_err(dev, "Modify QP(0x%lx) to ERR failed!\n",
3620                                 hr_qp->qpn);
3621                         return ret;
3622                 }
3623
3624                 /* Record issued doorbell */
3625                 sdb_issue_ptr = roce_read(hr_dev, ROCEE_SDB_ISSUE_PTR_REG);
3626                 qp_work_entry->sdb_issue_ptr = sdb_issue_ptr;
3627                 qp_work_entry->db_wait_stage = HNS_ROCE_V1_DB_STAGE1;
3628
3629                 /* Query db process status, until hw process completely */
3630                 ret = check_qp_db_process_status(hr_dev, hr_qp, sdb_issue_ptr,
3631                                                  &qp_work_entry->sdb_inv_cnt,
3632                                                  &qp_work_entry->db_wait_stage);
3633                 if (ret) {
3634                         dev_err(dev, "Check QP(0x%lx) db process status failed!\n",
3635                                 hr_qp->qpn);
3636                         return ret;
3637                 }
3638
3639                 if (qp_work_entry->db_wait_stage != HNS_ROCE_V1_DB_WAIT_OK) {
3640                         qp_work_entry->sche_cnt = 0;
3641                         *is_timeout = 1;
3642                         return 0;
3643                 }
3644
3645                 /* Modify qp to reset before destroying qp */
3646                 ret = hns_roce_v1_modify_qp(&hr_qp->ibqp, NULL, 0, hr_qp->state,
3647                                             IB_QPS_RESET);
3648                 if (ret) {
3649                         dev_err(dev, "Modify QP(0x%lx) to RST failed!\n",
3650                                 hr_qp->qpn);
3651                         return ret;
3652                 }
3653         }
3654
3655         return 0;
3656 }
3657
3658 static void hns_roce_v1_destroy_qp_work_fn(struct work_struct *work)
3659 {
3660         struct hns_roce_qp_work *qp_work_entry;
3661         struct hns_roce_v1_priv *priv;
3662         struct hns_roce_dev *hr_dev;
3663         struct hns_roce_qp *hr_qp;
3664         struct device *dev;
3665         unsigned long qpn;
3666         int ret;
3667
3668         qp_work_entry = container_of(work, struct hns_roce_qp_work, work);
3669         hr_dev = to_hr_dev(qp_work_entry->ib_dev);
3670         dev = &hr_dev->pdev->dev;
3671         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
3672         hr_qp = qp_work_entry->qp;
3673         qpn = hr_qp->qpn;
3674
3675         dev_dbg(dev, "Schedule destroy QP(0x%lx) work.\n", qpn);
3676
3677         qp_work_entry->sche_cnt++;
3678
3679         /* Query db process status, until hw process completely */
3680         ret = check_qp_db_process_status(hr_dev, hr_qp,
3681                                          qp_work_entry->sdb_issue_ptr,
3682                                          &qp_work_entry->sdb_inv_cnt,
3683                                          &qp_work_entry->db_wait_stage);
3684         if (ret) {
3685                 dev_err(dev, "Check QP(0x%lx) db process status failed!\n",
3686                         qpn);
3687                 return;
3688         }
3689
3690         if (qp_work_entry->db_wait_stage != HNS_ROCE_V1_DB_WAIT_OK &&
3691             priv->des_qp.requeue_flag) {
3692                 queue_work(priv->des_qp.qp_wq, work);
3693                 return;
3694         }
3695
3696         /* Modify qp to reset before destroying qp */
3697         ret = hns_roce_v1_modify_qp(&hr_qp->ibqp, NULL, 0, hr_qp->state,
3698                                     IB_QPS_RESET);
3699         if (ret) {
3700                 dev_err(dev, "Modify QP(0x%lx) to RST failed!\n", qpn);
3701                 return;
3702         }
3703
3704         hns_roce_qp_remove(hr_dev, hr_qp);
3705         hns_roce_qp_free(hr_dev, hr_qp);
3706
3707         if (hr_qp->ibqp.qp_type == IB_QPT_RC) {
3708                 /* RC QP, release QPN */
3709                 hns_roce_release_range_qp(hr_dev, qpn, 1);
3710                 kfree(hr_qp);
3711         } else
3712                 kfree(hr_to_hr_sqp(hr_qp));
3713
3714         kfree(qp_work_entry);
3715
3716         dev_dbg(dev, "Accomplished destroy QP(0x%lx) work.\n", qpn);
3717 }
3718
3719 int hns_roce_v1_destroy_qp(struct ib_qp *ibqp)
3720 {
3721         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3722         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3723         struct device *dev = &hr_dev->pdev->dev;
3724         struct hns_roce_qp_work qp_work_entry;
3725         struct hns_roce_qp_work *qp_work;
3726         struct hns_roce_v1_priv *priv;
3727         struct hns_roce_cq *send_cq, *recv_cq;
3728         int is_user = !!ibqp->pd->uobject;
3729         int is_timeout = 0;
3730         int ret;
3731
3732         ret = check_qp_reset_state(hr_dev, hr_qp, &qp_work_entry, &is_timeout);
3733         if (ret) {
3734                 dev_err(dev, "QP reset state check failed(%d)!\n", ret);
3735                 return ret;
3736         }
3737
3738         send_cq = to_hr_cq(hr_qp->ibqp.send_cq);
3739         recv_cq = to_hr_cq(hr_qp->ibqp.recv_cq);
3740
3741         hns_roce_lock_cqs(send_cq, recv_cq);
3742         if (!is_user) {
3743                 __hns_roce_v1_cq_clean(recv_cq, hr_qp->qpn, hr_qp->ibqp.srq ?
3744                                        to_hr_srq(hr_qp->ibqp.srq) : NULL);
3745                 if (send_cq != recv_cq)
3746                         __hns_roce_v1_cq_clean(send_cq, hr_qp->qpn, NULL);
3747         }
3748         hns_roce_unlock_cqs(send_cq, recv_cq);
3749
3750         if (!is_timeout) {
3751                 hns_roce_qp_remove(hr_dev, hr_qp);
3752                 hns_roce_qp_free(hr_dev, hr_qp);
3753
3754                 /* RC QP, release QPN */
3755                 if (hr_qp->ibqp.qp_type == IB_QPT_RC)
3756                         hns_roce_release_range_qp(hr_dev, hr_qp->qpn, 1);
3757         }
3758
3759         hns_roce_mtt_cleanup(hr_dev, &hr_qp->mtt);
3760
3761         if (is_user)
3762                 ib_umem_release(hr_qp->umem);
3763         else {
3764                 kfree(hr_qp->sq.wrid);
3765                 kfree(hr_qp->rq.wrid);
3766
3767                 hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf);
3768         }
3769
3770         if (!is_timeout) {
3771                 if (hr_qp->ibqp.qp_type == IB_QPT_RC)
3772                         kfree(hr_qp);
3773                 else
3774                         kfree(hr_to_hr_sqp(hr_qp));
3775         } else {
3776                 qp_work = kzalloc(sizeof(*qp_work), GFP_KERNEL);
3777                 if (!qp_work)
3778                         return -ENOMEM;
3779
3780                 INIT_WORK(&qp_work->work, hns_roce_v1_destroy_qp_work_fn);
3781                 qp_work->ib_dev = &hr_dev->ib_dev;
3782                 qp_work->qp             = hr_qp;
3783                 qp_work->db_wait_stage  = qp_work_entry.db_wait_stage;
3784                 qp_work->sdb_issue_ptr  = qp_work_entry.sdb_issue_ptr;
3785                 qp_work->sdb_inv_cnt    = qp_work_entry.sdb_inv_cnt;
3786                 qp_work->sche_cnt       = qp_work_entry.sche_cnt;
3787
3788                 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
3789                 queue_work(priv->des_qp.qp_wq, &qp_work->work);
3790                 dev_dbg(dev, "Begin destroy QP(0x%lx) work.\n", hr_qp->qpn);
3791         }
3792
3793         return 0;
3794 }
3795
3796 int hns_roce_v1_destroy_cq(struct ib_cq *ibcq)
3797 {
3798         struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
3799         struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
3800         struct device *dev = &hr_dev->pdev->dev;
3801         u32 cqe_cnt_ori;
3802         u32 cqe_cnt_cur;
3803         u32 cq_buf_size;
3804         int wait_time = 0;
3805         int ret = 0;
3806
3807         hns_roce_free_cq(hr_dev, hr_cq);
3808
3809         /*
3810          * Before freeing cq buffer, we need to ensure that the outstanding CQE
3811          * have been written by checking the CQE counter.
3812          */
3813         cqe_cnt_ori = roce_read(hr_dev, ROCEE_SCAEP_WR_CQE_CNT);
3814         while (1) {
3815                 if (roce_read(hr_dev, ROCEE_CAEP_CQE_WCMD_EMPTY) &
3816                     HNS_ROCE_CQE_WCMD_EMPTY_BIT)
3817                         break;
3818
3819                 cqe_cnt_cur = roce_read(hr_dev, ROCEE_SCAEP_WR_CQE_CNT);
3820                 if ((cqe_cnt_cur - cqe_cnt_ori) >= HNS_ROCE_MIN_CQE_CNT)
3821                         break;
3822
3823                 msleep(HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS);
3824                 if (wait_time > HNS_ROCE_MAX_FREE_CQ_WAIT_CNT) {
3825                         dev_warn(dev, "Destroy cq 0x%lx timeout!\n",
3826                                 hr_cq->cqn);
3827                         ret = -ETIMEDOUT;
3828                         break;
3829                 }
3830                 wait_time++;
3831         }
3832
3833         hns_roce_mtt_cleanup(hr_dev, &hr_cq->hr_buf.hr_mtt);
3834
3835         if (ibcq->uobject)
3836                 ib_umem_release(hr_cq->umem);
3837         else {
3838                 /* Free the buff of stored cq */
3839                 cq_buf_size = (ibcq->cqe + 1) * hr_dev->caps.cq_entry_sz;
3840                 hns_roce_buf_free(hr_dev, cq_buf_size, &hr_cq->hr_buf.hr_buf);
3841         }
3842
3843         kfree(hr_cq);
3844
3845         return ret;
3846 }
3847
3848 struct hns_roce_v1_priv hr_v1_priv;
3849
3850 struct hns_roce_hw hns_roce_hw_v1 = {
3851         .reset = hns_roce_v1_reset,
3852         .hw_profile = hns_roce_v1_profile,
3853         .hw_init = hns_roce_v1_init,
3854         .hw_exit = hns_roce_v1_exit,
3855         .set_gid = hns_roce_v1_set_gid,
3856         .set_mac = hns_roce_v1_set_mac,
3857         .set_mtu = hns_roce_v1_set_mtu,
3858         .write_mtpt = hns_roce_v1_write_mtpt,
3859         .write_cqc = hns_roce_v1_write_cqc,
3860         .clear_hem = hns_roce_v1_clear_hem,
3861         .modify_qp = hns_roce_v1_modify_qp,
3862         .query_qp = hns_roce_v1_query_qp,
3863         .destroy_qp = hns_roce_v1_destroy_qp,
3864         .post_send = hns_roce_v1_post_send,
3865         .post_recv = hns_roce_v1_post_recv,
3866         .req_notify_cq = hns_roce_v1_req_notify_cq,
3867         .poll_cq = hns_roce_v1_poll_cq,
3868         .dereg_mr = hns_roce_v1_dereg_mr,
3869         .destroy_cq = hns_roce_v1_destroy_cq,
3870         .priv = &hr_v1_priv,
3871 };