drivers/infiniband/hw/mlx4/qp.c

   1 /*
   2  * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
   3  * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #include <linux/log2.h>
  35 #include <linux/etherdevice.h>
  36 #include <net/ip.h>
  37 #include <linux/slab.h>
  38 #include <linux/netdevice.h>
  39
  40 #include <rdma/ib_cache.h>
  41 #include <rdma/ib_pack.h>
  42 #include <rdma/ib_addr.h>
  43 #include <rdma/ib_mad.h>
  44
  45 #include <linux/mlx4/driver.h>
  46 #include <linux/mlx4/qp.h>
  47
  48 #include "mlx4_ib.h"
  49 #include <rdma/mlx4-abi.h>
  50
  51 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
  52                              struct mlx4_ib_cq *recv_cq);
  53 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
  54                                struct mlx4_ib_cq *recv_cq);
  55 static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state);
  56
  57 enum {
  58         MLX4_IB_ACK_REQ_FREQ    = 8,
  59 };
  60
  61 enum {
  62         MLX4_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  63         MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  64         MLX4_IB_LINK_TYPE_IB            = 0,
  65         MLX4_IB_LINK_TYPE_ETH           = 1
  66 };
  67
  68 enum {
  69         /*
  70          * Largest possible UD header: send with GRH and immediate
  71          * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
  72          * tag.  (LRH would only use 8 bytes, so Ethernet is the
  73          * biggest case)
  74          */
  75         MLX4_IB_UD_HEADER_SIZE          = 82,
  76         MLX4_IB_LSO_HEADER_SPARE        = 128,
  77 };
  78
  79 struct mlx4_ib_sqp {
  80         struct mlx4_ib_qp       qp;
  81         int                     pkey_index;
  82         u32                     qkey;
  83         u32                     send_psn;
  84         struct ib_ud_header     ud_header;
  85         u8                      header_buf[MLX4_IB_UD_HEADER_SIZE];
  86         struct ib_qp            *roce_v2_gsi;
  87 };
  88
  89 enum {
  90         MLX4_IB_MIN_SQ_STRIDE   = 6,
  91         MLX4_IB_CACHE_LINE_SIZE = 64,
  92 };
  93
  94 enum {
  95         MLX4_RAW_QP_MTU         = 7,
  96         MLX4_RAW_QP_MSGMAX      = 31,
  97 };
  98
  99 #ifndef ETH_ALEN
 100 #define ETH_ALEN        6
 101 #endif
 102
 103 static const __be32 mlx4_ib_opcode[] = {
 104         [IB_WR_SEND]                            = cpu_to_be32(MLX4_OPCODE_SEND),
 105         [IB_WR_LSO]                             = cpu_to_be32(MLX4_OPCODE_LSO),
 106         [IB_WR_SEND_WITH_IMM]                   = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
 107         [IB_WR_RDMA_WRITE]                      = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
 108         [IB_WR_RDMA_WRITE_WITH_IMM]             = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
 109         [IB_WR_RDMA_READ]                       = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
 110         [IB_WR_ATOMIC_CMP_AND_SWP]              = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
 111         [IB_WR_ATOMIC_FETCH_AND_ADD]            = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
 112         [IB_WR_SEND_WITH_INV]                   = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
 113         [IB_WR_LOCAL_INV]                       = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
 114         [IB_WR_REG_MR]                          = cpu_to_be32(MLX4_OPCODE_FMR),
 115         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
 116         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
 117 };
 118
 119 enum mlx4_ib_source_type {
 120         MLX4_IB_QP_SRC  = 0,
 121         MLX4_IB_RWQ_SRC = 1,
 122 };
 123
 124 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
 125 {
 126         return container_of(mqp, struct mlx4_ib_sqp, qp);
 127 }
 128
 129 static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 130 {
 131         if (!mlx4_is_master(dev->dev))
 132                 return 0;
 133
 134         return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
 135                qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
 136                 8 * MLX4_MFUNC_MAX;
 137 }
 138
 139 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 140 {
 141         int proxy_sqp = 0;
 142         int real_sqp = 0;
 143         int i;
 144         /* PPF or Native -- real SQP */
 145         real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
 146                     qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
 147                     qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
 148         if (real_sqp)
 149                 return 1;
 150         /* VF or PF -- proxy SQP */
 151         if (mlx4_is_mfunc(dev->dev)) {
 152                 for (i = 0; i < dev->dev->caps.num_ports; i++) {
 153                         if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy ||
 154                             qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp1_proxy) {
 155                                 proxy_sqp = 1;
 156                                 break;
 157                         }
 158                 }
 159         }
 160         if (proxy_sqp)
 161                 return 1;
 162
 163         return !!(qp->flags & MLX4_IB_ROCE_V2_GSI_QP);
 164 }
 165
 166 /* used for INIT/CLOSE port logic */
 167 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 168 {
 169         int proxy_qp0 = 0;
 170         int real_qp0 = 0;
 171         int i;
 172         /* PPF or Native -- real QP0 */
 173         real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
 174                     qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
 175                     qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
 176         if (real_qp0)
 177                 return 1;
 178         /* VF or PF -- proxy QP0 */
 179         if (mlx4_is_mfunc(dev->dev)) {
 180                 for (i = 0; i < dev->dev->caps.num_ports; i++) {
 181                         if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy) {
 182                                 proxy_qp0 = 1;
 183                                 break;
 184                         }
 185                 }
 186         }
 187         return proxy_qp0;
 188 }
 189
 190 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
 191 {
 192         return mlx4_buf_offset(&qp->buf, offset);
 193 }
 194
 195 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
 196 {
 197         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 198 }
 199
 200 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
 201 {
 202         return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
 203 }
 204
 205 /*
 206  * Stamp a SQ WQE so that it is invalid if prefetched by marking the
 207  * first four bytes of every 64 byte chunk with 0xffffffff, except for
 208  * the very first chunk of the WQE.
 209  */
 210 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n)
 211 {
 212         __be32 *wqe;
 213         int i;
 214         int s;
 215         void *buf;
 216         struct mlx4_wqe_ctrl_seg *ctrl;
 217
 218         buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 219         ctrl = (struct mlx4_wqe_ctrl_seg *)buf;
 220         s = (ctrl->qpn_vlan.fence_size & 0x3f) << 4;
 221         for (i = 64; i < s; i += 64) {
 222                 wqe = buf + i;
 223                 *wqe = cpu_to_be32(0xffffffff);
 224         }
 225 }
 226
 227 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
 228 {
 229         struct ib_event event;
 230         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 231
 232         if (type == MLX4_EVENT_TYPE_PATH_MIG)
 233                 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
 234
 235         if (ibqp->event_handler) {
 236                 event.device     = ibqp->device;
 237                 event.element.qp = ibqp;
 238                 switch (type) {
 239                 case MLX4_EVENT_TYPE_PATH_MIG:
 240                         event.event = IB_EVENT_PATH_MIG;
 241                         break;
 242                 case MLX4_EVENT_TYPE_COMM_EST:
 243                         event.event = IB_EVENT_COMM_EST;
 244                         break;
 245                 case MLX4_EVENT_TYPE_SQ_DRAINED:
 246                         event.event = IB_EVENT_SQ_DRAINED;
 247                         break;
 248                 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
 249                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 250                         break;
 251                 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
 252                         event.event = IB_EVENT_QP_FATAL;
 253                         break;
 254                 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
 255                         event.event = IB_EVENT_PATH_MIG_ERR;
 256                         break;
 257                 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 258                         event.event = IB_EVENT_QP_REQ_ERR;
 259                         break;
 260                 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
 261                         event.event = IB_EVENT_QP_ACCESS_ERR;
 262                         break;
 263                 default:
 264                         pr_warn("Unexpected event type %d "
 265                                "on QP %06x\n", type, qp->qpn);
 266                         return;
 267                 }
 268
 269                 ibqp->event_handler(&event, ibqp->qp_context);
 270         }
 271 }
 272
 273 static void mlx4_ib_wq_event(struct mlx4_qp *qp, enum mlx4_event type)
 274 {
 275         pr_warn_ratelimited("Unexpected event type %d on WQ 0x%06x. Events are not supported for WQs\n",
 276                             type, qp->qpn);
 277 }
 278
 279 static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
 280 {
 281         /*
 282          * UD WQEs must have a datagram segment.
 283          * RC and UC WQEs might have a remote address segment.
 284          * MLX WQEs need two extra inline data segments (for the UD
 285          * header and space for the ICRC).
 286          */
 287         switch (type) {
 288         case MLX4_IB_QPT_UD:
 289                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 290                         sizeof (struct mlx4_wqe_datagram_seg) +
 291                         ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
 292         case MLX4_IB_QPT_PROXY_SMI_OWNER:
 293         case MLX4_IB_QPT_PROXY_SMI:
 294         case MLX4_IB_QPT_PROXY_GSI:
 295                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 296                         sizeof (struct mlx4_wqe_datagram_seg) + 64;
 297         case MLX4_IB_QPT_TUN_SMI_OWNER:
 298         case MLX4_IB_QPT_TUN_GSI:
 299                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 300                         sizeof (struct mlx4_wqe_datagram_seg);
 301
 302         case MLX4_IB_QPT_UC:
 303                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 304                         sizeof (struct mlx4_wqe_raddr_seg);
 305         case MLX4_IB_QPT_RC:
 306                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 307                         sizeof (struct mlx4_wqe_masked_atomic_seg) +
 308                         sizeof (struct mlx4_wqe_raddr_seg);
 309         case MLX4_IB_QPT_SMI:
 310         case MLX4_IB_QPT_GSI:
 311                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 312                         ALIGN(MLX4_IB_UD_HEADER_SIZE +
 313                               DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
 314                                            MLX4_INLINE_ALIGN) *
 315                               sizeof (struct mlx4_wqe_inline_seg),
 316                               sizeof (struct mlx4_wqe_data_seg)) +
 317                         ALIGN(4 +
 318                               sizeof (struct mlx4_wqe_inline_seg),
 319                               sizeof (struct mlx4_wqe_data_seg));
 320         default:
 321                 return sizeof (struct mlx4_wqe_ctrl_seg);
 322         }
 323 }
 324
 325 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 326                        int is_user, int has_rq, struct mlx4_ib_qp *qp,
 327                        u32 inl_recv_sz)
 328 {
 329         /* Sanity check RQ size before proceeding */
 330         if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
 331             cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
 332                 return -EINVAL;
 333
 334         if (!has_rq) {
 335                 if (cap->max_recv_wr || inl_recv_sz)
 336                         return -EINVAL;
 337
 338                 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
 339         } else {
 340                 u32 max_inl_recv_sz = dev->dev->caps.max_rq_sg *
 341                         sizeof(struct mlx4_wqe_data_seg);
 342                 u32 wqe_size;
 343
 344                 /* HW requires >= 1 RQ entry with >= 1 gather entry */
 345                 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge ||
 346                                 inl_recv_sz > max_inl_recv_sz))
 347                         return -EINVAL;
 348
 349                 qp->rq.wqe_cnt   = roundup_pow_of_two(max(1U, cap->max_recv_wr));
 350                 qp->rq.max_gs    = roundup_pow_of_two(max(1U, cap->max_recv_sge));
 351                 wqe_size = qp->rq.max_gs * sizeof(struct mlx4_wqe_data_seg);
 352                 qp->rq.wqe_shift = ilog2(max_t(u32, wqe_size, inl_recv_sz));
 353         }
 354
 355         /* leave userspace return values as they were, so as not to break ABI */
 356         if (is_user) {
 357                 cap->max_recv_wr  = qp->rq.max_post = qp->rq.wqe_cnt;
 358                 cap->max_recv_sge = qp->rq.max_gs;
 359         } else {
 360                 cap->max_recv_wr  = qp->rq.max_post =
 361                         min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
 362                 cap->max_recv_sge = min(qp->rq.max_gs,
 363                                         min(dev->dev->caps.max_sq_sg,
 364                                             dev->dev->caps.max_rq_sg));
 365         }
 366
 367         return 0;
 368 }
 369
 370 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 371                               enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp)
 372 {
 373         int s;
 374
 375         /* Sanity check SQ size before proceeding */
 376         if (cap->max_send_wr  > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
 377             cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
 378             cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
 379             sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
 380                 return -EINVAL;
 381
 382         /*
 383          * For MLX transport we need 2 extra S/G entries:
 384          * one for the header and one for the checksum at the end
 385          */
 386         if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
 387              type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
 388             cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
 389                 return -EINVAL;
 390
 391         s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
 392                 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
 393                 send_wqe_overhead(type, qp->flags);
 394
 395         if (s > dev->dev->caps.max_sq_desc_sz)
 396                 return -EINVAL;
 397
 398         qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
 399
 400         /*
 401          * We need to leave 2 KB + 1 WR of headroom in the SQ to
 402          * allow HW to prefetch.
 403          */
 404         qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + 1;
 405         qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr +
 406                                             qp->sq_spare_wqes);
 407
 408         qp->sq.max_gs =
 409                 (min(dev->dev->caps.max_sq_desc_sz,
 410                      (1 << qp->sq.wqe_shift)) -
 411                  send_wqe_overhead(type, qp->flags)) /
 412                 sizeof (struct mlx4_wqe_data_seg);
 413
 414         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 415                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 416         if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
 417                 qp->rq.offset = 0;
 418                 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 419         } else {
 420                 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
 421                 qp->sq.offset = 0;
 422         }
 423
 424         cap->max_send_wr  = qp->sq.max_post =
 425                 qp->sq.wqe_cnt - qp->sq_spare_wqes;
 426         cap->max_send_sge = min(qp->sq.max_gs,
 427                                 min(dev->dev->caps.max_sq_sg,
 428                                     dev->dev->caps.max_rq_sg));
 429         /* We don't support inline sends for kernel QPs (yet) */
 430         cap->max_inline_data = 0;
 431
 432         return 0;
 433 }
 434
 435 static int set_user_sq_size(struct mlx4_ib_dev *dev,
 436                             struct mlx4_ib_qp *qp,
 437                             struct mlx4_ib_create_qp *ucmd)
 438 {
 439         /* Sanity check SQ size before proceeding */
 440         if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes       ||
 441             ucmd->log_sq_stride >
 442                 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
 443             ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
 444                 return -EINVAL;
 445
 446         qp->sq.wqe_cnt   = 1 << ucmd->log_sq_bb_count;
 447         qp->sq.wqe_shift = ucmd->log_sq_stride;
 448
 449         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 450                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 451
 452         return 0;
 453 }
 454
 455 static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
 456 {
 457         int i;
 458
 459         qp->sqp_proxy_rcv =
 460                 kmalloc_array(qp->rq.wqe_cnt, sizeof(struct mlx4_ib_buf),
 461                               GFP_KERNEL);
 462         if (!qp->sqp_proxy_rcv)
 463                 return -ENOMEM;
 464         for (i = 0; i < qp->rq.wqe_cnt; i++) {
 465                 qp->sqp_proxy_rcv[i].addr =
 466                         kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
 467                                 GFP_KERNEL);
 468                 if (!qp->sqp_proxy_rcv[i].addr)
 469                         goto err;
 470                 qp->sqp_proxy_rcv[i].map =
 471                         ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
 472                                           sizeof (struct mlx4_ib_proxy_sqp_hdr),
 473                                           DMA_FROM_DEVICE);
 474                 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
 475                         kfree(qp->sqp_proxy_rcv[i].addr);
 476                         goto err;
 477                 }
 478         }
 479         return 0;
 480
 481 err:
 482         while (i > 0) {
 483                 --i;
 484                 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
 485                                     sizeof (struct mlx4_ib_proxy_sqp_hdr),
 486                                     DMA_FROM_DEVICE);
 487                 kfree(qp->sqp_proxy_rcv[i].addr);
 488         }
 489         kfree(qp->sqp_proxy_rcv);
 490         qp->sqp_proxy_rcv = NULL;
 491         return -ENOMEM;
 492 }
 493
 494 static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
 495 {
 496         int i;
 497
 498         for (i = 0; i < qp->rq.wqe_cnt; i++) {
 499                 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
 500                                     sizeof (struct mlx4_ib_proxy_sqp_hdr),
 501                                     DMA_FROM_DEVICE);
 502                 kfree(qp->sqp_proxy_rcv[i].addr);
 503         }
 504         kfree(qp->sqp_proxy_rcv);
 505 }
 506
 507 static int qp_has_rq(struct ib_qp_init_attr *attr)
 508 {
 509         if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
 510                 return 0;
 511
 512         return !attr->srq;
 513 }
 514
 515 static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
 516 {
 517         int i;
 518         for (i = 0; i < dev->caps.num_ports; i++) {
 519                 if (qpn == dev->caps.spec_qps[i].qp0_proxy)
 520                         return !!dev->caps.spec_qps[i].qp0_qkey;
 521         }
 522         return 0;
 523 }
 524
 525 static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev,
 526                                     struct mlx4_ib_qp *qp)
 527 {
 528         mutex_lock(&dev->counters_table[qp->port - 1].mutex);
 529         mlx4_counter_free(dev->dev, qp->counter_index->index);
 530         list_del(&qp->counter_index->list);
 531         mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
 532
 533         kfree(qp->counter_index);
 534         qp->counter_index = NULL;
 535 }
 536
 537 static int set_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_rss *rss_ctx,
 538                       struct ib_qp_init_attr *init_attr,
 539                       struct mlx4_ib_create_qp_rss *ucmd)
 540 {
 541         rss_ctx->base_qpn_tbl_sz = init_attr->rwq_ind_tbl->ind_tbl[0]->wq_num |
 542                 (init_attr->rwq_ind_tbl->log_ind_tbl_size << 24);
 543
 544         if ((ucmd->rx_hash_function == MLX4_IB_RX_HASH_FUNC_TOEPLITZ) &&
 545             (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP)) {
 546                 memcpy(rss_ctx->rss_key, ucmd->rx_hash_key,
 547                        MLX4_EN_RSS_KEY_SIZE);
 548         } else {
 549                 pr_debug("RX Hash function is not supported\n");
 550                 return (-EOPNOTSUPP);
 551         }
 552
 553         if (ucmd->rx_hash_fields_mask & ~(MLX4_IB_RX_HASH_SRC_IPV4      |
 554                                           MLX4_IB_RX_HASH_DST_IPV4      |
 555                                           MLX4_IB_RX_HASH_SRC_IPV6      |
 556                                           MLX4_IB_RX_HASH_DST_IPV6      |
 557                                           MLX4_IB_RX_HASH_SRC_PORT_TCP  |
 558                                           MLX4_IB_RX_HASH_DST_PORT_TCP  |
 559                                           MLX4_IB_RX_HASH_SRC_PORT_UDP  |
 560                                           MLX4_IB_RX_HASH_DST_PORT_UDP  |
 561                                           MLX4_IB_RX_HASH_INNER)) {
 562                 pr_debug("RX Hash fields_mask has unsupported mask (0x%llx)\n",
 563                          ucmd->rx_hash_fields_mask);
 564                 return (-EOPNOTSUPP);
 565         }
 566
 567         if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) &&
 568             (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) {
 569                 rss_ctx->flags = MLX4_RSS_IPV4;
 570         } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) ||
 571                    (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) {
 572                 pr_debug("RX Hash fields_mask is not supported - both IPv4 SRC and DST must be set\n");
 573                 return (-EOPNOTSUPP);
 574         }
 575
 576         if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) &&
 577             (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) {
 578                 rss_ctx->flags |= MLX4_RSS_IPV6;
 579         } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) ||
 580                    (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) {
 581                 pr_debug("RX Hash fields_mask is not supported - both IPv6 SRC and DST must be set\n");
 582                 return (-EOPNOTSUPP);
 583         }
 584
 585         if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) &&
 586             (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) {
 587                 if (!(dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UDP_RSS)) {
 588                         pr_debug("RX Hash fields_mask for UDP is not supported\n");
 589                         return (-EOPNOTSUPP);
 590                 }
 591
 592                 if (rss_ctx->flags & MLX4_RSS_IPV4)
 593                         rss_ctx->flags |= MLX4_RSS_UDP_IPV4;
 594                 if (rss_ctx->flags & MLX4_RSS_IPV6)
 595                         rss_ctx->flags |= MLX4_RSS_UDP_IPV6;
 596                 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) {
 597                         pr_debug("RX Hash fields_mask is not supported - UDP must be set with IPv4 or IPv6\n");
 598                         return (-EOPNOTSUPP);
 599                 }
 600         } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) ||
 601                    (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) {
 602                 pr_debug("RX Hash fields_mask is not supported - both UDP SRC and DST must be set\n");
 603                 return (-EOPNOTSUPP);
 604         }
 605
 606         if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) &&
 607             (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) {
 608                 if (rss_ctx->flags & MLX4_RSS_IPV4)
 609                         rss_ctx->flags |= MLX4_RSS_TCP_IPV4;
 610                 if (rss_ctx->flags & MLX4_RSS_IPV6)
 611                         rss_ctx->flags |= MLX4_RSS_TCP_IPV6;
 612                 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) {
 613                         pr_debug("RX Hash fields_mask is not supported - TCP must be set with IPv4 or IPv6\n");
 614                         return (-EOPNOTSUPP);
 615                 }
 616         } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) ||
 617                    (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) {
 618                 pr_debug("RX Hash fields_mask is not supported - both TCP SRC and DST must be set\n");
 619                 return (-EOPNOTSUPP);
 620         }
 621
 622         if (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_INNER) {
 623                 if (dev->dev->caps.tunnel_offload_mode ==
 624                     MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
 625                         /*
 626                          * Hash according to inner headers if exist, otherwise
 627                          * according to outer headers.
 628                          */
 629                         rss_ctx->flags |= MLX4_RSS_BY_INNER_HEADERS_IPONLY;
 630                 } else {
 631                         pr_debug("RSS Hash for inner headers isn't supported\n");
 632                         return (-EOPNOTSUPP);
 633                 }
 634         }
 635
 636         return 0;
 637 }
 638
 639 static int create_qp_rss(struct mlx4_ib_dev *dev,
 640                          struct ib_qp_init_attr *init_attr,
 641                          struct mlx4_ib_create_qp_rss *ucmd,
 642                          struct mlx4_ib_qp *qp)
 643 {
 644         int qpn;
 645         int err;
 646
 647         qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
 648
 649         err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn, 0, qp->mqp.usage);
 650         if (err)
 651                 return err;
 652
 653         err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
 654         if (err)
 655                 goto err_qpn;
 656
 657         mutex_init(&qp->mutex);
 658
 659         INIT_LIST_HEAD(&qp->gid_list);
 660         INIT_LIST_HEAD(&qp->steering_rules);
 661
 662         qp->mlx4_ib_qp_type = MLX4_IB_QPT_RAW_PACKET;
 663         qp->state = IB_QPS_RESET;
 664
 665         /* Set dummy send resources to be compatible with HV and PRM */
 666         qp->sq_no_prefetch = 1;
 667         qp->sq.wqe_cnt = 1;
 668         qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE;
 669         qp->buf_size = qp->sq.wqe_cnt << MLX4_IB_MIN_SQ_STRIDE;
 670         qp->mtt = (to_mqp(
 671                    (struct ib_qp *)init_attr->rwq_ind_tbl->ind_tbl[0]))->mtt;
 672
 673         qp->rss_ctx = kzalloc(sizeof(*qp->rss_ctx), GFP_KERNEL);
 674         if (!qp->rss_ctx) {
 675                 err = -ENOMEM;
 676                 goto err_qp_alloc;
 677         }
 678
 679         err = set_qp_rss(dev, qp->rss_ctx, init_attr, ucmd);
 680         if (err)
 681                 goto err;
 682
 683         return 0;
 684
 685 err:
 686         kfree(qp->rss_ctx);
 687
 688 err_qp_alloc:
 689         mlx4_qp_remove(dev->dev, &qp->mqp);
 690         mlx4_qp_free(dev->dev, &qp->mqp);
 691
 692 err_qpn:
 693         mlx4_qp_release_range(dev->dev, qpn, 1);
 694         return err;
 695 }
 696
 697 static struct ib_qp *_mlx4_ib_create_qp_rss(struct ib_pd *pd,
 698                                             struct ib_qp_init_attr *init_attr,
 699                                             struct ib_udata *udata)
 700 {
 701         struct mlx4_ib_qp *qp;
 702         struct mlx4_ib_create_qp_rss ucmd = {};
 703         size_t required_cmd_sz;
 704         int err;
 705
 706         if (!udata) {
 707                 pr_debug("RSS QP with NULL udata\n");
 708                 return ERR_PTR(-EINVAL);
 709         }
 710
 711         if (udata->outlen)
 712                 return ERR_PTR(-EOPNOTSUPP);
 713
 714         required_cmd_sz = offsetof(typeof(ucmd), reserved1) +
 715                                         sizeof(ucmd.reserved1);
 716         if (udata->inlen < required_cmd_sz) {
 717                 pr_debug("invalid inlen\n");
 718                 return ERR_PTR(-EINVAL);
 719         }
 720
 721         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
 722                 pr_debug("copy failed\n");
 723                 return ERR_PTR(-EFAULT);
 724         }
 725
 726         if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)))
 727                 return ERR_PTR(-EOPNOTSUPP);
 728
 729         if (ucmd.comp_mask || ucmd.reserved1)
 730                 return ERR_PTR(-EOPNOTSUPP);
 731
 732         if (udata->inlen > sizeof(ucmd) &&
 733             !ib_is_udata_cleared(udata, sizeof(ucmd),
 734                                  udata->inlen - sizeof(ucmd))) {
 735                 pr_debug("inlen is not supported\n");
 736                 return ERR_PTR(-EOPNOTSUPP);
 737         }
 738
 739         if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
 740                 pr_debug("RSS QP with unsupported QP type %d\n",
 741                          init_attr->qp_type);
 742                 return ERR_PTR(-EOPNOTSUPP);
 743         }
 744
 745         if (init_attr->create_flags) {
 746                 pr_debug("RSS QP doesn't support create flags\n");
 747                 return ERR_PTR(-EOPNOTSUPP);
 748         }
 749
 750         if (init_attr->send_cq || init_attr->cap.max_send_wr) {
 751                 pr_debug("RSS QP with unsupported send attributes\n");
 752                 return ERR_PTR(-EOPNOTSUPP);
 753         }
 754
 755         qp = kzalloc(sizeof(*qp), GFP_KERNEL);
 756         if (!qp)
 757                 return ERR_PTR(-ENOMEM);
 758
 759         qp->pri.vid = 0xFFFF;
 760         qp->alt.vid = 0xFFFF;
 761
 762         err = create_qp_rss(to_mdev(pd->device), init_attr, &ucmd, qp);
 763         if (err) {
 764                 kfree(qp);
 765                 return ERR_PTR(err);
 766         }
 767
 768         qp->ibqp.qp_num = qp->mqp.qpn;
 769
 770         return &qp->ibqp;
 771 }
 772
 773 /*
 774  * This function allocates a WQN from a range which is consecutive and aligned
 775  * to its size. In case the range is full, then it creates a new range and
 776  * allocates WQN from it. The new range will be used for following allocations.
 777  */
 778 static int mlx4_ib_alloc_wqn(struct mlx4_ib_ucontext *context,
 779                              struct mlx4_ib_qp *qp, int range_size, int *wqn)
 780 {
 781         struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device);
 782         struct mlx4_wqn_range *range;
 783         int err = 0;
 784
 785         mutex_lock(&context->wqn_ranges_mutex);
 786
 787         range = list_first_entry_or_null(&context->wqn_ranges_list,
 788                                          struct mlx4_wqn_range, list);
 789
 790         if (!range || (range->refcount == range->size) || range->dirty) {
 791                 range = kzalloc(sizeof(*range), GFP_KERNEL);
 792                 if (!range) {
 793                         err = -ENOMEM;
 794                         goto out;
 795                 }
 796
 797                 err = mlx4_qp_reserve_range(dev->dev, range_size,
 798                                             range_size, &range->base_wqn, 0,
 799                                             qp->mqp.usage);
 800                 if (err) {
 801                         kfree(range);
 802                         goto out;
 803                 }
 804
 805                 range->size = range_size;
 806                 list_add(&range->list, &context->wqn_ranges_list);
 807         } else if (range_size != 1) {
 808                 /*
 809                  * Requesting a new range (>1) when last range is still open, is
 810                  * not valid.
 811                  */
 812                 err = -EINVAL;
 813                 goto out;
 814         }
 815
 816         qp->wqn_range = range;
 817
 818         *wqn = range->base_wqn + range->refcount;
 819
 820         range->refcount++;
 821
 822 out:
 823         mutex_unlock(&context->wqn_ranges_mutex);
 824
 825         return err;
 826 }
 827
 828 static void mlx4_ib_release_wqn(struct mlx4_ib_ucontext *context,
 829                                 struct mlx4_ib_qp *qp, bool dirty_release)
 830 {
 831         struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device);
 832         struct mlx4_wqn_range *range;
 833
 834         mutex_lock(&context->wqn_ranges_mutex);
 835
 836         range = qp->wqn_range;
 837
 838         range->refcount--;
 839         if (!range->refcount) {
 840                 mlx4_qp_release_range(dev->dev, range->base_wqn,
 841                                       range->size);
 842                 list_del(&range->list);
 843                 kfree(range);
 844         } else if (dirty_release) {
 845         /*
 846          * A range which one of its WQNs is destroyed, won't be able to be
 847          * reused for further WQN allocations.
 848          * The next created WQ will allocate a new range.
 849          */
 850                 range->dirty = 1;
 851         }
 852
 853         mutex_unlock(&context->wqn_ranges_mutex);
 854 }
 855
 856 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
 857                             enum mlx4_ib_source_type src,
 858                             struct ib_qp_init_attr *init_attr,
 859                             struct ib_udata *udata, int sqpn,
 860                             struct mlx4_ib_qp **caller_qp)
 861 {
 862         int qpn;
 863         int err;
 864         struct mlx4_ib_sqp *sqp = NULL;
 865         struct mlx4_ib_qp *qp;
 866         enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
 867         struct mlx4_ib_cq *mcq;
 868         unsigned long flags;
 869         int range_size = 0;
 870
 871         /* When tunneling special qps, we use a plain UD qp */
 872         if (sqpn) {
 873                 if (mlx4_is_mfunc(dev->dev) &&
 874                     (!mlx4_is_master(dev->dev) ||
 875                      !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
 876                         if (init_attr->qp_type == IB_QPT_GSI)
 877                                 qp_type = MLX4_IB_QPT_PROXY_GSI;
 878                         else {
 879                                 if (mlx4_is_master(dev->dev) ||
 880                                     qp0_enabled_vf(dev->dev, sqpn))
 881                                         qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
 882                                 else
 883                                         qp_type = MLX4_IB_QPT_PROXY_SMI;
 884                         }
 885                 }
 886                 qpn = sqpn;
 887                 /* add extra sg entry for tunneling */
 888                 init_attr->cap.max_recv_sge++;
 889         } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
 890                 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
 891                         container_of(init_attr,
 892                                      struct mlx4_ib_qp_tunnel_init_attr, init_attr);
 893                 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
 894                      tnl_init->proxy_qp_type != IB_QPT_GSI)   ||
 895                     !mlx4_is_master(dev->dev))
 896                         return -EINVAL;
 897                 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
 898                         qp_type = MLX4_IB_QPT_TUN_GSI;
 899                 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
 900                          mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
 901                                              tnl_init->port))
 902                         qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
 903                 else
 904                         qp_type = MLX4_IB_QPT_TUN_SMI;
 905                 /* we are definitely in the PPF here, since we are creating
 906                  * tunnel QPs. base_tunnel_sqpn is therefore valid. */
 907                 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
 908                         + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
 909                 sqpn = qpn;
 910         }
 911
 912         if (!*caller_qp) {
 913                 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
 914                     (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
 915                                 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
 916                         sqp = kzalloc(sizeof(struct mlx4_ib_sqp), GFP_KERNEL);
 917                         if (!sqp)
 918                                 return -ENOMEM;
 919                         qp = &sqp->qp;
 920                         qp->pri.vid = 0xFFFF;
 921                         qp->alt.vid = 0xFFFF;
 922                 } else {
 923                         qp = kzalloc(sizeof(struct mlx4_ib_qp), GFP_KERNEL);
 924                         if (!qp)
 925                                 return -ENOMEM;
 926                         qp->pri.vid = 0xFFFF;
 927                         qp->alt.vid = 0xFFFF;
 928                 }
 929         } else
 930                 qp = *caller_qp;
 931
 932         qp->mlx4_ib_qp_type = qp_type;
 933
 934         mutex_init(&qp->mutex);
 935         spin_lock_init(&qp->sq.lock);
 936         spin_lock_init(&qp->rq.lock);
 937         INIT_LIST_HEAD(&qp->gid_list);
 938         INIT_LIST_HEAD(&qp->steering_rules);
 939
 940         qp->state        = IB_QPS_RESET;
 941         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
 942                 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
 943
 944
 945         if (pd->uobject) {
 946                 union {
 947                         struct mlx4_ib_create_qp qp;
 948                         struct mlx4_ib_create_wq wq;
 949                 } ucmd;
 950                 size_t copy_len;
 951                 int shift;
 952                 int n;
 953
 954                 copy_len = (src == MLX4_IB_QP_SRC) ?
 955                            sizeof(struct mlx4_ib_create_qp) :
 956                            min(sizeof(struct mlx4_ib_create_wq), udata->inlen);
 957
 958                 if (ib_copy_from_udata(&ucmd, udata, copy_len)) {
 959                         err = -EFAULT;
 960                         goto err;
 961                 }
 962
 963                 if (src == MLX4_IB_RWQ_SRC) {
 964                         if (ucmd.wq.comp_mask || ucmd.wq.reserved[0] ||
 965                             ucmd.wq.reserved[1] || ucmd.wq.reserved[2]) {
 966                                 pr_debug("user command isn't supported\n");
 967                                 err = -EOPNOTSUPP;
 968                                 goto err;
 969                         }
 970
 971                         if (ucmd.wq.log_range_size >
 972                             ilog2(dev->dev->caps.max_rss_tbl_sz)) {
 973                                 pr_debug("WQN range size must be equal or smaller than %d\n",
 974                                          dev->dev->caps.max_rss_tbl_sz);
 975                                 err = -EOPNOTSUPP;
 976                                 goto err;
 977                         }
 978                         range_size = 1 << ucmd.wq.log_range_size;
 979                 } else {
 980                         qp->inl_recv_sz = ucmd.qp.inl_recv_sz;
 981                 }
 982
 983                 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
 984                         if (!(dev->dev->caps.flags &
 985                               MLX4_DEV_CAP_FLAG_FCS_KEEP)) {
 986                                 pr_debug("scatter FCS is unsupported\n");
 987                                 err = -EOPNOTSUPP;
 988                                 goto err;
 989                         }
 990
 991                         qp->flags |= MLX4_IB_QP_SCATTER_FCS;
 992                 }
 993
 994                 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject,
 995                                   qp_has_rq(init_attr), qp, qp->inl_recv_sz);
 996                 if (err)
 997                         goto err;
 998
 999                 if (src == MLX4_IB_QP_SRC) {
1000                         qp->sq_no_prefetch = ucmd.qp.sq_no_prefetch;
1001
1002                         err = set_user_sq_size(dev, qp,
1003                                                (struct mlx4_ib_create_qp *)
1004                                                &ucmd);
1005                         if (err)
1006                                 goto err;
1007                 } else {
1008                         qp->sq_no_prefetch = 1;
1009                         qp->sq.wqe_cnt = 1;
1010                         qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE;
1011                         /* Allocated buffer expects to have at least that SQ
1012                          * size.
1013                          */
1014                         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
1015                                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
1016                 }
1017
1018                 qp->umem = ib_umem_get(pd->uobject->context,
1019                                 (src == MLX4_IB_QP_SRC) ? ucmd.qp.buf_addr :
1020                                 ucmd.wq.buf_addr, qp->buf_size, 0, 0);
1021                 if (IS_ERR(qp->umem)) {
1022                         err = PTR_ERR(qp->umem);
1023                         goto err;
1024                 }
1025
1026                 n = ib_umem_page_count(qp->umem);
1027                 shift = mlx4_ib_umem_calc_optimal_mtt_size(qp->umem, 0, &n);
1028                 err = mlx4_mtt_init(dev->dev, n, shift, &qp->mtt);
1029
1030                 if (err)
1031                         goto err_buf;
1032
1033                 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
1034                 if (err)
1035                         goto err_mtt;
1036
1037                 if (qp_has_rq(init_attr)) {
1038                         err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
1039                                 (src == MLX4_IB_QP_SRC) ? ucmd.qp.db_addr :
1040                                 ucmd.wq.db_addr, &qp->db);
1041                         if (err)
1042                                 goto err_mtt;
1043                 }
1044                 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
1045         } else {
1046                 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject,
1047                                   qp_has_rq(init_attr), qp, 0);
1048                 if (err)
1049                         goto err;
1050
1051                 qp->sq_no_prefetch = 0;
1052
1053                 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
1054                         qp->flags |= MLX4_IB_QP_LSO;
1055
1056                 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1057                         if (dev->steering_support ==
1058                             MLX4_STEERING_MODE_DEVICE_MANAGED)
1059                                 qp->flags |= MLX4_IB_QP_NETIF;
1060                         else {
1061                                 err = -EINVAL;
1062                                 goto err;
1063                         }
1064                 }
1065
1066                 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp);
1067                 if (err)
1068                         goto err;
1069
1070                 if (qp_has_rq(init_attr)) {
1071                         err = mlx4_db_alloc(dev->dev, &qp->db, 0);
1072                         if (err)
1073                                 goto err;
1074
1075                         *qp->db.db = 0;
1076                 }
1077
1078                 if (mlx4_buf_alloc(dev->dev, qp->buf_size,  PAGE_SIZE * 2,
1079                                    &qp->buf)) {
1080                         err = -ENOMEM;
1081                         goto err_db;
1082                 }
1083
1084                 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
1085                                     &qp->mtt);
1086                 if (err)
1087                         goto err_buf;
1088
1089                 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
1090                 if (err)
1091                         goto err_mtt;
1092
1093                 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1094                                              sizeof(u64), GFP_KERNEL);
1095                 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1096                                              sizeof(u64), GFP_KERNEL);
1097                 if (!qp->sq.wrid || !qp->rq.wrid) {
1098                         err = -ENOMEM;
1099                         goto err_wrid;
1100                 }
1101                 qp->mqp.usage = MLX4_RES_USAGE_DRIVER;
1102         }
1103
1104         if (sqpn) {
1105                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1106                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
1107                         if (alloc_proxy_bufs(pd->device, qp)) {
1108                                 err = -ENOMEM;
1109                                 goto err_wrid;
1110                         }
1111                 }
1112         } else if (src == MLX4_IB_RWQ_SRC) {
1113                 err = mlx4_ib_alloc_wqn(to_mucontext(pd->uobject->context), qp,
1114                                         range_size, &qpn);
1115                 if (err)
1116                         goto err_wrid;
1117         } else {
1118                 /* Raw packet QPNs may not have bits 6,7 set in their qp_num;
1119                  * otherwise, the WQE BlueFlame setup flow wrongly causes
1120                  * VLAN insertion. */
1121                 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
1122                         err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
1123                                                     (init_attr->cap.max_send_wr ?
1124                                                      MLX4_RESERVE_ETH_BF_QP : 0) |
1125                                                     (init_attr->cap.max_recv_wr ?
1126                                                      MLX4_RESERVE_A0_QP : 0),
1127                                                     qp->mqp.usage);
1128                 else
1129                         if (qp->flags & MLX4_IB_QP_NETIF)
1130                                 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
1131                         else
1132                                 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
1133                                                             &qpn, 0, qp->mqp.usage);
1134                 if (err)
1135                         goto err_proxy;
1136         }
1137
1138         if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
1139                 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1140
1141         err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
1142         if (err)
1143                 goto err_qpn;
1144
1145         if (init_attr->qp_type == IB_QPT_XRC_TGT)
1146                 qp->mqp.qpn |= (1 << 23);
1147
1148         /*
1149          * Hardware wants QPN written in big-endian order (after
1150          * shifting) for send doorbell.  Precompute this value to save
1151          * a little bit when posting sends.
1152          */
1153         qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
1154
1155         qp->mqp.event = (src == MLX4_IB_QP_SRC) ? mlx4_ib_qp_event :
1156                                                   mlx4_ib_wq_event;
1157
1158         if (!*caller_qp)
1159                 *caller_qp = qp;
1160
1161         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1162         mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
1163                          to_mcq(init_attr->recv_cq));
1164         /* Maintain device to QPs access, needed for further handling
1165          * via reset flow
1166          */
1167         list_add_tail(&qp->qps_list, &dev->qp_list);
1168         /* Maintain CQ to QPs access, needed for further handling
1169          * via reset flow
1170          */
1171         mcq = to_mcq(init_attr->send_cq);
1172         list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
1173         mcq = to_mcq(init_attr->recv_cq);
1174         list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
1175         mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
1176                            to_mcq(init_attr->recv_cq));
1177         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1178         return 0;
1179
1180 err_qpn:
1181         if (!sqpn) {
1182                 if (qp->flags & MLX4_IB_QP_NETIF)
1183                         mlx4_ib_steer_qp_free(dev, qpn, 1);
1184                 else if (src == MLX4_IB_RWQ_SRC)
1185                         mlx4_ib_release_wqn(to_mucontext(pd->uobject->context),
1186                                             qp, 0);
1187                 else
1188                         mlx4_qp_release_range(dev->dev, qpn, 1);
1189         }
1190 err_proxy:
1191         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1192                 free_proxy_bufs(pd->device, qp);
1193 err_wrid:
1194         if (pd->uobject) {
1195                 if (qp_has_rq(init_attr))
1196                         mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
1197         } else {
1198                 kvfree(qp->sq.wrid);
1199                 kvfree(qp->rq.wrid);
1200         }
1201
1202 err_mtt:
1203         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1204
1205 err_buf:
1206         if (pd->uobject)
1207                 ib_umem_release(qp->umem);
1208         else
1209                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
1210
1211 err_db:
1212         if (!pd->uobject && qp_has_rq(init_attr))
1213                 mlx4_db_free(dev->dev, &qp->db);
1214
1215 err:
1216         if (sqp)
1217                 kfree(sqp);
1218         else if (!*caller_qp)
1219                 kfree(qp);
1220         return err;
1221 }
1222
1223 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
1224 {
1225         switch (state) {
1226         case IB_QPS_RESET:      return MLX4_QP_STATE_RST;
1227         case IB_QPS_INIT:       return MLX4_QP_STATE_INIT;
1228         case IB_QPS_RTR:        return MLX4_QP_STATE_RTR;
1229         case IB_QPS_RTS:        return MLX4_QP_STATE_RTS;
1230         case IB_QPS_SQD:        return MLX4_QP_STATE_SQD;
1231         case IB_QPS_SQE:        return MLX4_QP_STATE_SQER;
1232         case IB_QPS_ERR:        return MLX4_QP_STATE_ERR;
1233         default:                return -1;
1234         }
1235 }
1236
1237 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
1238         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1239 {
1240         if (send_cq == recv_cq) {
1241                 spin_lock(&send_cq->lock);
1242                 __acquire(&recv_cq->lock);
1243         } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1244                 spin_lock(&send_cq->lock);
1245                 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
1246         } else {
1247                 spin_lock(&recv_cq->lock);
1248                 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
1249         }
1250 }
1251
1252 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
1253         __releases(&send_cq->lock) __releases(&recv_cq->lock)
1254 {
1255         if (send_cq == recv_cq) {
1256                 __release(&recv_cq->lock);
1257                 spin_unlock(&send_cq->lock);
1258         } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1259                 spin_unlock(&recv_cq->lock);
1260                 spin_unlock(&send_cq->lock);
1261         } else {
1262                 spin_unlock(&send_cq->lock);
1263                 spin_unlock(&recv_cq->lock);
1264         }
1265 }
1266
1267 static void del_gid_entries(struct mlx4_ib_qp *qp)
1268 {
1269         struct mlx4_ib_gid_entry *ge, *tmp;
1270
1271         list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1272                 list_del(&ge->list);
1273                 kfree(ge);
1274         }
1275 }
1276
1277 static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
1278 {
1279         if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
1280                 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
1281         else
1282                 return to_mpd(qp->ibqp.pd);
1283 }
1284
1285 static void get_cqs(struct mlx4_ib_qp *qp, enum mlx4_ib_source_type src,
1286                     struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
1287 {
1288         switch (qp->ibqp.qp_type) {
1289         case IB_QPT_XRC_TGT:
1290                 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
1291                 *recv_cq = *send_cq;
1292                 break;
1293         case IB_QPT_XRC_INI:
1294                 *send_cq = to_mcq(qp->ibqp.send_cq);
1295                 *recv_cq = *send_cq;
1296                 break;
1297         default:
1298                 *recv_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.recv_cq) :
1299                                                      to_mcq(qp->ibwq.cq);
1300                 *send_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.send_cq) :
1301                                                      *recv_cq;
1302                 break;
1303         }
1304 }
1305
1306 static void destroy_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1307 {
1308         if (qp->state != IB_QPS_RESET) {
1309                 int i;
1310
1311                 for (i = 0; i < (1 << qp->ibqp.rwq_ind_tbl->log_ind_tbl_size);
1312                      i++) {
1313                         struct ib_wq *ibwq = qp->ibqp.rwq_ind_tbl->ind_tbl[i];
1314                         struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
1315
1316                         mutex_lock(&wq->mutex);
1317
1318                         wq->rss_usecnt--;
1319
1320                         mutex_unlock(&wq->mutex);
1321                 }
1322
1323                 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1324                                    MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
1325                         pr_warn("modify QP %06x to RESET failed.\n",
1326                                 qp->mqp.qpn);
1327         }
1328
1329         mlx4_qp_remove(dev->dev, &qp->mqp);
1330         mlx4_qp_free(dev->dev, &qp->mqp);
1331         mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1332         del_gid_entries(qp);
1333         kfree(qp->rss_ctx);
1334 }
1335
1336 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
1337                               enum mlx4_ib_source_type src, int is_user)
1338 {
1339         struct mlx4_ib_cq *send_cq, *recv_cq;
1340         unsigned long flags;
1341
1342         if (qp->state != IB_QPS_RESET) {
1343                 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1344                                    MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
1345                         pr_warn("modify QP %06x to RESET failed.\n",
1346                                qp->mqp.qpn);
1347                 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
1348                         mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1349                         qp->pri.smac = 0;
1350                         qp->pri.smac_port = 0;
1351                 }
1352                 if (qp->alt.smac) {
1353                         mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1354                         qp->alt.smac = 0;
1355                 }
1356                 if (qp->pri.vid < 0x1000) {
1357                         mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1358                         qp->pri.vid = 0xFFFF;
1359                         qp->pri.candidate_vid = 0xFFFF;
1360                         qp->pri.update_vid = 0;
1361                 }
1362                 if (qp->alt.vid < 0x1000) {
1363                         mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1364                         qp->alt.vid = 0xFFFF;
1365                         qp->alt.candidate_vid = 0xFFFF;
1366                         qp->alt.update_vid = 0;
1367                 }
1368         }
1369
1370         get_cqs(qp, src, &send_cq, &recv_cq);
1371
1372         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1373         mlx4_ib_lock_cqs(send_cq, recv_cq);
1374
1375         /* del from lists under both locks above to protect reset flow paths */
1376         list_del(&qp->qps_list);
1377         list_del(&qp->cq_send_list);
1378         list_del(&qp->cq_recv_list);
1379         if (!is_user) {
1380                 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1381                                  qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1382                 if (send_cq != recv_cq)
1383                         __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1384         }
1385
1386         mlx4_qp_remove(dev->dev, &qp->mqp);
1387
1388         mlx4_ib_unlock_cqs(send_cq, recv_cq);
1389         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1390
1391         mlx4_qp_free(dev->dev, &qp->mqp);
1392
1393         if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1394                 if (qp->flags & MLX4_IB_QP_NETIF)
1395                         mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
1396                 else if (src == MLX4_IB_RWQ_SRC)
1397                         mlx4_ib_release_wqn(to_mucontext(
1398                                             qp->ibwq.uobject->context), qp, 1);
1399                 else
1400                         mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1401         }
1402
1403         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1404
1405         if (is_user) {
1406                 if (qp->rq.wqe_cnt) {
1407                         struct mlx4_ib_ucontext *mcontext = !src ?
1408                                 to_mucontext(qp->ibqp.uobject->context) :
1409                                 to_mucontext(qp->ibwq.uobject->context);
1410                         mlx4_ib_db_unmap_user(mcontext, &qp->db);
1411                 }
1412                 ib_umem_release(qp->umem);
1413         } else {
1414                 kvfree(qp->sq.wrid);
1415                 kvfree(qp->rq.wrid);
1416                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1417                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1418                         free_proxy_bufs(&dev->ib_dev, qp);
1419                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
1420                 if (qp->rq.wqe_cnt)
1421                         mlx4_db_free(dev->dev, &qp->db);
1422         }
1423
1424         del_gid_entries(qp);
1425 }
1426
1427 static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1428 {
1429         /* Native or PPF */
1430         if (!mlx4_is_mfunc(dev->dev) ||
1431             (mlx4_is_master(dev->dev) &&
1432              attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1433                 return  dev->dev->phys_caps.base_sqpn +
1434                         (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1435                         attr->port_num - 1;
1436         }
1437         /* PF or VF -- creating proxies */
1438         if (attr->qp_type == IB_QPT_SMI)
1439                 return dev->dev->caps.spec_qps[attr->port_num - 1].qp0_proxy;
1440         else
1441                 return dev->dev->caps.spec_qps[attr->port_num - 1].qp1_proxy;
1442 }
1443
1444 static struct ib_qp *_mlx4_ib_create_qp(struct ib_pd *pd,
1445                                         struct ib_qp_init_attr *init_attr,
1446                                         struct ib_udata *udata)
1447 {
1448         struct mlx4_ib_qp *qp = NULL;
1449         int err;
1450         int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1451         u16 xrcdn = 0;
1452
1453         if (init_attr->rwq_ind_tbl)
1454                 return _mlx4_ib_create_qp_rss(pd, init_attr, udata);
1455
1456         /*
1457          * We only support LSO, vendor flag1, and multicast loopback blocking,
1458          * and only for kernel UD QPs.
1459          */
1460         if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1461                                         MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
1462                                         MLX4_IB_SRIOV_TUNNEL_QP |
1463                                         MLX4_IB_SRIOV_SQP |
1464                                         MLX4_IB_QP_NETIF |
1465                                         MLX4_IB_QP_CREATE_ROCE_V2_GSI))
1466                 return ERR_PTR(-EINVAL);
1467
1468         if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1469                 if (init_attr->qp_type != IB_QPT_UD)
1470                         return ERR_PTR(-EINVAL);
1471         }
1472
1473         if (init_attr->create_flags) {
1474                 if (udata && init_attr->create_flags & ~(sup_u_create_flags))
1475                         return ERR_PTR(-EINVAL);
1476
1477                 if ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP |
1478                                                  MLX4_IB_QP_CREATE_ROCE_V2_GSI  |
1479                                                  MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) &&
1480                      init_attr->qp_type != IB_QPT_UD) ||
1481                     (init_attr->create_flags & MLX4_IB_SRIOV_SQP &&
1482                      init_attr->qp_type > IB_QPT_GSI) ||
1483                     (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI &&
1484                      init_attr->qp_type != IB_QPT_GSI))
1485                         return ERR_PTR(-EINVAL);
1486         }
1487
1488         switch (init_attr->qp_type) {
1489         case IB_QPT_XRC_TGT:
1490                 pd = to_mxrcd(init_attr->xrcd)->pd;
1491                 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1492                 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1493                 /* fall through */
1494         case IB_QPT_XRC_INI:
1495                 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1496                         return ERR_PTR(-ENOSYS);
1497                 init_attr->recv_cq = init_attr->send_cq;
1498                 /* fall through */
1499         case IB_QPT_RC:
1500         case IB_QPT_UC:
1501         case IB_QPT_RAW_PACKET:
1502                 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1503                 if (!qp)
1504                         return ERR_PTR(-ENOMEM);
1505                 qp->pri.vid = 0xFFFF;
1506                 qp->alt.vid = 0xFFFF;
1507                 /* fall through */
1508         case IB_QPT_UD:
1509         {
1510                 err = create_qp_common(to_mdev(pd->device), pd, MLX4_IB_QP_SRC,
1511                                        init_attr, udata, 0, &qp);
1512                 if (err) {
1513                         kfree(qp);
1514                         return ERR_PTR(err);
1515                 }
1516
1517                 qp->ibqp.qp_num = qp->mqp.qpn;
1518                 qp->xrcdn = xrcdn;
1519
1520                 break;
1521         }
1522         case IB_QPT_SMI:
1523         case IB_QPT_GSI:
1524         {
1525                 int sqpn;
1526
1527                 /* Userspace is not allowed to create special QPs: */
1528                 if (udata)
1529                         return ERR_PTR(-EINVAL);
1530                 if (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI) {
1531                         int res = mlx4_qp_reserve_range(to_mdev(pd->device)->dev,
1532                                                         1, 1, &sqpn, 0,
1533                                                         MLX4_RES_USAGE_DRIVER);
1534
1535                         if (res)
1536                                 return ERR_PTR(res);
1537                 } else {
1538                         sqpn = get_sqp_num(to_mdev(pd->device), init_attr);
1539                 }
1540
1541                 err = create_qp_common(to_mdev(pd->device), pd, MLX4_IB_QP_SRC,
1542                                        init_attr, udata, sqpn, &qp);
1543                 if (err)
1544                         return ERR_PTR(err);
1545
1546                 qp->port        = init_attr->port_num;
1547                 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 :
1548                         init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI ? sqpn : 1;
1549                 break;
1550         }
1551         default:
1552                 /* Don't support raw QPs */
1553                 return ERR_PTR(-EINVAL);
1554         }
1555
1556         return &qp->ibqp;
1557 }
1558
1559 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1560                                 struct ib_qp_init_attr *init_attr,
1561                                 struct ib_udata *udata) {
1562         struct ib_device *device = pd ? pd->device : init_attr->xrcd->device;
1563         struct ib_qp *ibqp;
1564         struct mlx4_ib_dev *dev = to_mdev(device);
1565
1566         ibqp = _mlx4_ib_create_qp(pd, init_attr, udata);
1567
1568         if (!IS_ERR(ibqp) &&
1569             (init_attr->qp_type == IB_QPT_GSI) &&
1570             !(init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI)) {
1571                 struct mlx4_ib_sqp *sqp = to_msqp((to_mqp(ibqp)));
1572                 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, init_attr->port_num);
1573
1574                 if (is_eth &&
1575                     dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
1576                         init_attr->create_flags |= MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1577                         sqp->roce_v2_gsi = ib_create_qp(pd, init_attr);
1578
1579                         if (IS_ERR(sqp->roce_v2_gsi)) {
1580                                 pr_err("Failed to create GSI QP for RoCEv2 (%ld)\n", PTR_ERR(sqp->roce_v2_gsi));
1581                                 sqp->roce_v2_gsi = NULL;
1582                         } else {
1583                                 sqp = to_msqp(to_mqp(sqp->roce_v2_gsi));
1584                                 sqp->qp.flags |= MLX4_IB_ROCE_V2_GSI_QP;
1585                         }
1586
1587                         init_attr->create_flags &= ~MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1588                 }
1589         }
1590         return ibqp;
1591 }
1592
1593 static int _mlx4_ib_destroy_qp(struct ib_qp *qp)
1594 {
1595         struct mlx4_ib_dev *dev = to_mdev(qp->device);
1596         struct mlx4_ib_qp *mqp = to_mqp(qp);
1597
1598         if (is_qp0(dev, mqp))
1599                 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1600
1601         if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI &&
1602             dev->qp1_proxy[mqp->port - 1] == mqp) {
1603                 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1604                 dev->qp1_proxy[mqp->port - 1] = NULL;
1605                 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1606         }
1607
1608         if (mqp->counter_index)
1609                 mlx4_ib_free_qp_counter(dev, mqp);
1610
1611         if (qp->rwq_ind_tbl) {
1612                 destroy_qp_rss(dev, mqp);
1613         } else {
1614                 struct mlx4_ib_pd *pd;
1615
1616                 pd = get_pd(mqp);
1617                 destroy_qp_common(dev, mqp, MLX4_IB_QP_SRC, !!pd->ibpd.uobject);
1618         }
1619
1620         if (is_sqp(dev, mqp))
1621                 kfree(to_msqp(mqp));
1622         else
1623                 kfree(mqp);
1624
1625         return 0;
1626 }
1627
1628 int mlx4_ib_destroy_qp(struct ib_qp *qp)
1629 {
1630         struct mlx4_ib_qp *mqp = to_mqp(qp);
1631
1632         if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
1633                 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
1634
1635                 if (sqp->roce_v2_gsi)
1636                         ib_destroy_qp(sqp->roce_v2_gsi);
1637         }
1638
1639         return _mlx4_ib_destroy_qp(qp);
1640 }
1641
1642 static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
1643 {
1644         switch (type) {
1645         case MLX4_IB_QPT_RC:            return MLX4_QP_ST_RC;
1646         case MLX4_IB_QPT_UC:            return MLX4_QP_ST_UC;
1647         case MLX4_IB_QPT_UD:            return MLX4_QP_ST_UD;
1648         case MLX4_IB_QPT_XRC_INI:
1649         case MLX4_IB_QPT_XRC_TGT:       return MLX4_QP_ST_XRC;
1650         case MLX4_IB_QPT_SMI:
1651         case MLX4_IB_QPT_GSI:
1652         case MLX4_IB_QPT_RAW_PACKET:    return MLX4_QP_ST_MLX;
1653
1654         case MLX4_IB_QPT_PROXY_SMI_OWNER:
1655         case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1656                                                 MLX4_QP_ST_MLX : -1);
1657         case MLX4_IB_QPT_PROXY_SMI:
1658         case MLX4_IB_QPT_TUN_SMI:
1659         case MLX4_IB_QPT_PROXY_GSI:
1660         case MLX4_IB_QPT_TUN_GSI:       return (mlx4_is_mfunc(dev->dev) ?
1661                                                 MLX4_QP_ST_UD : -1);
1662         default:                        return -1;
1663         }
1664 }
1665
1666 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
1667                                    int attr_mask)
1668 {
1669         u8 dest_rd_atomic;
1670         u32 access_flags;
1671         u32 hw_access_flags = 0;
1672
1673         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1674                 dest_rd_atomic = attr->max_dest_rd_atomic;
1675         else
1676                 dest_rd_atomic = qp->resp_depth;
1677
1678         if (attr_mask & IB_QP_ACCESS_FLAGS)
1679                 access_flags = attr->qp_access_flags;
1680         else
1681                 access_flags = qp->atomic_rd_en;
1682
1683         if (!dest_rd_atomic)
1684                 access_flags &= IB_ACCESS_REMOTE_WRITE;
1685
1686         if (access_flags & IB_ACCESS_REMOTE_READ)
1687                 hw_access_flags |= MLX4_QP_BIT_RRE;
1688         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1689                 hw_access_flags |= MLX4_QP_BIT_RAE;
1690         if (access_flags & IB_ACCESS_REMOTE_WRITE)
1691                 hw_access_flags |= MLX4_QP_BIT_RWE;
1692
1693         return cpu_to_be32(hw_access_flags);
1694 }
1695
1696 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
1697                             int attr_mask)
1698 {
1699         if (attr_mask & IB_QP_PKEY_INDEX)
1700                 sqp->pkey_index = attr->pkey_index;
1701         if (attr_mask & IB_QP_QKEY)
1702                 sqp->qkey = attr->qkey;
1703         if (attr_mask & IB_QP_SQ_PSN)
1704                 sqp->send_psn = attr->sq_psn;
1705 }
1706
1707 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1708 {
1709         path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1710 }
1711
1712 static int _mlx4_set_path(struct mlx4_ib_dev *dev,
1713                           const struct rdma_ah_attr *ah,
1714                           u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
1715                           struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
1716 {
1717         int vidx;
1718         int smac_index;
1719         int err;
1720
1721         path->grh_mylmc = rdma_ah_get_path_bits(ah) & 0x7f;
1722         path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
1723         if (rdma_ah_get_static_rate(ah)) {
1724                 path->static_rate = rdma_ah_get_static_rate(ah) +
1725                                     MLX4_STAT_RATE_OFFSET;
1726                 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1727                        !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1728                         --path->static_rate;
1729         } else
1730                 path->static_rate = 0;
1731
1732         if (rdma_ah_get_ah_flags(ah) & IB_AH_GRH) {
1733                 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
1734                 int real_sgid_index =
1735                         mlx4_ib_gid_index_to_real_index(dev, grh->sgid_attr);
1736
1737                 if (real_sgid_index < 0)
1738                         return real_sgid_index;
1739                 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) {
1740                         pr_err("sgid_index (%u) too large. max is %d\n",
1741                                real_sgid_index, dev->dev->caps.gid_table_len[port] - 1);
1742                         return -1;
1743                 }
1744
1745                 path->grh_mylmc |= 1 << 7;
1746                 path->mgid_index = real_sgid_index;
1747                 path->hop_limit  = grh->hop_limit;
1748                 path->tclass_flowlabel =
1749                         cpu_to_be32((grh->traffic_class << 20) |
1750                                     (grh->flow_label));
1751                 memcpy(path->rgid, grh->dgid.raw, 16);
1752         }
1753
1754         if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
1755                 if (!(rdma_ah_get_ah_flags(ah) & IB_AH_GRH))
1756                         return -1;
1757
1758                 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1759                         ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 7) << 3);
1760
1761                 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
1762                 if (vlan_tag < 0x1000) {
1763                         if (smac_info->vid < 0x1000) {
1764                                 /* both valid vlan ids */
1765                                 if (smac_info->vid != vlan_tag) {
1766                                         /* different VIDs.  unreg old and reg new */
1767                                         err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1768                                         if (err)
1769                                                 return err;
1770                                         smac_info->candidate_vid = vlan_tag;
1771                                         smac_info->candidate_vlan_index = vidx;
1772                                         smac_info->candidate_vlan_port = port;
1773                                         smac_info->update_vid = 1;
1774                                         path->vlan_index = vidx;
1775                                 } else {
1776                                         path->vlan_index = smac_info->vlan_index;
1777                                 }
1778                         } else {
1779                                 /* no current vlan tag in qp */
1780                                 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1781                                 if (err)
1782                                         return err;
1783                                 smac_info->candidate_vid = vlan_tag;
1784                                 smac_info->candidate_vlan_index = vidx;
1785                                 smac_info->candidate_vlan_port = port;
1786                                 smac_info->update_vid = 1;
1787                                 path->vlan_index = vidx;
1788                         }
1789                         path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
1790                         path->fl = 1 << 6;
1791                 } else {
1792                         /* have current vlan tag. unregister it at modify-qp success */
1793                         if (smac_info->vid < 0x1000) {
1794                                 smac_info->candidate_vid = 0xFFFF;
1795                                 smac_info->update_vid = 1;
1796                         }
1797                 }
1798
1799                 /* get smac_index for RoCE use.
1800                  * If no smac was yet assigned, register one.
1801                  * If one was already assigned, but the new mac differs,
1802                  * unregister the old one and register the new one.
1803                 */
1804                 if ((!smac_info->smac && !smac_info->smac_port) ||
1805                     smac_info->smac != smac) {
1806                         /* register candidate now, unreg if needed, after success */
1807                         smac_index = mlx4_register_mac(dev->dev, port, smac);
1808                         if (smac_index >= 0) {
1809                                 smac_info->candidate_smac_index = smac_index;
1810                                 smac_info->candidate_smac = smac;
1811                                 smac_info->candidate_smac_port = port;
1812                         } else {
1813                                 return -EINVAL;
1814                         }
1815                 } else {
1816                         smac_index = smac_info->smac_index;
1817                 }
1818                 memcpy(path->dmac, ah->roce.dmac, 6);
1819                 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1820                 /* put MAC table smac index for IBoE */
1821                 path->grh_mylmc = (u8) (smac_index) | 0x80;
1822         } else {
1823                 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1824                         ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 0xf) << 2);
1825         }
1826
1827         return 0;
1828 }
1829
1830 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1831                          enum ib_qp_attr_mask qp_attr_mask,
1832                          struct mlx4_ib_qp *mqp,
1833                          struct mlx4_qp_path *path, u8 port,
1834                          u16 vlan_id, u8 *smac)
1835 {
1836         return _mlx4_set_path(dev, &qp->ah_attr,
1837                               mlx4_mac_to_u64(smac),
1838                               vlan_id,
1839                               path, &mqp->pri, port);
1840 }
1841
1842 static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1843                              const struct ib_qp_attr *qp,
1844                              enum ib_qp_attr_mask qp_attr_mask,
1845                              struct mlx4_ib_qp *mqp,
1846                              struct mlx4_qp_path *path, u8 port)
1847 {
1848         return _mlx4_set_path(dev, &qp->alt_ah_attr,
1849                               0,
1850                               0xffff,
1851                               path, &mqp->alt, port);
1852 }
1853
1854 static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1855 {
1856         struct mlx4_ib_gid_entry *ge, *tmp;
1857
1858         list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1859                 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1860                         ge->added = 1;
1861                         ge->port = qp->port;
1862                 }
1863         }
1864 }
1865
1866 static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev,
1867                                     struct mlx4_ib_qp *qp,
1868                                     struct mlx4_qp_context *context)
1869 {
1870         u64 u64_mac;
1871         int smac_index;
1872
1873         u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
1874
1875         context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
1876         if (!qp->pri.smac && !qp->pri.smac_port) {
1877                 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1878                 if (smac_index >= 0) {
1879                         qp->pri.candidate_smac_index = smac_index;
1880                         qp->pri.candidate_smac = u64_mac;
1881                         qp->pri.candidate_smac_port = qp->port;
1882                         context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1883                 } else {
1884                         return -ENOENT;
1885                 }
1886         }
1887         return 0;
1888 }
1889
1890 static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1891 {
1892         struct counter_index *new_counter_index;
1893         int err;
1894         u32 tmp_idx;
1895
1896         if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) !=
1897             IB_LINK_LAYER_ETHERNET ||
1898             !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) ||
1899             !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK))
1900                 return 0;
1901
1902         err = mlx4_counter_alloc(dev->dev, &tmp_idx, MLX4_RES_USAGE_DRIVER);
1903         if (err)
1904                 return err;
1905
1906         new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL);
1907         if (!new_counter_index) {
1908                 mlx4_counter_free(dev->dev, tmp_idx);
1909                 return -ENOMEM;
1910         }
1911
1912         new_counter_index->index = tmp_idx;
1913         new_counter_index->allocated = 1;
1914         qp->counter_index = new_counter_index;
1915
1916         mutex_lock(&dev->counters_table[qp->port - 1].mutex);
1917         list_add_tail(&new_counter_index->list,
1918                       &dev->counters_table[qp->port - 1].counters_list);
1919         mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
1920
1921         return 0;
1922 }
1923
1924 enum {
1925         MLX4_QPC_ROCE_MODE_1 = 0,
1926         MLX4_QPC_ROCE_MODE_2 = 2,
1927         MLX4_QPC_ROCE_MODE_UNDEFINED = 0xff
1928 };
1929
1930 static u8 gid_type_to_qpc(enum ib_gid_type gid_type)
1931 {
1932         switch (gid_type) {
1933         case IB_GID_TYPE_ROCE:
1934                 return MLX4_QPC_ROCE_MODE_1;
1935         case IB_GID_TYPE_ROCE_UDP_ENCAP:
1936                 return MLX4_QPC_ROCE_MODE_2;
1937         default:
1938                 return MLX4_QPC_ROCE_MODE_UNDEFINED;
1939         }
1940 }
1941
1942 /*
1943  * Go over all RSS QP's childes (WQs) and apply their HW state according to
1944  * their logic state if the RSS QP is the first RSS QP associated for the WQ.
1945  */
1946 static int bringup_rss_rwqs(struct ib_rwq_ind_table *ind_tbl, u8 port_num)
1947 {
1948         int err = 0;
1949         int i;
1950
1951         for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) {
1952                 struct ib_wq *ibwq = ind_tbl->ind_tbl[i];
1953                 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
1954
1955                 mutex_lock(&wq->mutex);
1956
1957                 /* Mlx4_ib restrictions:
1958                  * WQ's is associated to a port according to the RSS QP it is
1959                  * associates to.
1960                  * In case the WQ is associated to a different port by another
1961                  * RSS QP, return a failure.
1962                  */
1963                 if ((wq->rss_usecnt > 0) && (wq->port != port_num)) {
1964                         err = -EINVAL;
1965                         mutex_unlock(&wq->mutex);
1966                         break;
1967                 }
1968                 wq->port = port_num;
1969                 if ((wq->rss_usecnt == 0) && (ibwq->state == IB_WQS_RDY)) {
1970                         err = _mlx4_ib_modify_wq(ibwq, IB_WQS_RDY);
1971                         if (err) {
1972                                 mutex_unlock(&wq->mutex);
1973                                 break;
1974                         }
1975                 }
1976                 wq->rss_usecnt++;
1977
1978                 mutex_unlock(&wq->mutex);
1979         }
1980
1981         if (i && err) {
1982                 int j;
1983
1984                 for (j = (i - 1); j >= 0; j--) {
1985                         struct ib_wq *ibwq = ind_tbl->ind_tbl[j];
1986                         struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
1987
1988                         mutex_lock(&wq->mutex);
1989
1990                         if ((wq->rss_usecnt == 1) &&
1991                             (ibwq->state == IB_WQS_RDY))
1992                                 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET))
1993                                         pr_warn("failed to reverse WQN=0x%06x\n",
1994                                                 ibwq->wq_num);
1995                         wq->rss_usecnt--;
1996
1997                         mutex_unlock(&wq->mutex);
1998                 }
1999         }
2000
2001         return err;
2002 }
2003
2004 static void bring_down_rss_rwqs(struct ib_rwq_ind_table *ind_tbl)
2005 {
2006         int i;
2007
2008         for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) {
2009                 struct ib_wq *ibwq = ind_tbl->ind_tbl[i];
2010                 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2011
2012                 mutex_lock(&wq->mutex);
2013
2014                 if ((wq->rss_usecnt == 1) && (ibwq->state == IB_WQS_RDY))
2015                         if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET))
2016                                 pr_warn("failed to reverse WQN=%x\n",
2017                                         ibwq->wq_num);
2018                 wq->rss_usecnt--;
2019
2020                 mutex_unlock(&wq->mutex);
2021         }
2022 }
2023
2024 static void fill_qp_rss_context(struct mlx4_qp_context *context,
2025                                 struct mlx4_ib_qp *qp)
2026 {
2027         struct mlx4_rss_context *rss_context;
2028
2029         rss_context = (void *)context + offsetof(struct mlx4_qp_context,
2030                         pri_path) + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
2031
2032         rss_context->base_qpn = cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz);
2033         rss_context->default_qpn =
2034                 cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz & 0xffffff);
2035         if (qp->rss_ctx->flags & (MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6))
2036                 rss_context->base_qpn_udp = rss_context->default_qpn;
2037         rss_context->flags = qp->rss_ctx->flags;
2038         /* Currently support just toeplitz */
2039         rss_context->hash_fn = MLX4_RSS_HASH_TOP;
2040
2041         memcpy(rss_context->rss_key, qp->rss_ctx->rss_key,
2042                MLX4_EN_RSS_KEY_SIZE);
2043 }
2044
2045 static int __mlx4_ib_modify_qp(void *src, enum mlx4_ib_source_type src_type,
2046                                const struct ib_qp_attr *attr, int attr_mask,
2047                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
2048 {
2049         struct ib_uobject *ibuobject;
2050         struct ib_srq  *ibsrq;
2051         const struct ib_gid_attr *gid_attr = NULL;
2052         struct ib_rwq_ind_table *rwq_ind_tbl;
2053         enum ib_qp_type qp_type;
2054         struct mlx4_ib_dev *dev;
2055         struct mlx4_ib_qp *qp;
2056         struct mlx4_ib_pd *pd;
2057         struct mlx4_ib_cq *send_cq, *recv_cq;
2058         struct mlx4_qp_context *context;
2059         enum mlx4_qp_optpar optpar = 0;
2060         int sqd_event;
2061         int steer_qp = 0;
2062         int err = -EINVAL;
2063         int counter_index;
2064
2065         if (src_type == MLX4_IB_RWQ_SRC) {
2066                 struct ib_wq *ibwq;
2067
2068                 ibwq        = (struct ib_wq *)src;
2069                 ibuobject   = ibwq->uobject;
2070                 ibsrq       = NULL;
2071                 rwq_ind_tbl = NULL;
2072                 qp_type     = IB_QPT_RAW_PACKET;
2073                 qp          = to_mqp((struct ib_qp *)ibwq);
2074                 dev         = to_mdev(ibwq->device);
2075                 pd          = to_mpd(ibwq->pd);
2076         } else {
2077                 struct ib_qp *ibqp;
2078
2079                 ibqp        = (struct ib_qp *)src;
2080                 ibuobject   = ibqp->uobject;
2081                 ibsrq       = ibqp->srq;
2082                 rwq_ind_tbl = ibqp->rwq_ind_tbl;
2083                 qp_type     = ibqp->qp_type;
2084                 qp          = to_mqp(ibqp);
2085                 dev         = to_mdev(ibqp->device);
2086                 pd          = get_pd(qp);
2087         }
2088
2089         /* APM is not supported under RoCE */
2090         if (attr_mask & IB_QP_ALT_PATH &&
2091             rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
2092             IB_LINK_LAYER_ETHERNET)
2093                 return -ENOTSUPP;
2094
2095         context = kzalloc(sizeof *context, GFP_KERNEL);
2096         if (!context)
2097                 return -ENOMEM;
2098
2099         context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
2100                                      (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
2101
2102         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
2103                 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
2104         else {
2105                 optpar |= MLX4_QP_OPTPAR_PM_STATE;
2106                 switch (attr->path_mig_state) {
2107                 case IB_MIG_MIGRATED:
2108                         context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
2109                         break;
2110                 case IB_MIG_REARM:
2111                         context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
2112                         break;
2113                 case IB_MIG_ARMED:
2114                         context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
2115                         break;
2116                 }
2117         }
2118
2119         if (qp->inl_recv_sz)
2120                 context->param3 |= cpu_to_be32(1 << 25);
2121
2122         if (qp->flags & MLX4_IB_QP_SCATTER_FCS)
2123                 context->param3 |= cpu_to_be32(1 << 29);
2124
2125         if (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI)
2126                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
2127         else if (qp_type == IB_QPT_RAW_PACKET)
2128                 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
2129         else if (qp_type == IB_QPT_UD) {
2130                 if (qp->flags & MLX4_IB_QP_LSO)
2131                         context->mtu_msgmax = (IB_MTU_4096 << 5) |
2132                                               ilog2(dev->dev->caps.max_gso_sz);
2133                 else
2134                         context->mtu_msgmax = (IB_MTU_4096 << 5) | 13;
2135         } else if (attr_mask & IB_QP_PATH_MTU) {
2136                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
2137                         pr_err("path MTU (%u) is invalid\n",
2138                                attr->path_mtu);
2139                         goto out;
2140                 }
2141                 context->mtu_msgmax = (attr->path_mtu << 5) |
2142                         ilog2(dev->dev->caps.max_msg_sz);
2143         }
2144
2145         if (!rwq_ind_tbl) { /* PRM RSS receive side should be left zeros */
2146                 if (qp->rq.wqe_cnt)
2147                         context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
2148                 context->rq_size_stride |= qp->rq.wqe_shift - 4;
2149         }
2150
2151         if (qp->sq.wqe_cnt)
2152                 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
2153         context->sq_size_stride |= qp->sq.wqe_shift - 4;
2154
2155         if (new_state == IB_QPS_RESET && qp->counter_index)
2156                 mlx4_ib_free_qp_counter(dev, qp);
2157
2158         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2159                 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
2160                 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
2161                 if (qp_type == IB_QPT_RAW_PACKET)
2162                         context->param3 |= cpu_to_be32(1 << 30);
2163         }
2164
2165         if (ibuobject)
2166                 context->usr_page = cpu_to_be32(
2167                         mlx4_to_hw_uar_index(dev->dev,
2168                                              to_mucontext(ibuobject->context)
2169                                              ->uar.index));
2170         else
2171                 context->usr_page = cpu_to_be32(
2172                         mlx4_to_hw_uar_index(dev->dev, dev->priv_uar.index));
2173
2174         if (attr_mask & IB_QP_DEST_QPN)
2175                 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
2176
2177         if (attr_mask & IB_QP_PORT) {
2178                 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
2179                     !(attr_mask & IB_QP_AV)) {
2180                         mlx4_set_sched(&context->pri_path, attr->port_num);
2181                         optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
2182                 }
2183         }
2184
2185         if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
2186                 err = create_qp_lb_counter(dev, qp);
2187                 if (err)
2188                         goto out;
2189
2190                 counter_index =
2191                         dev->counters_table[qp->port - 1].default_counter;
2192                 if (qp->counter_index)
2193                         counter_index = qp->counter_index->index;
2194
2195                 if (counter_index != -1) {
2196                         context->pri_path.counter_index = counter_index;
2197                         optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
2198                         if (qp->counter_index) {
2199                                 context->pri_path.fl |=
2200                                         MLX4_FL_ETH_SRC_CHECK_MC_LB;
2201                                 context->pri_path.vlan_control |=
2202                                         MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
2203                         }
2204                 } else
2205                         context->pri_path.counter_index =
2206                                 MLX4_SINK_COUNTER_INDEX(dev->dev);
2207
2208                 if (qp->flags & MLX4_IB_QP_NETIF) {
2209                         mlx4_ib_steer_qp_reg(dev, qp, 1);
2210                         steer_qp = 1;
2211                 }
2212
2213                 if (qp_type == IB_QPT_GSI) {
2214                         enum ib_gid_type gid_type = qp->flags & MLX4_IB_ROCE_V2_GSI_QP ?
2215                                 IB_GID_TYPE_ROCE_UDP_ENCAP : IB_GID_TYPE_ROCE;
2216                         u8 qpc_roce_mode = gid_type_to_qpc(gid_type);
2217
2218                         context->rlkey_roce_mode |= (qpc_roce_mode << 6);
2219                 }
2220         }
2221
2222         if (attr_mask & IB_QP_PKEY_INDEX) {
2223                 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
2224                         context->pri_path.disable_pkey_check = 0x40;
2225                 context->pri_path.pkey_index = attr->pkey_index;
2226                 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
2227         }
2228
2229         if (attr_mask & IB_QP_AV) {
2230                 u8 port_num = mlx4_is_bonded(dev->dev) ? 1 :
2231                         attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2232                 u16 vlan = 0xffff;
2233                 u8 smac[ETH_ALEN];
2234                 int is_eth =
2235                         rdma_cap_eth_ah(&dev->ib_dev, port_num) &&
2236                         rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
2237
2238                 if (is_eth) {
2239                         gid_attr = attr->ah_attr.grh.sgid_attr;
2240                         vlan = rdma_vlan_dev_vlan_id(gid_attr->ndev);
2241                         memcpy(smac, gid_attr->ndev->dev_addr, ETH_ALEN);
2242                 }
2243
2244                 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
2245                                   port_num, vlan, smac))
2246                         goto out;
2247
2248                 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
2249                            MLX4_QP_OPTPAR_SCHED_QUEUE);
2250
2251                 if (is_eth &&
2252                     (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR)) {
2253                         u8 qpc_roce_mode = gid_type_to_qpc(gid_attr->gid_type);
2254
2255                         if (qpc_roce_mode == MLX4_QPC_ROCE_MODE_UNDEFINED) {
2256                                 err = -EINVAL;
2257                                 goto out;
2258                         }
2259                         context->rlkey_roce_mode |= (qpc_roce_mode << 6);
2260                 }
2261
2262         }
2263
2264         if (attr_mask & IB_QP_TIMEOUT) {
2265                 context->pri_path.ackto |= attr->timeout << 3;
2266                 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
2267         }
2268
2269         if (attr_mask & IB_QP_ALT_PATH) {
2270                 if (attr->alt_port_num == 0 ||
2271                     attr->alt_port_num > dev->dev->caps.num_ports)
2272                         goto out;
2273
2274                 if (attr->alt_pkey_index >=
2275                     dev->dev->caps.pkey_table_len[attr->alt_port_num])
2276                         goto out;
2277
2278                 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
2279                                       &context->alt_path,
2280                                       attr->alt_port_num))
2281                         goto out;
2282
2283                 context->alt_path.pkey_index = attr->alt_pkey_index;
2284                 context->alt_path.ackto = attr->alt_timeout << 3;
2285                 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
2286         }
2287
2288         context->pd = cpu_to_be32(pd->pdn);
2289
2290         if (!rwq_ind_tbl) {
2291                 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
2292                 get_cqs(qp, src_type, &send_cq, &recv_cq);
2293         } else { /* Set dummy CQs to be compatible with HV and PRM */
2294                 send_cq = to_mcq(rwq_ind_tbl->ind_tbl[0]->cq);
2295                 recv_cq = send_cq;
2296         }
2297         context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
2298         context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
2299
2300         /* Set "fast registration enabled" for all kernel QPs */
2301         if (!ibuobject)
2302                 context->params1 |= cpu_to_be32(1 << 11);
2303
2304         if (attr_mask & IB_QP_RNR_RETRY) {
2305                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2306                 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
2307         }
2308
2309         if (attr_mask & IB_QP_RETRY_CNT) {
2310                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2311                 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
2312         }
2313
2314         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2315                 if (attr->max_rd_atomic)
2316                         context->params1 |=
2317                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2318                 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
2319         }
2320
2321         if (attr_mask & IB_QP_SQ_PSN)
2322                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2323
2324         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2325                 if (attr->max_dest_rd_atomic)
2326                         context->params2 |=
2327                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2328                 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
2329         }
2330
2331         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
2332                 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
2333                 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
2334         }
2335
2336         if (ibsrq)
2337                 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
2338
2339         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2340                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2341                 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
2342         }
2343         if (attr_mask & IB_QP_RQ_PSN)
2344                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2345
2346         /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
2347         if (attr_mask & IB_QP_QKEY) {
2348                 if (qp->mlx4_ib_qp_type &
2349                     (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
2350                         context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
2351                 else {
2352                         if (mlx4_is_mfunc(dev->dev) &&
2353                             !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
2354                             (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
2355                             MLX4_RESERVED_QKEY_BASE) {
2356                                 pr_err("Cannot use reserved QKEY"
2357                                        " 0x%x (range 0xffff0000..0xffffffff"
2358                                        " is reserved)\n", attr->qkey);
2359                                 err = -EINVAL;
2360                                 goto out;
2361                         }
2362                         context->qkey = cpu_to_be32(attr->qkey);
2363                 }
2364                 optpar |= MLX4_QP_OPTPAR_Q_KEY;
2365         }
2366
2367         if (ibsrq)
2368                 context->srqn = cpu_to_be32(1 << 24 |
2369                                             to_msrq(ibsrq)->msrq.srqn);
2370
2371         if (qp->rq.wqe_cnt &&
2372             cur_state == IB_QPS_RESET &&
2373             new_state == IB_QPS_INIT)
2374                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2375
2376         if (cur_state == IB_QPS_INIT &&
2377             new_state == IB_QPS_RTR  &&
2378             (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI ||
2379              qp_type == IB_QPT_UD || qp_type == IB_QPT_RAW_PACKET)) {
2380                 context->pri_path.sched_queue = (qp->port - 1) << 6;
2381                 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2382                     qp->mlx4_ib_qp_type &
2383                     (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
2384                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
2385                         if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
2386                                 context->pri_path.fl = 0x80;
2387                 } else {
2388                         if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
2389                                 context->pri_path.fl = 0x80;
2390                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
2391                 }
2392                 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
2393                     IB_LINK_LAYER_ETHERNET) {
2394                         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
2395                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
2396                                 context->pri_path.feup = 1 << 7; /* don't fsm */
2397                         /* handle smac_index */
2398                         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
2399                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
2400                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
2401                                 err = handle_eth_ud_smac_index(dev, qp, context);
2402                                 if (err) {
2403                                         err = -EINVAL;
2404                                         goto out;
2405                                 }
2406                                 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
2407                                         dev->qp1_proxy[qp->port - 1] = qp;
2408                         }
2409                 }
2410         }
2411
2412         if (qp_type == IB_QPT_RAW_PACKET) {
2413                 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
2414                                         MLX4_IB_LINK_TYPE_ETH;
2415                 if (dev->dev->caps.tunnel_offload_mode ==  MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
2416                         /* set QP to receive both tunneled & non-tunneled packets */
2417                         if (!rwq_ind_tbl)
2418                                 context->srqn = cpu_to_be32(7 << 28);
2419                 }
2420         }
2421
2422         if (qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
2423                 int is_eth = rdma_port_get_link_layer(
2424                                 &dev->ib_dev, qp->port) ==
2425                                 IB_LINK_LAYER_ETHERNET;
2426                 if (is_eth) {
2427                         context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
2428                         optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
2429                 }
2430         }
2431
2432         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
2433             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
2434                 sqd_event = 1;
2435         else
2436                 sqd_event = 0;
2437
2438         if (!ibuobject &&
2439             cur_state == IB_QPS_RESET &&
2440             new_state == IB_QPS_INIT)
2441                 context->rlkey_roce_mode |= (1 << 4);
2442
2443         /*
2444          * Before passing a kernel QP to the HW, make sure that the
2445          * ownership bits of the send queue are set and the SQ
2446          * headroom is stamped so that the hardware doesn't start
2447          * processing stale work requests.
2448          */
2449         if (!ibuobject &&
2450             cur_state == IB_QPS_RESET &&
2451             new_state == IB_QPS_INIT) {
2452                 struct mlx4_wqe_ctrl_seg *ctrl;
2453                 int i;
2454
2455                 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
2456                         ctrl = get_send_wqe(qp, i);
2457                         ctrl->owner_opcode = cpu_to_be32(1 << 31);
2458                         ctrl->qpn_vlan.fence_size =
2459                                 1 << (qp->sq.wqe_shift - 4);
2460                         stamp_send_wqe(qp, i);
2461                 }
2462         }
2463
2464         if (rwq_ind_tbl &&
2465             cur_state == IB_QPS_RESET &&
2466             new_state == IB_QPS_INIT) {
2467                 fill_qp_rss_context(context, qp);
2468                 context->flags |= cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET);
2469         }
2470
2471         err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
2472                              to_mlx4_state(new_state), context, optpar,
2473                              sqd_event, &qp->mqp);
2474         if (err)
2475                 goto out;
2476
2477         qp->state = new_state;
2478
2479         if (attr_mask & IB_QP_ACCESS_FLAGS)
2480                 qp->atomic_rd_en = attr->qp_access_flags;
2481         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2482                 qp->resp_depth = attr->max_dest_rd_atomic;
2483         if (attr_mask & IB_QP_PORT) {
2484                 qp->port = attr->port_num;
2485                 update_mcg_macs(dev, qp);
2486         }
2487         if (attr_mask & IB_QP_ALT_PATH)
2488                 qp->alt_port = attr->alt_port_num;
2489
2490         if (is_sqp(dev, qp))
2491                 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
2492
2493         /*
2494          * If we moved QP0 to RTR, bring the IB link up; if we moved
2495          * QP0 to RESET or ERROR, bring the link back down.
2496          */
2497         if (is_qp0(dev, qp)) {
2498                 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
2499                         if (mlx4_INIT_PORT(dev->dev, qp->port))
2500                                 pr_warn("INIT_PORT failed for port %d\n",
2501                                        qp->port);
2502
2503                 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2504                     (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
2505                         mlx4_CLOSE_PORT(dev->dev, qp->port);
2506         }
2507
2508         /*
2509          * If we moved a kernel QP to RESET, clean up all old CQ
2510          * entries and reinitialize the QP.
2511          */
2512         if (new_state == IB_QPS_RESET) {
2513                 if (!ibuobject) {
2514                         mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
2515                                          ibsrq ? to_msrq(ibsrq) : NULL);
2516                         if (send_cq != recv_cq)
2517                                 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
2518
2519                         qp->rq.head = 0;
2520                         qp->rq.tail = 0;
2521                         qp->sq.head = 0;
2522                         qp->sq.tail = 0;
2523                         qp->sq_next_wqe = 0;
2524                         if (qp->rq.wqe_cnt)
2525                                 *qp->db.db  = 0;
2526
2527                         if (qp->flags & MLX4_IB_QP_NETIF)
2528                                 mlx4_ib_steer_qp_reg(dev, qp, 0);
2529                 }
2530                 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2531                         mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2532                         qp->pri.smac = 0;
2533                         qp->pri.smac_port = 0;
2534                 }
2535                 if (qp->alt.smac) {
2536                         mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2537                         qp->alt.smac = 0;
2538                 }
2539                 if (qp->pri.vid < 0x1000) {
2540                         mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
2541                         qp->pri.vid = 0xFFFF;
2542                         qp->pri.candidate_vid = 0xFFFF;
2543                         qp->pri.update_vid = 0;
2544                 }
2545
2546                 if (qp->alt.vid < 0x1000) {
2547                         mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
2548                         qp->alt.vid = 0xFFFF;
2549                         qp->alt.candidate_vid = 0xFFFF;
2550                         qp->alt.update_vid = 0;
2551                 }
2552         }
2553 out:
2554         if (err && qp->counter_index)
2555                 mlx4_ib_free_qp_counter(dev, qp);
2556         if (err && steer_qp)
2557                 mlx4_ib_steer_qp_reg(dev, qp, 0);
2558         kfree(context);
2559         if (qp->pri.candidate_smac ||
2560             (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
2561                 if (err) {
2562                         mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
2563                 } else {
2564                         if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
2565                                 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2566                         qp->pri.smac = qp->pri.candidate_smac;
2567                         qp->pri.smac_index = qp->pri.candidate_smac_index;
2568                         qp->pri.smac_port = qp->pri.candidate_smac_port;
2569                 }
2570                 qp->pri.candidate_smac = 0;
2571                 qp->pri.candidate_smac_index = 0;
2572                 qp->pri.candidate_smac_port = 0;
2573         }
2574         if (qp->alt.candidate_smac) {
2575                 if (err) {
2576                         mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
2577                 } else {
2578                         if (qp->alt.smac)
2579                                 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2580                         qp->alt.smac = qp->alt.candidate_smac;
2581                         qp->alt.smac_index = qp->alt.candidate_smac_index;
2582                         qp->alt.smac_port = qp->alt.candidate_smac_port;
2583                 }
2584                 qp->alt.candidate_smac = 0;
2585                 qp->alt.candidate_smac_index = 0;
2586                 qp->alt.candidate_smac_port = 0;
2587         }
2588
2589         if (qp->pri.update_vid) {
2590                 if (err) {
2591                         if (qp->pri.candidate_vid < 0x1000)
2592                                 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
2593                                                      qp->pri.candidate_vid);
2594                 } else {
2595                         if (qp->pri.vid < 0x1000)
2596                                 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
2597                                                      qp->pri.vid);
2598                         qp->pri.vid = qp->pri.candidate_vid;
2599                         qp->pri.vlan_port = qp->pri.candidate_vlan_port;
2600                         qp->pri.vlan_index =  qp->pri.candidate_vlan_index;
2601                 }
2602                 qp->pri.candidate_vid = 0xFFFF;
2603                 qp->pri.update_vid = 0;
2604         }
2605
2606         if (qp->alt.update_vid) {
2607                 if (err) {
2608                         if (qp->alt.candidate_vid < 0x1000)
2609                                 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
2610                                                      qp->alt.candidate_vid);
2611                 } else {
2612                         if (qp->alt.vid < 0x1000)
2613                                 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
2614                                                      qp->alt.vid);
2615                         qp->alt.vid = qp->alt.candidate_vid;
2616                         qp->alt.vlan_port = qp->alt.candidate_vlan_port;
2617                         qp->alt.vlan_index =  qp->alt.candidate_vlan_index;
2618                 }
2619                 qp->alt.candidate_vid = 0xFFFF;
2620                 qp->alt.update_vid = 0;
2621         }
2622
2623         return err;
2624 }
2625
2626 enum {
2627         MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK = (IB_QP_STATE       |
2628                                               IB_QP_PORT),
2629 };
2630
2631 static int _mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2632                               int attr_mask, struct ib_udata *udata)
2633 {
2634         enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
2635         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2636         struct mlx4_ib_qp *qp = to_mqp(ibqp);
2637         enum ib_qp_state cur_state, new_state;
2638         int err = -EINVAL;
2639         mutex_lock(&qp->mutex);
2640
2641         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2642         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2643
2644         if (cur_state != new_state || cur_state != IB_QPS_RESET) {
2645                 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2646                 ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2647         }
2648
2649         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
2650                                 attr_mask, ll)) {
2651                 pr_debug("qpn 0x%x: invalid attribute mask specified "
2652                          "for transition %d to %d. qp_type %d,"
2653                          " attr_mask 0x%x\n",
2654                          ibqp->qp_num, cur_state, new_state,
2655                          ibqp->qp_type, attr_mask);
2656                 goto out;
2657         }
2658
2659         if (ibqp->rwq_ind_tbl) {
2660                 if (!(((cur_state == IB_QPS_RESET) &&
2661                        (new_state == IB_QPS_INIT)) ||
2662                       ((cur_state == IB_QPS_INIT)  &&
2663                        (new_state == IB_QPS_RTR)))) {
2664                         pr_debug("qpn 0x%x: RSS QP unsupported transition %d to %d\n",
2665                                  ibqp->qp_num, cur_state, new_state);
2666
2667                         err = -EOPNOTSUPP;
2668                         goto out;
2669                 }
2670
2671                 if (attr_mask & ~MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK) {
2672                         pr_debug("qpn 0x%x: RSS QP unsupported attribute mask 0x%x for transition %d to %d\n",
2673                                  ibqp->qp_num, attr_mask, cur_state, new_state);
2674
2675                         err = -EOPNOTSUPP;
2676                         goto out;
2677                 }
2678         }
2679
2680         if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
2681                 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2682                         if ((ibqp->qp_type == IB_QPT_RC) ||
2683                             (ibqp->qp_type == IB_QPT_UD) ||
2684                             (ibqp->qp_type == IB_QPT_UC) ||
2685                             (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2686                             (ibqp->qp_type == IB_QPT_XRC_INI)) {
2687                                 attr->port_num = mlx4_ib_bond_next_port(dev);
2688                         }
2689                 } else {
2690                         /* no sense in changing port_num
2691                          * when ports are bonded */
2692                         attr_mask &= ~IB_QP_PORT;
2693                 }
2694         }
2695
2696         if ((attr_mask & IB_QP_PORT) &&
2697             (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
2698                 pr_debug("qpn 0x%x: invalid port number (%d) specified "
2699                          "for transition %d to %d. qp_type %d\n",
2700                          ibqp->qp_num, attr->port_num, cur_state,
2701                          new_state, ibqp->qp_type);
2702                 goto out;
2703         }
2704
2705         if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
2706             (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
2707              IB_LINK_LAYER_ETHERNET))
2708                 goto out;
2709
2710         if (attr_mask & IB_QP_PKEY_INDEX) {
2711                 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2712                 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
2713                         pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
2714                                  "for transition %d to %d. qp_type %d\n",
2715                                  ibqp->qp_num, attr->pkey_index, cur_state,
2716                                  new_state, ibqp->qp_type);
2717                         goto out;
2718                 }
2719         }
2720
2721         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2722             attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
2723                 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
2724                          "Transition %d to %d. qp_type %d\n",
2725                          ibqp->qp_num, attr->max_rd_atomic, cur_state,
2726                          new_state, ibqp->qp_type);
2727                 goto out;
2728         }
2729
2730         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2731             attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
2732                 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
2733                          "Transition %d to %d. qp_type %d\n",
2734                          ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
2735                          new_state, ibqp->qp_type);
2736                 goto out;
2737         }
2738
2739         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2740                 err = 0;
2741                 goto out;
2742         }
2743
2744         if (ibqp->rwq_ind_tbl && (new_state == IB_QPS_INIT)) {
2745                 err = bringup_rss_rwqs(ibqp->rwq_ind_tbl, attr->port_num);
2746                 if (err)
2747                         goto out;
2748         }
2749
2750         err = __mlx4_ib_modify_qp(ibqp, MLX4_IB_QP_SRC, attr, attr_mask,
2751                                   cur_state, new_state);
2752
2753         if (ibqp->rwq_ind_tbl && err)
2754                 bring_down_rss_rwqs(ibqp->rwq_ind_tbl);
2755
2756         if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
2757                 attr->port_num = 1;
2758
2759 out:
2760         mutex_unlock(&qp->mutex);
2761         return err;
2762 }
2763
2764 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2765                       int attr_mask, struct ib_udata *udata)
2766 {
2767         struct mlx4_ib_qp *mqp = to_mqp(ibqp);
2768         int ret;
2769
2770         ret = _mlx4_ib_modify_qp(ibqp, attr, attr_mask, udata);
2771
2772         if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
2773                 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
2774                 int err = 0;
2775
2776                 if (sqp->roce_v2_gsi)
2777                         err = ib_modify_qp(sqp->roce_v2_gsi, attr, attr_mask);
2778                 if (err)
2779                         pr_err("Failed to modify GSI QP for RoCEv2 (%d)\n",
2780                                err);
2781         }
2782         return ret;
2783 }
2784
2785 static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
2786 {
2787         int i;
2788         for (i = 0; i < dev->caps.num_ports; i++) {
2789                 if (qpn == dev->caps.spec_qps[i].qp0_proxy ||
2790                     qpn == dev->caps.spec_qps[i].qp0_tunnel) {
2791                         *qkey = dev->caps.spec_qps[i].qp0_qkey;
2792                         return 0;
2793                 }
2794         }
2795         return -EINVAL;
2796 }
2797
2798 static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
2799                                   const struct ib_ud_wr *wr,
2800                                   void *wqe, unsigned *mlx_seg_len)
2801 {
2802         struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
2803         struct ib_device *ib_dev = &mdev->ib_dev;
2804         struct mlx4_wqe_mlx_seg *mlx = wqe;
2805         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2806         struct mlx4_ib_ah *ah = to_mah(wr->ah);
2807         u16 pkey;
2808         u32 qkey;
2809         int send_size;
2810         int header_size;
2811         int spc;
2812         int err;
2813         int i;
2814
2815         if (wr->wr.opcode != IB_WR_SEND)
2816                 return -EINVAL;
2817
2818         send_size = 0;
2819
2820         for (i = 0; i < wr->wr.num_sge; ++i)
2821                 send_size += wr->wr.sg_list[i].length;
2822
2823         /* for proxy-qp0 sends, need to add in size of tunnel header */
2824         /* for tunnel-qp0 sends, tunnel header is already in s/g list */
2825         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
2826                 send_size += sizeof (struct mlx4_ib_tunnel_header);
2827
2828         ib_ud_header_init(send_size, 1, 0, 0, 0, 0, 0, 0, &sqp->ud_header);
2829
2830         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2831                 sqp->ud_header.lrh.service_level =
2832                         be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2833                 sqp->ud_header.lrh.destination_lid =
2834                         cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2835                 sqp->ud_header.lrh.source_lid =
2836                         cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2837         }
2838
2839         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2840
2841         /* force loopback */
2842         mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2843         mlx->rlid = sqp->ud_header.lrh.destination_lid;
2844
2845         sqp->ud_header.lrh.virtual_lane    = 0;
2846         sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
2847         err = ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
2848         if (err)
2849                 return err;
2850         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2851         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
2852                 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
2853         else
2854                 sqp->ud_header.bth.destination_qpn =
2855                         cpu_to_be32(mdev->dev->caps.spec_qps[sqp->qp.port - 1].qp0_tunnel);
2856
2857         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2858         if (mlx4_is_master(mdev->dev)) {
2859                 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2860                         return -EINVAL;
2861         } else {
2862                 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2863                         return -EINVAL;
2864         }
2865         sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2866         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2867
2868         sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
2869         sqp->ud_header.immediate_present = 0;
2870
2871         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2872
2873         /*
2874          * Inline data segments may not cross a 64 byte boundary.  If
2875          * our UD header is bigger than the space available up to the
2876          * next 64 byte boundary in the WQE, use two inline data
2877          * segments to hold the UD header.
2878          */
2879         spc = MLX4_INLINE_ALIGN -
2880               ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2881         if (header_size <= spc) {
2882                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2883                 memcpy(inl + 1, sqp->header_buf, header_size);
2884                 i = 1;
2885         } else {
2886                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2887                 memcpy(inl + 1, sqp->header_buf, spc);
2888
2889                 inl = (void *) (inl + 1) + spc;
2890                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2891                 /*
2892                  * Need a barrier here to make sure all the data is
2893                  * visible before the byte_count field is set.
2894                  * Otherwise the HCA prefetcher could grab the 64-byte
2895                  * chunk with this inline segment and get a valid (!=
2896                  * 0xffffffff) byte count but stale data, and end up
2897                  * generating a packet with bad headers.
2898                  *
2899                  * The first inline segment's byte_count field doesn't
2900                  * need a barrier, because it comes after a
2901                  * control/MLX segment and therefore is at an offset
2902                  * of 16 mod 64.
2903                  */
2904                 wmb();
2905                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2906                 i = 2;
2907         }
2908
2909         *mlx_seg_len =
2910         ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2911         return 0;
2912 }
2913
2914 static u8 sl_to_vl(struct mlx4_ib_dev *dev, u8 sl, int port_num)
2915 {
2916         union sl2vl_tbl_to_u64 tmp_vltab;
2917         u8 vl;
2918
2919         if (sl > 15)
2920                 return 0xf;
2921         tmp_vltab.sl64 = atomic64_read(&dev->sl2vl[port_num - 1]);
2922         vl = tmp_vltab.sl8[sl >> 1];
2923         if (sl & 1)
2924                 vl &= 0x0f;
2925         else
2926                 vl >>= 4;
2927         return vl;
2928 }
2929
2930 static int fill_gid_by_hw_index(struct mlx4_ib_dev *ibdev, u8 port_num,
2931                                 int index, union ib_gid *gid,
2932                                 enum ib_gid_type *gid_type)
2933 {
2934         struct mlx4_ib_iboe *iboe = &ibdev->iboe;
2935         struct mlx4_port_gid_table *port_gid_table;
2936         unsigned long flags;
2937
2938         port_gid_table = &iboe->gids[port_num - 1];
2939         spin_lock_irqsave(&iboe->lock, flags);
2940         memcpy(gid, &port_gid_table->gids[index].gid, sizeof(*gid));
2941         *gid_type = port_gid_table->gids[index].gid_type;
2942         spin_unlock_irqrestore(&iboe->lock, flags);
2943         if (rdma_is_zero_gid(gid))
2944                 return -ENOENT;
2945
2946         return 0;
2947 }
2948
2949 #define MLX4_ROCEV2_QP1_SPORT 0xC000
2950 static int build_mlx_header(struct mlx4_ib_sqp *sqp, const struct ib_ud_wr *wr,
2951                             void *wqe, unsigned *mlx_seg_len)
2952 {
2953         struct ib_device *ib_dev = sqp->qp.ibqp.device;
2954         struct mlx4_ib_dev *ibdev = to_mdev(ib_dev);
2955         struct mlx4_wqe_mlx_seg *mlx = wqe;
2956         struct mlx4_wqe_ctrl_seg *ctrl = wqe;
2957         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2958         struct mlx4_ib_ah *ah = to_mah(wr->ah);
2959         union ib_gid sgid;
2960         u16 pkey;
2961         int send_size;
2962         int header_size;
2963         int spc;
2964         int i;
2965         int err = 0;
2966         u16 vlan = 0xffff;
2967         bool is_eth;
2968         bool is_vlan = false;
2969         bool is_grh;
2970         bool is_udp = false;
2971         int ip_version = 0;
2972
2973         send_size = 0;
2974         for (i = 0; i < wr->wr.num_sge; ++i)
2975                 send_size += wr->wr.sg_list[i].length;
2976
2977         is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
2978         is_grh = mlx4_ib_ah_grh_present(ah);
2979         if (is_eth) {
2980                 enum ib_gid_type gid_type;
2981                 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2982                         /* When multi-function is enabled, the ib_core gid
2983                          * indexes don't necessarily match the hw ones, so
2984                          * we must use our own cache */
2985                         err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
2986                                                            be32_to_cpu(ah->av.ib.port_pd) >> 24,
2987                                                            ah->av.ib.gid_index, &sgid.raw[0]);
2988                         if (err)
2989                                 return err;
2990                 } else  {
2991                         err = fill_gid_by_hw_index(ibdev, sqp->qp.port,
2992                                             ah->av.ib.gid_index,
2993                                             &sgid, &gid_type);
2994                         if (!err) {
2995                                 is_udp = gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
2996                                 if (is_udp) {
2997                                         if (ipv6_addr_v4mapped((struct in6_addr *)&sgid))
2998                                                 ip_version = 4;
2999                                         else
3000                                                 ip_version = 6;
3001                                         is_grh = false;
3002                                 }
3003                         } else {
3004                                 return err;
3005                         }
3006                 }
3007                 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
3008                         vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
3009                         is_vlan = 1;
3010                 }
3011         }
3012         err = ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh,
3013                           ip_version, is_udp, 0, &sqp->ud_header);
3014         if (err)
3015                 return err;
3016
3017         if (!is_eth) {
3018                 sqp->ud_header.lrh.service_level =
3019                         be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
3020                 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
3021                 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
3022         }
3023
3024         if (is_grh || (ip_version == 6)) {
3025                 sqp->ud_header.grh.traffic_class =
3026                         (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
3027                 sqp->ud_header.grh.flow_label    =
3028                         ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
3029                 sqp->ud_header.grh.hop_limit     = ah->av.ib.hop_limit;
3030                 if (is_eth) {
3031                         memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
3032                 } else {
3033                         if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
3034                                 /* When multi-function is enabled, the ib_core gid
3035                                  * indexes don't necessarily match the hw ones, so
3036                                  * we must use our own cache
3037                                  */
3038                                 sqp->ud_header.grh.source_gid.global.subnet_prefix =
3039                                         cpu_to_be64(atomic64_read(&(to_mdev(ib_dev)->sriov.
3040                                                                     demux[sqp->qp.port - 1].
3041                                                                     subnet_prefix)));
3042                                 sqp->ud_header.grh.source_gid.global.interface_id =
3043                                         to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
3044                                                        guid_cache[ah->av.ib.gid_index];
3045                         } else {
3046                                 sqp->ud_header.grh.source_gid =
3047                                         ah->ibah.sgid_attr->gid;
3048                         }
3049                 }
3050                 memcpy(sqp->ud_header.grh.destination_gid.raw,
3051                        ah->av.ib.dgid, 16);
3052         }
3053
3054         if (ip_version == 4) {
3055                 sqp->ud_header.ip4.tos =
3056                         (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
3057                 sqp->ud_header.ip4.id = 0;
3058                 sqp->ud_header.ip4.frag_off = htons(IP_DF);
3059                 sqp->ud_header.ip4.ttl = ah->av.eth.hop_limit;
3060
3061                 memcpy(&sqp->ud_header.ip4.saddr,
3062                        sgid.raw + 12, 4);
3063                 memcpy(&sqp->ud_header.ip4.daddr, ah->av.ib.dgid + 12, 4);
3064                 sqp->ud_header.ip4.check = ib_ud_ip4_csum(&sqp->ud_header);
3065         }
3066
3067         if (is_udp) {
3068                 sqp->ud_header.udp.dport = htons(ROCE_V2_UDP_DPORT);
3069                 sqp->ud_header.udp.sport = htons(MLX4_ROCEV2_QP1_SPORT);
3070                 sqp->ud_header.udp.csum = 0;
3071         }
3072
3073         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
3074
3075         if (!is_eth) {
3076                 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
3077                                           (sqp->ud_header.lrh.destination_lid ==
3078                                            IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
3079                                           (sqp->ud_header.lrh.service_level << 8));
3080                 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
3081                         mlx->flags |= cpu_to_be32(0x1); /* force loopback */
3082                 mlx->rlid = sqp->ud_header.lrh.destination_lid;
3083         }
3084
3085         switch (wr->wr.opcode) {
3086         case IB_WR_SEND:
3087                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
3088                 sqp->ud_header.immediate_present = 0;
3089                 break;
3090         case IB_WR_SEND_WITH_IMM:
3091                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
3092                 sqp->ud_header.immediate_present = 1;
3093                 sqp->ud_header.immediate_data    = wr->wr.ex.imm_data;
3094                 break;
3095         default:
3096                 return -EINVAL;
3097         }
3098
3099         if (is_eth) {
3100                 struct in6_addr in6;
3101                 u16 ether_type;
3102                 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
3103
3104                 ether_type = (!is_udp) ? ETH_P_IBOE:
3105                         (ip_version == 4 ? ETH_P_IP : ETH_P_IPV6);
3106
3107                 mlx->sched_prio = cpu_to_be16(pcp);
3108
3109                 ether_addr_copy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac);
3110                 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
3111                 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
3112                 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
3113                 memcpy(&in6, sgid.raw, sizeof(in6));
3114
3115
3116                 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
3117                         mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
3118                 if (!is_vlan) {
3119                         sqp->ud_header.eth.type = cpu_to_be16(ether_type);
3120                 } else {
3121                         sqp->ud_header.vlan.type = cpu_to_be16(ether_type);
3122                         sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
3123                 }
3124         } else {
3125                 sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 :
3126                                                         sl_to_vl(to_mdev(ib_dev),
3127                                                                  sqp->ud_header.lrh.service_level,
3128                                                                  sqp->qp.port);
3129                 if (sqp->qp.ibqp.qp_num && sqp->ud_header.lrh.virtual_lane == 15)
3130                         return -EINVAL;
3131                 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
3132                         sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
3133         }
3134         sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
3135         if (!sqp->qp.ibqp.qp_num)
3136                 err = ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index,
3137                                          &pkey);
3138         else
3139                 err = ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->pkey_index,
3140                                          &pkey);
3141         if (err)
3142                 return err;
3143
3144         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
3145         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
3146         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
3147         sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ?
3148                                                sqp->qkey : wr->remote_qkey);
3149         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
3150
3151         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
3152
3153         if (0) {
3154                 pr_err("built UD header of size %d:\n", header_size);
3155                 for (i = 0; i < header_size / 4; ++i) {
3156                         if (i % 8 == 0)
3157                                 pr_err("  [%02x] ", i * 4);
3158                         pr_cont(" %08x",
3159                                 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
3160                         if ((i + 1) % 8 == 0)
3161                                 pr_cont("\n");
3162                 }
3163                 pr_err("\n");
3164         }
3165
3166         /*
3167          * Inline data segments may not cross a 64 byte boundary.  If
3168          * our UD header is bigger than the space available up to the
3169          * next 64 byte boundary in the WQE, use two inline data
3170          * segments to hold the UD header.
3171          */
3172         spc = MLX4_INLINE_ALIGN -
3173                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
3174         if (header_size <= spc) {
3175                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
3176                 memcpy(inl + 1, sqp->header_buf, header_size);
3177                 i = 1;
3178         } else {
3179                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
3180                 memcpy(inl + 1, sqp->header_buf, spc);
3181
3182                 inl = (void *) (inl + 1) + spc;
3183                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
3184                 /*
3185                  * Need a barrier here to make sure all the data is
3186                  * visible before the byte_count field is set.
3187                  * Otherwise the HCA prefetcher could grab the 64-byte
3188                  * chunk with this inline segment and get a valid (!=
3189                  * 0xffffffff) byte count but stale data, and end up
3190                  * generating a packet with bad headers.
3191                  *
3192                  * The first inline segment's byte_count field doesn't
3193                  * need a barrier, because it comes after a
3194                  * control/MLX segment and therefore is at an offset
3195                  * of 16 mod 64.
3196                  */
3197                 wmb();
3198                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
3199                 i = 2;
3200         }
3201
3202         *mlx_seg_len =
3203                 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
3204         return 0;
3205 }
3206
3207 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3208 {
3209         unsigned cur;
3210         struct mlx4_ib_cq *cq;
3211
3212         cur = wq->head - wq->tail;
3213         if (likely(cur + nreq < wq->max_post))
3214                 return 0;
3215
3216         cq = to_mcq(ib_cq);
3217         spin_lock(&cq->lock);
3218         cur = wq->head - wq->tail;
3219         spin_unlock(&cq->lock);
3220
3221         return cur + nreq >= wq->max_post;
3222 }
3223
3224 static __be32 convert_access(int acc)
3225 {
3226         return (acc & IB_ACCESS_REMOTE_ATOMIC ?
3227                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC)       : 0) |
3228                (acc & IB_ACCESS_REMOTE_WRITE  ?
3229                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
3230                (acc & IB_ACCESS_REMOTE_READ   ?
3231                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ)  : 0) |
3232                (acc & IB_ACCESS_LOCAL_WRITE   ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE)  : 0) |
3233                 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
3234 }
3235
3236 static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg,
3237                         const struct ib_reg_wr *wr)
3238 {
3239         struct mlx4_ib_mr *mr = to_mmr(wr->mr);
3240
3241         fseg->flags             = convert_access(wr->access);
3242         fseg->mem_key           = cpu_to_be32(wr->key);
3243         fseg->buf_list          = cpu_to_be64(mr->page_map);
3244         fseg->start_addr        = cpu_to_be64(mr->ibmr.iova);
3245         fseg->reg_len           = cpu_to_be64(mr->ibmr.length);
3246         fseg->offset            = 0; /* XXX -- is this just for ZBVA? */
3247         fseg->page_size         = cpu_to_be32(ilog2(mr->ibmr.page_size));
3248         fseg->reserved[0]       = 0;
3249         fseg->reserved[1]       = 0;
3250 }
3251
3252 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
3253 {
3254         memset(iseg, 0, sizeof(*iseg));
3255         iseg->mem_key = cpu_to_be32(rkey);
3256 }
3257
3258 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
3259                                           u64 remote_addr, u32 rkey)
3260 {
3261         rseg->raddr    = cpu_to_be64(remote_addr);
3262         rseg->rkey     = cpu_to_be32(rkey);
3263         rseg->reserved = 0;
3264 }
3265
3266 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg,
3267                            const struct ib_atomic_wr *wr)
3268 {
3269         if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
3270                 aseg->swap_add = cpu_to_be64(wr->swap);
3271                 aseg->compare  = cpu_to_be64(wr->compare_add);
3272         } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
3273                 aseg->swap_add = cpu_to_be64(wr->compare_add);
3274                 aseg->compare  = cpu_to_be64(wr->compare_add_mask);
3275         } else {
3276                 aseg->swap_add = cpu_to_be64(wr->compare_add);
3277                 aseg->compare  = 0;
3278         }
3279
3280 }
3281
3282 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
3283                                   const struct ib_atomic_wr *wr)
3284 {
3285         aseg->swap_add          = cpu_to_be64(wr->swap);
3286         aseg->swap_add_mask     = cpu_to_be64(wr->swap_mask);
3287         aseg->compare           = cpu_to_be64(wr->compare_add);
3288         aseg->compare_mask      = cpu_to_be64(wr->compare_add_mask);
3289 }
3290
3291 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
3292                              const struct ib_ud_wr *wr)
3293 {
3294         memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av));
3295         dseg->dqpn = cpu_to_be32(wr->remote_qpn);
3296         dseg->qkey = cpu_to_be32(wr->remote_qkey);
3297         dseg->vlan = to_mah(wr->ah)->av.eth.vlan;
3298         memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6);
3299 }
3300
3301 static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
3302                                     struct mlx4_wqe_datagram_seg *dseg,
3303                                     const struct ib_ud_wr *wr,
3304                                     enum mlx4_ib_qp_type qpt)
3305 {
3306         union mlx4_ext_av *av = &to_mah(wr->ah)->av;
3307         struct mlx4_av sqp_av = {0};
3308         int port = *((u8 *) &av->ib.port_pd) & 0x3;
3309
3310         /* force loopback */
3311         sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
3312         sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
3313         sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
3314                         cpu_to_be32(0xf0000000);
3315
3316         memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
3317         if (qpt == MLX4_IB_QPT_PROXY_GSI)
3318                 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp1_tunnel);
3319         else
3320                 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp0_tunnel);
3321         /* Use QKEY from the QP context, which is set by master */
3322         dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
3323 }
3324
3325 static void build_tunnel_header(const struct ib_ud_wr *wr, void *wqe,
3326                                 unsigned *mlx_seg_len)
3327 {
3328         struct mlx4_wqe_inline_seg *inl = wqe;
3329         struct mlx4_ib_tunnel_header hdr;
3330         struct mlx4_ib_ah *ah = to_mah(wr->ah);
3331         int spc;
3332         int i;
3333
3334         memcpy(&hdr.av, &ah->av, sizeof hdr.av);
3335         hdr.remote_qpn = cpu_to_be32(wr->remote_qpn);
3336         hdr.pkey_index = cpu_to_be16(wr->pkey_index);
3337         hdr.qkey = cpu_to_be32(wr->remote_qkey);
3338         memcpy(hdr.mac, ah->av.eth.mac, 6);
3339         hdr.vlan = ah->av.eth.vlan;
3340
3341         spc = MLX4_INLINE_ALIGN -
3342                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
3343         if (sizeof (hdr) <= spc) {
3344                 memcpy(inl + 1, &hdr, sizeof (hdr));
3345                 wmb();
3346                 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
3347                 i = 1;
3348         } else {
3349                 memcpy(inl + 1, &hdr, spc);
3350                 wmb();
3351                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
3352
3353                 inl = (void *) (inl + 1) + spc;
3354                 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
3355                 wmb();
3356                 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
3357                 i = 2;
3358         }
3359
3360         *mlx_seg_len =
3361                 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
3362 }
3363
3364 static void set_mlx_icrc_seg(void *dseg)
3365 {
3366         u32 *t = dseg;
3367         struct mlx4_wqe_inline_seg *iseg = dseg;
3368
3369         t[1] = 0;
3370
3371         /*
3372          * Need a barrier here before writing the byte_count field to
3373          * make sure that all the data is visible before the
3374          * byte_count field is set.  Otherwise, if the segment begins
3375          * a new cacheline, the HCA prefetcher could grab the 64-byte
3376          * chunk and get a valid (!= * 0xffffffff) byte count but
3377          * stale data, and end up sending the wrong data.
3378          */
3379         wmb();
3380
3381         iseg->byte_count = cpu_to_be32((1 << 31) | 4);
3382 }
3383
3384 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
3385 {
3386         dseg->lkey       = cpu_to_be32(sg->lkey);
3387         dseg->addr       = cpu_to_be64(sg->addr);
3388
3389         /*
3390          * Need a barrier here before writing the byte_count field to
3391          * make sure that all the data is visible before the
3392          * byte_count field is set.  Otherwise, if the segment begins
3393          * a new cacheline, the HCA prefetcher could grab the 64-byte
3394          * chunk and get a valid (!= * 0xffffffff) byte count but
3395          * stale data, and end up sending the wrong data.
3396          */
3397         wmb();
3398
3399         dseg->byte_count = cpu_to_be32(sg->length);
3400 }
3401
3402 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
3403 {
3404         dseg->byte_count = cpu_to_be32(sg->length);
3405         dseg->lkey       = cpu_to_be32(sg->lkey);
3406         dseg->addr       = cpu_to_be64(sg->addr);
3407 }
3408
3409 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe,
3410                          const struct ib_ud_wr *wr, struct mlx4_ib_qp *qp,
3411                          unsigned *lso_seg_len, __be32 *lso_hdr_sz, __be32 *blh)
3412 {
3413         unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16);
3414
3415         if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
3416                 *blh = cpu_to_be32(1 << 6);
3417
3418         if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
3419                      wr->wr.num_sge > qp->sq.max_gs - (halign >> 4)))
3420                 return -EINVAL;
3421
3422         memcpy(wqe->header, wr->header, wr->hlen);
3423
3424         *lso_hdr_sz  = cpu_to_be32(wr->mss << 16 | wr->hlen);
3425         *lso_seg_len = halign;
3426         return 0;
3427 }
3428
3429 static __be32 send_ieth(const struct ib_send_wr *wr)
3430 {
3431         switch (wr->opcode) {
3432         case IB_WR_SEND_WITH_IMM:
3433         case IB_WR_RDMA_WRITE_WITH_IMM:
3434                 return wr->ex.imm_data;
3435
3436         case IB_WR_SEND_WITH_INV:
3437                 return cpu_to_be32(wr->ex.invalidate_rkey);
3438
3439         default:
3440                 return 0;
3441         }
3442 }
3443
3444 static void add_zero_len_inline(void *wqe)
3445 {
3446         struct mlx4_wqe_inline_seg *inl = wqe;
3447         memset(wqe, 0, 16);
3448         inl->byte_count = cpu_to_be32(1 << 31);
3449 }
3450
3451 static int _mlx4_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
3452                               const struct ib_send_wr **bad_wr, bool drain)
3453 {
3454         struct mlx4_ib_qp *qp = to_mqp(ibqp);
3455         void *wqe;
3456         struct mlx4_wqe_ctrl_seg *ctrl;
3457         struct mlx4_wqe_data_seg *dseg;
3458         unsigned long flags;
3459         int nreq;
3460         int err = 0;
3461         unsigned ind;
3462         int uninitialized_var(size);
3463         unsigned uninitialized_var(seglen);
3464         __be32 dummy;
3465         __be32 *lso_wqe;
3466         __be32 uninitialized_var(lso_hdr_sz);
3467         __be32 blh;
3468         int i;
3469         struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
3470
3471         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
3472                 struct mlx4_ib_sqp *sqp = to_msqp(qp);
3473
3474                 if (sqp->roce_v2_gsi) {
3475                         struct mlx4_ib_ah *ah = to_mah(ud_wr(wr)->ah);
3476                         enum ib_gid_type gid_type;
3477                         union ib_gid gid;
3478
3479                         if (!fill_gid_by_hw_index(mdev, sqp->qp.port,
3480                                            ah->av.ib.gid_index,
3481                                            &gid, &gid_type))
3482                                 qp = (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) ?
3483                                                 to_mqp(sqp->roce_v2_gsi) : qp;
3484                         else
3485                                 pr_err("Failed to get gid at index %d. RoCEv2 will not work properly\n",
3486                                        ah->av.ib.gid_index);
3487                 }
3488         }
3489
3490         spin_lock_irqsave(&qp->sq.lock, flags);
3491         if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR &&
3492             !drain) {
3493                 err = -EIO;
3494                 *bad_wr = wr;
3495                 nreq = 0;
3496                 goto out;
3497         }
3498
3499         ind = qp->sq_next_wqe;
3500
3501         for (nreq = 0; wr; ++nreq, wr = wr->next) {
3502                 lso_wqe = &dummy;
3503                 blh = 0;
3504
3505                 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
3506                         err = -ENOMEM;
3507                         *bad_wr = wr;
3508                         goto out;
3509                 }
3510
3511                 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
3512                         err = -EINVAL;
3513                         *bad_wr = wr;
3514                         goto out;
3515                 }
3516
3517                 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
3518                 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
3519
3520                 ctrl->srcrb_flags =
3521                         (wr->send_flags & IB_SEND_SIGNALED ?
3522                          cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
3523                         (wr->send_flags & IB_SEND_SOLICITED ?
3524                          cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
3525                         ((wr->send_flags & IB_SEND_IP_CSUM) ?
3526                          cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
3527                                      MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
3528                         qp->sq_signal_bits;
3529
3530                 ctrl->imm = send_ieth(wr);
3531
3532                 wqe += sizeof *ctrl;
3533                 size = sizeof *ctrl / 16;
3534
3535                 switch (qp->mlx4_ib_qp_type) {
3536                 case MLX4_IB_QPT_RC:
3537                 case MLX4_IB_QPT_UC:
3538                         switch (wr->opcode) {
3539                         case IB_WR_ATOMIC_CMP_AND_SWP:
3540                         case IB_WR_ATOMIC_FETCH_AND_ADD:
3541                         case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
3542                                 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3543                                               atomic_wr(wr)->rkey);
3544                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
3545
3546                                 set_atomic_seg(wqe, atomic_wr(wr));
3547                                 wqe  += sizeof (struct mlx4_wqe_atomic_seg);
3548
3549                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3550                                          sizeof (struct mlx4_wqe_atomic_seg)) / 16;
3551
3552                                 break;
3553
3554                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
3555                                 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3556                                               atomic_wr(wr)->rkey);
3557                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
3558
3559                                 set_masked_atomic_seg(wqe, atomic_wr(wr));
3560                                 wqe  += sizeof (struct mlx4_wqe_masked_atomic_seg);
3561
3562                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3563                                          sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
3564
3565                                 break;
3566
3567                         case IB_WR_RDMA_READ:
3568                         case IB_WR_RDMA_WRITE:
3569                         case IB_WR_RDMA_WRITE_WITH_IMM:
3570                                 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
3571                                               rdma_wr(wr)->rkey);
3572                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
3573                                 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
3574                                 break;
3575
3576                         case IB_WR_LOCAL_INV:
3577                                 ctrl->srcrb_flags |=
3578                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
3579                                 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
3580                                 wqe  += sizeof (struct mlx4_wqe_local_inval_seg);
3581                                 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
3582                                 break;
3583
3584                         case IB_WR_REG_MR:
3585                                 ctrl->srcrb_flags |=
3586                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
3587                                 set_reg_seg(wqe, reg_wr(wr));
3588                                 wqe  += sizeof(struct mlx4_wqe_fmr_seg);
3589                                 size += sizeof(struct mlx4_wqe_fmr_seg) / 16;
3590                                 break;
3591
3592                         default:
3593                                 /* No extra segments required for sends */
3594                                 break;
3595                         }
3596                         break;
3597
3598                 case MLX4_IB_QPT_TUN_SMI_OWNER:
3599                         err =  build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3600                                         ctrl, &seglen);
3601                         if (unlikely(err)) {
3602                                 *bad_wr = wr;
3603                                 goto out;
3604                         }
3605                         wqe  += seglen;
3606                         size += seglen / 16;
3607                         break;
3608                 case MLX4_IB_QPT_TUN_SMI:
3609                 case MLX4_IB_QPT_TUN_GSI:
3610                         /* this is a UD qp used in MAD responses to slaves. */
3611                         set_datagram_seg(wqe, ud_wr(wr));
3612                         /* set the forced-loopback bit in the data seg av */
3613                         *(__be32 *) wqe |= cpu_to_be32(0x80000000);
3614                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
3615                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3616                         break;
3617                 case MLX4_IB_QPT_UD:
3618                         set_datagram_seg(wqe, ud_wr(wr));
3619                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
3620                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3621
3622                         if (wr->opcode == IB_WR_LSO) {
3623                                 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen,
3624                                                 &lso_hdr_sz, &blh);
3625                                 if (unlikely(err)) {
3626                                         *bad_wr = wr;
3627                                         goto out;
3628                                 }
3629                                 lso_wqe = (__be32 *) wqe;
3630                                 wqe  += seglen;
3631                                 size += seglen / 16;
3632                         }
3633                         break;
3634
3635                 case MLX4_IB_QPT_PROXY_SMI_OWNER:
3636                         err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3637                                         ctrl, &seglen);
3638                         if (unlikely(err)) {
3639                                 *bad_wr = wr;
3640                                 goto out;
3641                         }
3642                         wqe  += seglen;
3643                         size += seglen / 16;
3644                         /* to start tunnel header on a cache-line boundary */
3645                         add_zero_len_inline(wqe);
3646                         wqe += 16;
3647                         size++;
3648                         build_tunnel_header(ud_wr(wr), wqe, &seglen);
3649                         wqe  += seglen;
3650                         size += seglen / 16;
3651                         break;
3652                 case MLX4_IB_QPT_PROXY_SMI:
3653                 case MLX4_IB_QPT_PROXY_GSI:
3654                         /* If we are tunneling special qps, this is a UD qp.
3655                          * In this case we first add a UD segment targeting
3656                          * the tunnel qp, and then add a header with address
3657                          * information */
3658                         set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe,
3659                                                 ud_wr(wr),
3660                                                 qp->mlx4_ib_qp_type);
3661                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
3662                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3663                         build_tunnel_header(ud_wr(wr), wqe, &seglen);
3664                         wqe  += seglen;
3665                         size += seglen / 16;
3666                         break;
3667
3668                 case MLX4_IB_QPT_SMI:
3669                 case MLX4_IB_QPT_GSI:
3670                         err = build_mlx_header(to_msqp(qp), ud_wr(wr), ctrl,
3671                                         &seglen);
3672                         if (unlikely(err)) {
3673                                 *bad_wr = wr;
3674                                 goto out;
3675                         }
3676                         wqe  += seglen;
3677                         size += seglen / 16;
3678                         break;
3679
3680                 default:
3681                         break;
3682                 }
3683
3684                 /*
3685                  * Write data segments in reverse order, so as to
3686                  * overwrite cacheline stamp last within each
3687                  * cacheline.  This avoids issues with WQE
3688                  * prefetching.
3689                  */
3690
3691                 dseg = wqe;
3692                 dseg += wr->num_sge - 1;
3693                 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
3694
3695                 /* Add one more inline data segment for ICRC for MLX sends */
3696                 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
3697                              qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
3698                              qp->mlx4_ib_qp_type &
3699                              (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
3700                         set_mlx_icrc_seg(dseg + 1);
3701                         size += sizeof (struct mlx4_wqe_data_seg) / 16;
3702                 }
3703
3704                 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
3705                         set_data_seg(dseg, wr->sg_list + i);
3706
3707                 /*
3708                  * Possibly overwrite stamping in cacheline with LSO
3709                  * segment only after making sure all data segments
3710                  * are written.
3711                  */
3712                 wmb();
3713                 *lso_wqe = lso_hdr_sz;
3714
3715                 ctrl->qpn_vlan.fence_size = (wr->send_flags & IB_SEND_FENCE ?
3716                                              MLX4_WQE_CTRL_FENCE : 0) | size;
3717
3718                 /*
3719                  * Make sure descriptor is fully written before
3720                  * setting ownership bit (because HW can start
3721                  * executing as soon as we do).
3722                  */
3723                 wmb();
3724
3725                 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
3726                         *bad_wr = wr;
3727                         err = -EINVAL;
3728                         goto out;
3729                 }
3730
3731                 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
3732                         (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
3733
3734                 /*
3735                  * We can improve latency by not stamping the last
3736                  * send queue WQE until after ringing the doorbell, so
3737                  * only stamp here if there are still more WQEs to post.
3738                  */
3739                 if (wr->next)
3740                         stamp_send_wqe(qp, ind + qp->sq_spare_wqes);
3741                 ind++;
3742         }
3743
3744 out:
3745         if (likely(nreq)) {
3746                 qp->sq.head += nreq;
3747
3748                 /*
3749                  * Make sure that descriptors are written before
3750                  * doorbell record.
3751                  */
3752                 wmb();
3753
3754                 writel_relaxed(qp->doorbell_qpn,
3755                         to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
3756
3757                 /*
3758                  * Make sure doorbells don't leak out of SQ spinlock
3759                  * and reach the HCA out of order.
3760                  */
3761                 mmiowb();
3762
3763                 stamp_send_wqe(qp, ind + qp->sq_spare_wqes - 1);
3764
3765                 qp->sq_next_wqe = ind;
3766         }
3767
3768         spin_unlock_irqrestore(&qp->sq.lock, flags);
3769
3770         return err;
3771 }
3772
3773 int mlx4_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
3774                       const struct ib_send_wr **bad_wr)
3775 {
3776         return _mlx4_ib_post_send(ibqp, wr, bad_wr, false);
3777 }
3778
3779 static int _mlx4_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
3780                               const struct ib_recv_wr **bad_wr, bool drain)
3781 {
3782         struct mlx4_ib_qp *qp = to_mqp(ibqp);
3783         struct mlx4_wqe_data_seg *scat;
3784         unsigned long flags;
3785         int err = 0;
3786         int nreq;
3787         int ind;
3788         int max_gs;
3789         int i;
3790         struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
3791
3792         max_gs = qp->rq.max_gs;
3793         spin_lock_irqsave(&qp->rq.lock, flags);
3794
3795         if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR &&
3796             !drain) {
3797                 err = -EIO;
3798                 *bad_wr = wr;
3799                 nreq = 0;
3800                 goto out;
3801         }
3802
3803         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
3804
3805         for (nreq = 0; wr; ++nreq, wr = wr->next) {
3806                 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
3807                         err = -ENOMEM;
3808                         *bad_wr = wr;
3809                         goto out;
3810                 }
3811
3812                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3813                         err = -EINVAL;
3814                         *bad_wr = wr;
3815                         goto out;
3816                 }
3817
3818                 scat = get_recv_wqe(qp, ind);
3819
3820                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
3821                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
3822                         ib_dma_sync_single_for_device(ibqp->device,
3823                                                       qp->sqp_proxy_rcv[ind].map,
3824                                                       sizeof (struct mlx4_ib_proxy_sqp_hdr),
3825                                                       DMA_FROM_DEVICE);
3826                         scat->byte_count =
3827                                 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
3828                         /* use dma lkey from upper layer entry */
3829                         scat->lkey = cpu_to_be32(wr->sg_list->lkey);
3830                         scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
3831                         scat++;
3832                         max_gs--;
3833                 }
3834
3835                 for (i = 0; i < wr->num_sge; ++i)
3836                         __set_data_seg(scat + i, wr->sg_list + i);
3837
3838                 if (i < max_gs) {
3839                         scat[i].byte_count = 0;
3840                         scat[i].lkey       = cpu_to_be32(MLX4_INVALID_LKEY);
3841                         scat[i].addr       = 0;
3842                 }
3843
3844                 qp->rq.wrid[ind] = wr->wr_id;
3845
3846                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
3847         }
3848
3849 out:
3850         if (likely(nreq)) {
3851                 qp->rq.head += nreq;
3852
3853                 /*
3854                  * Make sure that descriptors are written before
3855                  * doorbell record.
3856                  */
3857                 wmb();
3858
3859                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3860         }
3861
3862         spin_unlock_irqrestore(&qp->rq.lock, flags);
3863
3864         return err;
3865 }
3866
3867 int mlx4_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
3868                       const struct ib_recv_wr **bad_wr)
3869 {
3870         return _mlx4_ib_post_recv(ibqp, wr, bad_wr, false);
3871 }
3872
3873 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
3874 {
3875         switch (mlx4_state) {
3876         case MLX4_QP_STATE_RST:      return IB_QPS_RESET;
3877         case MLX4_QP_STATE_INIT:     return IB_QPS_INIT;
3878         case MLX4_QP_STATE_RTR:      return IB_QPS_RTR;
3879         case MLX4_QP_STATE_RTS:      return IB_QPS_RTS;
3880         case MLX4_QP_STATE_SQ_DRAINING:
3881         case MLX4_QP_STATE_SQD:      return IB_QPS_SQD;
3882         case MLX4_QP_STATE_SQER:     return IB_QPS_SQE;
3883         case MLX4_QP_STATE_ERR:      return IB_QPS_ERR;
3884         default:                     return -1;
3885         }
3886 }
3887
3888 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
3889 {
3890         switch (mlx4_mig_state) {
3891         case MLX4_QP_PM_ARMED:          return IB_MIG_ARMED;
3892         case MLX4_QP_PM_REARM:          return IB_MIG_REARM;
3893         case MLX4_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
3894         default: return -1;
3895         }
3896 }
3897
3898 static int to_ib_qp_access_flags(int mlx4_flags)
3899 {
3900         int ib_flags = 0;
3901
3902         if (mlx4_flags & MLX4_QP_BIT_RRE)
3903                 ib_flags |= IB_ACCESS_REMOTE_READ;
3904         if (mlx4_flags & MLX4_QP_BIT_RWE)
3905                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
3906         if (mlx4_flags & MLX4_QP_BIT_RAE)
3907                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3908
3909         return ib_flags;
3910 }
3911
3912 static void to_rdma_ah_attr(struct mlx4_ib_dev *ibdev,
3913                             struct rdma_ah_attr *ah_attr,
3914                             struct mlx4_qp_path *path)
3915 {
3916         struct mlx4_dev *dev = ibdev->dev;
3917         u8 port_num = path->sched_queue & 0x40 ? 2 : 1;
3918
3919         memset(ah_attr, 0, sizeof(*ah_attr));
3920         if (port_num == 0 || port_num > dev->caps.num_ports)
3921                 return;
3922         ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port_num);
3923
3924         if (ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE)
3925                 rdma_ah_set_sl(ah_attr, ((path->sched_queue >> 3) & 0x7) |
3926                                ((path->sched_queue & 4) << 1));
3927         else
3928                 rdma_ah_set_sl(ah_attr, (path->sched_queue >> 2) & 0xf);
3929         rdma_ah_set_port_num(ah_attr, port_num);
3930
3931         rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
3932         rdma_ah_set_path_bits(ah_attr, path->grh_mylmc & 0x7f);
3933         rdma_ah_set_static_rate(ah_attr,
3934                                 path->static_rate ? path->static_rate - 5 : 0);
3935         if (path->grh_mylmc & (1 << 7)) {
3936                 rdma_ah_set_grh(ah_attr, NULL,
3937                                 be32_to_cpu(path->tclass_flowlabel) & 0xfffff,
3938                                 path->mgid_index,
3939                                 path->hop_limit,
3940                                 (be32_to_cpu(path->tclass_flowlabel)
3941                                  >> 20) & 0xff);
3942                 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
3943         }
3944 }
3945
3946 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
3947                      struct ib_qp_init_attr *qp_init_attr)
3948 {
3949         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
3950         struct mlx4_ib_qp *qp = to_mqp(ibqp);
3951         struct mlx4_qp_context context;
3952         int mlx4_state;
3953         int err = 0;
3954
3955         if (ibqp->rwq_ind_tbl)
3956                 return -EOPNOTSUPP;
3957
3958         mutex_lock(&qp->mutex);
3959
3960         if (qp->state == IB_QPS_RESET) {
3961                 qp_attr->qp_state = IB_QPS_RESET;
3962                 goto done;
3963         }
3964
3965         err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
3966         if (err) {
3967                 err = -EINVAL;
3968                 goto out;
3969         }
3970
3971         mlx4_state = be32_to_cpu(context.flags) >> 28;
3972
3973         qp->state                    = to_ib_qp_state(mlx4_state);
3974         qp_attr->qp_state            = qp->state;
3975         qp_attr->path_mtu            = context.mtu_msgmax >> 5;
3976         qp_attr->path_mig_state      =
3977                 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
3978         qp_attr->qkey                = be32_to_cpu(context.qkey);
3979         qp_attr->rq_psn              = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
3980         qp_attr->sq_psn              = be32_to_cpu(context.next_send_psn) & 0xffffff;
3981         qp_attr->dest_qp_num         = be32_to_cpu(context.remote_qpn) & 0xffffff;
3982         qp_attr->qp_access_flags     =
3983                 to_ib_qp_access_flags(be32_to_cpu(context.params2));
3984
3985         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
3986                 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
3987                 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
3988                 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
3989                 qp_attr->alt_port_num   =
3990                         rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
3991         }
3992
3993         qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
3994         if (qp_attr->qp_state == IB_QPS_INIT)
3995                 qp_attr->port_num = qp->port;
3996         else
3997                 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
3998
3999         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4000         qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
4001
4002         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
4003
4004         qp_attr->max_dest_rd_atomic =
4005                 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
4006         qp_attr->min_rnr_timer      =
4007                 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
4008         qp_attr->timeout            = context.pri_path.ackto >> 3;
4009         qp_attr->retry_cnt          = (be32_to_cpu(context.params1) >> 16) & 0x7;
4010         qp_attr->rnr_retry          = (be32_to_cpu(context.params1) >> 13) & 0x7;
4011         qp_attr->alt_timeout        = context.alt_path.ackto >> 3;
4012
4013 done:
4014         qp_attr->cur_qp_state        = qp_attr->qp_state;
4015         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
4016         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
4017
4018         if (!ibqp->uobject) {
4019                 qp_attr->cap.max_send_wr  = qp->sq.wqe_cnt;
4020                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
4021         } else {
4022                 qp_attr->cap.max_send_wr  = 0;
4023                 qp_attr->cap.max_send_sge = 0;
4024         }
4025
4026         /*
4027          * We don't support inline sends for kernel QPs (yet), and we
4028          * don't know what userspace's value should be.
4029          */
4030         qp_attr->cap.max_inline_data = 0;
4031
4032         qp_init_attr->cap            = qp_attr->cap;
4033
4034         qp_init_attr->create_flags = 0;
4035         if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4036                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4037
4038         if (qp->flags & MLX4_IB_QP_LSO)
4039                 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
4040
4041         if (qp->flags & MLX4_IB_QP_NETIF)
4042                 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
4043
4044         qp_init_attr->sq_sig_type =
4045                 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
4046                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4047
4048 out:
4049         mutex_unlock(&qp->mutex);
4050         return err;
4051 }
4052
4053 struct ib_wq *mlx4_ib_create_wq(struct ib_pd *pd,
4054                                 struct ib_wq_init_attr *init_attr,
4055                                 struct ib_udata *udata)
4056 {
4057         struct mlx4_ib_dev *dev;
4058         struct ib_qp_init_attr ib_qp_init_attr;
4059         struct mlx4_ib_qp *qp;
4060         struct mlx4_ib_create_wq ucmd;
4061         int err, required_cmd_sz;
4062
4063         if (!(udata && pd->uobject))
4064                 return ERR_PTR(-EINVAL);
4065
4066         required_cmd_sz = offsetof(typeof(ucmd), comp_mask) +
4067                           sizeof(ucmd.comp_mask);
4068         if (udata->inlen < required_cmd_sz) {
4069                 pr_debug("invalid inlen\n");
4070                 return ERR_PTR(-EINVAL);
4071         }
4072
4073         if (udata->inlen > sizeof(ucmd) &&
4074             !ib_is_udata_cleared(udata, sizeof(ucmd),
4075                                  udata->inlen - sizeof(ucmd))) {
4076                 pr_debug("inlen is not supported\n");
4077                 return ERR_PTR(-EOPNOTSUPP);
4078         }
4079
4080         if (udata->outlen)
4081                 return ERR_PTR(-EOPNOTSUPP);
4082
4083         dev = to_mdev(pd->device);
4084
4085         if (init_attr->wq_type != IB_WQT_RQ) {
4086                 pr_debug("unsupported wq type %d\n", init_attr->wq_type);
4087                 return ERR_PTR(-EOPNOTSUPP);
4088         }
4089
4090         if (init_attr->create_flags & ~IB_WQ_FLAGS_SCATTER_FCS) {
4091                 pr_debug("unsupported create_flags %u\n",
4092                          init_attr->create_flags);
4093                 return ERR_PTR(-EOPNOTSUPP);
4094         }
4095
4096         qp = kzalloc(sizeof(*qp), GFP_KERNEL);
4097         if (!qp)
4098                 return ERR_PTR(-ENOMEM);
4099
4100         qp->pri.vid = 0xFFFF;
4101         qp->alt.vid = 0xFFFF;
4102
4103         memset(&ib_qp_init_attr, 0, sizeof(ib_qp_init_attr));
4104         ib_qp_init_attr.qp_context = init_attr->wq_context;
4105         ib_qp_init_attr.qp_type = IB_QPT_RAW_PACKET;
4106         ib_qp_init_attr.cap.max_recv_wr = init_attr->max_wr;
4107         ib_qp_init_attr.cap.max_recv_sge = init_attr->max_sge;
4108         ib_qp_init_attr.recv_cq = init_attr->cq;
4109         ib_qp_init_attr.send_cq = ib_qp_init_attr.recv_cq; /* Dummy CQ */
4110
4111         if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS)
4112                 ib_qp_init_attr.create_flags |= IB_QP_CREATE_SCATTER_FCS;
4113
4114         err = create_qp_common(dev, pd, MLX4_IB_RWQ_SRC, &ib_qp_init_attr,
4115                                udata, 0, &qp);
4116         if (err) {
4117                 kfree(qp);
4118                 return ERR_PTR(err);
4119         }
4120
4121         qp->ibwq.event_handler = init_attr->event_handler;
4122         qp->ibwq.wq_num = qp->mqp.qpn;
4123         qp->ibwq.state = IB_WQS_RESET;
4124
4125         return &qp->ibwq;
4126 }
4127
4128 static int ib_wq2qp_state(enum ib_wq_state state)
4129 {
4130         switch (state) {
4131         case IB_WQS_RESET:
4132                 return IB_QPS_RESET;
4133         case IB_WQS_RDY:
4134                 return IB_QPS_RTR;
4135         default:
4136                 return IB_QPS_ERR;
4137         }
4138 }
4139
4140 static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state)
4141 {
4142         struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4143         enum ib_qp_state qp_cur_state;
4144         enum ib_qp_state qp_new_state;
4145         int attr_mask;
4146         int err;
4147
4148         /* ib_qp.state represents the WQ HW state while ib_wq.state represents
4149          * the WQ logic state.
4150          */
4151         qp_cur_state = qp->state;
4152         qp_new_state = ib_wq2qp_state(new_state);
4153
4154         if (ib_wq2qp_state(new_state) == qp_cur_state)
4155                 return 0;
4156
4157         if (new_state == IB_WQS_RDY) {
4158                 struct ib_qp_attr attr = {};
4159
4160                 attr.port_num = qp->port;
4161                 attr_mask = IB_QP_PORT;
4162
4163                 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, &attr,
4164                                           attr_mask, IB_QPS_RESET, IB_QPS_INIT);
4165                 if (err) {
4166                         pr_debug("WQN=0x%06x failed to apply RST->INIT on the HW QP\n",
4167                                  ibwq->wq_num);
4168                         return err;
4169                 }
4170
4171                 qp_cur_state = IB_QPS_INIT;
4172         }
4173
4174         attr_mask = 0;
4175         err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL, attr_mask,
4176                                   qp_cur_state,  qp_new_state);
4177
4178         if (err && (qp_cur_state == IB_QPS_INIT)) {
4179                 qp_new_state = IB_QPS_RESET;
4180                 if (__mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL,
4181                                         attr_mask, IB_QPS_INIT, IB_QPS_RESET)) {
4182                         pr_warn("WQN=0x%06x failed with reverting HW's resources failure\n",
4183                                 ibwq->wq_num);
4184                         qp_new_state = IB_QPS_INIT;
4185                 }
4186         }
4187
4188         qp->state = qp_new_state;
4189
4190         return err;
4191 }
4192
4193 int mlx4_ib_modify_wq(struct ib_wq *ibwq, struct ib_wq_attr *wq_attr,
4194                       u32 wq_attr_mask, struct ib_udata *udata)
4195 {
4196         struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4197         struct mlx4_ib_modify_wq ucmd = {};
4198         size_t required_cmd_sz;
4199         enum ib_wq_state cur_state, new_state;
4200         int err = 0;
4201
4202         required_cmd_sz = offsetof(typeof(ucmd), reserved) +
4203                                    sizeof(ucmd.reserved);
4204         if (udata->inlen < required_cmd_sz)
4205                 return -EINVAL;
4206
4207         if (udata->inlen > sizeof(ucmd) &&
4208             !ib_is_udata_cleared(udata, sizeof(ucmd),
4209                                  udata->inlen - sizeof(ucmd)))
4210                 return -EOPNOTSUPP;
4211
4212         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4213                 return -EFAULT;
4214
4215         if (ucmd.comp_mask || ucmd.reserved)
4216                 return -EOPNOTSUPP;
4217
4218         if (wq_attr_mask & IB_WQ_FLAGS)
4219                 return -EOPNOTSUPP;
4220
4221         cur_state = wq_attr_mask & IB_WQ_CUR_STATE ? wq_attr->curr_wq_state :
4222                                                      ibwq->state;
4223         new_state = wq_attr_mask & IB_WQ_STATE ? wq_attr->wq_state : cur_state;
4224
4225         if (cur_state  < IB_WQS_RESET || cur_state  > IB_WQS_ERR ||
4226             new_state < IB_WQS_RESET || new_state > IB_WQS_ERR)
4227                 return -EINVAL;
4228
4229         if ((new_state == IB_WQS_RDY) && (cur_state == IB_WQS_ERR))
4230                 return -EINVAL;
4231
4232         if ((new_state == IB_WQS_ERR) && (cur_state == IB_WQS_RESET))
4233                 return -EINVAL;
4234
4235         /* Need to protect against the parent RSS which also may modify WQ
4236          * state.
4237          */
4238         mutex_lock(&qp->mutex);
4239
4240         /* Can update HW state only if a RSS QP has already associated to this
4241          * WQ, so we can apply its port on the WQ.
4242          */
4243         if (qp->rss_usecnt)
4244                 err = _mlx4_ib_modify_wq(ibwq, new_state);
4245
4246         if (!err)
4247                 ibwq->state = new_state;
4248
4249         mutex_unlock(&qp->mutex);
4250
4251         return err;
4252 }
4253
4254 int mlx4_ib_destroy_wq(struct ib_wq *ibwq)
4255 {
4256         struct mlx4_ib_dev *dev = to_mdev(ibwq->device);
4257         struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4258
4259         if (qp->counter_index)
4260                 mlx4_ib_free_qp_counter(dev, qp);
4261
4262         destroy_qp_common(dev, qp, MLX4_IB_RWQ_SRC, 1);
4263
4264         kfree(qp);
4265
4266         return 0;
4267 }
4268
4269 struct ib_rwq_ind_table
4270 *mlx4_ib_create_rwq_ind_table(struct ib_device *device,
4271                               struct ib_rwq_ind_table_init_attr *init_attr,
4272                               struct ib_udata *udata)
4273 {
4274         struct ib_rwq_ind_table *rwq_ind_table;
4275         struct mlx4_ib_create_rwq_ind_tbl_resp resp = {};
4276         unsigned int ind_tbl_size = 1 << init_attr->log_ind_tbl_size;
4277         unsigned int base_wqn;
4278         size_t min_resp_len;
4279         int i;
4280         int err;
4281
4282         if (udata->inlen > 0 &&
4283             !ib_is_udata_cleared(udata, 0,
4284                                  udata->inlen))
4285                 return ERR_PTR(-EOPNOTSUPP);
4286
4287         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4288         if (udata->outlen && udata->outlen < min_resp_len)
4289                 return ERR_PTR(-EINVAL);
4290
4291         if (ind_tbl_size >
4292             device->attrs.rss_caps.max_rwq_indirection_table_size) {
4293                 pr_debug("log_ind_tbl_size = %d is bigger than supported = %d\n",
4294                          ind_tbl_size,
4295                          device->attrs.rss_caps.max_rwq_indirection_table_size);
4296                 return ERR_PTR(-EINVAL);
4297         }
4298
4299         base_wqn = init_attr->ind_tbl[0]->wq_num;
4300
4301         if (base_wqn % ind_tbl_size) {
4302                 pr_debug("WQN=0x%x isn't aligned with indirection table size\n",
4303                          base_wqn);
4304                 return ERR_PTR(-EINVAL);
4305         }
4306
4307         for (i = 1; i < ind_tbl_size; i++) {
4308                 if (++base_wqn != init_attr->ind_tbl[i]->wq_num) {
4309                         pr_debug("indirection table's WQNs aren't consecutive\n");
4310                         return ERR_PTR(-EINVAL);
4311                 }
4312         }
4313
4314         rwq_ind_table = kzalloc(sizeof(*rwq_ind_table), GFP_KERNEL);
4315         if (!rwq_ind_table)
4316                 return ERR_PTR(-ENOMEM);
4317
4318         if (udata->outlen) {
4319                 resp.response_length = offsetof(typeof(resp), response_length) +
4320                                         sizeof(resp.response_length);
4321                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4322                 if (err)
4323                         goto err;
4324         }
4325
4326         return rwq_ind_table;
4327
4328 err:
4329         kfree(rwq_ind_table);
4330         return ERR_PTR(err);
4331 }
4332
4333 int mlx4_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
4334 {
4335         kfree(ib_rwq_ind_tbl);
4336         return 0;
4337 }
4338
4339 struct mlx4_ib_drain_cqe {
4340         struct ib_cqe cqe;
4341         struct completion done;
4342 };
4343
4344 static void mlx4_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
4345 {
4346         struct mlx4_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
4347                                                      struct mlx4_ib_drain_cqe,
4348                                                      cqe);
4349
4350         complete(&cqe->done);
4351 }
4352
4353 /* This function returns only once the drained WR was completed */
4354 static void handle_drain_completion(struct ib_cq *cq,
4355                                     struct mlx4_ib_drain_cqe *sdrain,
4356                                     struct mlx4_ib_dev *dev)
4357 {
4358         struct mlx4_dev *mdev = dev->dev;
4359
4360         if (cq->poll_ctx == IB_POLL_DIRECT) {
4361                 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
4362                         ib_process_cq_direct(cq, -1);
4363                 return;
4364         }
4365
4366         if (mdev->persist->state == MLX4_DEVICE_STATE_INTERNAL_ERROR) {
4367                 struct mlx4_ib_cq *mcq = to_mcq(cq);
4368                 bool triggered = false;
4369                 unsigned long flags;
4370
4371                 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
4372                 /* Make sure that the CQ handler won't run if wasn't run yet */
4373                 if (!mcq->mcq.reset_notify_added)
4374                         mcq->mcq.reset_notify_added = 1;
4375                 else
4376                         triggered = true;
4377                 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
4378
4379                 if (triggered) {
4380                         /* Wait for any scheduled/running task to be ended */
4381                         switch (cq->poll_ctx) {
4382                         case IB_POLL_SOFTIRQ:
4383                                 irq_poll_disable(&cq->iop);
4384                                 irq_poll_enable(&cq->iop);
4385                                 break;
4386                         case IB_POLL_WORKQUEUE:
4387                                 cancel_work_sync(&cq->work);
4388                                 break;
4389                         default:
4390                                 WARN_ON_ONCE(1);
4391                         }
4392                 }
4393
4394                 /* Run the CQ handler - this makes sure that the drain WR will
4395                  * be processed if wasn't processed yet.
4396                  */
4397                 mcq->mcq.comp(&mcq->mcq);
4398         }
4399
4400         wait_for_completion(&sdrain->done);
4401 }
4402
4403 void mlx4_ib_drain_sq(struct ib_qp *qp)
4404 {
4405         struct ib_cq *cq = qp->send_cq;
4406         struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
4407         struct mlx4_ib_drain_cqe sdrain;
4408         const struct ib_send_wr *bad_swr;
4409         struct ib_rdma_wr swr = {
4410                 .wr = {
4411                         .next = NULL,
4412                         { .wr_cqe       = &sdrain.cqe, },
4413                         .opcode = IB_WR_RDMA_WRITE,
4414                 },
4415         };
4416         int ret;
4417         struct mlx4_ib_dev *dev = to_mdev(qp->device);
4418         struct mlx4_dev *mdev = dev->dev;
4419
4420         ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
4421         if (ret && mdev->persist->state != MLX4_DEVICE_STATE_INTERNAL_ERROR) {
4422                 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
4423                 return;
4424         }
4425
4426         sdrain.cqe.done = mlx4_ib_drain_qp_done;
4427         init_completion(&sdrain.done);
4428
4429         ret = _mlx4_ib_post_send(qp, &swr.wr, &bad_swr, true);
4430         if (ret) {
4431                 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
4432                 return;
4433         }
4434
4435         handle_drain_completion(cq, &sdrain, dev);
4436 }
4437
4438 void mlx4_ib_drain_rq(struct ib_qp *qp)
4439 {
4440         struct ib_cq *cq = qp->recv_cq;
4441         struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
4442         struct mlx4_ib_drain_cqe rdrain;
4443         struct ib_recv_wr rwr = {};
4444         const struct ib_recv_wr *bad_rwr;
4445         int ret;
4446         struct mlx4_ib_dev *dev = to_mdev(qp->device);
4447         struct mlx4_dev *mdev = dev->dev;
4448
4449         ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
4450         if (ret && mdev->persist->state != MLX4_DEVICE_STATE_INTERNAL_ERROR) {
4451                 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
4452                 return;
4453         }
4454
4455         rwr.wr_cqe = &rdrain.cqe;
4456         rdrain.cqe.done = mlx4_ib_drain_qp_done;
4457         init_completion(&rdrain.done);
4458
4459         ret = _mlx4_ib_post_recv(qp, &rwr, &bad_rwr, true);
4460         if (ret) {
4461                 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
4462                 return;
4463         }
4464
4465         handle_drain_completion(cq, &rdrain, dev);
4466 }