drivers/infiniband/hw/mlx5/main.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/debugfs.h>
  34 #include <linux/highmem.h>
  35 #include <linux/module.h>
  36 #include <linux/init.h>
  37 #include <linux/errno.h>
  38 #include <linux/pci.h>
  39 #include <linux/dma-mapping.h>
  40 #include <linux/slab.h>
  41 #include <linux/bitmap.h>
  42 #if defined(CONFIG_X86)
  43 #include <asm/pat.h>
  44 #endif
  45 #include <linux/sched.h>
  46 #include <linux/sched/mm.h>
  47 #include <linux/sched/task.h>
  48 #include <linux/delay.h>
  49 #include <rdma/ib_user_verbs.h>
  50 #include <rdma/ib_addr.h>
  51 #include <rdma/ib_cache.h>
  52 #include <linux/mlx5/port.h>
  53 #include <linux/mlx5/vport.h>
  54 #include <linux/mlx5/fs.h>
  55 #include <linux/list.h>
  56 #include <rdma/ib_smi.h>
  57 #include <rdma/ib_umem.h>
  58 #include <linux/in.h>
  59 #include <linux/etherdevice.h>
  60 #include "mlx5_ib.h"
  61 #include "ib_rep.h"
  62 #include "cmd.h"
  63 #include <linux/mlx5/fs_helpers.h>
  64 #include <linux/mlx5/accel.h>
  65 #include <rdma/uverbs_std_types.h>
  66 #include <rdma/mlx5_user_ioctl_verbs.h>
  67 #include <rdma/mlx5_user_ioctl_cmds.h>
  68
  69 #define UVERBS_MODULE_NAME mlx5_ib
  70 #include <rdma/uverbs_named_ioctl.h>
  71
  72 #define DRIVER_NAME "mlx5_ib"
  73 #define DRIVER_VERSION "5.0-0"
  74
  75 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
  76 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
  77 MODULE_LICENSE("Dual BSD/GPL");
  78
  79 static char mlx5_version[] =
  80         DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
  81         DRIVER_VERSION "\n";
  82
  83 struct mlx5_ib_event_work {
  84         struct work_struct      work;
  85         struct mlx5_core_dev    *dev;
  86         void                    *context;
  87         enum mlx5_dev_event     event;
  88         unsigned long           param;
  89 };
  90
  91 enum {
  92         MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
  93 };
  94
  95 static struct workqueue_struct *mlx5_ib_event_wq;
  96 static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
  97 static LIST_HEAD(mlx5_ib_dev_list);
  98 /*
  99  * This mutex should be held when accessing either of the above lists
 100  */
 101 static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
 102
 103 /* We can't use an array for xlt_emergency_page because dma_map_single
 104  * doesn't work on kernel modules memory
 105  */
 106 static unsigned long xlt_emergency_page;
 107 static struct mutex xlt_emergency_page_mutex;
 108
 109 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
 110 {
 111         struct mlx5_ib_dev *dev;
 112
 113         mutex_lock(&mlx5_ib_multiport_mutex);
 114         dev = mpi->ibdev;
 115         mutex_unlock(&mlx5_ib_multiport_mutex);
 116         return dev;
 117 }
 118
 119 static enum rdma_link_layer
 120 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
 121 {
 122         switch (port_type_cap) {
 123         case MLX5_CAP_PORT_TYPE_IB:
 124                 return IB_LINK_LAYER_INFINIBAND;
 125         case MLX5_CAP_PORT_TYPE_ETH:
 126                 return IB_LINK_LAYER_ETHERNET;
 127         default:
 128                 return IB_LINK_LAYER_UNSPECIFIED;
 129         }
 130 }
 131
 132 static enum rdma_link_layer
 133 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
 134 {
 135         struct mlx5_ib_dev *dev = to_mdev(device);
 136         int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
 137
 138         return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
 139 }
 140
 141 static int get_port_state(struct ib_device *ibdev,
 142                           u8 port_num,
 143                           enum ib_port_state *state)
 144 {
 145         struct ib_port_attr attr;
 146         int ret;
 147
 148         memset(&attr, 0, sizeof(attr));
 149         ret = ibdev->query_port(ibdev, port_num, &attr);
 150         if (!ret)
 151                 *state = attr.state;
 152         return ret;
 153 }
 154
 155 static int mlx5_netdev_event(struct notifier_block *this,
 156                              unsigned long event, void *ptr)
 157 {
 158         struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
 159         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
 160         u8 port_num = roce->native_port_num;
 161         struct mlx5_core_dev *mdev;
 162         struct mlx5_ib_dev *ibdev;
 163
 164         ibdev = roce->dev;
 165         mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
 166         if (!mdev)
 167                 return NOTIFY_DONE;
 168
 169         switch (event) {
 170         case NETDEV_REGISTER:
 171         case NETDEV_UNREGISTER:
 172                 write_lock(&roce->netdev_lock);
 173                 if (ibdev->rep) {
 174                         struct mlx5_eswitch *esw = ibdev->mdev->priv.eswitch;
 175                         struct net_device *rep_ndev;
 176
 177                         rep_ndev = mlx5_ib_get_rep_netdev(esw,
 178                                                           ibdev->rep->vport);
 179                         if (rep_ndev == ndev)
 180                                 roce->netdev = (event == NETDEV_UNREGISTER) ?
 181                                         NULL : ndev;
 182                 } else if (ndev->dev.parent == &mdev->pdev->dev) {
 183                         roce->netdev = (event == NETDEV_UNREGISTER) ?
 184                                 NULL : ndev;
 185                 }
 186                 write_unlock(&roce->netdev_lock);
 187                 break;
 188
 189         case NETDEV_CHANGE:
 190         case NETDEV_UP:
 191         case NETDEV_DOWN: {
 192                 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
 193                 struct net_device *upper = NULL;
 194
 195                 if (lag_ndev) {
 196                         upper = netdev_master_upper_dev_get(lag_ndev);
 197                         dev_put(lag_ndev);
 198                 }
 199
 200                 if ((upper == ndev || (!upper && ndev == roce->netdev))
 201                     && ibdev->ib_active) {
 202                         struct ib_event ibev = { };
 203                         enum ib_port_state port_state;
 204
 205                         if (get_port_state(&ibdev->ib_dev, port_num,
 206                                            &port_state))
 207                                 goto done;
 208
 209                         if (roce->last_port_state == port_state)
 210                                 goto done;
 211
 212                         roce->last_port_state = port_state;
 213                         ibev.device = &ibdev->ib_dev;
 214                         if (port_state == IB_PORT_DOWN)
 215                                 ibev.event = IB_EVENT_PORT_ERR;
 216                         else if (port_state == IB_PORT_ACTIVE)
 217                                 ibev.event = IB_EVENT_PORT_ACTIVE;
 218                         else
 219                                 goto done;
 220
 221                         ibev.element.port_num = port_num;
 222                         ib_dispatch_event(&ibev);
 223                 }
 224                 break;
 225         }
 226
 227         default:
 228                 break;
 229         }
 230 done:
 231         mlx5_ib_put_native_port_mdev(ibdev, port_num);
 232         return NOTIFY_DONE;
 233 }
 234
 235 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
 236                                              u8 port_num)
 237 {
 238         struct mlx5_ib_dev *ibdev = to_mdev(device);
 239         struct net_device *ndev;
 240         struct mlx5_core_dev *mdev;
 241
 242         mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
 243         if (!mdev)
 244                 return NULL;
 245
 246         ndev = mlx5_lag_get_roce_netdev(mdev);
 247         if (ndev)
 248                 goto out;
 249
 250         /* Ensure ndev does not disappear before we invoke dev_hold()
 251          */
 252         read_lock(&ibdev->roce[port_num - 1].netdev_lock);
 253         ndev = ibdev->roce[port_num - 1].netdev;
 254         if (ndev)
 255                 dev_hold(ndev);
 256         read_unlock(&ibdev->roce[port_num - 1].netdev_lock);
 257
 258 out:
 259         mlx5_ib_put_native_port_mdev(ibdev, port_num);
 260         return ndev;
 261 }
 262
 263 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
 264                                                    u8 ib_port_num,
 265                                                    u8 *native_port_num)
 266 {
 267         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
 268                                                           ib_port_num);
 269         struct mlx5_core_dev *mdev = NULL;
 270         struct mlx5_ib_multiport_info *mpi;
 271         struct mlx5_ib_port *port;
 272
 273         if (!mlx5_core_mp_enabled(ibdev->mdev) ||
 274             ll != IB_LINK_LAYER_ETHERNET) {
 275                 if (native_port_num)
 276                         *native_port_num = ib_port_num;
 277                 return ibdev->mdev;
 278         }
 279
 280         if (native_port_num)
 281                 *native_port_num = 1;
 282
 283         port = &ibdev->port[ib_port_num - 1];
 284         if (!port)
 285                 return NULL;
 286
 287         spin_lock(&port->mp.mpi_lock);
 288         mpi = ibdev->port[ib_port_num - 1].mp.mpi;
 289         if (mpi && !mpi->unaffiliate) {
 290                 mdev = mpi->mdev;
 291                 /* If it's the master no need to refcount, it'll exist
 292                  * as long as the ib_dev exists.
 293                  */
 294                 if (!mpi->is_master)
 295                         mpi->mdev_refcnt++;
 296         }
 297         spin_unlock(&port->mp.mpi_lock);
 298
 299         return mdev;
 300 }
 301
 302 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
 303 {
 304         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
 305                                                           port_num);
 306         struct mlx5_ib_multiport_info *mpi;
 307         struct mlx5_ib_port *port;
 308
 309         if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
 310                 return;
 311
 312         port = &ibdev->port[port_num - 1];
 313
 314         spin_lock(&port->mp.mpi_lock);
 315         mpi = ibdev->port[port_num - 1].mp.mpi;
 316         if (mpi->is_master)
 317                 goto out;
 318
 319         mpi->mdev_refcnt--;
 320         if (mpi->unaffiliate)
 321                 complete(&mpi->unref_comp);
 322 out:
 323         spin_unlock(&port->mp.mpi_lock);
 324 }
 325
 326 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
 327                                     u8 *active_width)
 328 {
 329         switch (eth_proto_oper) {
 330         case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
 331         case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
 332         case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
 333         case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
 334                 *active_width = IB_WIDTH_1X;
 335                 *active_speed = IB_SPEED_SDR;
 336                 break;
 337         case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
 338         case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
 339         case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
 340         case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
 341         case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
 342         case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
 343         case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
 344                 *active_width = IB_WIDTH_1X;
 345                 *active_speed = IB_SPEED_QDR;
 346                 break;
 347         case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
 348         case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
 349         case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
 350                 *active_width = IB_WIDTH_1X;
 351                 *active_speed = IB_SPEED_EDR;
 352                 break;
 353         case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
 354         case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
 355         case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
 356         case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
 357                 *active_width = IB_WIDTH_4X;
 358                 *active_speed = IB_SPEED_QDR;
 359                 break;
 360         case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
 361         case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
 362         case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
 363                 *active_width = IB_WIDTH_1X;
 364                 *active_speed = IB_SPEED_HDR;
 365                 break;
 366         case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
 367                 *active_width = IB_WIDTH_4X;
 368                 *active_speed = IB_SPEED_FDR;
 369                 break;
 370         case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
 371         case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
 372         case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
 373         case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
 374                 *active_width = IB_WIDTH_4X;
 375                 *active_speed = IB_SPEED_EDR;
 376                 break;
 377         default:
 378                 return -EINVAL;
 379         }
 380
 381         return 0;
 382 }
 383
 384 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
 385                                 struct ib_port_attr *props)
 386 {
 387         struct mlx5_ib_dev *dev = to_mdev(device);
 388         struct mlx5_core_dev *mdev;
 389         struct net_device *ndev, *upper;
 390         enum ib_mtu ndev_ib_mtu;
 391         bool put_mdev = true;
 392         u16 qkey_viol_cntr;
 393         u32 eth_prot_oper;
 394         u8 mdev_port_num;
 395         int err;
 396
 397         mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
 398         if (!mdev) {
 399                 /* This means the port isn't affiliated yet. Get the
 400                  * info for the master port instead.
 401                  */
 402                 put_mdev = false;
 403                 mdev = dev->mdev;
 404                 mdev_port_num = 1;
 405                 port_num = 1;
 406         }
 407
 408         /* Possible bad flows are checked before filling out props so in case
 409          * of an error it will still be zeroed out.
 410          */
 411         err = mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper,
 412                                              mdev_port_num);
 413         if (err)
 414                 goto out;
 415
 416         props->active_width     = IB_WIDTH_4X;
 417         props->active_speed     = IB_SPEED_QDR;
 418
 419         translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
 420                                  &props->active_width);
 421
 422         props->port_cap_flags |= IB_PORT_CM_SUP;
 423         props->ip_gids = true;
 424
 425         props->gid_tbl_len      = MLX5_CAP_ROCE(dev->mdev,
 426                                                 roce_address_table_size);
 427         props->max_mtu          = IB_MTU_4096;
 428         props->max_msg_sz       = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
 429         props->pkey_tbl_len     = 1;
 430         props->state            = IB_PORT_DOWN;
 431         props->phys_state       = 3;
 432
 433         mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
 434         props->qkey_viol_cntr = qkey_viol_cntr;
 435
 436         /* If this is a stub query for an unaffiliated port stop here */
 437         if (!put_mdev)
 438                 goto out;
 439
 440         ndev = mlx5_ib_get_netdev(device, port_num);
 441         if (!ndev)
 442                 goto out;
 443
 444         if (mlx5_lag_is_active(dev->mdev)) {
 445                 rcu_read_lock();
 446                 upper = netdev_master_upper_dev_get_rcu(ndev);
 447                 if (upper) {
 448                         dev_put(ndev);
 449                         ndev = upper;
 450                         dev_hold(ndev);
 451                 }
 452                 rcu_read_unlock();
 453         }
 454
 455         if (netif_running(ndev) && netif_carrier_ok(ndev)) {
 456                 props->state      = IB_PORT_ACTIVE;
 457                 props->phys_state = 5;
 458         }
 459
 460         ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
 461
 462         dev_put(ndev);
 463
 464         props->active_mtu       = min(props->max_mtu, ndev_ib_mtu);
 465 out:
 466         if (put_mdev)
 467                 mlx5_ib_put_native_port_mdev(dev, port_num);
 468         return err;
 469 }
 470
 471 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
 472                          unsigned int index, const union ib_gid *gid,
 473                          const struct ib_gid_attr *attr)
 474 {
 475         enum ib_gid_type gid_type = IB_GID_TYPE_IB;
 476         u8 roce_version = 0;
 477         u8 roce_l3_type = 0;
 478         bool vlan = false;
 479         u8 mac[ETH_ALEN];
 480         u16 vlan_id = 0;
 481
 482         if (gid) {
 483                 gid_type = attr->gid_type;
 484                 ether_addr_copy(mac, attr->ndev->dev_addr);
 485
 486                 if (is_vlan_dev(attr->ndev)) {
 487                         vlan = true;
 488                         vlan_id = vlan_dev_vlan_id(attr->ndev);
 489                 }
 490         }
 491
 492         switch (gid_type) {
 493         case IB_GID_TYPE_IB:
 494                 roce_version = MLX5_ROCE_VERSION_1;
 495                 break;
 496         case IB_GID_TYPE_ROCE_UDP_ENCAP:
 497                 roce_version = MLX5_ROCE_VERSION_2;
 498                 if (ipv6_addr_v4mapped((void *)gid))
 499                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
 500                 else
 501                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
 502                 break;
 503
 504         default:
 505                 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
 506         }
 507
 508         return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
 509                                       roce_l3_type, gid->raw, mac, vlan,
 510                                       vlan_id, port_num);
 511 }
 512
 513 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
 514                            __always_unused void **context)
 515 {
 516         return set_roce_addr(to_mdev(attr->device), attr->port_num,
 517                              attr->index, &attr->gid, attr);
 518 }
 519
 520 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
 521                            __always_unused void **context)
 522 {
 523         return set_roce_addr(to_mdev(attr->device), attr->port_num,
 524                              attr->index, NULL, NULL);
 525 }
 526
 527 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev,
 528                                const struct ib_gid_attr *attr)
 529 {
 530         if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
 531                 return 0;
 532
 533         return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
 534 }
 535
 536 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
 537 {
 538         if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
 539                 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
 540         return 0;
 541 }
 542
 543 enum {
 544         MLX5_VPORT_ACCESS_METHOD_MAD,
 545         MLX5_VPORT_ACCESS_METHOD_HCA,
 546         MLX5_VPORT_ACCESS_METHOD_NIC,
 547 };
 548
 549 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
 550 {
 551         if (mlx5_use_mad_ifc(to_mdev(ibdev)))
 552                 return MLX5_VPORT_ACCESS_METHOD_MAD;
 553
 554         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 555             IB_LINK_LAYER_ETHERNET)
 556                 return MLX5_VPORT_ACCESS_METHOD_NIC;
 557
 558         return MLX5_VPORT_ACCESS_METHOD_HCA;
 559 }
 560
 561 static void get_atomic_caps(struct mlx5_ib_dev *dev,
 562                             u8 atomic_size_qp,
 563                             struct ib_device_attr *props)
 564 {
 565         u8 tmp;
 566         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
 567         u8 atomic_req_8B_endianness_mode =
 568                 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
 569
 570         /* Check if HW supports 8 bytes standard atomic operations and capable
 571          * of host endianness respond
 572          */
 573         tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
 574         if (((atomic_operations & tmp) == tmp) &&
 575             (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
 576             (atomic_req_8B_endianness_mode)) {
 577                 props->atomic_cap = IB_ATOMIC_HCA;
 578         } else {
 579                 props->atomic_cap = IB_ATOMIC_NONE;
 580         }
 581 }
 582
 583 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
 584                                struct ib_device_attr *props)
 585 {
 586         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
 587
 588         get_atomic_caps(dev, atomic_size_qp, props);
 589 }
 590
 591 static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
 592                                struct ib_device_attr *props)
 593 {
 594         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
 595
 596         get_atomic_caps(dev, atomic_size_qp, props);
 597 }
 598
 599 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
 600 {
 601         struct ib_device_attr props = {};
 602
 603         get_atomic_caps_dc(dev, &props);
 604         return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
 605 }
 606 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
 607                                         __be64 *sys_image_guid)
 608 {
 609         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 610         struct mlx5_core_dev *mdev = dev->mdev;
 611         u64 tmp;
 612         int err;
 613
 614         switch (mlx5_get_vport_access_method(ibdev)) {
 615         case MLX5_VPORT_ACCESS_METHOD_MAD:
 616                 return mlx5_query_mad_ifc_system_image_guid(ibdev,
 617                                                             sys_image_guid);
 618
 619         case MLX5_VPORT_ACCESS_METHOD_HCA:
 620                 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
 621                 break;
 622
 623         case MLX5_VPORT_ACCESS_METHOD_NIC:
 624                 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
 625                 break;
 626
 627         default:
 628                 return -EINVAL;
 629         }
 630
 631         if (!err)
 632                 *sys_image_guid = cpu_to_be64(tmp);
 633
 634         return err;
 635
 636 }
 637
 638 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
 639                                 u16 *max_pkeys)
 640 {
 641         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 642         struct mlx5_core_dev *mdev = dev->mdev;
 643
 644         switch (mlx5_get_vport_access_method(ibdev)) {
 645         case MLX5_VPORT_ACCESS_METHOD_MAD:
 646                 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
 647
 648         case MLX5_VPORT_ACCESS_METHOD_HCA:
 649         case MLX5_VPORT_ACCESS_METHOD_NIC:
 650                 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
 651                                                 pkey_table_size));
 652                 return 0;
 653
 654         default:
 655                 return -EINVAL;
 656         }
 657 }
 658
 659 static int mlx5_query_vendor_id(struct ib_device *ibdev,
 660                                 u32 *vendor_id)
 661 {
 662         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 663
 664         switch (mlx5_get_vport_access_method(ibdev)) {
 665         case MLX5_VPORT_ACCESS_METHOD_MAD:
 666                 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
 667
 668         case MLX5_VPORT_ACCESS_METHOD_HCA:
 669         case MLX5_VPORT_ACCESS_METHOD_NIC:
 670                 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
 671
 672         default:
 673                 return -EINVAL;
 674         }
 675 }
 676
 677 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
 678                                 __be64 *node_guid)
 679 {
 680         u64 tmp;
 681         int err;
 682
 683         switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
 684         case MLX5_VPORT_ACCESS_METHOD_MAD:
 685                 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
 686
 687         case MLX5_VPORT_ACCESS_METHOD_HCA:
 688                 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
 689                 break;
 690
 691         case MLX5_VPORT_ACCESS_METHOD_NIC:
 692                 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
 693                 break;
 694
 695         default:
 696                 return -EINVAL;
 697         }
 698
 699         if (!err)
 700                 *node_guid = cpu_to_be64(tmp);
 701
 702         return err;
 703 }
 704
 705 struct mlx5_reg_node_desc {
 706         u8      desc[IB_DEVICE_NODE_DESC_MAX];
 707 };
 708
 709 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
 710 {
 711         struct mlx5_reg_node_desc in;
 712
 713         if (mlx5_use_mad_ifc(dev))
 714                 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
 715
 716         memset(&in, 0, sizeof(in));
 717
 718         return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
 719                                     sizeof(struct mlx5_reg_node_desc),
 720                                     MLX5_REG_NODE_DESC, 0, 0);
 721 }
 722
 723 static int mlx5_ib_query_device(struct ib_device *ibdev,
 724                                 struct ib_device_attr *props,
 725                                 struct ib_udata *uhw)
 726 {
 727         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 728         struct mlx5_core_dev *mdev = dev->mdev;
 729         int err = -ENOMEM;
 730         int max_sq_desc;
 731         int max_rq_sg;
 732         int max_sq_sg;
 733         u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
 734         bool raw_support = !mlx5_core_mp_enabled(mdev);
 735         struct mlx5_ib_query_device_resp resp = {};
 736         size_t resp_len;
 737         u64 max_tso;
 738
 739         resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
 740         if (uhw->outlen && uhw->outlen < resp_len)
 741                 return -EINVAL;
 742         else
 743                 resp.response_length = resp_len;
 744
 745         if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
 746                 return -EINVAL;
 747
 748         memset(props, 0, sizeof(*props));
 749         err = mlx5_query_system_image_guid(ibdev,
 750                                            &props->sys_image_guid);
 751         if (err)
 752                 return err;
 753
 754         err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
 755         if (err)
 756                 return err;
 757
 758         err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
 759         if (err)
 760                 return err;
 761
 762         props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
 763                 (fw_rev_min(dev->mdev) << 16) |
 764                 fw_rev_sub(dev->mdev);
 765         props->device_cap_flags    = IB_DEVICE_CHANGE_PHY_PORT |
 766                 IB_DEVICE_PORT_ACTIVE_EVENT             |
 767                 IB_DEVICE_SYS_IMAGE_GUID                |
 768                 IB_DEVICE_RC_RNR_NAK_GEN;
 769
 770         if (MLX5_CAP_GEN(mdev, pkv))
 771                 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
 772         if (MLX5_CAP_GEN(mdev, qkv))
 773                 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
 774         if (MLX5_CAP_GEN(mdev, apm))
 775                 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
 776         if (MLX5_CAP_GEN(mdev, xrc))
 777                 props->device_cap_flags |= IB_DEVICE_XRC;
 778         if (MLX5_CAP_GEN(mdev, imaicl)) {
 779                 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
 780                                            IB_DEVICE_MEM_WINDOW_TYPE_2B;
 781                 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 782                 /* We support 'Gappy' memory registration too */
 783                 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
 784         }
 785         props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
 786         if (MLX5_CAP_GEN(mdev, sho)) {
 787                 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
 788                 /* At this stage no support for signature handover */
 789                 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
 790                                       IB_PROT_T10DIF_TYPE_2 |
 791                                       IB_PROT_T10DIF_TYPE_3;
 792                 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
 793                                        IB_GUARD_T10DIF_CSUM;
 794         }
 795         if (MLX5_CAP_GEN(mdev, block_lb_mc))
 796                 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
 797
 798         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
 799                 if (MLX5_CAP_ETH(mdev, csum_cap)) {
 800                         /* Legacy bit to support old userspace libraries */
 801                         props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
 802                         props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
 803                 }
 804
 805                 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
 806                         props->raw_packet_caps |=
 807                                 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
 808
 809                 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
 810                         max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
 811                         if (max_tso) {
 812                                 resp.tso_caps.max_tso = 1 << max_tso;
 813                                 resp.tso_caps.supported_qpts |=
 814                                         1 << IB_QPT_RAW_PACKET;
 815                                 resp.response_length += sizeof(resp.tso_caps);
 816                         }
 817                 }
 818
 819                 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
 820                         resp.rss_caps.rx_hash_function =
 821                                                 MLX5_RX_HASH_FUNC_TOEPLITZ;
 822                         resp.rss_caps.rx_hash_fields_mask =
 823                                                 MLX5_RX_HASH_SRC_IPV4 |
 824                                                 MLX5_RX_HASH_DST_IPV4 |
 825                                                 MLX5_RX_HASH_SRC_IPV6 |
 826                                                 MLX5_RX_HASH_DST_IPV6 |
 827                                                 MLX5_RX_HASH_SRC_PORT_TCP |
 828                                                 MLX5_RX_HASH_DST_PORT_TCP |
 829                                                 MLX5_RX_HASH_SRC_PORT_UDP |
 830                                                 MLX5_RX_HASH_DST_PORT_UDP |
 831                                                 MLX5_RX_HASH_INNER;
 832                         if (mlx5_accel_ipsec_device_caps(dev->mdev) &
 833                             MLX5_ACCEL_IPSEC_CAP_DEVICE)
 834                                 resp.rss_caps.rx_hash_fields_mask |=
 835                                         MLX5_RX_HASH_IPSEC_SPI;
 836                         resp.response_length += sizeof(resp.rss_caps);
 837                 }
 838         } else {
 839                 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
 840                         resp.response_length += sizeof(resp.tso_caps);
 841                 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
 842                         resp.response_length += sizeof(resp.rss_caps);
 843         }
 844
 845         if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
 846                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 847                 props->device_cap_flags |= IB_DEVICE_UD_TSO;
 848         }
 849
 850         if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
 851             MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
 852             raw_support)
 853                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
 854
 855         if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
 856             MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
 857                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 858
 859         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
 860             MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
 861             raw_support) {
 862                 /* Legacy bit to support old userspace libraries */
 863                 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
 864                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
 865         }
 866
 867         if (MLX5_CAP_DEV_MEM(mdev, memic)) {
 868                 props->max_dm_size =
 869                         MLX5_CAP_DEV_MEM(mdev, max_memic_size);
 870         }
 871
 872         if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
 873                 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
 874
 875         if (MLX5_CAP_GEN(mdev, end_pad))
 876                 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
 877
 878         props->vendor_part_id      = mdev->pdev->device;
 879         props->hw_ver              = mdev->pdev->revision;
 880
 881         props->max_mr_size         = ~0ull;
 882         props->page_size_cap       = ~(min_page_size - 1);
 883         props->max_qp              = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
 884         props->max_qp_wr           = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 885         max_rq_sg =  MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
 886                      sizeof(struct mlx5_wqe_data_seg);
 887         max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
 888         max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
 889                      sizeof(struct mlx5_wqe_raddr_seg)) /
 890                 sizeof(struct mlx5_wqe_data_seg);
 891         props->max_send_sge = max_sq_sg;
 892         props->max_recv_sge = max_rq_sg;
 893         props->max_sge_rd          = MLX5_MAX_SGE_RD;
 894         props->max_cq              = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
 895         props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
 896         props->max_mr              = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 897         props->max_pd              = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
 898         props->max_qp_rd_atom      = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
 899         props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
 900         props->max_srq             = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
 901         props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
 902         props->local_ca_ack_delay  = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
 903         props->max_res_rd_atom     = props->max_qp_rd_atom * props->max_qp;
 904         props->max_srq_sge         = max_rq_sg - 1;
 905         props->max_fast_reg_page_list_len =
 906                 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
 907         get_atomic_caps_qp(dev, props);
 908         props->masked_atomic_cap   = IB_ATOMIC_NONE;
 909         props->max_mcast_grp       = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
 910         props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
 911         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
 912                                            props->max_mcast_grp;
 913         props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
 914         props->max_ah = INT_MAX;
 915         props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
 916         props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
 917
 918 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 919         if (MLX5_CAP_GEN(mdev, pg))
 920                 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
 921         props->odp_caps = dev->odp_caps;
 922 #endif
 923
 924         if (MLX5_CAP_GEN(mdev, cd))
 925                 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
 926
 927         if (!mlx5_core_is_pf(mdev))
 928                 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
 929
 930         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 931             IB_LINK_LAYER_ETHERNET && raw_support) {
 932                 props->rss_caps.max_rwq_indirection_tables =
 933                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
 934                 props->rss_caps.max_rwq_indirection_table_size =
 935                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
 936                 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
 937                 props->max_wq_type_rq =
 938                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
 939         }
 940
 941         if (MLX5_CAP_GEN(mdev, tag_matching)) {
 942                 props->tm_caps.max_num_tags =
 943                         (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
 944                 props->tm_caps.max_ops =
 945                         1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 946                 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
 947         }
 948
 949         if (MLX5_CAP_GEN(mdev, tag_matching) &&
 950             MLX5_CAP_GEN(mdev, rndv_offload_rc)) {
 951                 props->tm_caps.flags = IB_TM_CAP_RNDV_RC;
 952                 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
 953         }
 954
 955         if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
 956                 props->cq_caps.max_cq_moderation_count =
 957                                                 MLX5_MAX_CQ_COUNT;
 958                 props->cq_caps.max_cq_moderation_period =
 959                                                 MLX5_MAX_CQ_PERIOD;
 960         }
 961
 962         if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
 963                 resp.response_length += sizeof(resp.cqe_comp_caps);
 964
 965                 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
 966                         resp.cqe_comp_caps.max_num =
 967                                 MLX5_CAP_GEN(dev->mdev,
 968                                              cqe_compression_max_num);
 969
 970                         resp.cqe_comp_caps.supported_format =
 971                                 MLX5_IB_CQE_RES_FORMAT_HASH |
 972                                 MLX5_IB_CQE_RES_FORMAT_CSUM;
 973
 974                         if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
 975                                 resp.cqe_comp_caps.supported_format |=
 976                                         MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
 977                 }
 978         }
 979
 980         if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) &&
 981             raw_support) {
 982                 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
 983                     MLX5_CAP_GEN(mdev, qos)) {
 984                         resp.packet_pacing_caps.qp_rate_limit_max =
 985                                 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
 986                         resp.packet_pacing_caps.qp_rate_limit_min =
 987                                 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
 988                         resp.packet_pacing_caps.supported_qpts |=
 989                                 1 << IB_QPT_RAW_PACKET;
 990                         if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
 991                             MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
 992                                 resp.packet_pacing_caps.cap_flags |=
 993                                         MLX5_IB_PP_SUPPORT_BURST;
 994                 }
 995                 resp.response_length += sizeof(resp.packet_pacing_caps);
 996         }
 997
 998         if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
 999                         uhw->outlen)) {
1000                 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1001                         resp.mlx5_ib_support_multi_pkt_send_wqes =
1002                                 MLX5_IB_ALLOW_MPW;
1003
1004                 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1005                         resp.mlx5_ib_support_multi_pkt_send_wqes |=
1006                                 MLX5_IB_SUPPORT_EMPW;
1007
1008                 resp.response_length +=
1009                         sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1010         }
1011
1012         if (field_avail(typeof(resp), flags, uhw->outlen)) {
1013                 resp.response_length += sizeof(resp.flags);
1014
1015                 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1016                         resp.flags |=
1017                                 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
1018
1019                 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1020                         resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
1021         }
1022
1023         if (field_avail(typeof(resp), sw_parsing_caps,
1024                         uhw->outlen)) {
1025                 resp.response_length += sizeof(resp.sw_parsing_caps);
1026                 if (MLX5_CAP_ETH(mdev, swp)) {
1027                         resp.sw_parsing_caps.sw_parsing_offloads |=
1028                                 MLX5_IB_SW_PARSING;
1029
1030                         if (MLX5_CAP_ETH(mdev, swp_csum))
1031                                 resp.sw_parsing_caps.sw_parsing_offloads |=
1032                                         MLX5_IB_SW_PARSING_CSUM;
1033
1034                         if (MLX5_CAP_ETH(mdev, swp_lso))
1035                                 resp.sw_parsing_caps.sw_parsing_offloads |=
1036                                         MLX5_IB_SW_PARSING_LSO;
1037
1038                         if (resp.sw_parsing_caps.sw_parsing_offloads)
1039                                 resp.sw_parsing_caps.supported_qpts =
1040                                         BIT(IB_QPT_RAW_PACKET);
1041                 }
1042         }
1043
1044         if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) &&
1045             raw_support) {
1046                 resp.response_length += sizeof(resp.striding_rq_caps);
1047                 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1048                         resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1049                                 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1050                         resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1051                                 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1052                         resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
1053                                 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1054                         resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1055                                 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1056                         resp.striding_rq_caps.supported_qpts =
1057                                 BIT(IB_QPT_RAW_PACKET);
1058                 }
1059         }
1060
1061         if (field_avail(typeof(resp), tunnel_offloads_caps,
1062                         uhw->outlen)) {
1063                 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1064                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1065                         resp.tunnel_offloads_caps |=
1066                                 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1067                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1068                         resp.tunnel_offloads_caps |=
1069                                 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1070                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1071                         resp.tunnel_offloads_caps |=
1072                                 MLX5_IB_TUNNELED_OFFLOADS_GRE;
1073                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre))
1074                         resp.tunnel_offloads_caps |=
1075                                 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
1076                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp))
1077                         resp.tunnel_offloads_caps |=
1078                                 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
1079         }
1080
1081         if (uhw->outlen) {
1082                 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1083
1084                 if (err)
1085                         return err;
1086         }
1087
1088         return 0;
1089 }
1090
1091 enum mlx5_ib_width {
1092         MLX5_IB_WIDTH_1X        = 1 << 0,
1093         MLX5_IB_WIDTH_2X        = 1 << 1,
1094         MLX5_IB_WIDTH_4X        = 1 << 2,
1095         MLX5_IB_WIDTH_8X        = 1 << 3,
1096         MLX5_IB_WIDTH_12X       = 1 << 4
1097 };
1098
1099 static void translate_active_width(struct ib_device *ibdev, u8 active_width,
1100                                   u8 *ib_width)
1101 {
1102         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1103
1104         if (active_width & MLX5_IB_WIDTH_1X)
1105                 *ib_width = IB_WIDTH_1X;
1106         else if (active_width & MLX5_IB_WIDTH_4X)
1107                 *ib_width = IB_WIDTH_4X;
1108         else if (active_width & MLX5_IB_WIDTH_8X)
1109                 *ib_width = IB_WIDTH_8X;
1110         else if (active_width & MLX5_IB_WIDTH_12X)
1111                 *ib_width = IB_WIDTH_12X;
1112         else {
1113                 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n",
1114                             (int)active_width);
1115                 *ib_width = IB_WIDTH_4X;
1116         }
1117
1118         return;
1119 }
1120
1121 static int mlx5_mtu_to_ib_mtu(int mtu)
1122 {
1123         switch (mtu) {
1124         case 256: return 1;
1125         case 512: return 2;
1126         case 1024: return 3;
1127         case 2048: return 4;
1128         case 4096: return 5;
1129         default:
1130                 pr_warn("invalid mtu\n");
1131                 return -1;
1132         }
1133 }
1134
1135 enum ib_max_vl_num {
1136         __IB_MAX_VL_0           = 1,
1137         __IB_MAX_VL_0_1         = 2,
1138         __IB_MAX_VL_0_3         = 3,
1139         __IB_MAX_VL_0_7         = 4,
1140         __IB_MAX_VL_0_14        = 5,
1141 };
1142
1143 enum mlx5_vl_hw_cap {
1144         MLX5_VL_HW_0    = 1,
1145         MLX5_VL_HW_0_1  = 2,
1146         MLX5_VL_HW_0_2  = 3,
1147         MLX5_VL_HW_0_3  = 4,
1148         MLX5_VL_HW_0_4  = 5,
1149         MLX5_VL_HW_0_5  = 6,
1150         MLX5_VL_HW_0_6  = 7,
1151         MLX5_VL_HW_0_7  = 8,
1152         MLX5_VL_HW_0_14 = 15
1153 };
1154
1155 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1156                                 u8 *max_vl_num)
1157 {
1158         switch (vl_hw_cap) {
1159         case MLX5_VL_HW_0:
1160                 *max_vl_num = __IB_MAX_VL_0;
1161                 break;
1162         case MLX5_VL_HW_0_1:
1163                 *max_vl_num = __IB_MAX_VL_0_1;
1164                 break;
1165         case MLX5_VL_HW_0_3:
1166                 *max_vl_num = __IB_MAX_VL_0_3;
1167                 break;
1168         case MLX5_VL_HW_0_7:
1169                 *max_vl_num = __IB_MAX_VL_0_7;
1170                 break;
1171         case MLX5_VL_HW_0_14:
1172                 *max_vl_num = __IB_MAX_VL_0_14;
1173                 break;
1174
1175         default:
1176                 return -EINVAL;
1177         }
1178
1179         return 0;
1180 }
1181
1182 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1183                                struct ib_port_attr *props)
1184 {
1185         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1186         struct mlx5_core_dev *mdev = dev->mdev;
1187         struct mlx5_hca_vport_context *rep;
1188         u16 max_mtu;
1189         u16 oper_mtu;
1190         int err;
1191         u8 ib_link_width_oper;
1192         u8 vl_hw_cap;
1193
1194         rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1195         if (!rep) {
1196                 err = -ENOMEM;
1197                 goto out;
1198         }
1199
1200         /* props being zeroed by the caller, avoid zeroing it here */
1201
1202         err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
1203         if (err)
1204                 goto out;
1205
1206         props->lid              = rep->lid;
1207         props->lmc              = rep->lmc;
1208         props->sm_lid           = rep->sm_lid;
1209         props->sm_sl            = rep->sm_sl;
1210         props->state            = rep->vport_state;
1211         props->phys_state       = rep->port_physical_state;
1212         props->port_cap_flags   = rep->cap_mask1;
1213         props->gid_tbl_len      = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1214         props->max_msg_sz       = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1215         props->pkey_tbl_len     = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1216         props->bad_pkey_cntr    = rep->pkey_violation_counter;
1217         props->qkey_viol_cntr   = rep->qkey_violation_counter;
1218         props->subnet_timeout   = rep->subnet_timeout;
1219         props->init_type_reply  = rep->init_type_reply;
1220
1221         err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1222         if (err)
1223                 goto out;
1224
1225         translate_active_width(ibdev, ib_link_width_oper, &props->active_width);
1226
1227         err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
1228         if (err)
1229                 goto out;
1230
1231         mlx5_query_port_max_mtu(mdev, &max_mtu, port);
1232
1233         props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
1234
1235         mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
1236
1237         props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
1238
1239         err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1240         if (err)
1241                 goto out;
1242
1243         err = translate_max_vl_num(ibdev, vl_hw_cap,
1244                                    &props->max_vl_num);
1245 out:
1246         kfree(rep);
1247         return err;
1248 }
1249
1250 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1251                        struct ib_port_attr *props)
1252 {
1253         unsigned int count;
1254         int ret;
1255
1256         switch (mlx5_get_vport_access_method(ibdev)) {
1257         case MLX5_VPORT_ACCESS_METHOD_MAD:
1258                 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1259                 break;
1260
1261         case MLX5_VPORT_ACCESS_METHOD_HCA:
1262                 ret = mlx5_query_hca_port(ibdev, port, props);
1263                 break;
1264
1265         case MLX5_VPORT_ACCESS_METHOD_NIC:
1266                 ret = mlx5_query_port_roce(ibdev, port, props);
1267                 break;
1268
1269         default:
1270                 ret = -EINVAL;
1271         }
1272
1273         if (!ret && props) {
1274                 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1275                 struct mlx5_core_dev *mdev;
1276                 bool put_mdev = true;
1277
1278                 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1279                 if (!mdev) {
1280                         /* If the port isn't affiliated yet query the master.
1281                          * The master and slave will have the same values.
1282                          */
1283                         mdev = dev->mdev;
1284                         port = 1;
1285                         put_mdev = false;
1286                 }
1287                 count = mlx5_core_reserved_gids_count(mdev);
1288                 if (put_mdev)
1289                         mlx5_ib_put_native_port_mdev(dev, port);
1290                 props->gid_tbl_len -= count;
1291         }
1292         return ret;
1293 }
1294
1295 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
1296                                   struct ib_port_attr *props)
1297 {
1298         int ret;
1299
1300         /* Only link layer == ethernet is valid for representors */
1301         ret = mlx5_query_port_roce(ibdev, port, props);
1302         if (ret || !props)
1303                 return ret;
1304
1305         /* We don't support GIDS */
1306         props->gid_tbl_len = 0;
1307
1308         return ret;
1309 }
1310
1311 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1312                              union ib_gid *gid)
1313 {
1314         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1315         struct mlx5_core_dev *mdev = dev->mdev;
1316
1317         switch (mlx5_get_vport_access_method(ibdev)) {
1318         case MLX5_VPORT_ACCESS_METHOD_MAD:
1319                 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1320
1321         case MLX5_VPORT_ACCESS_METHOD_HCA:
1322                 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1323
1324         default:
1325                 return -EINVAL;
1326         }
1327
1328 }
1329
1330 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1331                                    u16 index, u16 *pkey)
1332 {
1333         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1334         struct mlx5_core_dev *mdev;
1335         bool put_mdev = true;
1336         u8 mdev_port_num;
1337         int err;
1338
1339         mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1340         if (!mdev) {
1341                 /* The port isn't affiliated yet, get the PKey from the master
1342                  * port. For RoCE the PKey tables will be the same.
1343                  */
1344                 put_mdev = false;
1345                 mdev = dev->mdev;
1346                 mdev_port_num = 1;
1347         }
1348
1349         err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1350                                         index, pkey);
1351         if (put_mdev)
1352                 mlx5_ib_put_native_port_mdev(dev, port);
1353
1354         return err;
1355 }
1356
1357 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1358                               u16 *pkey)
1359 {
1360         switch (mlx5_get_vport_access_method(ibdev)) {
1361         case MLX5_VPORT_ACCESS_METHOD_MAD:
1362                 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1363
1364         case MLX5_VPORT_ACCESS_METHOD_HCA:
1365         case MLX5_VPORT_ACCESS_METHOD_NIC:
1366                 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1367         default:
1368                 return -EINVAL;
1369         }
1370 }
1371
1372 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1373                                  struct ib_device_modify *props)
1374 {
1375         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1376         struct mlx5_reg_node_desc in;
1377         struct mlx5_reg_node_desc out;
1378         int err;
1379
1380         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1381                 return -EOPNOTSUPP;
1382
1383         if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1384                 return 0;
1385
1386         /*
1387          * If possible, pass node desc to FW, so it can generate
1388          * a 144 trap.  If cmd fails, just ignore.
1389          */
1390         memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1391         err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1392                                    sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1393         if (err)
1394                 return err;
1395
1396         memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1397
1398         return err;
1399 }
1400
1401 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1402                                 u32 value)
1403 {
1404         struct mlx5_hca_vport_context ctx = {};
1405         struct mlx5_core_dev *mdev;
1406         u8 mdev_port_num;
1407         int err;
1408
1409         mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1410         if (!mdev)
1411                 return -ENODEV;
1412
1413         err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
1414         if (err)
1415                 goto out;
1416
1417         if (~ctx.cap_mask1_perm & mask) {
1418                 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1419                              mask, ctx.cap_mask1_perm);
1420                 err = -EINVAL;
1421                 goto out;
1422         }
1423
1424         ctx.cap_mask1 = value;
1425         ctx.cap_mask1_perm = mask;
1426         err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1427                                                  0, &ctx);
1428
1429 out:
1430         mlx5_ib_put_native_port_mdev(dev, port_num);
1431
1432         return err;
1433 }
1434
1435 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1436                                struct ib_port_modify *props)
1437 {
1438         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1439         struct ib_port_attr attr;
1440         u32 tmp;
1441         int err;
1442         u32 change_mask;
1443         u32 value;
1444         bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1445                       IB_LINK_LAYER_INFINIBAND);
1446
1447         /* CM layer calls ib_modify_port() regardless of the link layer. For
1448          * Ethernet ports, qkey violation and Port capabilities are meaningless.
1449          */
1450         if (!is_ib)
1451                 return 0;
1452
1453         if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1454                 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1455                 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1456                 return set_port_caps_atomic(dev, port, change_mask, value);
1457         }
1458
1459         mutex_lock(&dev->cap_mask_mutex);
1460
1461         err = ib_query_port(ibdev, port, &attr);
1462         if (err)
1463                 goto out;
1464
1465         tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1466                 ~props->clr_port_cap_mask;
1467
1468         err = mlx5_set_port_caps(dev->mdev, port, tmp);
1469
1470 out:
1471         mutex_unlock(&dev->cap_mask_mutex);
1472         return err;
1473 }
1474
1475 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1476 {
1477         mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1478                     caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1479 }
1480
1481 static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1482 {
1483         /* Large page with non 4k uar support might limit the dynamic size */
1484         if (uars_per_sys_page == 1  && PAGE_SIZE > 4096)
1485                 return MLX5_MIN_DYN_BFREGS;
1486
1487         return MLX5_MAX_DYN_BFREGS;
1488 }
1489
1490 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1491                              struct mlx5_ib_alloc_ucontext_req_v2 *req,
1492                              struct mlx5_bfreg_info *bfregi)
1493 {
1494         int uars_per_sys_page;
1495         int bfregs_per_sys_page;
1496         int ref_bfregs = req->total_num_bfregs;
1497
1498         if (req->total_num_bfregs == 0)
1499                 return -EINVAL;
1500
1501         BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1502         BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1503
1504         if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1505                 return -ENOMEM;
1506
1507         uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1508         bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1509         /* This holds the required static allocation asked by the user */
1510         req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1511         if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1512                 return -EINVAL;
1513
1514         bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1515         bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1516         bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1517         bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1518
1519         mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
1520                     MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1521                     lib_uar_4k ? "yes" : "no", ref_bfregs,
1522                     req->total_num_bfregs, bfregi->total_num_bfregs,
1523                     bfregi->num_sys_pages);
1524
1525         return 0;
1526 }
1527
1528 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1529 {
1530         struct mlx5_bfreg_info *bfregi;
1531         int err;
1532         int i;
1533
1534         bfregi = &context->bfregi;
1535         for (i = 0; i < bfregi->num_static_sys_pages; i++) {
1536                 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1537                 if (err)
1538                         goto error;
1539
1540                 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1541         }
1542
1543         for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1544                 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1545
1546         return 0;
1547
1548 error:
1549         for (--i; i >= 0; i--)
1550                 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1551                         mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1552
1553         return err;
1554 }
1555
1556 static void deallocate_uars(struct mlx5_ib_dev *dev,
1557                             struct mlx5_ib_ucontext *context)
1558 {
1559         struct mlx5_bfreg_info *bfregi;
1560         int i;
1561
1562         bfregi = &context->bfregi;
1563         for (i = 0; i < bfregi->num_sys_pages; i++)
1564                 if (i < bfregi->num_static_sys_pages ||
1565                     bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1566                         mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1567 }
1568
1569 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn)
1570 {
1571         int err;
1572
1573         if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1574                 return 0;
1575
1576         err = mlx5_core_alloc_transport_domain(dev->mdev, tdn);
1577         if (err)
1578                 return err;
1579
1580         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1581             (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1582              !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1583                 return err;
1584
1585         mutex_lock(&dev->lb_mutex);
1586         dev->user_td++;
1587
1588         if (dev->user_td == 2)
1589                 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1590
1591         mutex_unlock(&dev->lb_mutex);
1592         return err;
1593 }
1594
1595 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn)
1596 {
1597         if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1598                 return;
1599
1600         mlx5_core_dealloc_transport_domain(dev->mdev, tdn);
1601
1602         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1603             (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1604              !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1605                 return;
1606
1607         mutex_lock(&dev->lb_mutex);
1608         dev->user_td--;
1609
1610         if (dev->user_td < 2)
1611                 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1612
1613         mutex_unlock(&dev->lb_mutex);
1614 }
1615
1616 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1617                                                   struct ib_udata *udata)
1618 {
1619         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1620         struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1621         struct mlx5_ib_alloc_ucontext_resp resp = {};
1622         struct mlx5_core_dev *mdev = dev->mdev;
1623         struct mlx5_ib_ucontext *context;
1624         struct mlx5_bfreg_info *bfregi;
1625         int ver;
1626         int err;
1627         size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1628                                      max_cqe_version);
1629         u32 dump_fill_mkey;
1630         bool lib_uar_4k;
1631
1632         if (!dev->ib_active)
1633                 return ERR_PTR(-EAGAIN);
1634
1635         if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1636                 ver = 0;
1637         else if (udata->inlen >= min_req_v2)
1638                 ver = 2;
1639         else
1640                 return ERR_PTR(-EINVAL);
1641
1642         err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1643         if (err)
1644                 return ERR_PTR(err);
1645
1646         if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
1647                 return ERR_PTR(-EOPNOTSUPP);
1648
1649         if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1650                 return ERR_PTR(-EOPNOTSUPP);
1651
1652         req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1653                                     MLX5_NON_FP_BFREGS_PER_UAR);
1654         if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1655                 return ERR_PTR(-EINVAL);
1656
1657         resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1658         if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1659                 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1660         resp.cache_line_size = cache_line_size();
1661         resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1662         resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1663         resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1664         resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1665         resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1666         resp.cqe_version = min_t(__u8,
1667                                  (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1668                                  req.max_cqe_version);
1669         resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1670                                 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1671         resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1672                                         MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
1673         resp.response_length = min(offsetof(typeof(resp), response_length) +
1674                                    sizeof(resp.response_length), udata->outlen);
1675
1676         if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1677                 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS))
1678                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1679                 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1680                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1681                 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1682                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1683                 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1684                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1685                 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1686         }
1687
1688         context = kzalloc(sizeof(*context), GFP_KERNEL);
1689         if (!context)
1690                 return ERR_PTR(-ENOMEM);
1691
1692         lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1693         bfregi = &context->bfregi;
1694
1695         /* updates req->total_num_bfregs */
1696         err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
1697         if (err)
1698                 goto out_ctx;
1699
1700         mutex_init(&bfregi->lock);
1701         bfregi->lib_uar_4k = lib_uar_4k;
1702         bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
1703                                 GFP_KERNEL);
1704         if (!bfregi->count) {
1705                 err = -ENOMEM;
1706                 goto out_ctx;
1707         }
1708
1709         bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1710                                     sizeof(*bfregi->sys_pages),
1711                                     GFP_KERNEL);
1712         if (!bfregi->sys_pages) {
1713                 err = -ENOMEM;
1714                 goto out_count;
1715         }
1716
1717         err = allocate_uars(dev, context);
1718         if (err)
1719                 goto out_sys_pages;
1720
1721 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1722         context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1723 #endif
1724
1725         err = mlx5_ib_alloc_transport_domain(dev, &context->tdn);
1726         if (err)
1727                 goto out_uars;
1728
1729         if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
1730                 /* Block DEVX on Infiniband as of SELinux */
1731                 if (mlx5_ib_port_link_layer(ibdev, 1) != IB_LINK_LAYER_ETHERNET) {
1732                         err = -EPERM;
1733                         goto out_td;
1734                 }
1735
1736                 err = mlx5_ib_devx_create(dev, context);
1737                 if (err)
1738                         goto out_td;
1739         }
1740
1741         if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1742                 err = mlx5_cmd_dump_fill_mkey(dev->mdev, &dump_fill_mkey);
1743                 if (err)
1744                         goto out_mdev;
1745         }
1746
1747         INIT_LIST_HEAD(&context->vma_private_list);
1748         mutex_init(&context->vma_private_list_mutex);
1749         INIT_LIST_HEAD(&context->db_page_list);
1750         mutex_init(&context->db_page_mutex);
1751
1752         resp.tot_bfregs = req.total_num_bfregs;
1753         resp.num_ports = dev->num_ports;
1754
1755         if (field_avail(typeof(resp), cqe_version, udata->outlen))
1756                 resp.response_length += sizeof(resp.cqe_version);
1757
1758         if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1759                 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1760                                       MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1761                 resp.response_length += sizeof(resp.cmds_supp_uhw);
1762         }
1763
1764         if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1765                 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1766                         mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1767                         resp.eth_min_inline++;
1768                 }
1769                 resp.response_length += sizeof(resp.eth_min_inline);
1770         }
1771
1772         if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
1773                 if (mdev->clock_info)
1774                         resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1775                 resp.response_length += sizeof(resp.clock_info_versions);
1776         }
1777
1778         /*
1779          * We don't want to expose information from the PCI bar that is located
1780          * after 4096 bytes, so if the arch only supports larger pages, let's
1781          * pretend we don't support reading the HCA's core clock. This is also
1782          * forced by mmap function.
1783          */
1784         if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1785                 if (PAGE_SIZE <= 4096) {
1786                         resp.comp_mask |=
1787                                 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1788                         resp.hca_core_clock_offset =
1789                                 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1790                 }
1791                 resp.response_length += sizeof(resp.hca_core_clock_offset);
1792         }
1793
1794         if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1795                 resp.response_length += sizeof(resp.log_uar_size);
1796
1797         if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1798                 resp.response_length += sizeof(resp.num_uars_per_page);
1799
1800         if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1801                 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1802                 resp.response_length += sizeof(resp.num_dyn_bfregs);
1803         }
1804
1805         if (field_avail(typeof(resp), dump_fill_mkey, udata->outlen)) {
1806                 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1807                         resp.dump_fill_mkey = dump_fill_mkey;
1808                         resp.comp_mask |=
1809                                 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1810                 }
1811                 resp.response_length += sizeof(resp.dump_fill_mkey);
1812         }
1813
1814         err = ib_copy_to_udata(udata, &resp, resp.response_length);
1815         if (err)
1816                 goto out_mdev;
1817
1818         bfregi->ver = ver;
1819         bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1820         context->cqe_version = resp.cqe_version;
1821         context->lib_caps = req.lib_caps;
1822         print_lib_caps(dev, context->lib_caps);
1823
1824         if (mlx5_lag_is_active(dev->mdev)) {
1825                 u8 port = mlx5_core_native_port_num(dev->mdev);
1826
1827                 atomic_set(&context->tx_port_affinity,
1828                            atomic_add_return(
1829                                    1, &dev->roce[port].tx_port_affinity));
1830         }
1831
1832         return &context->ibucontext;
1833
1834 out_mdev:
1835         if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
1836                 mlx5_ib_devx_destroy(dev, context);
1837 out_td:
1838         mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1839
1840 out_uars:
1841         deallocate_uars(dev, context);
1842
1843 out_sys_pages:
1844         kfree(bfregi->sys_pages);
1845
1846 out_count:
1847         kfree(bfregi->count);
1848
1849 out_ctx:
1850         kfree(context);
1851
1852         return ERR_PTR(err);
1853 }
1854
1855 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1856 {
1857         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1858         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1859         struct mlx5_bfreg_info *bfregi;
1860
1861         if (context->devx_uid)
1862                 mlx5_ib_devx_destroy(dev, context);
1863
1864         bfregi = &context->bfregi;
1865         mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1866
1867         deallocate_uars(dev, context);
1868         kfree(bfregi->sys_pages);
1869         kfree(bfregi->count);
1870         kfree(context);
1871
1872         return 0;
1873 }
1874
1875 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
1876                                  int uar_idx)
1877 {
1878         int fw_uars_per_page;
1879
1880         fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1881
1882         return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
1883 }
1884
1885 static int get_command(unsigned long offset)
1886 {
1887         return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1888 }
1889
1890 static int get_arg(unsigned long offset)
1891 {
1892         return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1893 }
1894
1895 static int get_index(unsigned long offset)
1896 {
1897         return get_arg(offset);
1898 }
1899
1900 /* Index resides in an extra byte to enable larger values than 255 */
1901 static int get_extended_index(unsigned long offset)
1902 {
1903         return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
1904 }
1905
1906 static void  mlx5_ib_vma_open(struct vm_area_struct *area)
1907 {
1908         /* vma_open is called when a new VMA is created on top of our VMA.  This
1909          * is done through either mremap flow or split_vma (usually due to
1910          * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1911          * as this VMA is strongly hardware related.  Therefore we set the
1912          * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1913          * calling us again and trying to do incorrect actions.  We assume that
1914          * the original VMA size is exactly a single page, and therefore all
1915          * "splitting" operation will not happen to it.
1916          */
1917         area->vm_ops = NULL;
1918 }
1919
1920 static void  mlx5_ib_vma_close(struct vm_area_struct *area)
1921 {
1922         struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1923
1924         /* It's guaranteed that all VMAs opened on a FD are closed before the
1925          * file itself is closed, therefore no sync is needed with the regular
1926          * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1927          * However need a sync with accessing the vma as part of
1928          * mlx5_ib_disassociate_ucontext.
1929          * The close operation is usually called under mm->mmap_sem except when
1930          * process is exiting.
1931          * The exiting case is handled explicitly as part of
1932          * mlx5_ib_disassociate_ucontext.
1933          */
1934         mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1935
1936         /* setting the vma context pointer to null in the mlx5_ib driver's
1937          * private data, to protect a race condition in
1938          * mlx5_ib_disassociate_ucontext().
1939          */
1940         mlx5_ib_vma_priv_data->vma = NULL;
1941         mutex_lock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
1942         list_del(&mlx5_ib_vma_priv_data->list);
1943         mutex_unlock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
1944         kfree(mlx5_ib_vma_priv_data);
1945 }
1946
1947 static const struct vm_operations_struct mlx5_ib_vm_ops = {
1948         .open = mlx5_ib_vma_open,
1949         .close = mlx5_ib_vma_close
1950 };
1951
1952 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1953                                 struct mlx5_ib_ucontext *ctx)
1954 {
1955         struct mlx5_ib_vma_private_data *vma_prv;
1956         struct list_head *vma_head = &ctx->vma_private_list;
1957
1958         vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1959         if (!vma_prv)
1960                 return -ENOMEM;
1961
1962         vma_prv->vma = vma;
1963         vma_prv->vma_private_list_mutex = &ctx->vma_private_list_mutex;
1964         vma->vm_private_data = vma_prv;
1965         vma->vm_ops =  &mlx5_ib_vm_ops;
1966
1967         mutex_lock(&ctx->vma_private_list_mutex);
1968         list_add(&vma_prv->list, vma_head);
1969         mutex_unlock(&ctx->vma_private_list_mutex);
1970
1971         return 0;
1972 }
1973
1974 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1975 {
1976         struct vm_area_struct *vma;
1977         struct mlx5_ib_vma_private_data *vma_private, *n;
1978         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1979
1980         mutex_lock(&context->vma_private_list_mutex);
1981         list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1982                                  list) {
1983                 vma = vma_private->vma;
1984                 zap_vma_ptes(vma, vma->vm_start, PAGE_SIZE);
1985                 /* context going to be destroyed, should
1986                  * not access ops any more.
1987                  */
1988                 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
1989                 vma->vm_ops = NULL;
1990                 list_del(&vma_private->list);
1991                 kfree(vma_private);
1992         }
1993         mutex_unlock(&context->vma_private_list_mutex);
1994 }
1995
1996 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1997 {
1998         switch (cmd) {
1999         case MLX5_IB_MMAP_WC_PAGE:
2000                 return "WC";
2001         case MLX5_IB_MMAP_REGULAR_PAGE:
2002                 return "best effort WC";
2003         case MLX5_IB_MMAP_NC_PAGE:
2004                 return "NC";
2005         case MLX5_IB_MMAP_DEVICE_MEM:
2006                 return "Device Memory";
2007         default:
2008                 return NULL;
2009         }
2010 }
2011
2012 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2013                                         struct vm_area_struct *vma,
2014                                         struct mlx5_ib_ucontext *context)
2015 {
2016         phys_addr_t pfn;
2017         int err;
2018
2019         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2020                 return -EINVAL;
2021
2022         if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2023                 return -EOPNOTSUPP;
2024
2025         if (vma->vm_flags & VM_WRITE)
2026                 return -EPERM;
2027         vma->vm_flags &= ~VM_MAYWRITE;
2028
2029         if (!dev->mdev->clock_info_page)
2030                 return -EOPNOTSUPP;
2031
2032         pfn = page_to_pfn(dev->mdev->clock_info_page);
2033         err = remap_pfn_range(vma, vma->vm_start, pfn, PAGE_SIZE,
2034                               vma->vm_page_prot);
2035         if (err)
2036                 return err;
2037
2038         return mlx5_ib_set_vma_data(vma, context);
2039 }
2040
2041 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
2042                     struct vm_area_struct *vma,
2043                     struct mlx5_ib_ucontext *context)
2044 {
2045         struct mlx5_bfreg_info *bfregi = &context->bfregi;
2046         int err;
2047         unsigned long idx;
2048         phys_addr_t pfn;
2049         pgprot_t prot;
2050         u32 bfreg_dyn_idx = 0;
2051         u32 uar_index;
2052         int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2053         int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2054                                 bfregi->num_static_sys_pages;
2055
2056         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2057                 return -EINVAL;
2058
2059         if (dyn_uar)
2060                 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2061         else
2062                 idx = get_index(vma->vm_pgoff);
2063
2064         if (idx >= max_valid_idx) {
2065                 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2066                              idx, max_valid_idx);
2067                 return -EINVAL;
2068         }
2069
2070         switch (cmd) {
2071         case MLX5_IB_MMAP_WC_PAGE:
2072         case MLX5_IB_MMAP_ALLOC_WC:
2073 /* Some architectures don't support WC memory */
2074 #if defined(CONFIG_X86)
2075                 if (!pat_enabled())
2076                         return -EPERM;
2077 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2078                         return -EPERM;
2079 #endif
2080         /* fall through */
2081         case MLX5_IB_MMAP_REGULAR_PAGE:
2082                 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2083                 prot = pgprot_writecombine(vma->vm_page_prot);
2084                 break;
2085         case MLX5_IB_MMAP_NC_PAGE:
2086                 prot = pgprot_noncached(vma->vm_page_prot);
2087                 break;
2088         default:
2089                 return -EINVAL;
2090         }
2091
2092         if (dyn_uar) {
2093                 int uars_per_page;
2094
2095                 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2096                 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2097                 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2098                         mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2099                                      bfreg_dyn_idx, bfregi->total_num_bfregs);
2100                         return -EINVAL;
2101                 }
2102
2103                 mutex_lock(&bfregi->lock);
2104                 /* Fail if uar already allocated, first bfreg index of each
2105                  * page holds its count.
2106                  */
2107                 if (bfregi->count[bfreg_dyn_idx]) {
2108                         mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2109                         mutex_unlock(&bfregi->lock);
2110                         return -EINVAL;
2111                 }
2112
2113                 bfregi->count[bfreg_dyn_idx]++;
2114                 mutex_unlock(&bfregi->lock);
2115
2116                 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2117                 if (err) {
2118                         mlx5_ib_warn(dev, "UAR alloc failed\n");
2119                         goto free_bfreg;
2120                 }
2121         } else {
2122                 uar_index = bfregi->sys_pages[idx];
2123         }
2124
2125         pfn = uar_index2pfn(dev, uar_index);
2126         mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2127
2128         vma->vm_page_prot = prot;
2129         err = io_remap_pfn_range(vma, vma->vm_start, pfn,
2130                                  PAGE_SIZE, vma->vm_page_prot);
2131         if (err) {
2132                 mlx5_ib_err(dev,
2133                             "io_remap_pfn_range failed with error=%d, mmap_cmd=%s\n",
2134                             err, mmap_cmd2str(cmd));
2135                 err = -EAGAIN;
2136                 goto err;
2137         }
2138
2139         err = mlx5_ib_set_vma_data(vma, context);
2140         if (err)
2141                 goto err;
2142
2143         if (dyn_uar)
2144                 bfregi->sys_pages[idx] = uar_index;
2145         return 0;
2146
2147 err:
2148         if (!dyn_uar)
2149                 return err;
2150
2151         mlx5_cmd_free_uar(dev->mdev, idx);
2152
2153 free_bfreg:
2154         mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2155
2156         return err;
2157 }
2158
2159 static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
2160 {
2161         struct mlx5_ib_ucontext *mctx = to_mucontext(context);
2162         struct mlx5_ib_dev *dev = to_mdev(context->device);
2163         u16 page_idx = get_extended_index(vma->vm_pgoff);
2164         size_t map_size = vma->vm_end - vma->vm_start;
2165         u32 npages = map_size >> PAGE_SHIFT;
2166         phys_addr_t pfn;
2167         pgprot_t prot;
2168
2169         if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) !=
2170             page_idx + npages)
2171                 return -EINVAL;
2172
2173         pfn = ((pci_resource_start(dev->mdev->pdev, 0) +
2174               MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >>
2175               PAGE_SHIFT) +
2176               page_idx;
2177         prot = pgprot_writecombine(vma->vm_page_prot);
2178         vma->vm_page_prot = prot;
2179
2180         if (io_remap_pfn_range(vma, vma->vm_start, pfn, map_size,
2181                                vma->vm_page_prot))
2182                 return -EAGAIN;
2183
2184         return mlx5_ib_set_vma_data(vma, mctx);
2185 }
2186
2187 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2188 {
2189         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2190         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2191         unsigned long command;
2192         phys_addr_t pfn;
2193
2194         command = get_command(vma->vm_pgoff);
2195         switch (command) {
2196         case MLX5_IB_MMAP_WC_PAGE:
2197         case MLX5_IB_MMAP_NC_PAGE:
2198         case MLX5_IB_MMAP_REGULAR_PAGE:
2199         case MLX5_IB_MMAP_ALLOC_WC:
2200                 return uar_mmap(dev, command, vma, context);
2201
2202         case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2203                 return -ENOSYS;
2204
2205         case MLX5_IB_MMAP_CORE_CLOCK:
2206                 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2207                         return -EINVAL;
2208
2209                 if (vma->vm_flags & VM_WRITE)
2210                         return -EPERM;
2211                 vma->vm_flags &= ~VM_MAYWRITE;
2212
2213                 /* Don't expose to user-space information it shouldn't have */
2214                 if (PAGE_SIZE > 4096)
2215                         return -EOPNOTSUPP;
2216
2217                 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
2218                 pfn = (dev->mdev->iseg_base +
2219                        offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2220                         PAGE_SHIFT;
2221                 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
2222                                        PAGE_SIZE, vma->vm_page_prot))
2223                         return -EAGAIN;
2224                 break;
2225         case MLX5_IB_MMAP_CLOCK_INFO:
2226                 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
2227
2228         case MLX5_IB_MMAP_DEVICE_MEM:
2229                 return dm_mmap(ibcontext, vma);
2230
2231         default:
2232                 return -EINVAL;
2233         }
2234
2235         return 0;
2236 }
2237
2238 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
2239                                struct ib_ucontext *context,
2240                                struct ib_dm_alloc_attr *attr,
2241                                struct uverbs_attr_bundle *attrs)
2242 {
2243         u64 act_size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
2244         struct mlx5_memic *memic = &to_mdev(ibdev)->memic;
2245         phys_addr_t memic_addr;
2246         struct mlx5_ib_dm *dm;
2247         u64 start_offset;
2248         u32 page_idx;
2249         int err;
2250
2251         dm = kzalloc(sizeof(*dm), GFP_KERNEL);
2252         if (!dm)
2253                 return ERR_PTR(-ENOMEM);
2254
2255         mlx5_ib_dbg(to_mdev(ibdev), "alloc_memic req: user_length=0x%llx act_length=0x%llx log_alignment=%d\n",
2256                     attr->length, act_size, attr->alignment);
2257
2258         err = mlx5_cmd_alloc_memic(memic, &memic_addr,
2259                                    act_size, attr->alignment);
2260         if (err)
2261                 goto err_free;
2262
2263         start_offset = memic_addr & ~PAGE_MASK;
2264         page_idx = (memic_addr - pci_resource_start(memic->dev->pdev, 0) -
2265                     MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2266                     PAGE_SHIFT;
2267
2268         err = uverbs_copy_to(attrs,
2269                              MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2270                              &start_offset, sizeof(start_offset));
2271         if (err)
2272                 goto err_dealloc;
2273
2274         err = uverbs_copy_to(attrs,
2275                              MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
2276                              &page_idx, sizeof(page_idx));
2277         if (err)
2278                 goto err_dealloc;
2279
2280         bitmap_set(to_mucontext(context)->dm_pages, page_idx,
2281                    DIV_ROUND_UP(act_size, PAGE_SIZE));
2282
2283         dm->dev_addr = memic_addr;
2284
2285         return &dm->ibdm;
2286
2287 err_dealloc:
2288         mlx5_cmd_dealloc_memic(memic, memic_addr,
2289                                act_size);
2290 err_free:
2291         kfree(dm);
2292         return ERR_PTR(err);
2293 }
2294
2295 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm)
2296 {
2297         struct mlx5_memic *memic = &to_mdev(ibdm->device)->memic;
2298         struct mlx5_ib_dm *dm = to_mdm(ibdm);
2299         u64 act_size = roundup(dm->ibdm.length, MLX5_MEMIC_BASE_SIZE);
2300         u32 page_idx;
2301         int ret;
2302
2303         ret = mlx5_cmd_dealloc_memic(memic, dm->dev_addr, act_size);
2304         if (ret)
2305                 return ret;
2306
2307         page_idx = (dm->dev_addr - pci_resource_start(memic->dev->pdev, 0) -
2308                     MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2309                     PAGE_SHIFT;
2310         bitmap_clear(to_mucontext(ibdm->uobject->context)->dm_pages,
2311                      page_idx,
2312                      DIV_ROUND_UP(act_size, PAGE_SIZE));
2313
2314         kfree(dm);
2315
2316         return 0;
2317 }
2318
2319 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
2320                                       struct ib_ucontext *context,
2321                                       struct ib_udata *udata)
2322 {
2323         struct mlx5_ib_alloc_pd_resp resp;
2324         struct mlx5_ib_pd *pd;
2325         int err;
2326
2327         pd = kmalloc(sizeof(*pd), GFP_KERNEL);
2328         if (!pd)
2329                 return ERR_PTR(-ENOMEM);
2330
2331         err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
2332         if (err) {
2333                 kfree(pd);
2334                 return ERR_PTR(err);
2335         }
2336
2337         if (context) {
2338                 resp.pdn = pd->pdn;
2339                 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
2340                         mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
2341                         kfree(pd);
2342                         return ERR_PTR(-EFAULT);
2343                 }
2344         }
2345
2346         return &pd->ibpd;
2347 }
2348
2349 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
2350 {
2351         struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2352         struct mlx5_ib_pd *mpd = to_mpd(pd);
2353
2354         mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
2355         kfree(mpd);
2356
2357         return 0;
2358 }
2359
2360 enum {
2361         MATCH_CRITERIA_ENABLE_OUTER_BIT,
2362         MATCH_CRITERIA_ENABLE_MISC_BIT,
2363         MATCH_CRITERIA_ENABLE_INNER_BIT,
2364         MATCH_CRITERIA_ENABLE_MISC2_BIT
2365 };
2366
2367 #define HEADER_IS_ZERO(match_criteria, headers)                            \
2368         !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2369                     0, MLX5_FLD_SZ_BYTES(fte_match_param, headers)))       \
2370
2371 static u8 get_match_criteria_enable(u32 *match_criteria)
2372 {
2373         u8 match_criteria_enable;
2374
2375         match_criteria_enable =
2376                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2377                 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2378         match_criteria_enable |=
2379                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2380                 MATCH_CRITERIA_ENABLE_MISC_BIT;
2381         match_criteria_enable |=
2382                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2383                 MATCH_CRITERIA_ENABLE_INNER_BIT;
2384         match_criteria_enable |=
2385                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
2386                 MATCH_CRITERIA_ENABLE_MISC2_BIT;
2387
2388         return match_criteria_enable;
2389 }
2390
2391 static int set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
2392 {
2393         u8 entry_mask;
2394         u8 entry_val;
2395         int err = 0;
2396
2397         if (!mask)
2398                 goto out;
2399
2400         entry_mask = MLX5_GET(fte_match_set_lyr_2_4, outer_c,
2401                               ip_protocol);
2402         entry_val = MLX5_GET(fte_match_set_lyr_2_4, outer_v,
2403                              ip_protocol);
2404         if (!entry_mask) {
2405                 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2406                 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
2407                 goto out;
2408         }
2409         /* Don't override existing ip protocol */
2410         if (mask != entry_mask || val != entry_val)
2411                 err = -EINVAL;
2412 out:
2413         return err;
2414 }
2415
2416 static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val,
2417                            bool inner)
2418 {
2419         if (inner) {
2420                 MLX5_SET(fte_match_set_misc,
2421                          misc_c, inner_ipv6_flow_label, mask);
2422                 MLX5_SET(fte_match_set_misc,
2423                          misc_v, inner_ipv6_flow_label, val);
2424         } else {
2425                 MLX5_SET(fte_match_set_misc,
2426                          misc_c, outer_ipv6_flow_label, mask);
2427                 MLX5_SET(fte_match_set_misc,
2428                          misc_v, outer_ipv6_flow_label, val);
2429         }
2430 }
2431
2432 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2433 {
2434         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2435         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2436         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2437         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2438 }
2439
2440 static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask)
2441 {
2442         if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) &&
2443             !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL))
2444                 return -EOPNOTSUPP;
2445
2446         if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) &&
2447             !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP))
2448                 return -EOPNOTSUPP;
2449
2450         if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) &&
2451             !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS))
2452                 return -EOPNOTSUPP;
2453
2454         if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) &&
2455             !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL))
2456                 return -EOPNOTSUPP;
2457
2458         return 0;
2459 }
2460
2461 #define LAST_ETH_FIELD vlan_tag
2462 #define LAST_IB_FIELD sl
2463 #define LAST_IPV4_FIELD tos
2464 #define LAST_IPV6_FIELD traffic_class
2465 #define LAST_TCP_UDP_FIELD src_port
2466 #define LAST_TUNNEL_FIELD tunnel_id
2467 #define LAST_FLOW_TAG_FIELD tag_id
2468 #define LAST_DROP_FIELD size
2469 #define LAST_COUNTERS_FIELD counters
2470
2471 /* Field is the last supported field */
2472 #define FIELDS_NOT_SUPPORTED(filter, field)\
2473         memchr_inv((void *)&filter.field  +\
2474                    sizeof(filter.field), 0,\
2475                    sizeof(filter) -\
2476                    offsetof(typeof(filter), field) -\
2477                    sizeof(filter.field))
2478
2479 static int parse_flow_flow_action(const union ib_flow_spec *ib_spec,
2480                                   const struct ib_flow_attr *flow_attr,
2481                                   struct mlx5_flow_act *action)
2482 {
2483         struct mlx5_ib_flow_action *maction = to_mflow_act(ib_spec->action.act);
2484
2485         switch (maction->ib_action.type) {
2486         case IB_FLOW_ACTION_ESP:
2487                 /* Currently only AES_GCM keymat is supported by the driver */
2488                 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx;
2489                 action->action |= flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS ?
2490                         MLX5_FLOW_CONTEXT_ACTION_ENCRYPT :
2491                         MLX5_FLOW_CONTEXT_ACTION_DECRYPT;
2492                 return 0;
2493         default:
2494                 return -EOPNOTSUPP;
2495         }
2496 }
2497
2498 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
2499                            u32 *match_v, const union ib_flow_spec *ib_spec,
2500                            const struct ib_flow_attr *flow_attr,
2501                            struct mlx5_flow_act *action, u32 prev_type)
2502 {
2503         void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2504                                            misc_parameters);
2505         void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2506                                            misc_parameters);
2507         void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c,
2508                                             misc_parameters_2);
2509         void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v,
2510                                             misc_parameters_2);
2511         void *headers_c;
2512         void *headers_v;
2513         int match_ipv;
2514         int ret;
2515
2516         if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2517                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2518                                          inner_headers);
2519                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2520                                          inner_headers);
2521                 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2522                                         ft_field_support.inner_ip_version);
2523         } else {
2524                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2525                                          outer_headers);
2526                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2527                                          outer_headers);
2528                 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2529                                         ft_field_support.outer_ip_version);
2530         }
2531
2532         switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
2533         case IB_FLOW_SPEC_ETH:
2534                 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
2535                         return -EOPNOTSUPP;
2536
2537                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2538                                              dmac_47_16),
2539                                 ib_spec->eth.mask.dst_mac);
2540                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2541                                              dmac_47_16),
2542                                 ib_spec->eth.val.dst_mac);
2543
2544                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2545                                              smac_47_16),
2546                                 ib_spec->eth.mask.src_mac);
2547                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2548                                              smac_47_16),
2549                                 ib_spec->eth.val.src_mac);
2550
2551                 if (ib_spec->eth.mask.vlan_tag) {
2552                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2553                                  cvlan_tag, 1);
2554                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2555                                  cvlan_tag, 1);
2556
2557                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2558                                  first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2559                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2560                                  first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2561
2562                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2563                                  first_cfi,
2564                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2565                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2566                                  first_cfi,
2567                                  ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2568
2569                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2570                                  first_prio,
2571                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2572                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2573                                  first_prio,
2574                                  ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2575                 }
2576                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2577                          ethertype, ntohs(ib_spec->eth.mask.ether_type));
2578                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2579                          ethertype, ntohs(ib_spec->eth.val.ether_type));
2580                 break;
2581         case IB_FLOW_SPEC_IPV4:
2582                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
2583                         return -EOPNOTSUPP;
2584
2585                 if (match_ipv) {
2586                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2587                                  ip_version, 0xf);
2588                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2589                                  ip_version, MLX5_FS_IPV4_VERSION);
2590                 } else {
2591                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2592                                  ethertype, 0xffff);
2593                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2594                                  ethertype, ETH_P_IP);
2595                 }
2596
2597                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2598                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2599                        &ib_spec->ipv4.mask.src_ip,
2600                        sizeof(ib_spec->ipv4.mask.src_ip));
2601                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2602                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2603                        &ib_spec->ipv4.val.src_ip,
2604                        sizeof(ib_spec->ipv4.val.src_ip));
2605                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2606                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2607                        &ib_spec->ipv4.mask.dst_ip,
2608                        sizeof(ib_spec->ipv4.mask.dst_ip));
2609                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2610                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2611                        &ib_spec->ipv4.val.dst_ip,
2612                        sizeof(ib_spec->ipv4.val.dst_ip));
2613
2614                 set_tos(headers_c, headers_v,
2615                         ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2616
2617                 if (set_proto(headers_c, headers_v,
2618                               ib_spec->ipv4.mask.proto,
2619                               ib_spec->ipv4.val.proto))
2620                         return -EINVAL;
2621                 break;
2622         case IB_FLOW_SPEC_IPV6:
2623                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
2624                         return -EOPNOTSUPP;
2625
2626                 if (match_ipv) {
2627                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2628                                  ip_version, 0xf);
2629                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2630                                  ip_version, MLX5_FS_IPV6_VERSION);
2631                 } else {
2632                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2633                                  ethertype, 0xffff);
2634                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2635                                  ethertype, ETH_P_IPV6);
2636                 }
2637
2638                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2639                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2640                        &ib_spec->ipv6.mask.src_ip,
2641                        sizeof(ib_spec->ipv6.mask.src_ip));
2642                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2643                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2644                        &ib_spec->ipv6.val.src_ip,
2645                        sizeof(ib_spec->ipv6.val.src_ip));
2646                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2647                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2648                        &ib_spec->ipv6.mask.dst_ip,
2649                        sizeof(ib_spec->ipv6.mask.dst_ip));
2650                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2651                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2652                        &ib_spec->ipv6.val.dst_ip,
2653                        sizeof(ib_spec->ipv6.val.dst_ip));
2654
2655                 set_tos(headers_c, headers_v,
2656                         ib_spec->ipv6.mask.traffic_class,
2657                         ib_spec->ipv6.val.traffic_class);
2658
2659                 if (set_proto(headers_c, headers_v,
2660                               ib_spec->ipv6.mask.next_hdr,
2661                               ib_spec->ipv6.val.next_hdr))
2662                         return -EINVAL;
2663
2664                 set_flow_label(misc_params_c, misc_params_v,
2665                                ntohl(ib_spec->ipv6.mask.flow_label),
2666                                ntohl(ib_spec->ipv6.val.flow_label),
2667                                ib_spec->type & IB_FLOW_SPEC_INNER);
2668                 break;
2669         case IB_FLOW_SPEC_ESP:
2670                 if (ib_spec->esp.mask.seq)
2671                         return -EOPNOTSUPP;
2672
2673                 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi,
2674                          ntohl(ib_spec->esp.mask.spi));
2675                 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi,
2676                          ntohl(ib_spec->esp.val.spi));
2677                 break;
2678         case IB_FLOW_SPEC_TCP:
2679                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2680                                          LAST_TCP_UDP_FIELD))
2681                         return -EOPNOTSUPP;
2682
2683                 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_TCP))
2684                         return -EINVAL;
2685
2686                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
2687                          ntohs(ib_spec->tcp_udp.mask.src_port));
2688                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
2689                          ntohs(ib_spec->tcp_udp.val.src_port));
2690
2691                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
2692                          ntohs(ib_spec->tcp_udp.mask.dst_port));
2693                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
2694                          ntohs(ib_spec->tcp_udp.val.dst_port));
2695                 break;
2696         case IB_FLOW_SPEC_UDP:
2697                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2698                                          LAST_TCP_UDP_FIELD))
2699                         return -EOPNOTSUPP;
2700
2701                 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_UDP))
2702                         return -EINVAL;
2703
2704                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
2705                          ntohs(ib_spec->tcp_udp.mask.src_port));
2706                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
2707                          ntohs(ib_spec->tcp_udp.val.src_port));
2708
2709                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
2710                          ntohs(ib_spec->tcp_udp.mask.dst_port));
2711                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
2712                          ntohs(ib_spec->tcp_udp.val.dst_port));
2713                 break;
2714         case IB_FLOW_SPEC_GRE:
2715                 if (ib_spec->gre.mask.c_ks_res0_ver)
2716                         return -EOPNOTSUPP;
2717
2718                 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_GRE))
2719                         return -EINVAL;
2720
2721                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2722                          0xff);
2723                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2724                          IPPROTO_GRE);
2725
2726                 MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol,
2727                          ntohs(ib_spec->gre.mask.protocol));
2728                 MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol,
2729                          ntohs(ib_spec->gre.val.protocol));
2730
2731                 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c,
2732                                     gre_key_h),
2733                        &ib_spec->gre.mask.key,
2734                        sizeof(ib_spec->gre.mask.key));
2735                 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v,
2736                                     gre_key_h),
2737                        &ib_spec->gre.val.key,
2738                        sizeof(ib_spec->gre.val.key));
2739                 break;
2740         case IB_FLOW_SPEC_MPLS:
2741                 switch (prev_type) {
2742                 case IB_FLOW_SPEC_UDP:
2743                         if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2744                                                    ft_field_support.outer_first_mpls_over_udp),
2745                                                    &ib_spec->mpls.mask.tag))
2746                                 return -EOPNOTSUPP;
2747
2748                         memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2749                                             outer_first_mpls_over_udp),
2750                                &ib_spec->mpls.val.tag,
2751                                sizeof(ib_spec->mpls.val.tag));
2752                         memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2753                                             outer_first_mpls_over_udp),
2754                                &ib_spec->mpls.mask.tag,
2755                                sizeof(ib_spec->mpls.mask.tag));
2756                         break;
2757                 case IB_FLOW_SPEC_GRE:
2758                         if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2759                                                    ft_field_support.outer_first_mpls_over_gre),
2760                                                    &ib_spec->mpls.mask.tag))
2761                                 return -EOPNOTSUPP;
2762
2763                         memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2764                                             outer_first_mpls_over_gre),
2765                                &ib_spec->mpls.val.tag,
2766                                sizeof(ib_spec->mpls.val.tag));
2767                         memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2768                                             outer_first_mpls_over_gre),
2769                                &ib_spec->mpls.mask.tag,
2770                                sizeof(ib_spec->mpls.mask.tag));
2771                         break;
2772                 default:
2773                         if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2774                                 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2775                                                            ft_field_support.inner_first_mpls),
2776                                                            &ib_spec->mpls.mask.tag))
2777                                         return -EOPNOTSUPP;
2778
2779                                 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2780                                                     inner_first_mpls),
2781                                        &ib_spec->mpls.val.tag,
2782                                        sizeof(ib_spec->mpls.val.tag));
2783                                 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2784                                                     inner_first_mpls),
2785                                        &ib_spec->mpls.mask.tag,
2786                                        sizeof(ib_spec->mpls.mask.tag));
2787                         } else {
2788                                 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2789                                                            ft_field_support.outer_first_mpls),
2790                                                            &ib_spec->mpls.mask.tag))
2791                                         return -EOPNOTSUPP;
2792
2793                                 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2794                                                     outer_first_mpls),
2795                                        &ib_spec->mpls.val.tag,
2796                                        sizeof(ib_spec->mpls.val.tag));
2797                                 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2798                                                     outer_first_mpls),
2799                                        &ib_spec->mpls.mask.tag,
2800                                        sizeof(ib_spec->mpls.mask.tag));
2801                         }
2802                 }
2803                 break;
2804         case IB_FLOW_SPEC_VXLAN_TUNNEL:
2805                 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2806                                          LAST_TUNNEL_FIELD))
2807                         return -EOPNOTSUPP;
2808
2809                 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2810                          ntohl(ib_spec->tunnel.mask.tunnel_id));
2811                 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2812                          ntohl(ib_spec->tunnel.val.tunnel_id));
2813                 break;
2814         case IB_FLOW_SPEC_ACTION_TAG:
2815                 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2816                                          LAST_FLOW_TAG_FIELD))
2817                         return -EOPNOTSUPP;
2818                 if (ib_spec->flow_tag.tag_id >= BIT(24))
2819                         return -EINVAL;
2820
2821                 action->flow_tag = ib_spec->flow_tag.tag_id;
2822                 action->has_flow_tag = true;
2823                 break;
2824         case IB_FLOW_SPEC_ACTION_DROP:
2825                 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2826                                          LAST_DROP_FIELD))
2827                         return -EOPNOTSUPP;
2828                 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
2829                 break;
2830         case IB_FLOW_SPEC_ACTION_HANDLE:
2831                 ret = parse_flow_flow_action(ib_spec, flow_attr, action);
2832                 if (ret)
2833                         return ret;
2834                 break;
2835         case IB_FLOW_SPEC_ACTION_COUNT:
2836                 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count,
2837                                          LAST_COUNTERS_FIELD))
2838                         return -EOPNOTSUPP;
2839
2840                 /* for now support only one counters spec per flow */
2841                 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
2842                         return -EINVAL;
2843
2844                 action->counters = ib_spec->flow_count.counters;
2845                 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2846                 break;
2847         default:
2848                 return -EINVAL;
2849         }
2850
2851         return 0;
2852 }
2853
2854 /* If a flow could catch both multicast and unicast packets,
2855  * it won't fall into the multicast flow steering table and this rule
2856  * could steal other multicast packets.
2857  */
2858 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
2859 {
2860         union ib_flow_spec *flow_spec;
2861
2862         if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
2863             ib_attr->num_of_specs < 1)
2864                 return false;
2865
2866         flow_spec = (union ib_flow_spec *)(ib_attr + 1);
2867         if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
2868                 struct ib_flow_spec_ipv4 *ipv4_spec;
2869
2870                 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
2871                 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
2872                         return true;
2873
2874                 return false;
2875         }
2876
2877         if (flow_spec->type == IB_FLOW_SPEC_ETH) {
2878                 struct ib_flow_spec_eth *eth_spec;
2879
2880                 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
2881                 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2882                        is_multicast_ether_addr(eth_spec->val.dst_mac);
2883         }
2884
2885         return false;
2886 }
2887
2888 enum valid_spec {
2889         VALID_SPEC_INVALID,
2890         VALID_SPEC_VALID,
2891         VALID_SPEC_NA,
2892 };
2893
2894 static enum valid_spec
2895 is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev,
2896                      const struct mlx5_flow_spec *spec,
2897                      const struct mlx5_flow_act *flow_act,
2898                      bool egress)
2899 {
2900         const u32 *match_c = spec->match_criteria;
2901         bool is_crypto =
2902                 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2903                                      MLX5_FLOW_CONTEXT_ACTION_DECRYPT));
2904         bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c);
2905         bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP;
2906
2907         /*
2908          * Currently only crypto is supported in egress, when regular egress
2909          * rules would be supported, always return VALID_SPEC_NA.
2910          */
2911         if (!is_crypto)
2912                 return egress ? VALID_SPEC_INVALID : VALID_SPEC_NA;
2913
2914         return is_crypto && is_ipsec &&
2915                 (!egress || (!is_drop && !flow_act->has_flow_tag)) ?
2916                 VALID_SPEC_VALID : VALID_SPEC_INVALID;
2917 }
2918
2919 static bool is_valid_spec(struct mlx5_core_dev *mdev,
2920                           const struct mlx5_flow_spec *spec,
2921                           const struct mlx5_flow_act *flow_act,
2922                           bool egress)
2923 {
2924         /* We curretly only support ipsec egress flow */
2925         return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID;
2926 }
2927
2928 static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2929                                const struct ib_flow_attr *flow_attr,
2930                                bool check_inner)
2931 {
2932         union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
2933         int match_ipv = check_inner ?
2934                         MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2935                                         ft_field_support.inner_ip_version) :
2936                         MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2937                                         ft_field_support.outer_ip_version);
2938         int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2939         bool ipv4_spec_valid, ipv6_spec_valid;
2940         unsigned int ip_spec_type = 0;
2941         bool has_ethertype = false;
2942         unsigned int spec_index;
2943         bool mask_valid = true;
2944         u16 eth_type = 0;
2945         bool type_valid;
2946
2947         /* Validate that ethertype is correct */
2948         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2949                 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
2950                     ib_spec->eth.mask.ether_type) {
2951                         mask_valid = (ib_spec->eth.mask.ether_type ==
2952                                       htons(0xffff));
2953                         has_ethertype = true;
2954                         eth_type = ntohs(ib_spec->eth.val.ether_type);
2955                 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2956                            (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2957                         ip_spec_type = ib_spec->type;
2958                 }
2959                 ib_spec = (void *)ib_spec + ib_spec->size;
2960         }
2961
2962         type_valid = (!has_ethertype) || (!ip_spec_type);
2963         if (!type_valid && mask_valid) {
2964                 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2965                         (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2966                 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2967                         (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
2968
2969                 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2970                              (((eth_type == ETH_P_MPLS_UC) ||
2971                                (eth_type == ETH_P_MPLS_MC)) && match_ipv);
2972         }
2973
2974         return type_valid;
2975 }
2976
2977 static bool is_valid_attr(struct mlx5_core_dev *mdev,
2978                           const struct ib_flow_attr *flow_attr)
2979 {
2980         return is_valid_ethertype(mdev, flow_attr, false) &&
2981                is_valid_ethertype(mdev, flow_attr, true);
2982 }
2983
2984 static void put_flow_table(struct mlx5_ib_dev *dev,
2985                            struct mlx5_ib_flow_prio *prio, bool ft_added)
2986 {
2987         prio->refcount -= !!ft_added;
2988         if (!prio->refcount) {
2989                 mlx5_destroy_flow_table(prio->flow_table);
2990                 prio->flow_table = NULL;
2991         }
2992 }
2993
2994 static void counters_clear_description(struct ib_counters *counters)
2995 {
2996         struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
2997
2998         mutex_lock(&mcounters->mcntrs_mutex);
2999         kfree(mcounters->counters_data);
3000         mcounters->counters_data = NULL;
3001         mcounters->cntrs_max_index = 0;
3002         mutex_unlock(&mcounters->mcntrs_mutex);
3003 }
3004
3005 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
3006 {
3007         struct mlx5_ib_flow_handler *handler = container_of(flow_id,
3008                                                           struct mlx5_ib_flow_handler,
3009                                                           ibflow);
3010         struct mlx5_ib_flow_handler *iter, *tmp;
3011         struct mlx5_ib_dev *dev = handler->dev;
3012
3013         mutex_lock(&dev->flow_db->lock);
3014
3015         list_for_each_entry_safe(iter, tmp, &handler->list, list) {
3016                 mlx5_del_flow_rules(iter->rule);
3017                 put_flow_table(dev, iter->prio, true);
3018                 list_del(&iter->list);
3019                 kfree(iter);
3020         }
3021
3022         mlx5_del_flow_rules(handler->rule);
3023         put_flow_table(dev, handler->prio, true);
3024         if (handler->ibcounters &&
3025             atomic_read(&handler->ibcounters->usecnt) == 1)
3026                 counters_clear_description(handler->ibcounters);
3027
3028         mutex_unlock(&dev->flow_db->lock);
3029         if (handler->flow_matcher)
3030                 atomic_dec(&handler->flow_matcher->usecnt);
3031         kfree(handler);
3032
3033         return 0;
3034 }
3035
3036 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
3037 {
3038         priority *= 2;
3039         if (!dont_trap)
3040                 priority++;
3041         return priority;
3042 }
3043
3044 enum flow_table_type {
3045         MLX5_IB_FT_RX,
3046         MLX5_IB_FT_TX
3047 };
3048
3049 #define MLX5_FS_MAX_TYPES        6
3050 #define MLX5_FS_MAX_ENTRIES      BIT(16)
3051
3052 static struct mlx5_ib_flow_prio *_get_prio(struct mlx5_flow_namespace *ns,
3053                                            struct mlx5_ib_flow_prio *prio,
3054                                            int priority,
3055                                            int num_entries, int num_groups)
3056 {
3057         struct mlx5_flow_table *ft;
3058
3059         ft = mlx5_create_auto_grouped_flow_table(ns, priority,
3060                                                  num_entries,
3061                                                  num_groups,
3062                                                  0, 0);
3063         if (IS_ERR(ft))
3064                 return ERR_CAST(ft);
3065
3066         prio->flow_table = ft;
3067         prio->refcount = 0;
3068         return prio;
3069 }
3070
3071 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
3072                                                 struct ib_flow_attr *flow_attr,
3073                                                 enum flow_table_type ft_type)
3074 {
3075         bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
3076         struct mlx5_flow_namespace *ns = NULL;
3077         struct mlx5_ib_flow_prio *prio;
3078         struct mlx5_flow_table *ft;
3079         int max_table_size;
3080         int num_entries;
3081         int num_groups;
3082         int priority;
3083
3084         max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3085                                                        log_max_ft_size));
3086         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
3087                 if (ft_type == MLX5_IB_FT_TX)
3088                         priority = 0;
3089                 else if (flow_is_multicast_only(flow_attr) &&
3090                          !dont_trap)
3091                         priority = MLX5_IB_FLOW_MCAST_PRIO;
3092                 else
3093                         priority = ib_prio_to_core_prio(flow_attr->priority,
3094                                                         dont_trap);
3095                 ns = mlx5_get_flow_namespace(dev->mdev,
3096                                              ft_type == MLX5_IB_FT_TX ?
3097                                              MLX5_FLOW_NAMESPACE_EGRESS :
3098                                              MLX5_FLOW_NAMESPACE_BYPASS);
3099                 num_entries = MLX5_FS_MAX_ENTRIES;
3100                 num_groups = MLX5_FS_MAX_TYPES;
3101                 prio = &dev->flow_db->prios[priority];
3102         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3103                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3104                 ns = mlx5_get_flow_namespace(dev->mdev,
3105                                              MLX5_FLOW_NAMESPACE_LEFTOVERS);
3106                 build_leftovers_ft_param(&priority,
3107                                          &num_entries,
3108                                          &num_groups);
3109                 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
3110         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3111                 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
3112                                         allow_sniffer_and_nic_rx_shared_tir))
3113                         return ERR_PTR(-ENOTSUPP);
3114
3115                 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
3116                                              MLX5_FLOW_NAMESPACE_SNIFFER_RX :
3117                                              MLX5_FLOW_NAMESPACE_SNIFFER_TX);
3118
3119                 prio = &dev->flow_db->sniffer[ft_type];
3120                 priority = 0;
3121                 num_entries = 1;
3122                 num_groups = 1;
3123         }
3124
3125         if (!ns)
3126                 return ERR_PTR(-ENOTSUPP);
3127
3128         if (num_entries > max_table_size)
3129                 return ERR_PTR(-ENOMEM);
3130
3131         ft = prio->flow_table;
3132         if (!ft)
3133                 return _get_prio(ns, prio, priority, num_entries, num_groups);
3134
3135         return prio;
3136 }
3137
3138 static void set_underlay_qp(struct mlx5_ib_dev *dev,
3139                             struct mlx5_flow_spec *spec,
3140                             u32 underlay_qpn)
3141 {
3142         void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
3143                                            spec->match_criteria,
3144                                            misc_parameters);
3145         void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3146                                            misc_parameters);
3147
3148         if (underlay_qpn &&
3149             MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3150                                       ft_field_support.bth_dst_qp)) {
3151                 MLX5_SET(fte_match_set_misc,
3152                          misc_params_v, bth_dst_qp, underlay_qpn);
3153                 MLX5_SET(fte_match_set_misc,
3154                          misc_params_c, bth_dst_qp, 0xffffff);
3155         }
3156 }
3157
3158 static int read_flow_counters(struct ib_device *ibdev,
3159                               struct mlx5_read_counters_attr *read_attr)
3160 {
3161         struct mlx5_fc *fc = read_attr->hw_cntrs_hndl;
3162         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3163
3164         return mlx5_fc_query(dev->mdev, fc,
3165                              &read_attr->out[IB_COUNTER_PACKETS],
3166                              &read_attr->out[IB_COUNTER_BYTES]);
3167 }
3168
3169 /* flow counters currently expose two counters packets and bytes */
3170 #define FLOW_COUNTERS_NUM 2
3171 static int counters_set_description(struct ib_counters *counters,
3172                                     enum mlx5_ib_counters_type counters_type,
3173                                     struct mlx5_ib_flow_counters_desc *desc_data,
3174                                     u32 ncounters)
3175 {
3176         struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3177         u32 cntrs_max_index = 0;
3178         int i;
3179
3180         if (counters_type != MLX5_IB_COUNTERS_FLOW)
3181                 return -EINVAL;
3182
3183         /* init the fields for the object */
3184         mcounters->type = counters_type;
3185         mcounters->read_counters = read_flow_counters;
3186         mcounters->counters_num = FLOW_COUNTERS_NUM;
3187         mcounters->ncounters = ncounters;
3188         /* each counter entry have both description and index pair */
3189         for (i = 0; i < ncounters; i++) {
3190                 if (desc_data[i].description > IB_COUNTER_BYTES)
3191                         return -EINVAL;
3192
3193                 if (cntrs_max_index <= desc_data[i].index)
3194                         cntrs_max_index = desc_data[i].index + 1;
3195         }
3196
3197         mutex_lock(&mcounters->mcntrs_mutex);
3198         mcounters->counters_data = desc_data;
3199         mcounters->cntrs_max_index = cntrs_max_index;
3200         mutex_unlock(&mcounters->mcntrs_mutex);
3201
3202         return 0;
3203 }
3204
3205 #define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2))
3206 static int flow_counters_set_data(struct ib_counters *ibcounters,
3207                                   struct mlx5_ib_create_flow *ucmd)
3208 {
3209         struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters);
3210         struct mlx5_ib_flow_counters_data *cntrs_data = NULL;
3211         struct mlx5_ib_flow_counters_desc *desc_data = NULL;
3212         bool hw_hndl = false;
3213         int ret = 0;
3214
3215         if (ucmd && ucmd->ncounters_data != 0) {
3216                 cntrs_data = ucmd->data;
3217                 if (cntrs_data->ncounters > MAX_COUNTERS_NUM)
3218                         return -EINVAL;
3219
3220                 desc_data = kcalloc(cntrs_data->ncounters,
3221                                     sizeof(*desc_data),
3222                                     GFP_KERNEL);
3223                 if (!desc_data)
3224                         return  -ENOMEM;
3225
3226                 if (copy_from_user(desc_data,
3227                                    u64_to_user_ptr(cntrs_data->counters_data),
3228                                    sizeof(*desc_data) * cntrs_data->ncounters)) {
3229                         ret = -EFAULT;
3230                         goto free;
3231                 }
3232         }
3233
3234         if (!mcounters->hw_cntrs_hndl) {
3235                 mcounters->hw_cntrs_hndl = mlx5_fc_create(
3236                         to_mdev(ibcounters->device)->mdev, false);
3237                 if (IS_ERR(mcounters->hw_cntrs_hndl)) {
3238                         ret = PTR_ERR(mcounters->hw_cntrs_hndl);
3239                         goto free;
3240                 }
3241                 hw_hndl = true;
3242         }
3243
3244         if (desc_data) {
3245                 /* counters already bound to at least one flow */
3246                 if (mcounters->cntrs_max_index) {
3247                         ret = -EINVAL;
3248                         goto free_hndl;
3249                 }
3250
3251                 ret = counters_set_description(ibcounters,
3252                                                MLX5_IB_COUNTERS_FLOW,
3253                                                desc_data,
3254                                                cntrs_data->ncounters);
3255                 if (ret)
3256                         goto free_hndl;
3257
3258         } else if (!mcounters->cntrs_max_index) {
3259                 /* counters not bound yet, must have udata passed */
3260                 ret = -EINVAL;
3261                 goto free_hndl;
3262         }
3263
3264         return 0;
3265
3266 free_hndl:
3267         if (hw_hndl) {
3268                 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev,
3269                                 mcounters->hw_cntrs_hndl);
3270                 mcounters->hw_cntrs_hndl = NULL;
3271         }
3272 free:
3273         kfree(desc_data);
3274         return ret;
3275 }
3276
3277 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
3278                                                       struct mlx5_ib_flow_prio *ft_prio,
3279                                                       const struct ib_flow_attr *flow_attr,
3280                                                       struct mlx5_flow_destination *dst,
3281                                                       u32 underlay_qpn,
3282                                                       struct mlx5_ib_create_flow *ucmd)
3283 {
3284         struct mlx5_flow_table  *ft = ft_prio->flow_table;
3285         struct mlx5_ib_flow_handler *handler;
3286         struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG};
3287         struct mlx5_flow_spec *spec;
3288         struct mlx5_flow_destination dest_arr[2] = {};
3289         struct mlx5_flow_destination *rule_dst = dest_arr;
3290         const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
3291         unsigned int spec_index;
3292         u32 prev_type = 0;
3293         int err = 0;
3294         int dest_num = 0;
3295         bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3296
3297         if (!is_valid_attr(dev->mdev, flow_attr))
3298                 return ERR_PTR(-EINVAL);
3299
3300         spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
3301         handler = kzalloc(sizeof(*handler), GFP_KERNEL);
3302         if (!handler || !spec) {
3303                 err = -ENOMEM;
3304                 goto free;
3305         }
3306
3307         INIT_LIST_HEAD(&handler->list);
3308
3309         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
3310                 err = parse_flow_attr(dev->mdev, spec->match_criteria,
3311                                       spec->match_value,
3312                                       ib_flow, flow_attr, &flow_act,
3313                                       prev_type);
3314                 if (err < 0)
3315                         goto free;
3316
3317                 prev_type = ((union ib_flow_spec *)ib_flow)->type;
3318                 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
3319         }
3320
3321         if (dst && !(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP)) {
3322                 memcpy(&dest_arr[0], dst, sizeof(*dst));
3323                 dest_num++;
3324         }
3325
3326         if (!flow_is_multicast_only(flow_attr))
3327                 set_underlay_qp(dev, spec, underlay_qpn);
3328
3329         if (dev->rep) {
3330                 void *misc;
3331
3332                 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3333                                     misc_parameters);
3334                 MLX5_SET(fte_match_set_misc, misc, source_port,
3335                          dev->rep->vport);
3336                 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3337                                     misc_parameters);
3338                 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3339         }
3340
3341         spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
3342
3343         if (is_egress &&
3344             !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) {
3345                 err = -EINVAL;
3346                 goto free;
3347         }
3348
3349         if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
3350                 err = flow_counters_set_data(flow_act.counters, ucmd);
3351                 if (err)
3352                         goto free;
3353
3354                 handler->ibcounters = flow_act.counters;
3355                 dest_arr[dest_num].type =
3356                         MLX5_FLOW_DESTINATION_TYPE_COUNTER;
3357                 dest_arr[dest_num].counter =
3358                         to_mcounters(flow_act.counters)->hw_cntrs_hndl;
3359                 dest_num++;
3360         }
3361
3362         if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) {
3363                 if (!dest_num)
3364                         rule_dst = NULL;
3365         } else {
3366                 if (is_egress)
3367                         flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
3368                 else
3369                         flow_act.action |=
3370                                 dest_num ?  MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
3371                                         MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
3372         }
3373
3374         if (flow_act.has_flow_tag &&
3375             (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3376              flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3377                 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
3378                              flow_act.flow_tag, flow_attr->type);
3379                 err = -EINVAL;
3380                 goto free;
3381         }
3382         handler->rule = mlx5_add_flow_rules(ft, spec,
3383                                             &flow_act,
3384                                             rule_dst, dest_num);
3385
3386         if (IS_ERR(handler->rule)) {
3387                 err = PTR_ERR(handler->rule);
3388                 goto free;
3389         }
3390
3391         ft_prio->refcount++;
3392         handler->prio = ft_prio;
3393         handler->dev = dev;
3394
3395         ft_prio->flow_table = ft;
3396 free:
3397         if (err && handler) {
3398                 if (handler->ibcounters &&
3399                     atomic_read(&handler->ibcounters->usecnt) == 1)
3400                         counters_clear_description(handler->ibcounters);
3401                 kfree(handler);
3402         }
3403         kvfree(spec);
3404         return err ? ERR_PTR(err) : handler;
3405 }
3406
3407 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
3408                                                      struct mlx5_ib_flow_prio *ft_prio,
3409                                                      const struct ib_flow_attr *flow_attr,
3410                                                      struct mlx5_flow_destination *dst)
3411 {
3412         return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL);
3413 }
3414
3415 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
3416                                                           struct mlx5_ib_flow_prio *ft_prio,
3417                                                           struct ib_flow_attr *flow_attr,
3418                                                           struct mlx5_flow_destination *dst)
3419 {
3420         struct mlx5_ib_flow_handler *handler_dst = NULL;
3421         struct mlx5_ib_flow_handler *handler = NULL;
3422
3423         handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
3424         if (!IS_ERR(handler)) {
3425                 handler_dst = create_flow_rule(dev, ft_prio,
3426                                                flow_attr, dst);
3427                 if (IS_ERR(handler_dst)) {
3428                         mlx5_del_flow_rules(handler->rule);
3429                         ft_prio->refcount--;
3430                         kfree(handler);
3431                         handler = handler_dst;
3432                 } else {
3433                         list_add(&handler_dst->list, &handler->list);
3434                 }
3435         }
3436
3437         return handler;
3438 }
3439 enum {
3440         LEFTOVERS_MC,
3441         LEFTOVERS_UC,
3442 };
3443
3444 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
3445                                                           struct mlx5_ib_flow_prio *ft_prio,
3446                                                           struct ib_flow_attr *flow_attr,
3447                                                           struct mlx5_flow_destination *dst)
3448 {
3449         struct mlx5_ib_flow_handler *handler_ucast = NULL;
3450         struct mlx5_ib_flow_handler *handler = NULL;
3451
3452         static struct {
3453                 struct ib_flow_attr     flow_attr;
3454                 struct ib_flow_spec_eth eth_flow;
3455         } leftovers_specs[] = {
3456                 [LEFTOVERS_MC] = {
3457                         .flow_attr = {
3458                                 .num_of_specs = 1,
3459                                 .size = sizeof(leftovers_specs[0])
3460                         },
3461                         .eth_flow = {
3462                                 .type = IB_FLOW_SPEC_ETH,
3463                                 .size = sizeof(struct ib_flow_spec_eth),
3464                                 .mask = {.dst_mac = {0x1} },
3465                                 .val =  {.dst_mac = {0x1} }
3466                         }
3467                 },
3468                 [LEFTOVERS_UC] = {
3469                         .flow_attr = {
3470                                 .num_of_specs = 1,
3471                                 .size = sizeof(leftovers_specs[0])
3472                         },
3473                         .eth_flow = {
3474                                 .type = IB_FLOW_SPEC_ETH,
3475                                 .size = sizeof(struct ib_flow_spec_eth),
3476                                 .mask = {.dst_mac = {0x1} },
3477                                 .val = {.dst_mac = {} }
3478                         }
3479                 }
3480         };
3481
3482         handler = create_flow_rule(dev, ft_prio,
3483                                    &leftovers_specs[LEFTOVERS_MC].flow_attr,
3484                                    dst);
3485         if (!IS_ERR(handler) &&
3486             flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
3487                 handler_ucast = create_flow_rule(dev, ft_prio,
3488                                                  &leftovers_specs[LEFTOVERS_UC].flow_attr,
3489                                                  dst);
3490                 if (IS_ERR(handler_ucast)) {
3491                         mlx5_del_flow_rules(handler->rule);
3492                         ft_prio->refcount--;
3493                         kfree(handler);
3494                         handler = handler_ucast;
3495                 } else {
3496                         list_add(&handler_ucast->list, &handler->list);
3497                 }
3498         }
3499
3500         return handler;
3501 }
3502
3503 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
3504                                                         struct mlx5_ib_flow_prio *ft_rx,
3505                                                         struct mlx5_ib_flow_prio *ft_tx,
3506                                                         struct mlx5_flow_destination *dst)
3507 {
3508         struct mlx5_ib_flow_handler *handler_rx;
3509         struct mlx5_ib_flow_handler *handler_tx;
3510         int err;
3511         static const struct ib_flow_attr flow_attr  = {
3512                 .num_of_specs = 0,
3513                 .size = sizeof(flow_attr)
3514         };
3515
3516         handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
3517         if (IS_ERR(handler_rx)) {
3518                 err = PTR_ERR(handler_rx);
3519                 goto err;
3520         }
3521
3522         handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
3523         if (IS_ERR(handler_tx)) {
3524                 err = PTR_ERR(handler_tx);
3525                 goto err_tx;
3526         }
3527
3528         list_add(&handler_tx->list, &handler_rx->list);
3529
3530         return handler_rx;
3531
3532 err_tx:
3533         mlx5_del_flow_rules(handler_rx->rule);
3534         ft_rx->refcount--;
3535         kfree(handler_rx);
3536 err:
3537         return ERR_PTR(err);
3538 }
3539
3540 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
3541                                            struct ib_flow_attr *flow_attr,
3542                                            int domain,
3543                                            struct ib_udata *udata)
3544 {
3545         struct mlx5_ib_dev *dev = to_mdev(qp->device);
3546         struct mlx5_ib_qp *mqp = to_mqp(qp);
3547         struct mlx5_ib_flow_handler *handler = NULL;
3548         struct mlx5_flow_destination *dst = NULL;
3549         struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
3550         struct mlx5_ib_flow_prio *ft_prio;
3551         bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3552         struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr;
3553         size_t min_ucmd_sz, required_ucmd_sz;
3554         int err;
3555         int underlay_qpn;
3556
3557         if (udata && udata->inlen) {
3558                 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) +
3559                                 sizeof(ucmd_hdr.reserved);
3560                 if (udata->inlen < min_ucmd_sz)
3561                         return ERR_PTR(-EOPNOTSUPP);
3562
3563                 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz);
3564                 if (err)
3565                         return ERR_PTR(err);
3566
3567                 /* currently supports only one counters data */
3568                 if (ucmd_hdr.ncounters_data > 1)
3569                         return ERR_PTR(-EINVAL);
3570
3571                 required_ucmd_sz = min_ucmd_sz +
3572                         sizeof(struct mlx5_ib_flow_counters_data) *
3573                         ucmd_hdr.ncounters_data;
3574                 if (udata->inlen > required_ucmd_sz &&
3575                     !ib_is_udata_cleared(udata, required_ucmd_sz,
3576                                          udata->inlen - required_ucmd_sz))
3577                         return ERR_PTR(-EOPNOTSUPP);
3578
3579                 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL);
3580                 if (!ucmd)
3581                         return ERR_PTR(-ENOMEM);
3582
3583                 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz);
3584                 if (err)
3585                         goto free_ucmd;
3586         }
3587
3588         if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) {
3589                 err = -ENOMEM;
3590                 goto free_ucmd;
3591         }
3592
3593         if (domain != IB_FLOW_DOMAIN_USER ||
3594             flow_attr->port > dev->num_ports ||
3595             (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP |
3596                                   IB_FLOW_ATTR_FLAGS_EGRESS))) {
3597                 err = -EINVAL;
3598                 goto free_ucmd;
3599         }
3600
3601         if (is_egress &&
3602             (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3603              flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3604                 err = -EINVAL;
3605                 goto free_ucmd;
3606         }
3607
3608         dst = kzalloc(sizeof(*dst), GFP_KERNEL);
3609         if (!dst) {
3610                 err = -ENOMEM;
3611                 goto free_ucmd;
3612         }
3613
3614         mutex_lock(&dev->flow_db->lock);
3615
3616         ft_prio = get_flow_table(dev, flow_attr,
3617                                  is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX);
3618         if (IS_ERR(ft_prio)) {
3619                 err = PTR_ERR(ft_prio);
3620                 goto unlock;
3621         }
3622         if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3623                 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3624                 if (IS_ERR(ft_prio_tx)) {
3625                         err = PTR_ERR(ft_prio_tx);
3626                         ft_prio_tx = NULL;
3627                         goto destroy_ft;
3628                 }
3629         }
3630
3631         if (is_egress) {
3632                 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3633         } else {
3634                 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
3635                 if (mqp->flags & MLX5_IB_QP_RSS)
3636                         dst->tir_num = mqp->rss_qp.tirn;
3637                 else
3638                         dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3639         }
3640
3641         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
3642                 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)  {
3643                         handler = create_dont_trap_rule(dev, ft_prio,
3644                                                         flow_attr, dst);
3645                 } else {
3646                         underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3647                                         mqp->underlay_qpn : 0;
3648                         handler = _create_flow_rule(dev, ft_prio, flow_attr,
3649                                                     dst, underlay_qpn, ucmd);
3650                 }
3651         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3652                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3653                 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3654                                                 dst);
3655         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3656                 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
3657         } else {
3658                 err = -EINVAL;
3659                 goto destroy_ft;
3660         }
3661
3662         if (IS_ERR(handler)) {
3663                 err = PTR_ERR(handler);
3664                 handler = NULL;
3665                 goto destroy_ft;
3666         }
3667
3668         mutex_unlock(&dev->flow_db->lock);
3669         kfree(dst);
3670         kfree(ucmd);
3671
3672         return &handler->ibflow;
3673
3674 destroy_ft:
3675         put_flow_table(dev, ft_prio, false);
3676         if (ft_prio_tx)
3677                 put_flow_table(dev, ft_prio_tx, false);
3678 unlock:
3679         mutex_unlock(&dev->flow_db->lock);
3680         kfree(dst);
3681 free_ucmd:
3682         kfree(ucmd);
3683         return ERR_PTR(err);
3684 }
3685
3686 static struct mlx5_ib_flow_prio *_get_flow_table(struct mlx5_ib_dev *dev,
3687                                                  int priority, bool mcast)
3688 {
3689         int max_table_size;
3690         struct mlx5_flow_namespace *ns = NULL;
3691         struct mlx5_ib_flow_prio *prio;
3692
3693         max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3694                              log_max_ft_size));
3695         if (max_table_size < MLX5_FS_MAX_ENTRIES)
3696                 return ERR_PTR(-ENOMEM);
3697
3698         if (mcast)
3699                 priority = MLX5_IB_FLOW_MCAST_PRIO;
3700         else
3701                 priority = ib_prio_to_core_prio(priority, false);
3702
3703         ns = mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS);
3704         if (!ns)
3705                 return ERR_PTR(-ENOTSUPP);
3706
3707         prio = &dev->flow_db->prios[priority];
3708
3709         if (prio->flow_table)
3710                 return prio;
3711
3712         return _get_prio(ns, prio, priority, MLX5_FS_MAX_ENTRIES,
3713                          MLX5_FS_MAX_TYPES);
3714 }
3715
3716 static struct mlx5_ib_flow_handler *
3717 _create_raw_flow_rule(struct mlx5_ib_dev *dev,
3718                       struct mlx5_ib_flow_prio *ft_prio,
3719                       struct mlx5_flow_destination *dst,
3720                       struct mlx5_ib_flow_matcher  *fs_matcher,
3721                       void *cmd_in, int inlen)
3722 {
3723         struct mlx5_ib_flow_handler *handler;
3724         struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG};
3725         struct mlx5_flow_spec *spec;
3726         struct mlx5_flow_table *ft = ft_prio->flow_table;
3727         int err = 0;
3728
3729         spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
3730         handler = kzalloc(sizeof(*handler), GFP_KERNEL);
3731         if (!handler || !spec) {
3732                 err = -ENOMEM;
3733                 goto free;
3734         }
3735
3736         INIT_LIST_HEAD(&handler->list);
3737
3738         memcpy(spec->match_value, cmd_in, inlen);
3739         memcpy(spec->match_criteria, fs_matcher->matcher_mask.match_params,
3740                fs_matcher->mask_len);
3741         spec->match_criteria_enable = fs_matcher->match_criteria_enable;
3742
3743         flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3744         handler->rule = mlx5_add_flow_rules(ft, spec,
3745                                             &flow_act, dst, 1);
3746
3747         if (IS_ERR(handler->rule)) {
3748                 err = PTR_ERR(handler->rule);
3749                 goto free;
3750         }
3751
3752         ft_prio->refcount++;
3753         handler->prio = ft_prio;
3754         handler->dev = dev;
3755         ft_prio->flow_table = ft;
3756
3757 free:
3758         if (err)
3759                 kfree(handler);
3760         kvfree(spec);
3761         return err ? ERR_PTR(err) : handler;
3762 }
3763
3764 static bool raw_fs_is_multicast(struct mlx5_ib_flow_matcher *fs_matcher,
3765                                 void *match_v)
3766 {
3767         void *match_c;
3768         void *match_v_set_lyr_2_4, *match_c_set_lyr_2_4;
3769         void *dmac, *dmac_mask;
3770         void *ipv4, *ipv4_mask;
3771
3772         if (!(fs_matcher->match_criteria_enable &
3773               (1 << MATCH_CRITERIA_ENABLE_OUTER_BIT)))
3774                 return false;
3775
3776         match_c = fs_matcher->matcher_mask.match_params;
3777         match_v_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_v,
3778                                            outer_headers);
3779         match_c_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_c,
3780                                            outer_headers);
3781
3782         dmac = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
3783                             dmac_47_16);
3784         dmac_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
3785                                  dmac_47_16);
3786
3787         if (is_multicast_ether_addr(dmac) &&
3788             is_multicast_ether_addr(dmac_mask))
3789                 return true;
3790
3791         ipv4 = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
3792                             dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
3793
3794         ipv4_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
3795                                  dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
3796
3797         if (ipv4_is_multicast(*(__be32 *)(ipv4)) &&
3798             ipv4_is_multicast(*(__be32 *)(ipv4_mask)))
3799                 return true;
3800
3801         return false;
3802 }
3803
3804 struct mlx5_ib_flow_handler *
3805 mlx5_ib_raw_fs_rule_add(struct mlx5_ib_dev *dev,
3806                         struct mlx5_ib_flow_matcher *fs_matcher,
3807                         void *cmd_in, int inlen, int dest_id,
3808                         int dest_type)
3809 {
3810         struct mlx5_flow_destination *dst;
3811         struct mlx5_ib_flow_prio *ft_prio;
3812         int priority = fs_matcher->priority;
3813         struct mlx5_ib_flow_handler *handler;
3814         bool mcast;
3815         int err;
3816
3817         if (fs_matcher->flow_type != MLX5_IB_FLOW_TYPE_NORMAL)
3818                 return ERR_PTR(-EOPNOTSUPP);
3819
3820         if (fs_matcher->priority > MLX5_IB_FLOW_LAST_PRIO)
3821                 return ERR_PTR(-ENOMEM);
3822
3823         dst = kzalloc(sizeof(*dst), GFP_KERNEL);
3824         if (!dst)
3825                 return ERR_PTR(-ENOMEM);
3826
3827         mcast = raw_fs_is_multicast(fs_matcher, cmd_in);
3828         mutex_lock(&dev->flow_db->lock);
3829
3830         ft_prio = _get_flow_table(dev, priority, mcast);
3831         if (IS_ERR(ft_prio)) {
3832                 err = PTR_ERR(ft_prio);
3833                 goto unlock;
3834         }
3835
3836         if (dest_type == MLX5_FLOW_DESTINATION_TYPE_TIR) {
3837                 dst->type = dest_type;
3838                 dst->tir_num = dest_id;
3839         } else {
3840                 dst->type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM;
3841                 dst->ft_num = dest_id;
3842         }
3843
3844         handler = _create_raw_flow_rule(dev, ft_prio, dst, fs_matcher, cmd_in,
3845                                         inlen);
3846
3847         if (IS_ERR(handler)) {
3848                 err = PTR_ERR(handler);
3849                 goto destroy_ft;
3850         }
3851
3852         mutex_unlock(&dev->flow_db->lock);
3853         atomic_inc(&fs_matcher->usecnt);
3854         handler->flow_matcher = fs_matcher;
3855
3856         kfree(dst);
3857
3858         return handler;
3859
3860 destroy_ft:
3861         put_flow_table(dev, ft_prio, false);
3862 unlock:
3863         mutex_unlock(&dev->flow_db->lock);
3864         kfree(dst);
3865
3866         return ERR_PTR(err);
3867 }
3868
3869 static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags)
3870 {
3871         u32 flags = 0;
3872
3873         if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA)
3874                 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA;
3875
3876         return flags;
3877 }
3878
3879 #define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED      MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA
3880 static struct ib_flow_action *
3881 mlx5_ib_create_flow_action_esp(struct ib_device *device,
3882                                const struct ib_flow_action_attrs_esp *attr,
3883                                struct uverbs_attr_bundle *attrs)
3884 {
3885         struct mlx5_ib_dev *mdev = to_mdev(device);
3886         struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm;
3887         struct mlx5_accel_esp_xfrm_attrs accel_attrs = {};
3888         struct mlx5_ib_flow_action *action;
3889         u64 action_flags;
3890         u64 flags;
3891         int err = 0;
3892
3893         err = uverbs_get_flags64(
3894                 &action_flags, attrs, MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
3895                 ((MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1) - 1));
3896         if (err)
3897                 return ERR_PTR(err);
3898
3899         flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags);
3900
3901         /* We current only support a subset of the standard features. Only a
3902          * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn
3903          * (with overlap). Full offload mode isn't supported.
3904          */
3905         if (!attr->keymat || attr->replay || attr->encap ||
3906             attr->spi || attr->seq || attr->tfc_pad ||
3907             attr->hard_limit_pkts ||
3908             (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3909                              IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)))
3910                 return ERR_PTR(-EOPNOTSUPP);
3911
3912         if (attr->keymat->protocol !=
3913             IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM)
3914                 return ERR_PTR(-EOPNOTSUPP);
3915
3916         aes_gcm = &attr->keymat->keymat.aes_gcm;
3917
3918         if (aes_gcm->icv_len != 16 ||
3919             aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ)
3920                 return ERR_PTR(-EOPNOTSUPP);
3921
3922         action = kmalloc(sizeof(*action), GFP_KERNEL);
3923         if (!action)
3924                 return ERR_PTR(-ENOMEM);
3925
3926         action->esp_aes_gcm.ib_flags = attr->flags;
3927         memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key,
3928                sizeof(accel_attrs.keymat.aes_gcm.aes_key));
3929         accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8;
3930         memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt,
3931                sizeof(accel_attrs.keymat.aes_gcm.salt));
3932         memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv,
3933                sizeof(accel_attrs.keymat.aes_gcm.seq_iv));
3934         accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8;
3935         accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ;
3936         accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM;
3937
3938         accel_attrs.esn = attr->esn;
3939         if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED)
3940                 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED;
3941         if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
3942                 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3943
3944         if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)
3945                 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT;
3946
3947         action->esp_aes_gcm.ctx =
3948                 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags);
3949         if (IS_ERR(action->esp_aes_gcm.ctx)) {
3950                 err = PTR_ERR(action->esp_aes_gcm.ctx);
3951                 goto err_parse;
3952         }
3953
3954         action->esp_aes_gcm.ib_flags = attr->flags;
3955
3956         return &action->ib_action;
3957
3958 err_parse:
3959         kfree(action);
3960         return ERR_PTR(err);
3961 }
3962
3963 static int
3964 mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action,
3965                                const struct ib_flow_action_attrs_esp *attr,
3966                                struct uverbs_attr_bundle *attrs)
3967 {
3968         struct mlx5_ib_flow_action *maction = to_mflow_act(action);
3969         struct mlx5_accel_esp_xfrm_attrs accel_attrs;
3970         int err = 0;
3971
3972         if (attr->keymat || attr->replay || attr->encap ||
3973             attr->spi || attr->seq || attr->tfc_pad ||
3974             attr->hard_limit_pkts ||
3975             (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3976                              IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS |
3977                              IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)))
3978                 return -EOPNOTSUPP;
3979
3980         /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can
3981          * be modified.
3982          */
3983         if (!(maction->esp_aes_gcm.ib_flags &
3984               IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) &&
3985             attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3986                            IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))
3987                 return -EINVAL;
3988
3989         memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs,
3990                sizeof(accel_attrs));
3991
3992         accel_attrs.esn = attr->esn;
3993         if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
3994                 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3995         else
3996                 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3997
3998         err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx,
3999                                          &accel_attrs);
4000         if (err)
4001                 return err;
4002
4003         maction->esp_aes_gcm.ib_flags &=
4004                 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4005         maction->esp_aes_gcm.ib_flags |=
4006                 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4007
4008         return 0;
4009 }
4010
4011 static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action)
4012 {
4013         struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4014
4015         switch (action->type) {
4016         case IB_FLOW_ACTION_ESP:
4017                 /*
4018                  * We only support aes_gcm by now, so we implicitly know this is
4019                  * the underline crypto.
4020                  */
4021                 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx);
4022                 break;
4023         default:
4024                 WARN_ON(true);
4025                 break;
4026         }
4027
4028         kfree(maction);
4029         return 0;
4030 }
4031
4032 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4033 {
4034         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4035         struct mlx5_ib_qp *mqp = to_mqp(ibqp);
4036         int err;
4037
4038         if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
4039                 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
4040                 return -EOPNOTSUPP;
4041         }
4042
4043         err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
4044         if (err)
4045                 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
4046                              ibqp->qp_num, gid->raw);
4047
4048         return err;
4049 }
4050
4051 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4052 {
4053         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4054         int err;
4055
4056         err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
4057         if (err)
4058                 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
4059                              ibqp->qp_num, gid->raw);
4060
4061         return err;
4062 }
4063
4064 static int init_node_data(struct mlx5_ib_dev *dev)
4065 {
4066         int err;
4067
4068         err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
4069         if (err)
4070                 return err;
4071
4072         dev->mdev->rev_id = dev->mdev->pdev->revision;
4073
4074         return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
4075 }
4076
4077 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
4078                              char *buf)
4079 {
4080         struct mlx5_ib_dev *dev =
4081                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4082
4083         return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
4084 }
4085
4086 static ssize_t show_reg_pages(struct device *device,
4087                               struct device_attribute *attr, char *buf)
4088 {
4089         struct mlx5_ib_dev *dev =
4090                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4091
4092         return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
4093 }
4094
4095 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
4096                         char *buf)
4097 {
4098         struct mlx5_ib_dev *dev =
4099                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4100         return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
4101 }
4102
4103 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
4104                         char *buf)
4105 {
4106         struct mlx5_ib_dev *dev =
4107                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4108         return sprintf(buf, "%x\n", dev->mdev->rev_id);
4109 }
4110
4111 static ssize_t show_board(struct device *device, struct device_attribute *attr,
4112                           char *buf)
4113 {
4114         struct mlx5_ib_dev *dev =
4115                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4116         return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
4117                        dev->mdev->board_id);
4118 }
4119
4120 static DEVICE_ATTR(hw_rev,   S_IRUGO, show_rev,    NULL);
4121 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca,    NULL);
4122 static DEVICE_ATTR(board_id, S_IRUGO, show_board,  NULL);
4123 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
4124 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
4125
4126 static struct device_attribute *mlx5_class_attributes[] = {
4127         &dev_attr_hw_rev,
4128         &dev_attr_hca_type,
4129         &dev_attr_board_id,
4130         &dev_attr_fw_pages,
4131         &dev_attr_reg_pages,
4132 };
4133
4134 static void pkey_change_handler(struct work_struct *work)
4135 {
4136         struct mlx5_ib_port_resources *ports =
4137                 container_of(work, struct mlx5_ib_port_resources,
4138                              pkey_change_work);
4139
4140         mutex_lock(&ports->devr->mutex);
4141         mlx5_ib_gsi_pkey_change(ports->gsi);
4142         mutex_unlock(&ports->devr->mutex);
4143 }
4144
4145 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
4146 {
4147         struct mlx5_ib_qp *mqp;
4148         struct mlx5_ib_cq *send_mcq, *recv_mcq;
4149         struct mlx5_core_cq *mcq;
4150         struct list_head cq_armed_list;
4151         unsigned long flags_qp;
4152         unsigned long flags_cq;
4153         unsigned long flags;
4154
4155         INIT_LIST_HEAD(&cq_armed_list);
4156
4157         /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
4158         spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
4159         list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
4160                 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
4161                 if (mqp->sq.tail != mqp->sq.head) {
4162                         send_mcq = to_mcq(mqp->ibqp.send_cq);
4163                         spin_lock_irqsave(&send_mcq->lock, flags_cq);
4164                         if (send_mcq->mcq.comp &&
4165                             mqp->ibqp.send_cq->comp_handler) {
4166                                 if (!send_mcq->mcq.reset_notify_added) {
4167                                         send_mcq->mcq.reset_notify_added = 1;
4168                                         list_add_tail(&send_mcq->mcq.reset_notify,
4169                                                       &cq_armed_list);
4170                                 }
4171                         }
4172                         spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
4173                 }
4174                 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
4175                 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
4176                 /* no handling is needed for SRQ */
4177                 if (!mqp->ibqp.srq) {
4178                         if (mqp->rq.tail != mqp->rq.head) {
4179                                 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
4180                                 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
4181                                 if (recv_mcq->mcq.comp &&
4182                                     mqp->ibqp.recv_cq->comp_handler) {
4183                                         if (!recv_mcq->mcq.reset_notify_added) {
4184                                                 recv_mcq->mcq.reset_notify_added = 1;
4185                                                 list_add_tail(&recv_mcq->mcq.reset_notify,
4186                                                               &cq_armed_list);
4187                                         }
4188                                 }
4189                                 spin_unlock_irqrestore(&recv_mcq->lock,
4190                                                        flags_cq);
4191                         }
4192                 }
4193                 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
4194         }
4195         /*At that point all inflight post send were put to be executed as of we
4196          * lock/unlock above locks Now need to arm all involved CQs.
4197          */
4198         list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
4199                 mcq->comp(mcq);
4200         }
4201         spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
4202 }
4203
4204 static void delay_drop_handler(struct work_struct *work)
4205 {
4206         int err;
4207         struct mlx5_ib_delay_drop *delay_drop =
4208                 container_of(work, struct mlx5_ib_delay_drop,
4209                              delay_drop_work);
4210
4211         atomic_inc(&delay_drop->events_cnt);
4212
4213         mutex_lock(&delay_drop->lock);
4214         err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
4215                                        delay_drop->timeout);
4216         if (err) {
4217                 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
4218                              delay_drop->timeout);
4219                 delay_drop->activate = false;
4220         }
4221         mutex_unlock(&delay_drop->lock);
4222 }
4223
4224 static void mlx5_ib_handle_event(struct work_struct *_work)
4225 {
4226         struct mlx5_ib_event_work *work =
4227                 container_of(_work, struct mlx5_ib_event_work, work);
4228         struct mlx5_ib_dev *ibdev;
4229         struct ib_event ibev;
4230         bool fatal = false;
4231         u8 port = (u8)work->param;
4232
4233         if (mlx5_core_is_mp_slave(work->dev)) {
4234                 ibdev = mlx5_ib_get_ibdev_from_mpi(work->context);
4235                 if (!ibdev)
4236                         goto out;
4237         } else {
4238                 ibdev = work->context;
4239         }
4240
4241         switch (work->event) {
4242         case MLX5_DEV_EVENT_SYS_ERROR:
4243                 ibev.event = IB_EVENT_DEVICE_FATAL;
4244                 mlx5_ib_handle_internal_error(ibdev);
4245                 fatal = true;
4246                 break;
4247
4248         case MLX5_DEV_EVENT_PORT_UP:
4249         case MLX5_DEV_EVENT_PORT_DOWN:
4250         case MLX5_DEV_EVENT_PORT_INITIALIZED:
4251                 /* In RoCE, port up/down events are handled in
4252                  * mlx5_netdev_event().
4253                  */
4254                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4255                         IB_LINK_LAYER_ETHERNET)
4256                         goto out;
4257
4258                 ibev.event = (work->event == MLX5_DEV_EVENT_PORT_UP) ?
4259                              IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
4260                 break;
4261
4262         case MLX5_DEV_EVENT_LID_CHANGE:
4263                 ibev.event = IB_EVENT_LID_CHANGE;
4264                 break;
4265
4266         case MLX5_DEV_EVENT_PKEY_CHANGE:
4267                 ibev.event = IB_EVENT_PKEY_CHANGE;
4268                 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
4269                 break;
4270
4271         case MLX5_DEV_EVENT_GUID_CHANGE:
4272                 ibev.event = IB_EVENT_GID_CHANGE;
4273                 break;
4274
4275         case MLX5_DEV_EVENT_CLIENT_REREG:
4276                 ibev.event = IB_EVENT_CLIENT_REREGISTER;
4277                 break;
4278         case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT:
4279                 schedule_work(&ibdev->delay_drop.delay_drop_work);
4280                 goto out;
4281         default:
4282                 goto out;
4283         }
4284
4285         ibev.device           = &ibdev->ib_dev;
4286         ibev.element.port_num = port;
4287
4288         if (!rdma_is_port_valid(&ibdev->ib_dev, port)) {
4289                 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
4290                 goto out;
4291         }
4292
4293         if (ibdev->ib_active)
4294                 ib_dispatch_event(&ibev);
4295
4296         if (fatal)
4297                 ibdev->ib_active = false;
4298 out:
4299         kfree(work);
4300 }
4301
4302 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
4303                           enum mlx5_dev_event event, unsigned long param)
4304 {
4305         struct mlx5_ib_event_work *work;
4306
4307         work = kmalloc(sizeof(*work), GFP_ATOMIC);
4308         if (!work)
4309                 return;
4310
4311         INIT_WORK(&work->work, mlx5_ib_handle_event);
4312         work->dev = dev;
4313         work->param = param;
4314         work->context = context;
4315         work->event = event;
4316
4317         queue_work(mlx5_ib_event_wq, &work->work);
4318 }
4319
4320 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
4321 {
4322         struct mlx5_hca_vport_context vport_ctx;
4323         int err;
4324         int port;
4325
4326         for (port = 1; port <= dev->num_ports; port++) {
4327                 dev->mdev->port_caps[port - 1].has_smi = false;
4328                 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
4329                     MLX5_CAP_PORT_TYPE_IB) {
4330                         if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
4331                                 err = mlx5_query_hca_vport_context(dev->mdev, 0,
4332                                                                    port, 0,
4333                                                                    &vport_ctx);
4334                                 if (err) {
4335                                         mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
4336                                                     port, err);
4337                                         return err;
4338                                 }
4339                                 dev->mdev->port_caps[port - 1].has_smi =
4340                                         vport_ctx.has_smi;
4341                         } else {
4342                                 dev->mdev->port_caps[port - 1].has_smi = true;
4343                         }
4344                 }
4345         }
4346         return 0;
4347 }
4348
4349 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
4350 {
4351         int port;
4352
4353         for (port = 1; port <= dev->num_ports; port++)
4354                 mlx5_query_ext_port_caps(dev, port);
4355 }
4356
4357 static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
4358 {
4359         struct ib_device_attr *dprops = NULL;
4360         struct ib_port_attr *pprops = NULL;
4361         int err = -ENOMEM;
4362         struct ib_udata uhw = {.inlen = 0, .outlen = 0};
4363
4364         pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
4365         if (!pprops)
4366                 goto out;
4367
4368         dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
4369         if (!dprops)
4370                 goto out;
4371
4372         err = set_has_smi_cap(dev);
4373         if (err)
4374                 goto out;
4375
4376         err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
4377         if (err) {
4378                 mlx5_ib_warn(dev, "query_device failed %d\n", err);
4379                 goto out;
4380         }
4381
4382         memset(pprops, 0, sizeof(*pprops));
4383         err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
4384         if (err) {
4385                 mlx5_ib_warn(dev, "query_port %d failed %d\n",
4386                              port, err);
4387                 goto out;
4388         }
4389
4390         dev->mdev->port_caps[port - 1].pkey_table_len =
4391                                         dprops->max_pkeys;
4392         dev->mdev->port_caps[port - 1].gid_table_len =
4393                                         pprops->gid_tbl_len;
4394         mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
4395                     port, dprops->max_pkeys, pprops->gid_tbl_len);
4396
4397 out:
4398         kfree(pprops);
4399         kfree(dprops);
4400
4401         return err;
4402 }
4403
4404 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
4405 {
4406         int err;
4407
4408         err = mlx5_mr_cache_cleanup(dev);
4409         if (err)
4410                 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4411
4412         if (dev->umrc.qp)
4413                 mlx5_ib_destroy_qp(dev->umrc.qp);
4414         if (dev->umrc.cq)
4415                 ib_free_cq(dev->umrc.cq);
4416         if (dev->umrc.pd)
4417                 ib_dealloc_pd(dev->umrc.pd);
4418 }
4419
4420 enum {
4421         MAX_UMR_WR = 128,
4422 };
4423
4424 static int create_umr_res(struct mlx5_ib_dev *dev)
4425 {
4426         struct ib_qp_init_attr *init_attr = NULL;
4427         struct ib_qp_attr *attr = NULL;
4428         struct ib_pd *pd;
4429         struct ib_cq *cq;
4430         struct ib_qp *qp;
4431         int ret;
4432
4433         attr = kzalloc(sizeof(*attr), GFP_KERNEL);
4434         init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
4435         if (!attr || !init_attr) {
4436                 ret = -ENOMEM;
4437                 goto error_0;
4438         }
4439
4440         pd = ib_alloc_pd(&dev->ib_dev, 0);
4441         if (IS_ERR(pd)) {
4442                 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
4443                 ret = PTR_ERR(pd);
4444                 goto error_0;
4445         }
4446
4447         cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
4448         if (IS_ERR(cq)) {
4449                 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
4450                 ret = PTR_ERR(cq);
4451                 goto error_2;
4452         }
4453
4454         init_attr->send_cq = cq;
4455         init_attr->recv_cq = cq;
4456         init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
4457         init_attr->cap.max_send_wr = MAX_UMR_WR;
4458         init_attr->cap.max_send_sge = 1;
4459         init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
4460         init_attr->port_num = 1;
4461         qp = mlx5_ib_create_qp(pd, init_attr, NULL);
4462         if (IS_ERR(qp)) {
4463                 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
4464                 ret = PTR_ERR(qp);
4465                 goto error_3;
4466         }
4467         qp->device     = &dev->ib_dev;
4468         qp->real_qp    = qp;
4469         qp->uobject    = NULL;
4470         qp->qp_type    = MLX5_IB_QPT_REG_UMR;
4471         qp->send_cq    = init_attr->send_cq;
4472         qp->recv_cq    = init_attr->recv_cq;
4473
4474         attr->qp_state = IB_QPS_INIT;
4475         attr->port_num = 1;
4476         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
4477                                 IB_QP_PORT, NULL);
4478         if (ret) {
4479                 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
4480                 goto error_4;
4481         }
4482
4483         memset(attr, 0, sizeof(*attr));
4484         attr->qp_state = IB_QPS_RTR;
4485         attr->path_mtu = IB_MTU_256;
4486
4487         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4488         if (ret) {
4489                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
4490                 goto error_4;
4491         }
4492
4493         memset(attr, 0, sizeof(*attr));
4494         attr->qp_state = IB_QPS_RTS;
4495         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4496         if (ret) {
4497                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
4498                 goto error_4;
4499         }
4500
4501         dev->umrc.qp = qp;
4502         dev->umrc.cq = cq;
4503         dev->umrc.pd = pd;
4504
4505         sema_init(&dev->umrc.sem, MAX_UMR_WR);
4506         ret = mlx5_mr_cache_init(dev);
4507         if (ret) {
4508                 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4509                 goto error_4;
4510         }
4511
4512         kfree(attr);
4513         kfree(init_attr);
4514
4515         return 0;
4516
4517 error_4:
4518         mlx5_ib_destroy_qp(qp);
4519         dev->umrc.qp = NULL;
4520
4521 error_3:
4522         ib_free_cq(cq);
4523         dev->umrc.cq = NULL;
4524
4525 error_2:
4526         ib_dealloc_pd(pd);
4527         dev->umrc.pd = NULL;
4528
4529 error_0:
4530         kfree(attr);
4531         kfree(init_attr);
4532         return ret;
4533 }
4534
4535 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
4536 {
4537         switch (umr_fence_cap) {
4538         case MLX5_CAP_UMR_FENCE_NONE:
4539                 return MLX5_FENCE_MODE_NONE;
4540         case MLX5_CAP_UMR_FENCE_SMALL:
4541                 return MLX5_FENCE_MODE_INITIATOR_SMALL;
4542         default:
4543                 return MLX5_FENCE_MODE_STRONG_ORDERING;
4544         }
4545 }
4546
4547 static int create_dev_resources(struct mlx5_ib_resources *devr)
4548 {
4549         struct ib_srq_init_attr attr;
4550         struct mlx5_ib_dev *dev;
4551         struct ib_cq_init_attr cq_attr = {.cqe = 1};
4552         int port;
4553         int ret = 0;
4554
4555         dev = container_of(devr, struct mlx5_ib_dev, devr);
4556
4557         mutex_init(&devr->mutex);
4558
4559         devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
4560         if (IS_ERR(devr->p0)) {
4561                 ret = PTR_ERR(devr->p0);
4562                 goto error0;
4563         }
4564         devr->p0->device  = &dev->ib_dev;
4565         devr->p0->uobject = NULL;
4566         atomic_set(&devr->p0->usecnt, 0);
4567
4568         devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
4569         if (IS_ERR(devr->c0)) {
4570                 ret = PTR_ERR(devr->c0);
4571                 goto error1;
4572         }
4573         devr->c0->device        = &dev->ib_dev;
4574         devr->c0->uobject       = NULL;
4575         devr->c0->comp_handler  = NULL;
4576         devr->c0->event_handler = NULL;
4577         devr->c0->cq_context    = NULL;
4578         atomic_set(&devr->c0->usecnt, 0);
4579
4580         devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4581         if (IS_ERR(devr->x0)) {
4582                 ret = PTR_ERR(devr->x0);
4583                 goto error2;
4584         }
4585         devr->x0->device = &dev->ib_dev;
4586         devr->x0->inode = NULL;
4587         atomic_set(&devr->x0->usecnt, 0);
4588         mutex_init(&devr->x0->tgt_qp_mutex);
4589         INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
4590
4591         devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4592         if (IS_ERR(devr->x1)) {
4593                 ret = PTR_ERR(devr->x1);
4594                 goto error3;
4595         }
4596         devr->x1->device = &dev->ib_dev;
4597         devr->x1->inode = NULL;
4598         atomic_set(&devr->x1->usecnt, 0);
4599         mutex_init(&devr->x1->tgt_qp_mutex);
4600         INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
4601
4602         memset(&attr, 0, sizeof(attr));
4603         attr.attr.max_sge = 1;
4604         attr.attr.max_wr = 1;
4605         attr.srq_type = IB_SRQT_XRC;
4606         attr.ext.cq = devr->c0;
4607         attr.ext.xrc.xrcd = devr->x0;
4608
4609         devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4610         if (IS_ERR(devr->s0)) {
4611                 ret = PTR_ERR(devr->s0);
4612                 goto error4;
4613         }
4614         devr->s0->device        = &dev->ib_dev;
4615         devr->s0->pd            = devr->p0;
4616         devr->s0->uobject       = NULL;
4617         devr->s0->event_handler = NULL;
4618         devr->s0->srq_context   = NULL;
4619         devr->s0->srq_type      = IB_SRQT_XRC;
4620         devr->s0->ext.xrc.xrcd  = devr->x0;
4621         devr->s0->ext.cq        = devr->c0;
4622         atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
4623         atomic_inc(&devr->s0->ext.cq->usecnt);
4624         atomic_inc(&devr->p0->usecnt);
4625         atomic_set(&devr->s0->usecnt, 0);
4626
4627         memset(&attr, 0, sizeof(attr));
4628         attr.attr.max_sge = 1;
4629         attr.attr.max_wr = 1;
4630         attr.srq_type = IB_SRQT_BASIC;
4631         devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4632         if (IS_ERR(devr->s1)) {
4633                 ret = PTR_ERR(devr->s1);
4634                 goto error5;
4635         }
4636         devr->s1->device        = &dev->ib_dev;
4637         devr->s1->pd            = devr->p0;
4638         devr->s1->uobject       = NULL;
4639         devr->s1->event_handler = NULL;
4640         devr->s1->srq_context   = NULL;
4641         devr->s1->srq_type      = IB_SRQT_BASIC;
4642         devr->s1->ext.cq        = devr->c0;
4643         atomic_inc(&devr->p0->usecnt);
4644         atomic_set(&devr->s1->usecnt, 0);
4645
4646         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
4647                 INIT_WORK(&devr->ports[port].pkey_change_work,
4648                           pkey_change_handler);
4649                 devr->ports[port].devr = devr;
4650         }
4651
4652         return 0;
4653
4654 error5:
4655         mlx5_ib_destroy_srq(devr->s0);
4656 error4:
4657         mlx5_ib_dealloc_xrcd(devr->x1);
4658 error3:
4659         mlx5_ib_dealloc_xrcd(devr->x0);
4660 error2:
4661         mlx5_ib_destroy_cq(devr->c0);
4662 error1:
4663         mlx5_ib_dealloc_pd(devr->p0);
4664 error0:
4665         return ret;
4666 }
4667
4668 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
4669 {
4670         struct mlx5_ib_dev *dev =
4671                 container_of(devr, struct mlx5_ib_dev, devr);
4672         int port;
4673
4674         mlx5_ib_destroy_srq(devr->s1);
4675         mlx5_ib_destroy_srq(devr->s0);
4676         mlx5_ib_dealloc_xrcd(devr->x0);
4677         mlx5_ib_dealloc_xrcd(devr->x1);
4678         mlx5_ib_destroy_cq(devr->c0);
4679         mlx5_ib_dealloc_pd(devr->p0);
4680
4681         /* Make sure no change P_Key work items are still executing */
4682         for (port = 0; port < dev->num_ports; ++port)
4683                 cancel_work_sync(&devr->ports[port].pkey_change_work);
4684 }
4685
4686 static u32 get_core_cap_flags(struct ib_device *ibdev,
4687                               struct mlx5_hca_vport_context *rep)
4688 {
4689         struct mlx5_ib_dev *dev = to_mdev(ibdev);
4690         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
4691         u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
4692         u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
4693         bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
4694         u32 ret = 0;
4695
4696         if (rep->grh_required)
4697                 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
4698
4699         if (ll == IB_LINK_LAYER_INFINIBAND)
4700                 return ret | RDMA_CORE_PORT_IBA_IB;
4701
4702         if (raw_support)
4703                 ret |= RDMA_CORE_PORT_RAW_PACKET;
4704
4705         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
4706                 return ret;
4707
4708         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
4709                 return ret;
4710
4711         if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
4712                 ret |= RDMA_CORE_PORT_IBA_ROCE;
4713
4714         if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
4715                 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
4716
4717         return ret;
4718 }
4719
4720 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
4721                                struct ib_port_immutable *immutable)
4722 {
4723         struct ib_port_attr attr;
4724         struct mlx5_ib_dev *dev = to_mdev(ibdev);
4725         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
4726         struct mlx5_hca_vport_context rep = {0};
4727         int err;
4728
4729         err = ib_query_port(ibdev, port_num, &attr);
4730         if (err)
4731                 return err;
4732
4733         if (ll == IB_LINK_LAYER_INFINIBAND) {
4734                 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
4735                                                    &rep);
4736                 if (err)
4737                         return err;
4738         }
4739
4740         immutable->pkey_tbl_len = attr.pkey_tbl_len;
4741         immutable->gid_tbl_len = attr.gid_tbl_len;
4742         immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
4743         if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
4744                 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
4745
4746         return 0;
4747 }
4748
4749 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
4750                                    struct ib_port_immutable *immutable)
4751 {
4752         struct ib_port_attr attr;
4753         int err;
4754
4755         immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4756
4757         err = ib_query_port(ibdev, port_num, &attr);
4758         if (err)
4759                 return err;
4760
4761         immutable->pkey_tbl_len = attr.pkey_tbl_len;
4762         immutable->gid_tbl_len = attr.gid_tbl_len;
4763         immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4764
4765         return 0;
4766 }
4767
4768 static void get_dev_fw_str(struct ib_device *ibdev, char *str)
4769 {
4770         struct mlx5_ib_dev *dev =
4771                 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
4772         snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
4773                  fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
4774                  fw_rev_sub(dev->mdev));
4775 }
4776
4777 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
4778 {
4779         struct mlx5_core_dev *mdev = dev->mdev;
4780         struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
4781                                                                  MLX5_FLOW_NAMESPACE_LAG);
4782         struct mlx5_flow_table *ft;
4783         int err;
4784
4785         if (!ns || !mlx5_lag_is_active(mdev))
4786                 return 0;
4787
4788         err = mlx5_cmd_create_vport_lag(mdev);
4789         if (err)
4790                 return err;
4791
4792         ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
4793         if (IS_ERR(ft)) {
4794                 err = PTR_ERR(ft);
4795                 goto err_destroy_vport_lag;
4796         }
4797
4798         dev->flow_db->lag_demux_ft = ft;
4799         return 0;
4800
4801 err_destroy_vport_lag:
4802         mlx5_cmd_destroy_vport_lag(mdev);
4803         return err;
4804 }
4805
4806 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
4807 {
4808         struct mlx5_core_dev *mdev = dev->mdev;
4809
4810         if (dev->flow_db->lag_demux_ft) {
4811                 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
4812                 dev->flow_db->lag_demux_ft = NULL;
4813
4814                 mlx5_cmd_destroy_vport_lag(mdev);
4815         }
4816 }
4817
4818 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
4819 {
4820         int err;
4821
4822         dev->roce[port_num].nb.notifier_call = mlx5_netdev_event;
4823         err = register_netdevice_notifier(&dev->roce[port_num].nb);
4824         if (err) {
4825                 dev->roce[port_num].nb.notifier_call = NULL;
4826                 return err;
4827         }
4828
4829         return 0;
4830 }
4831
4832 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
4833 {
4834         if (dev->roce[port_num].nb.notifier_call) {
4835                 unregister_netdevice_notifier(&dev->roce[port_num].nb);
4836                 dev->roce[port_num].nb.notifier_call = NULL;
4837         }
4838 }
4839
4840 static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
4841 {
4842         int err;
4843
4844         if (MLX5_CAP_GEN(dev->mdev, roce)) {
4845                 err = mlx5_nic_vport_enable_roce(dev->mdev);
4846                 if (err)
4847                         return err;
4848         }
4849
4850         err = mlx5_eth_lag_init(dev);
4851         if (err)
4852                 goto err_disable_roce;
4853
4854         return 0;
4855
4856 err_disable_roce:
4857         if (MLX5_CAP_GEN(dev->mdev, roce))
4858                 mlx5_nic_vport_disable_roce(dev->mdev);
4859
4860         return err;
4861 }
4862
4863 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
4864 {
4865         mlx5_eth_lag_cleanup(dev);
4866         if (MLX5_CAP_GEN(dev->mdev, roce))
4867                 mlx5_nic_vport_disable_roce(dev->mdev);
4868 }
4869
4870 struct mlx5_ib_counter {
4871         const char *name;
4872         size_t offset;
4873 };
4874
4875 #define INIT_Q_COUNTER(_name)           \
4876         { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
4877
4878 static const struct mlx5_ib_counter basic_q_cnts[] = {
4879         INIT_Q_COUNTER(rx_write_requests),
4880         INIT_Q_COUNTER(rx_read_requests),
4881         INIT_Q_COUNTER(rx_atomic_requests),
4882         INIT_Q_COUNTER(out_of_buffer),
4883 };
4884
4885 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
4886         INIT_Q_COUNTER(out_of_sequence),
4887 };
4888
4889 static const struct mlx5_ib_counter retrans_q_cnts[] = {
4890         INIT_Q_COUNTER(duplicate_request),
4891         INIT_Q_COUNTER(rnr_nak_retry_err),
4892         INIT_Q_COUNTER(packet_seq_err),
4893         INIT_Q_COUNTER(implied_nak_seq_err),
4894         INIT_Q_COUNTER(local_ack_timeout_err),
4895 };
4896
4897 #define INIT_CONG_COUNTER(_name)                \
4898         { .name = #_name, .offset =     \
4899                 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
4900
4901 static const struct mlx5_ib_counter cong_cnts[] = {
4902         INIT_CONG_COUNTER(rp_cnp_ignored),
4903         INIT_CONG_COUNTER(rp_cnp_handled),
4904         INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
4905         INIT_CONG_COUNTER(np_cnp_sent),
4906 };
4907
4908 static const struct mlx5_ib_counter extended_err_cnts[] = {
4909         INIT_Q_COUNTER(resp_local_length_error),
4910         INIT_Q_COUNTER(resp_cqe_error),
4911         INIT_Q_COUNTER(req_cqe_error),
4912         INIT_Q_COUNTER(req_remote_invalid_request),
4913         INIT_Q_COUNTER(req_remote_access_errors),
4914         INIT_Q_COUNTER(resp_remote_access_errors),
4915         INIT_Q_COUNTER(resp_cqe_flush_error),
4916         INIT_Q_COUNTER(req_cqe_flush_error),
4917 };
4918
4919 #define INIT_EXT_PPCNT_COUNTER(_name)           \
4920         { .name = #_name, .offset =     \
4921         MLX5_BYTE_OFF(ppcnt_reg, \
4922                       counter_set.eth_extended_cntrs_grp_data_layout._name##_high)}
4923
4924 static const struct mlx5_ib_counter ext_ppcnt_cnts[] = {
4925         INIT_EXT_PPCNT_COUNTER(rx_icrc_encapsulated),
4926 };
4927
4928 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
4929 {
4930         int i;
4931
4932         for (i = 0; i < dev->num_ports; i++) {
4933                 if (dev->port[i].cnts.set_id_valid)
4934                         mlx5_core_dealloc_q_counter(dev->mdev,
4935                                                     dev->port[i].cnts.set_id);
4936                 kfree(dev->port[i].cnts.names);
4937                 kfree(dev->port[i].cnts.offsets);
4938         }
4939 }
4940
4941 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
4942                                     struct mlx5_ib_counters *cnts)
4943 {
4944         u32 num_counters;
4945
4946         num_counters = ARRAY_SIZE(basic_q_cnts);
4947
4948         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
4949                 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
4950
4951         if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
4952                 num_counters += ARRAY_SIZE(retrans_q_cnts);
4953
4954         if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
4955                 num_counters += ARRAY_SIZE(extended_err_cnts);
4956
4957         cnts->num_q_counters = num_counters;
4958
4959         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4960                 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
4961                 num_counters += ARRAY_SIZE(cong_cnts);
4962         }
4963         if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
4964                 cnts->num_ext_ppcnt_counters = ARRAY_SIZE(ext_ppcnt_cnts);
4965                 num_counters += ARRAY_SIZE(ext_ppcnt_cnts);
4966         }
4967         cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
4968         if (!cnts->names)
4969                 return -ENOMEM;
4970
4971         cnts->offsets = kcalloc(num_counters,
4972                                 sizeof(cnts->offsets), GFP_KERNEL);
4973         if (!cnts->offsets)
4974                 goto err_names;
4975
4976         return 0;
4977
4978 err_names:
4979         kfree(cnts->names);
4980         cnts->names = NULL;
4981         return -ENOMEM;
4982 }
4983
4984 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
4985                                   const char **names,
4986                                   size_t *offsets)
4987 {
4988         int i;
4989         int j = 0;
4990
4991         for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
4992                 names[j] = basic_q_cnts[i].name;
4993                 offsets[j] = basic_q_cnts[i].offset;
4994         }
4995
4996         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
4997                 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
4998                         names[j] = out_of_seq_q_cnts[i].name;
4999                         offsets[j] = out_of_seq_q_cnts[i].offset;
5000                 }
5001         }
5002
5003         if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
5004                 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
5005                         names[j] = retrans_q_cnts[i].name;
5006                         offsets[j] = retrans_q_cnts[i].offset;
5007                 }
5008         }
5009
5010         if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
5011                 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
5012                         names[j] = extended_err_cnts[i].name;
5013                         offsets[j] = extended_err_cnts[i].offset;
5014                 }
5015         }
5016
5017         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5018                 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
5019                         names[j] = cong_cnts[i].name;
5020                         offsets[j] = cong_cnts[i].offset;
5021                 }
5022         }
5023
5024         if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5025                 for (i = 0; i < ARRAY_SIZE(ext_ppcnt_cnts); i++, j++) {
5026                         names[j] = ext_ppcnt_cnts[i].name;
5027                         offsets[j] = ext_ppcnt_cnts[i].offset;
5028                 }
5029         }
5030 }
5031
5032 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
5033 {
5034         int err = 0;
5035         int i;
5036
5037         for (i = 0; i < dev->num_ports; i++) {
5038                 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
5039                 if (err)
5040                         goto err_alloc;
5041
5042                 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
5043                                       dev->port[i].cnts.offsets);
5044
5045                 err = mlx5_core_alloc_q_counter(dev->mdev,
5046                                                 &dev->port[i].cnts.set_id);
5047                 if (err) {
5048                         mlx5_ib_warn(dev,
5049                                      "couldn't allocate queue counter for port %d, err %d\n",
5050                                      i + 1, err);
5051                         goto err_alloc;
5052                 }
5053                 dev->port[i].cnts.set_id_valid = true;
5054         }
5055
5056         return 0;
5057
5058 err_alloc:
5059         mlx5_ib_dealloc_counters(dev);
5060         return err;
5061 }
5062
5063 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
5064                                                     u8 port_num)
5065 {
5066         struct mlx5_ib_dev *dev = to_mdev(ibdev);
5067         struct mlx5_ib_port *port = &dev->port[port_num - 1];
5068
5069         /* We support only per port stats */
5070         if (port_num == 0)
5071                 return NULL;
5072
5073         return rdma_alloc_hw_stats_struct(port->cnts.names,
5074                                           port->cnts.num_q_counters +
5075                                           port->cnts.num_cong_counters +
5076                                           port->cnts.num_ext_ppcnt_counters,
5077                                           RDMA_HW_STATS_DEFAULT_LIFESPAN);
5078 }
5079
5080 static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
5081                                     struct mlx5_ib_port *port,
5082                                     struct rdma_hw_stats *stats)
5083 {
5084         int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
5085         void *out;
5086         __be32 val;
5087         int ret, i;
5088
5089         out = kvzalloc(outlen, GFP_KERNEL);
5090         if (!out)
5091                 return -ENOMEM;
5092
5093         ret = mlx5_core_query_q_counter(mdev,
5094                                         port->cnts.set_id, 0,
5095                                         out, outlen);
5096         if (ret)
5097                 goto free;
5098
5099         for (i = 0; i < port->cnts.num_q_counters; i++) {
5100                 val = *(__be32 *)(out + port->cnts.offsets[i]);
5101                 stats->value[i] = (u64)be32_to_cpu(val);
5102         }
5103
5104 free:
5105         kvfree(out);
5106         return ret;
5107 }
5108
5109 static int mlx5_ib_query_ext_ppcnt_counters(struct mlx5_ib_dev *dev,
5110                                           struct mlx5_ib_port *port,
5111                                           struct rdma_hw_stats *stats)
5112 {
5113         int offset = port->cnts.num_q_counters + port->cnts.num_cong_counters;
5114         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
5115         int ret, i;
5116         void *out;
5117
5118         out = kvzalloc(sz, GFP_KERNEL);
5119         if (!out)
5120                 return -ENOMEM;
5121
5122         ret = mlx5_cmd_query_ext_ppcnt_counters(dev->mdev, out);
5123         if (ret)
5124                 goto free;
5125
5126         for (i = 0; i < port->cnts.num_ext_ppcnt_counters; i++) {
5127                 stats->value[i + offset] =
5128                         be64_to_cpup((__be64 *)(out +
5129                                     port->cnts.offsets[i + offset]));
5130         }
5131
5132 free:
5133         kvfree(out);
5134         return ret;
5135 }
5136
5137 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
5138                                 struct rdma_hw_stats *stats,
5139                                 u8 port_num, int index)
5140 {
5141         struct mlx5_ib_dev *dev = to_mdev(ibdev);
5142         struct mlx5_ib_port *port = &dev->port[port_num - 1];
5143         struct mlx5_core_dev *mdev;
5144         int ret, num_counters;
5145         u8 mdev_port_num;
5146
5147         if (!stats)
5148                 return -EINVAL;
5149
5150         num_counters = port->cnts.num_q_counters +
5151                        port->cnts.num_cong_counters +
5152                        port->cnts.num_ext_ppcnt_counters;
5153
5154         /* q_counters are per IB device, query the master mdev */
5155         ret = mlx5_ib_query_q_counters(dev->mdev, port, stats);
5156         if (ret)
5157                 return ret;
5158
5159         if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5160                 ret =  mlx5_ib_query_ext_ppcnt_counters(dev, port, stats);
5161                 if (ret)
5162                         return ret;
5163         }
5164
5165         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5166                 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
5167                                                     &mdev_port_num);
5168                 if (!mdev) {
5169                         /* If port is not affiliated yet, its in down state
5170                          * which doesn't have any counters yet, so it would be
5171                          * zero. So no need to read from the HCA.
5172                          */
5173                         goto done;
5174                 }
5175                 ret = mlx5_lag_query_cong_counters(dev->mdev,
5176                                                    stats->value +
5177                                                    port->cnts.num_q_counters,
5178                                                    port->cnts.num_cong_counters,
5179                                                    port->cnts.offsets +
5180                                                    port->cnts.num_q_counters);
5181
5182                 mlx5_ib_put_native_port_mdev(dev, port_num);
5183                 if (ret)
5184                         return ret;
5185         }
5186
5187 done:
5188         return num_counters;
5189 }
5190
5191 static struct net_device*
5192 mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
5193                           u8 port_num,
5194                           enum rdma_netdev_t type,
5195                           const char *name,
5196                           unsigned char name_assign_type,
5197                           void (*setup)(struct net_device *))
5198 {
5199         struct net_device *netdev;
5200
5201         if (type != RDMA_NETDEV_IPOIB)
5202                 return ERR_PTR(-EOPNOTSUPP);
5203
5204         netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
5205                                         name, setup);
5206         return netdev;
5207 }
5208
5209 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
5210 {
5211         if (!dev->delay_drop.dbg)
5212                 return;
5213         debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
5214         kfree(dev->delay_drop.dbg);
5215         dev->delay_drop.dbg = NULL;
5216 }
5217
5218 static void cancel_delay_drop(struct mlx5_ib_dev *dev)
5219 {
5220         if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5221                 return;
5222
5223         cancel_work_sync(&dev->delay_drop.delay_drop_work);
5224         delay_drop_debugfs_cleanup(dev);
5225 }
5226
5227 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
5228                                        size_t count, loff_t *pos)
5229 {
5230         struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5231         char lbuf[20];
5232         int len;
5233
5234         len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
5235         return simple_read_from_buffer(buf, count, pos, lbuf, len);
5236 }
5237
5238 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
5239                                         size_t count, loff_t *pos)
5240 {
5241         struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5242         u32 timeout;
5243         u32 var;
5244
5245         if (kstrtouint_from_user(buf, count, 0, &var))
5246                 return -EFAULT;
5247
5248         timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
5249                         1000);
5250         if (timeout != var)
5251                 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
5252                             timeout);
5253
5254         delay_drop->timeout = timeout;
5255
5256         return count;
5257 }
5258
5259 static const struct file_operations fops_delay_drop_timeout = {
5260         .owner  = THIS_MODULE,
5261         .open   = simple_open,
5262         .write  = delay_drop_timeout_write,
5263         .read   = delay_drop_timeout_read,
5264 };
5265
5266 static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
5267 {
5268         struct mlx5_ib_dbg_delay_drop *dbg;
5269
5270         if (!mlx5_debugfs_root)
5271                 return 0;
5272
5273         dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
5274         if (!dbg)
5275                 return -ENOMEM;
5276
5277         dev->delay_drop.dbg = dbg;
5278
5279         dbg->dir_debugfs =
5280                 debugfs_create_dir("delay_drop",
5281                                    dev->mdev->priv.dbg_root);
5282         if (!dbg->dir_debugfs)
5283                 goto out_debugfs;
5284
5285         dbg->events_cnt_debugfs =
5286                 debugfs_create_atomic_t("num_timeout_events", 0400,
5287                                         dbg->dir_debugfs,
5288                                         &dev->delay_drop.events_cnt);
5289         if (!dbg->events_cnt_debugfs)
5290                 goto out_debugfs;
5291
5292         dbg->rqs_cnt_debugfs =
5293                 debugfs_create_atomic_t("num_rqs", 0400,
5294                                         dbg->dir_debugfs,
5295                                         &dev->delay_drop.rqs_cnt);
5296         if (!dbg->rqs_cnt_debugfs)
5297                 goto out_debugfs;
5298
5299         dbg->timeout_debugfs =
5300                 debugfs_create_file("timeout", 0600,
5301                                     dbg->dir_debugfs,
5302                                     &dev->delay_drop,
5303                                     &fops_delay_drop_timeout);
5304         if (!dbg->timeout_debugfs)
5305                 goto out_debugfs;
5306
5307         return 0;
5308
5309 out_debugfs:
5310         delay_drop_debugfs_cleanup(dev);
5311         return -ENOMEM;
5312 }
5313
5314 static void init_delay_drop(struct mlx5_ib_dev *dev)
5315 {
5316         if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5317                 return;
5318
5319         mutex_init(&dev->delay_drop.lock);
5320         dev->delay_drop.dev = dev;
5321         dev->delay_drop.activate = false;
5322         dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
5323         INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
5324         atomic_set(&dev->delay_drop.rqs_cnt, 0);
5325         atomic_set(&dev->delay_drop.events_cnt, 0);
5326
5327         if (delay_drop_debugfs_init(dev))
5328                 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
5329 }
5330
5331 static const struct cpumask *
5332 mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector)
5333 {
5334         struct mlx5_ib_dev *dev = to_mdev(ibdev);
5335
5336         return mlx5_get_vector_affinity_hint(dev->mdev, comp_vector);
5337 }
5338
5339 /* The mlx5_ib_multiport_mutex should be held when calling this function */
5340 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
5341                                       struct mlx5_ib_multiport_info *mpi)
5342 {
5343         u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5344         struct mlx5_ib_port *port = &ibdev->port[port_num];
5345         int comps;
5346         int err;
5347         int i;
5348
5349         mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
5350
5351         spin_lock(&port->mp.mpi_lock);
5352         if (!mpi->ibdev) {
5353                 spin_unlock(&port->mp.mpi_lock);
5354                 return;
5355         }
5356         mpi->ibdev = NULL;
5357
5358         spin_unlock(&port->mp.mpi_lock);
5359         mlx5_remove_netdev_notifier(ibdev, port_num);
5360         spin_lock(&port->mp.mpi_lock);
5361
5362         comps = mpi->mdev_refcnt;
5363         if (comps) {
5364                 mpi->unaffiliate = true;
5365                 init_completion(&mpi->unref_comp);
5366                 spin_unlock(&port->mp.mpi_lock);
5367
5368                 for (i = 0; i < comps; i++)
5369                         wait_for_completion(&mpi->unref_comp);
5370
5371                 spin_lock(&port->mp.mpi_lock);
5372                 mpi->unaffiliate = false;
5373         }
5374
5375         port->mp.mpi = NULL;
5376
5377         spin_unlock(&port->mp.mpi_lock);
5378
5379         err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
5380
5381         mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
5382         /* Log an error, still needed to cleanup the pointers and add
5383          * it back to the list.
5384          */
5385         if (err)
5386                 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
5387                             port_num + 1);
5388
5389         ibdev->roce[port_num].last_port_state = IB_PORT_DOWN;
5390 }
5391
5392 /* The mlx5_ib_multiport_mutex should be held when calling this function */
5393 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
5394                                     struct mlx5_ib_multiport_info *mpi)
5395 {
5396         u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5397         int err;
5398
5399         spin_lock(&ibdev->port[port_num].mp.mpi_lock);
5400         if (ibdev->port[port_num].mp.mpi) {
5401                 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n",
5402                             port_num + 1);
5403                 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5404                 return false;
5405         }
5406
5407         ibdev->port[port_num].mp.mpi = mpi;
5408         mpi->ibdev = ibdev;
5409         spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5410
5411         err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
5412         if (err)
5413                 goto unbind;
5414
5415         err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
5416         if (err)
5417                 goto unbind;
5418
5419         err = mlx5_add_netdev_notifier(ibdev, port_num);
5420         if (err) {
5421                 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
5422                             port_num + 1);
5423                 goto unbind;
5424         }
5425
5426         err = mlx5_ib_init_cong_debugfs(ibdev, port_num);
5427         if (err)
5428                 goto unbind;
5429
5430         return true;
5431
5432 unbind:
5433         mlx5_ib_unbind_slave_port(ibdev, mpi);
5434         return false;
5435 }
5436
5437 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
5438 {
5439         int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5440         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5441                                                           port_num + 1);
5442         struct mlx5_ib_multiport_info *mpi;
5443         int err;
5444         int i;
5445
5446         if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5447                 return 0;
5448
5449         err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
5450                                                      &dev->sys_image_guid);
5451         if (err)
5452                 return err;
5453
5454         err = mlx5_nic_vport_enable_roce(dev->mdev);
5455         if (err)
5456                 return err;
5457
5458         mutex_lock(&mlx5_ib_multiport_mutex);
5459         for (i = 0; i < dev->num_ports; i++) {
5460                 bool bound = false;
5461
5462                 /* build a stub multiport info struct for the native port. */
5463                 if (i == port_num) {
5464                         mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5465                         if (!mpi) {
5466                                 mutex_unlock(&mlx5_ib_multiport_mutex);
5467                                 mlx5_nic_vport_disable_roce(dev->mdev);
5468                                 return -ENOMEM;
5469                         }
5470
5471                         mpi->is_master = true;
5472                         mpi->mdev = dev->mdev;
5473                         mpi->sys_image_guid = dev->sys_image_guid;
5474                         dev->port[i].mp.mpi = mpi;
5475                         mpi->ibdev = dev;
5476                         mpi = NULL;
5477                         continue;
5478                 }
5479
5480                 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
5481                                     list) {
5482                         if (dev->sys_image_guid == mpi->sys_image_guid &&
5483                             (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
5484                                 bound = mlx5_ib_bind_slave_port(dev, mpi);
5485                         }
5486
5487                         if (bound) {
5488                                 dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n");
5489                                 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
5490                                 list_del(&mpi->list);
5491                                 break;
5492                         }
5493                 }
5494                 if (!bound) {
5495                         get_port_caps(dev, i + 1);
5496                         mlx5_ib_dbg(dev, "no free port found for port %d\n",
5497                                     i + 1);
5498                 }
5499         }
5500
5501         list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
5502         mutex_unlock(&mlx5_ib_multiport_mutex);
5503         return err;
5504 }
5505
5506 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
5507 {
5508         int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5509         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5510                                                           port_num + 1);
5511         int i;
5512
5513         if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5514                 return;
5515
5516         mutex_lock(&mlx5_ib_multiport_mutex);
5517         for (i = 0; i < dev->num_ports; i++) {
5518                 if (dev->port[i].mp.mpi) {
5519                         /* Destroy the native port stub */
5520                         if (i == port_num) {
5521                                 kfree(dev->port[i].mp.mpi);
5522                                 dev->port[i].mp.mpi = NULL;
5523                         } else {
5524                                 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
5525                                 list_add_tail(&dev->port[i].mp.mpi->list,
5526                                               &mlx5_ib_unaffiliated_port_list);
5527                                 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
5528                         }
5529                 }
5530         }
5531
5532         mlx5_ib_dbg(dev, "removing from devlist\n");
5533         list_del(&dev->ib_dev_list);
5534         mutex_unlock(&mlx5_ib_multiport_mutex);
5535
5536         mlx5_nic_vport_disable_roce(dev->mdev);
5537 }
5538
5539 ADD_UVERBS_ATTRIBUTES_SIMPLE(
5540         mlx5_ib_dm,
5541         UVERBS_OBJECT_DM,
5542         UVERBS_METHOD_DM_ALLOC,
5543         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
5544                             UVERBS_ATTR_TYPE(u64),
5545                             UA_MANDATORY),
5546         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
5547                             UVERBS_ATTR_TYPE(u16),
5548                             UA_MANDATORY));
5549
5550 ADD_UVERBS_ATTRIBUTES_SIMPLE(
5551         mlx5_ib_flow_action,
5552         UVERBS_OBJECT_FLOW_ACTION,
5553         UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
5554         UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
5555                              enum mlx5_ib_uapi_flow_action_flags));
5556
5557 static int populate_specs_root(struct mlx5_ib_dev *dev)
5558 {
5559         const struct uverbs_object_tree_def **trees = dev->driver_trees;
5560         size_t num_trees = 0;
5561
5562         if (mlx5_accel_ipsec_device_caps(dev->mdev) &
5563             MLX5_ACCEL_IPSEC_CAP_DEVICE)
5564                 trees[num_trees++] = &mlx5_ib_flow_action;
5565
5566         if (MLX5_CAP_DEV_MEM(dev->mdev, memic))
5567                 trees[num_trees++] = &mlx5_ib_dm;
5568
5569         if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
5570             MLX5_GENERAL_OBJ_TYPES_CAP_UCTX)
5571                 trees[num_trees++] = mlx5_ib_get_devx_tree();
5572
5573         num_trees += mlx5_ib_get_flow_trees(trees + num_trees);
5574
5575         WARN_ON(num_trees >= ARRAY_SIZE(dev->driver_trees));
5576         trees[num_trees] = NULL;
5577         dev->ib_dev.driver_specs = trees;
5578
5579         return 0;
5580 }
5581
5582 static int mlx5_ib_read_counters(struct ib_counters *counters,
5583                                  struct ib_counters_read_attr *read_attr,
5584                                  struct uverbs_attr_bundle *attrs)
5585 {
5586         struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
5587         struct mlx5_read_counters_attr mread_attr = {};
5588         struct mlx5_ib_flow_counters_desc *desc;
5589         int ret, i;
5590
5591         mutex_lock(&mcounters->mcntrs_mutex);
5592         if (mcounters->cntrs_max_index > read_attr->ncounters) {
5593                 ret = -EINVAL;
5594                 goto err_bound;
5595         }
5596
5597         mread_attr.out = kcalloc(mcounters->counters_num, sizeof(u64),
5598                                  GFP_KERNEL);
5599         if (!mread_attr.out) {
5600                 ret = -ENOMEM;
5601                 goto err_bound;
5602         }
5603
5604         mread_attr.hw_cntrs_hndl = mcounters->hw_cntrs_hndl;
5605         mread_attr.flags = read_attr->flags;
5606         ret = mcounters->read_counters(counters->device, &mread_attr);
5607         if (ret)
5608                 goto err_read;
5609
5610         /* do the pass over the counters data array to assign according to the
5611          * descriptions and indexing pairs
5612          */
5613         desc = mcounters->counters_data;
5614         for (i = 0; i < mcounters->ncounters; i++)
5615                 read_attr->counters_buff[desc[i].index] += mread_attr.out[desc[i].description];
5616
5617 err_read:
5618         kfree(mread_attr.out);
5619 err_bound:
5620         mutex_unlock(&mcounters->mcntrs_mutex);
5621         return ret;
5622 }
5623
5624 static int mlx5_ib_destroy_counters(struct ib_counters *counters)
5625 {
5626         struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
5627
5628         counters_clear_description(counters);
5629         if (mcounters->hw_cntrs_hndl)
5630                 mlx5_fc_destroy(to_mdev(counters->device)->mdev,
5631                                 mcounters->hw_cntrs_hndl);
5632
5633         kfree(mcounters);
5634
5635         return 0;
5636 }
5637
5638 static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device,
5639                                                    struct uverbs_attr_bundle *attrs)
5640 {
5641         struct mlx5_ib_mcounters *mcounters;
5642
5643         mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL);
5644         if (!mcounters)
5645                 return ERR_PTR(-ENOMEM);
5646
5647         mutex_init(&mcounters->mcntrs_mutex);
5648
5649         return &mcounters->ibcntrs;
5650 }
5651
5652 void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
5653 {
5654         mlx5_ib_cleanup_multiport_master(dev);
5655 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5656         cleanup_srcu_struct(&dev->mr_srcu);
5657 #endif
5658         kfree(dev->port);
5659 }
5660
5661 int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
5662 {
5663         struct mlx5_core_dev *mdev = dev->mdev;
5664         const char *name;
5665         int err;
5666         int i;
5667
5668         dev->port = kcalloc(dev->num_ports, sizeof(*dev->port),
5669                             GFP_KERNEL);
5670         if (!dev->port)
5671                 return -ENOMEM;
5672
5673         for (i = 0; i < dev->num_ports; i++) {
5674                 spin_lock_init(&dev->port[i].mp.mpi_lock);
5675                 rwlock_init(&dev->roce[i].netdev_lock);
5676         }
5677
5678         err = mlx5_ib_init_multiport_master(dev);
5679         if (err)
5680                 goto err_free_port;
5681
5682         if (!mlx5_core_mp_enabled(mdev)) {
5683                 for (i = 1; i <= dev->num_ports; i++) {
5684                         err = get_port_caps(dev, i);
5685                         if (err)
5686                                 break;
5687                 }
5688         } else {
5689                 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
5690         }
5691         if (err)
5692                 goto err_mp;
5693
5694         if (mlx5_use_mad_ifc(dev))
5695                 get_ext_port_caps(dev);
5696
5697         if (!mlx5_lag_is_active(mdev))
5698                 name = "mlx5_%d";
5699         else
5700                 name = "mlx5_bond_%d";
5701
5702         strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
5703         dev->ib_dev.owner               = THIS_MODULE;
5704         dev->ib_dev.node_type           = RDMA_NODE_IB_CA;
5705         dev->ib_dev.local_dma_lkey      = 0 /* not supported for now */;
5706         dev->ib_dev.phys_port_cnt       = dev->num_ports;
5707         dev->ib_dev.num_comp_vectors    =
5708                 dev->mdev->priv.eq_table.num_comp_vectors;
5709         dev->ib_dev.dev.parent          = &mdev->pdev->dev;
5710
5711         mutex_init(&dev->cap_mask_mutex);
5712         INIT_LIST_HEAD(&dev->qp_list);
5713         spin_lock_init(&dev->reset_flow_resource_lock);
5714
5715         spin_lock_init(&dev->memic.memic_lock);
5716         dev->memic.dev = mdev;
5717
5718 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5719         err = init_srcu_struct(&dev->mr_srcu);
5720         if (err)
5721                 goto err_free_port;
5722 #endif
5723
5724         return 0;
5725 err_mp:
5726         mlx5_ib_cleanup_multiport_master(dev);
5727
5728 err_free_port:
5729         kfree(dev->port);
5730
5731         return -ENOMEM;
5732 }
5733
5734 static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev)
5735 {
5736         dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL);
5737
5738         if (!dev->flow_db)
5739                 return -ENOMEM;
5740
5741         mutex_init(&dev->flow_db->lock);
5742
5743         return 0;
5744 }
5745
5746 int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev)
5747 {
5748         struct mlx5_ib_dev *nic_dev;
5749
5750         nic_dev = mlx5_ib_get_uplink_ibdev(dev->mdev->priv.eswitch);
5751
5752         if (!nic_dev)
5753                 return -EINVAL;
5754
5755         dev->flow_db = nic_dev->flow_db;
5756
5757         return 0;
5758 }
5759
5760 static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev)
5761 {
5762         kfree(dev->flow_db);
5763 }
5764
5765 int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
5766 {
5767         struct mlx5_core_dev *mdev = dev->mdev;
5768         int err;
5769
5770         dev->ib_dev.uverbs_abi_ver      = MLX5_IB_UVERBS_ABI_VERSION;
5771         dev->ib_dev.uverbs_cmd_mask     =
5772                 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT)         |
5773                 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE)        |
5774                 (1ull << IB_USER_VERBS_CMD_QUERY_PORT)          |
5775                 (1ull << IB_USER_VERBS_CMD_ALLOC_PD)            |
5776                 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD)          |
5777                 (1ull << IB_USER_VERBS_CMD_CREATE_AH)           |
5778                 (1ull << IB_USER_VERBS_CMD_DESTROY_AH)          |
5779                 (1ull << IB_USER_VERBS_CMD_REG_MR)              |
5780                 (1ull << IB_USER_VERBS_CMD_REREG_MR)            |
5781                 (1ull << IB_USER_VERBS_CMD_DEREG_MR)            |
5782                 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
5783                 (1ull << IB_USER_VERBS_CMD_CREATE_CQ)           |
5784                 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ)           |
5785                 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ)          |
5786                 (1ull << IB_USER_VERBS_CMD_CREATE_QP)           |
5787                 (1ull << IB_USER_VERBS_CMD_MODIFY_QP)           |
5788                 (1ull << IB_USER_VERBS_CMD_QUERY_QP)            |
5789                 (1ull << IB_USER_VERBS_CMD_DESTROY_QP)          |
5790                 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST)        |
5791                 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST)        |
5792                 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ)          |
5793                 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ)          |
5794                 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ)           |
5795                 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ)         |
5796                 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ)         |
5797                 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
5798         dev->ib_dev.uverbs_ex_cmd_mask =
5799                 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE)     |
5800                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ)        |
5801                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP)        |
5802                 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP)        |
5803                 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
5804
5805         dev->ib_dev.query_device        = mlx5_ib_query_device;
5806         dev->ib_dev.get_link_layer      = mlx5_ib_port_link_layer;
5807         dev->ib_dev.query_gid           = mlx5_ib_query_gid;
5808         dev->ib_dev.add_gid             = mlx5_ib_add_gid;
5809         dev->ib_dev.del_gid             = mlx5_ib_del_gid;
5810         dev->ib_dev.query_pkey          = mlx5_ib_query_pkey;
5811         dev->ib_dev.modify_device       = mlx5_ib_modify_device;
5812         dev->ib_dev.modify_port         = mlx5_ib_modify_port;
5813         dev->ib_dev.alloc_ucontext      = mlx5_ib_alloc_ucontext;
5814         dev->ib_dev.dealloc_ucontext    = mlx5_ib_dealloc_ucontext;
5815         dev->ib_dev.mmap                = mlx5_ib_mmap;
5816         dev->ib_dev.alloc_pd            = mlx5_ib_alloc_pd;
5817         dev->ib_dev.dealloc_pd          = mlx5_ib_dealloc_pd;
5818         dev->ib_dev.create_ah           = mlx5_ib_create_ah;
5819         dev->ib_dev.query_ah            = mlx5_ib_query_ah;
5820         dev->ib_dev.destroy_ah          = mlx5_ib_destroy_ah;
5821         dev->ib_dev.create_srq          = mlx5_ib_create_srq;
5822         dev->ib_dev.modify_srq          = mlx5_ib_modify_srq;
5823         dev->ib_dev.query_srq           = mlx5_ib_query_srq;
5824         dev->ib_dev.destroy_srq         = mlx5_ib_destroy_srq;
5825         dev->ib_dev.post_srq_recv       = mlx5_ib_post_srq_recv;
5826         dev->ib_dev.create_qp           = mlx5_ib_create_qp;
5827         dev->ib_dev.modify_qp           = mlx5_ib_modify_qp;
5828         dev->ib_dev.query_qp            = mlx5_ib_query_qp;
5829         dev->ib_dev.destroy_qp          = mlx5_ib_destroy_qp;
5830         dev->ib_dev.drain_sq            = mlx5_ib_drain_sq;
5831         dev->ib_dev.drain_rq            = mlx5_ib_drain_rq;
5832         dev->ib_dev.post_send           = mlx5_ib_post_send;
5833         dev->ib_dev.post_recv           = mlx5_ib_post_recv;
5834         dev->ib_dev.create_cq           = mlx5_ib_create_cq;
5835         dev->ib_dev.modify_cq           = mlx5_ib_modify_cq;
5836         dev->ib_dev.resize_cq           = mlx5_ib_resize_cq;
5837         dev->ib_dev.destroy_cq          = mlx5_ib_destroy_cq;
5838         dev->ib_dev.poll_cq             = mlx5_ib_poll_cq;
5839         dev->ib_dev.req_notify_cq       = mlx5_ib_arm_cq;
5840         dev->ib_dev.get_dma_mr          = mlx5_ib_get_dma_mr;
5841         dev->ib_dev.reg_user_mr         = mlx5_ib_reg_user_mr;
5842         dev->ib_dev.rereg_user_mr       = mlx5_ib_rereg_user_mr;
5843         dev->ib_dev.dereg_mr            = mlx5_ib_dereg_mr;
5844         dev->ib_dev.attach_mcast        = mlx5_ib_mcg_attach;
5845         dev->ib_dev.detach_mcast        = mlx5_ib_mcg_detach;
5846         dev->ib_dev.process_mad         = mlx5_ib_process_mad;
5847         dev->ib_dev.alloc_mr            = mlx5_ib_alloc_mr;
5848         dev->ib_dev.map_mr_sg           = mlx5_ib_map_mr_sg;
5849         dev->ib_dev.check_mr_status     = mlx5_ib_check_mr_status;
5850         dev->ib_dev.get_dev_fw_str      = get_dev_fw_str;
5851         dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity;
5852         if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
5853                 dev->ib_dev.alloc_rdma_netdev   = mlx5_ib_alloc_rdma_netdev;
5854
5855         if (mlx5_core_is_pf(mdev)) {
5856                 dev->ib_dev.get_vf_config       = mlx5_ib_get_vf_config;
5857                 dev->ib_dev.set_vf_link_state   = mlx5_ib_set_vf_link_state;
5858                 dev->ib_dev.get_vf_stats        = mlx5_ib_get_vf_stats;
5859                 dev->ib_dev.set_vf_guid         = mlx5_ib_set_vf_guid;
5860         }
5861
5862         dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
5863
5864         dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
5865
5866         if (MLX5_CAP_GEN(mdev, imaicl)) {
5867                 dev->ib_dev.alloc_mw            = mlx5_ib_alloc_mw;
5868                 dev->ib_dev.dealloc_mw          = mlx5_ib_dealloc_mw;
5869                 dev->ib_dev.uverbs_cmd_mask |=
5870                         (1ull << IB_USER_VERBS_CMD_ALLOC_MW)    |
5871                         (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
5872         }
5873
5874         if (MLX5_CAP_GEN(mdev, xrc)) {
5875                 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
5876                 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
5877                 dev->ib_dev.uverbs_cmd_mask |=
5878                         (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
5879                         (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
5880         }
5881
5882         if (MLX5_CAP_DEV_MEM(mdev, memic)) {
5883                 dev->ib_dev.alloc_dm = mlx5_ib_alloc_dm;
5884                 dev->ib_dev.dealloc_dm = mlx5_ib_dealloc_dm;
5885                 dev->ib_dev.reg_dm_mr = mlx5_ib_reg_dm_mr;
5886         }
5887
5888         dev->ib_dev.create_flow = mlx5_ib_create_flow;
5889         dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
5890         dev->ib_dev.uverbs_ex_cmd_mask |=
5891                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
5892                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
5893         dev->ib_dev.create_flow_action_esp = mlx5_ib_create_flow_action_esp;
5894         dev->ib_dev.destroy_flow_action = mlx5_ib_destroy_flow_action;
5895         dev->ib_dev.modify_flow_action_esp = mlx5_ib_modify_flow_action_esp;
5896         dev->ib_dev.driver_id = RDMA_DRIVER_MLX5;
5897         dev->ib_dev.create_counters = mlx5_ib_create_counters;
5898         dev->ib_dev.destroy_counters = mlx5_ib_destroy_counters;
5899         dev->ib_dev.read_counters = mlx5_ib_read_counters;
5900
5901         err = init_node_data(dev);
5902         if (err)
5903                 return err;
5904
5905         if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
5906             (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
5907              MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
5908                 mutex_init(&dev->lb_mutex);
5909
5910         return 0;
5911 }
5912
5913 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
5914 {
5915         dev->ib_dev.get_port_immutable  = mlx5_port_immutable;
5916         dev->ib_dev.query_port          = mlx5_ib_query_port;
5917
5918         return 0;
5919 }
5920
5921 int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev)
5922 {
5923         dev->ib_dev.get_port_immutable  = mlx5_port_rep_immutable;
5924         dev->ib_dev.query_port          = mlx5_ib_rep_query_port;
5925
5926         return 0;
5927 }
5928
5929 static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev)
5930 {
5931         u8 port_num;
5932         int i;
5933
5934         for (i = 0; i < dev->num_ports; i++) {
5935                 dev->roce[i].dev = dev;
5936                 dev->roce[i].native_port_num = i + 1;
5937                 dev->roce[i].last_port_state = IB_PORT_DOWN;
5938         }
5939
5940         dev->ib_dev.get_netdev  = mlx5_ib_get_netdev;
5941         dev->ib_dev.create_wq    = mlx5_ib_create_wq;
5942         dev->ib_dev.modify_wq    = mlx5_ib_modify_wq;
5943         dev->ib_dev.destroy_wq   = mlx5_ib_destroy_wq;
5944         dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
5945         dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
5946
5947         dev->ib_dev.uverbs_ex_cmd_mask |=
5948                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
5949                         (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
5950                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
5951                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
5952                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
5953
5954         port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5955
5956         return mlx5_add_netdev_notifier(dev, port_num);
5957 }
5958
5959 static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev)
5960 {
5961         u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5962
5963         mlx5_remove_netdev_notifier(dev, port_num);
5964 }
5965
5966 int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev)
5967 {
5968         struct mlx5_core_dev *mdev = dev->mdev;
5969         enum rdma_link_layer ll;
5970         int port_type_cap;
5971         int err = 0;
5972
5973         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5974         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5975
5976         if (ll == IB_LINK_LAYER_ETHERNET)
5977                 err = mlx5_ib_stage_common_roce_init(dev);
5978
5979         return err;
5980 }
5981
5982 void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev)
5983 {
5984         mlx5_ib_stage_common_roce_cleanup(dev);
5985 }
5986
5987 static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
5988 {
5989         struct mlx5_core_dev *mdev = dev->mdev;
5990         enum rdma_link_layer ll;
5991         int port_type_cap;
5992         int err;
5993
5994         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5995         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5996
5997         if (ll == IB_LINK_LAYER_ETHERNET) {
5998                 err = mlx5_ib_stage_common_roce_init(dev);
5999                 if (err)
6000                         return err;
6001
6002                 err = mlx5_enable_eth(dev);
6003                 if (err)
6004                         goto cleanup;
6005         }
6006
6007         return 0;
6008 cleanup:
6009         mlx5_ib_stage_common_roce_cleanup(dev);
6010
6011         return err;
6012 }
6013
6014 static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
6015 {
6016         struct mlx5_core_dev *mdev = dev->mdev;
6017         enum rdma_link_layer ll;
6018         int port_type_cap;
6019
6020         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6021         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6022
6023         if (ll == IB_LINK_LAYER_ETHERNET) {
6024                 mlx5_disable_eth(dev);
6025                 mlx5_ib_stage_common_roce_cleanup(dev);
6026         }
6027 }
6028
6029 int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
6030 {
6031         return create_dev_resources(&dev->devr);
6032 }
6033
6034 void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
6035 {
6036         destroy_dev_resources(&dev->devr);
6037 }
6038
6039 static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
6040 {
6041         mlx5_ib_internal_fill_odp_caps(dev);
6042
6043         return mlx5_ib_odp_init_one(dev);
6044 }
6045
6046 int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
6047 {
6048         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
6049                 dev->ib_dev.get_hw_stats        = mlx5_ib_get_hw_stats;
6050                 dev->ib_dev.alloc_hw_stats      = mlx5_ib_alloc_hw_stats;
6051
6052                 return mlx5_ib_alloc_counters(dev);
6053         }
6054
6055         return 0;
6056 }
6057
6058 void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
6059 {
6060         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
6061                 mlx5_ib_dealloc_counters(dev);
6062 }
6063
6064 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
6065 {
6066         return mlx5_ib_init_cong_debugfs(dev,
6067                                          mlx5_core_native_port_num(dev->mdev) - 1);
6068 }
6069
6070 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
6071 {
6072         mlx5_ib_cleanup_cong_debugfs(dev,
6073                                      mlx5_core_native_port_num(dev->mdev) - 1);
6074 }
6075
6076 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
6077 {
6078         dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
6079         return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
6080 }
6081
6082 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
6083 {
6084         mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
6085 }
6086
6087 int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
6088 {
6089         int err;
6090
6091         err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
6092         if (err)
6093                 return err;
6094
6095         err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
6096         if (err)
6097                 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
6098
6099         return err;
6100 }
6101
6102 void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
6103 {
6104         mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
6105         mlx5_free_bfreg(dev->mdev, &dev->bfreg);
6106 }
6107
6108 static int mlx5_ib_stage_populate_specs(struct mlx5_ib_dev *dev)
6109 {
6110         return populate_specs_root(dev);
6111 }
6112
6113 int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
6114 {
6115         return ib_register_device(&dev->ib_dev, NULL);
6116 }
6117
6118 void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
6119 {
6120         destroy_umrc_res(dev);
6121 }
6122
6123 void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
6124 {
6125         ib_unregister_device(&dev->ib_dev);
6126 }
6127
6128 int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
6129 {
6130         return create_umr_res(dev);
6131 }
6132
6133 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
6134 {
6135         init_delay_drop(dev);
6136
6137         return 0;
6138 }
6139
6140 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
6141 {
6142         cancel_delay_drop(dev);
6143 }
6144
6145 int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev)
6146 {
6147         int err;
6148         int i;
6149
6150         for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
6151                 err = device_create_file(&dev->ib_dev.dev,
6152                                          mlx5_class_attributes[i]);
6153                 if (err)
6154                         return err;
6155         }
6156
6157         return 0;
6158 }
6159
6160 static int mlx5_ib_stage_rep_reg_init(struct mlx5_ib_dev *dev)
6161 {
6162         mlx5_ib_register_vport_reps(dev);
6163
6164         return 0;
6165 }
6166
6167 static void mlx5_ib_stage_rep_reg_cleanup(struct mlx5_ib_dev *dev)
6168 {
6169         mlx5_ib_unregister_vport_reps(dev);
6170 }
6171
6172 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
6173                       const struct mlx5_ib_profile *profile,
6174                       int stage)
6175 {
6176         /* Number of stages to cleanup */
6177         while (stage) {
6178                 stage--;
6179                 if (profile->stage[stage].cleanup)
6180                         profile->stage[stage].cleanup(dev);
6181         }
6182
6183         ib_dealloc_device((struct ib_device *)dev);
6184 }
6185
6186 void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
6187                     const struct mlx5_ib_profile *profile)
6188 {
6189         int err;
6190         int i;
6191
6192         printk_once(KERN_INFO "%s", mlx5_version);
6193
6194         for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
6195                 if (profile->stage[i].init) {
6196                         err = profile->stage[i].init(dev);
6197                         if (err)
6198                                 goto err_out;
6199                 }
6200         }
6201
6202         dev->profile = profile;
6203         dev->ib_active = true;
6204
6205         return dev;
6206
6207 err_out:
6208         __mlx5_ib_remove(dev, profile, i);
6209
6210         return NULL;
6211 }
6212
6213 static const struct mlx5_ib_profile pf_profile = {
6214         STAGE_CREATE(MLX5_IB_STAGE_INIT,
6215                      mlx5_ib_stage_init_init,
6216                      mlx5_ib_stage_init_cleanup),
6217         STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6218                      mlx5_ib_stage_flow_db_init,
6219                      mlx5_ib_stage_flow_db_cleanup),
6220         STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6221                      mlx5_ib_stage_caps_init,
6222                      NULL),
6223         STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6224                      mlx5_ib_stage_non_default_cb,
6225                      NULL),
6226         STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6227                      mlx5_ib_stage_roce_init,
6228                      mlx5_ib_stage_roce_cleanup),
6229         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6230                      mlx5_ib_stage_dev_res_init,
6231                      mlx5_ib_stage_dev_res_cleanup),
6232         STAGE_CREATE(MLX5_IB_STAGE_ODP,
6233                      mlx5_ib_stage_odp_init,
6234                      NULL),
6235         STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6236                      mlx5_ib_stage_counters_init,
6237                      mlx5_ib_stage_counters_cleanup),
6238         STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
6239                      mlx5_ib_stage_cong_debugfs_init,
6240                      mlx5_ib_stage_cong_debugfs_cleanup),
6241         STAGE_CREATE(MLX5_IB_STAGE_UAR,
6242                      mlx5_ib_stage_uar_init,
6243                      mlx5_ib_stage_uar_cleanup),
6244         STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6245                      mlx5_ib_stage_bfrag_init,
6246                      mlx5_ib_stage_bfrag_cleanup),
6247         STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6248                      NULL,
6249                      mlx5_ib_stage_pre_ib_reg_umr_cleanup),
6250         STAGE_CREATE(MLX5_IB_STAGE_SPECS,
6251                      mlx5_ib_stage_populate_specs,
6252                      NULL),
6253         STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6254                      mlx5_ib_stage_ib_reg_init,
6255                      mlx5_ib_stage_ib_reg_cleanup),
6256         STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6257                      mlx5_ib_stage_post_ib_reg_umr_init,
6258                      NULL),
6259         STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
6260                      mlx5_ib_stage_delay_drop_init,
6261                      mlx5_ib_stage_delay_drop_cleanup),
6262         STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
6263                      mlx5_ib_stage_class_attr_init,
6264                      NULL),
6265 };
6266
6267 static const struct mlx5_ib_profile nic_rep_profile = {
6268         STAGE_CREATE(MLX5_IB_STAGE_INIT,
6269                      mlx5_ib_stage_init_init,
6270                      mlx5_ib_stage_init_cleanup),
6271         STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6272                      mlx5_ib_stage_flow_db_init,
6273                      mlx5_ib_stage_flow_db_cleanup),
6274         STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6275                      mlx5_ib_stage_caps_init,
6276                      NULL),
6277         STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6278                      mlx5_ib_stage_rep_non_default_cb,
6279                      NULL),
6280         STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6281                      mlx5_ib_stage_rep_roce_init,
6282                      mlx5_ib_stage_rep_roce_cleanup),
6283         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6284                      mlx5_ib_stage_dev_res_init,
6285                      mlx5_ib_stage_dev_res_cleanup),
6286         STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6287                      mlx5_ib_stage_counters_init,
6288                      mlx5_ib_stage_counters_cleanup),
6289         STAGE_CREATE(MLX5_IB_STAGE_UAR,
6290                      mlx5_ib_stage_uar_init,
6291                      mlx5_ib_stage_uar_cleanup),
6292         STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6293                      mlx5_ib_stage_bfrag_init,
6294                      mlx5_ib_stage_bfrag_cleanup),
6295         STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6296                      NULL,
6297                      mlx5_ib_stage_pre_ib_reg_umr_cleanup),
6298         STAGE_CREATE(MLX5_IB_STAGE_SPECS,
6299                      mlx5_ib_stage_populate_specs,
6300                      NULL),
6301         STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6302                      mlx5_ib_stage_ib_reg_init,
6303                      mlx5_ib_stage_ib_reg_cleanup),
6304         STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6305                      mlx5_ib_stage_post_ib_reg_umr_init,
6306                      NULL),
6307         STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
6308                      mlx5_ib_stage_class_attr_init,
6309                      NULL),
6310         STAGE_CREATE(MLX5_IB_STAGE_REP_REG,
6311                      mlx5_ib_stage_rep_reg_init,
6312                      mlx5_ib_stage_rep_reg_cleanup),
6313 };
6314
6315 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev)
6316 {
6317         struct mlx5_ib_multiport_info *mpi;
6318         struct mlx5_ib_dev *dev;
6319         bool bound = false;
6320         int err;
6321
6322         mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
6323         if (!mpi)
6324                 return NULL;
6325
6326         mpi->mdev = mdev;
6327
6328         err = mlx5_query_nic_vport_system_image_guid(mdev,
6329                                                      &mpi->sys_image_guid);
6330         if (err) {
6331                 kfree(mpi);
6332                 return NULL;
6333         }
6334
6335         mutex_lock(&mlx5_ib_multiport_mutex);
6336         list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
6337                 if (dev->sys_image_guid == mpi->sys_image_guid)
6338                         bound = mlx5_ib_bind_slave_port(dev, mpi);
6339
6340                 if (bound) {
6341                         rdma_roce_rescan_device(&dev->ib_dev);
6342                         mpi->ibdev->ib_active = true;
6343                         break;
6344                 }
6345         }
6346
6347         if (!bound) {
6348                 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
6349                 dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n");
6350         }
6351         mutex_unlock(&mlx5_ib_multiport_mutex);
6352
6353         return mpi;
6354 }
6355
6356 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
6357 {
6358         enum rdma_link_layer ll;
6359         struct mlx5_ib_dev *dev;
6360         int port_type_cap;
6361
6362         printk_once(KERN_INFO "%s", mlx5_version);
6363
6364         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6365         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6366
6367         if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET)
6368                 return mlx5_ib_add_slave_port(mdev);
6369
6370         dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
6371         if (!dev)
6372                 return NULL;
6373
6374         dev->mdev = mdev;
6375         dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
6376                              MLX5_CAP_GEN(mdev, num_vhca_ports));
6377
6378         if (MLX5_ESWITCH_MANAGER(mdev) &&
6379             mlx5_ib_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) {
6380                 dev->rep = mlx5_ib_vport_rep(mdev->priv.eswitch, 0);
6381
6382                 return __mlx5_ib_add(dev, &nic_rep_profile);
6383         }
6384
6385         return __mlx5_ib_add(dev, &pf_profile);
6386 }
6387
6388 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
6389 {
6390         struct mlx5_ib_multiport_info *mpi;
6391         struct mlx5_ib_dev *dev;
6392
6393         if (mlx5_core_is_mp_slave(mdev)) {
6394                 mpi = context;
6395                 mutex_lock(&mlx5_ib_multiport_mutex);
6396                 if (mpi->ibdev)
6397                         mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
6398                 list_del(&mpi->list);
6399                 mutex_unlock(&mlx5_ib_multiport_mutex);
6400                 kfree(mpi);
6401                 return;
6402         }
6403
6404         dev = context;
6405         __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
6406 }
6407
6408 static struct mlx5_interface mlx5_ib_interface = {
6409         .add            = mlx5_ib_add,
6410         .remove         = mlx5_ib_remove,
6411         .event          = mlx5_ib_event,
6412 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
6413         .pfault         = mlx5_ib_pfault,
6414 #endif
6415         .protocol       = MLX5_INTERFACE_PROTOCOL_IB,
6416 };
6417
6418 unsigned long mlx5_ib_get_xlt_emergency_page(void)
6419 {
6420         mutex_lock(&xlt_emergency_page_mutex);
6421         return xlt_emergency_page;
6422 }
6423
6424 void mlx5_ib_put_xlt_emergency_page(void)
6425 {
6426         mutex_unlock(&xlt_emergency_page_mutex);
6427 }
6428
6429 static int __init mlx5_ib_init(void)
6430 {
6431         int err;
6432
6433         xlt_emergency_page = __get_free_page(GFP_KERNEL);
6434         if (!xlt_emergency_page)
6435                 return -ENOMEM;
6436
6437         mutex_init(&xlt_emergency_page_mutex);
6438
6439         mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
6440         if (!mlx5_ib_event_wq) {
6441                 free_page(xlt_emergency_page);
6442                 return -ENOMEM;
6443         }
6444
6445         mlx5_ib_odp_init();
6446
6447         err = mlx5_register_interface(&mlx5_ib_interface);
6448
6449         return err;
6450 }
6451
6452 static void __exit mlx5_ib_cleanup(void)
6453 {
6454         mlx5_unregister_interface(&mlx5_ib_interface);
6455         destroy_workqueue(mlx5_ib_event_wq);
6456         mutex_destroy(&xlt_emergency_page_mutex);
6457         free_page(xlt_emergency_page);
6458 }
6459
6460 module_init(mlx5_ib_init);
6461 module_exit(mlx5_ib_cleanup);