2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/module.h>
34 #include <rdma/ib_umem.h>
35 #include <rdma/ib_cache.h>
36 #include <rdma/ib_user_verbs.h>
37 #include <linux/mlx5/fs.h>
41 /* not supported currently */
42 static int wq_signature;
45 MLX5_IB_ACK_REQ_FREQ = 8,
49 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
50 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
51 MLX5_IB_LINK_TYPE_IB = 0,
52 MLX5_IB_LINK_TYPE_ETH = 1
56 MLX5_IB_SQ_STRIDE = 6,
57 MLX5_IB_SQ_UMR_INLINE_THRESHOLD = 64,
60 static const u32 mlx5_ib_opcode[] = {
61 [IB_WR_SEND] = MLX5_OPCODE_SEND,
62 [IB_WR_LSO] = MLX5_OPCODE_LSO,
63 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
64 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
65 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
66 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
67 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
68 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
69 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
70 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
71 [IB_WR_REG_MR] = MLX5_OPCODE_UMR,
72 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
73 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
74 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
77 struct mlx5_wqe_eth_pad {
81 enum raw_qp_set_mask_map {
82 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0,
83 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1,
86 struct mlx5_modify_raw_qp_param {
89 u32 set_mask; /* raw_qp_set_mask_map */
91 struct mlx5_rate_limit rl;
96 static void get_cqs(enum ib_qp_type qp_type,
97 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
98 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
100 static int is_qp0(enum ib_qp_type qp_type)
102 return qp_type == IB_QPT_SMI;
105 static int is_sqp(enum ib_qp_type qp_type)
107 return is_qp0(qp_type) || is_qp1(qp_type);
110 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
112 return mlx5_buf_offset(&qp->buf, offset);
115 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
117 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
120 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
122 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
126 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
128 * @qp: QP to copy from.
129 * @send: copy from the send queue when non-zero, use the receive queue
131 * @wqe_index: index to start copying from. For send work queues, the
132 * wqe_index is in units of MLX5_SEND_WQE_BB.
133 * For receive work queue, it is the number of work queue
134 * element in the queue.
135 * @buffer: destination buffer.
136 * @length: maximum number of bytes to copy.
138 * Copies at least a single WQE, but may copy more data.
140 * Return: the number of bytes copied, or an error code.
142 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
143 void *buffer, u32 length,
144 struct mlx5_ib_qp_base *base)
146 struct ib_device *ibdev = qp->ibqp.device;
147 struct mlx5_ib_dev *dev = to_mdev(ibdev);
148 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
151 struct ib_umem *umem = base->ubuffer.umem;
152 u32 first_copy_length;
156 if (wq->wqe_cnt == 0) {
157 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
162 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
163 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
165 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
168 if (offset > umem->length ||
169 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
172 first_copy_length = min_t(u32, offset + length, wq_end) - offset;
173 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
178 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
179 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
181 wqe_length = ds * MLX5_WQE_DS_UNITS;
183 wqe_length = 1 << wq->wqe_shift;
186 if (wqe_length <= first_copy_length)
187 return first_copy_length;
189 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
190 wqe_length - first_copy_length);
197 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
199 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
200 struct ib_event event;
202 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
203 /* This event is only valid for trans_qps */
204 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
207 if (ibqp->event_handler) {
208 event.device = ibqp->device;
209 event.element.qp = ibqp;
211 case MLX5_EVENT_TYPE_PATH_MIG:
212 event.event = IB_EVENT_PATH_MIG;
214 case MLX5_EVENT_TYPE_COMM_EST:
215 event.event = IB_EVENT_COMM_EST;
217 case MLX5_EVENT_TYPE_SQ_DRAINED:
218 event.event = IB_EVENT_SQ_DRAINED;
220 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
221 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
223 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
224 event.event = IB_EVENT_QP_FATAL;
226 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
227 event.event = IB_EVENT_PATH_MIG_ERR;
229 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
230 event.event = IB_EVENT_QP_REQ_ERR;
232 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
233 event.event = IB_EVENT_QP_ACCESS_ERR;
236 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
240 ibqp->event_handler(&event, ibqp->qp_context);
244 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
245 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
250 /* Sanity check RQ size before proceeding */
251 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
257 qp->rq.wqe_shift = 0;
258 cap->max_recv_wr = 0;
259 cap->max_recv_sge = 0;
262 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
263 if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift))
265 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
266 if ((1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) < qp->wq_sig)
268 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
269 qp->rq.max_post = qp->rq.wqe_cnt;
271 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
272 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
273 wqe_size = roundup_pow_of_two(wqe_size);
274 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
275 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
276 qp->rq.wqe_cnt = wq_size / wqe_size;
277 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
278 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
280 MLX5_CAP_GEN(dev->mdev,
284 qp->rq.wqe_shift = ilog2(wqe_size);
285 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
286 qp->rq.max_post = qp->rq.wqe_cnt;
293 static int sq_overhead(struct ib_qp_init_attr *attr)
297 switch (attr->qp_type) {
299 size += sizeof(struct mlx5_wqe_xrc_seg);
302 size += sizeof(struct mlx5_wqe_ctrl_seg) +
303 max(sizeof(struct mlx5_wqe_atomic_seg) +
304 sizeof(struct mlx5_wqe_raddr_seg),
305 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
306 sizeof(struct mlx5_mkey_seg) +
307 MLX5_IB_SQ_UMR_INLINE_THRESHOLD /
308 MLX5_IB_UMR_OCTOWORD);
315 size += sizeof(struct mlx5_wqe_ctrl_seg) +
316 max(sizeof(struct mlx5_wqe_raddr_seg),
317 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
318 sizeof(struct mlx5_mkey_seg));
322 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
323 size += sizeof(struct mlx5_wqe_eth_pad) +
324 sizeof(struct mlx5_wqe_eth_seg);
327 case MLX5_IB_QPT_HW_GSI:
328 size += sizeof(struct mlx5_wqe_ctrl_seg) +
329 sizeof(struct mlx5_wqe_datagram_seg);
332 case MLX5_IB_QPT_REG_UMR:
333 size += sizeof(struct mlx5_wqe_ctrl_seg) +
334 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
335 sizeof(struct mlx5_mkey_seg);
345 static int calc_send_wqe(struct ib_qp_init_attr *attr)
350 size = sq_overhead(attr);
354 if (attr->cap.max_inline_data) {
355 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
356 attr->cap.max_inline_data;
359 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
360 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
361 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
362 return MLX5_SIG_WQE_SIZE;
364 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
367 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
371 if (attr->qp_type == IB_QPT_RC)
372 max_sge = (min_t(int, wqe_size, 512) -
373 sizeof(struct mlx5_wqe_ctrl_seg) -
374 sizeof(struct mlx5_wqe_raddr_seg)) /
375 sizeof(struct mlx5_wqe_data_seg);
376 else if (attr->qp_type == IB_QPT_XRC_INI)
377 max_sge = (min_t(int, wqe_size, 512) -
378 sizeof(struct mlx5_wqe_ctrl_seg) -
379 sizeof(struct mlx5_wqe_xrc_seg) -
380 sizeof(struct mlx5_wqe_raddr_seg)) /
381 sizeof(struct mlx5_wqe_data_seg);
383 max_sge = (wqe_size - sq_overhead(attr)) /
384 sizeof(struct mlx5_wqe_data_seg);
386 return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
387 sizeof(struct mlx5_wqe_data_seg));
390 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
391 struct mlx5_ib_qp *qp)
396 if (!attr->cap.max_send_wr)
399 wqe_size = calc_send_wqe(attr);
400 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
404 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
405 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
406 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
410 qp->max_inline_data = wqe_size - sq_overhead(attr) -
411 sizeof(struct mlx5_wqe_inline_seg);
412 attr->cap.max_inline_data = qp->max_inline_data;
414 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
415 qp->signature_en = true;
417 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
418 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
419 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
420 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
421 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
423 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
426 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
427 qp->sq.max_gs = get_send_sge(attr, wqe_size);
428 if (qp->sq.max_gs < attr->cap.max_send_sge)
431 attr->cap.max_send_sge = qp->sq.max_gs;
432 qp->sq.max_post = wq_size / wqe_size;
433 attr->cap.max_send_wr = qp->sq.max_post;
438 static int set_user_buf_size(struct mlx5_ib_dev *dev,
439 struct mlx5_ib_qp *qp,
440 struct mlx5_ib_create_qp *ucmd,
441 struct mlx5_ib_qp_base *base,
442 struct ib_qp_init_attr *attr)
444 int desc_sz = 1 << qp->sq.wqe_shift;
446 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
447 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
448 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
452 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
453 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
454 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
458 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
460 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
461 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
463 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
467 if (attr->qp_type == IB_QPT_RAW_PACKET ||
468 qp->flags & MLX5_IB_QP_UNDERLAY) {
469 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
470 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
472 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
473 (qp->sq.wqe_cnt << 6);
479 static int qp_has_rq(struct ib_qp_init_attr *attr)
481 if (attr->qp_type == IB_QPT_XRC_INI ||
482 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
483 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
484 !attr->cap.max_recv_wr)
491 /* this is the first blue flame register in the array of bfregs assigned
492 * to a processes. Since we do not use it for blue flame but rather
493 * regular 64 bit doorbells, we do not need a lock for maintaiing
496 NUM_NON_BLUE_FLAME_BFREGS = 1,
499 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
501 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
504 static int num_med_bfreg(struct mlx5_ib_dev *dev,
505 struct mlx5_bfreg_info *bfregi)
509 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
510 NUM_NON_BLUE_FLAME_BFREGS;
512 return n >= 0 ? n : 0;
515 static int first_med_bfreg(struct mlx5_ib_dev *dev,
516 struct mlx5_bfreg_info *bfregi)
518 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM;
521 static int first_hi_bfreg(struct mlx5_ib_dev *dev,
522 struct mlx5_bfreg_info *bfregi)
526 med = num_med_bfreg(dev, bfregi);
530 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
531 struct mlx5_bfreg_info *bfregi)
535 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
536 if (!bfregi->count[i]) {
545 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
546 struct mlx5_bfreg_info *bfregi)
548 int minidx = first_med_bfreg(dev, bfregi);
554 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) {
555 if (bfregi->count[i] < bfregi->count[minidx])
557 if (!bfregi->count[minidx])
561 bfregi->count[minidx]++;
565 static int alloc_bfreg(struct mlx5_ib_dev *dev,
566 struct mlx5_bfreg_info *bfregi)
568 int bfregn = -ENOMEM;
570 mutex_lock(&bfregi->lock);
571 if (bfregi->ver >= 2) {
572 bfregn = alloc_high_class_bfreg(dev, bfregi);
574 bfregn = alloc_med_class_bfreg(dev, bfregi);
578 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
580 bfregi->count[bfregn]++;
582 mutex_unlock(&bfregi->lock);
587 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
589 mutex_lock(&bfregi->lock);
590 bfregi->count[bfregn]--;
591 mutex_unlock(&bfregi->lock);
594 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
597 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
598 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
599 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
600 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
601 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
602 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
603 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
608 static int to_mlx5_st(enum ib_qp_type type)
611 case IB_QPT_RC: return MLX5_QP_ST_RC;
612 case IB_QPT_UC: return MLX5_QP_ST_UC;
613 case IB_QPT_UD: return MLX5_QP_ST_UD;
614 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
616 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
617 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
618 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
619 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI;
620 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
621 case IB_QPT_RAW_PACKET:
622 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
624 default: return -EINVAL;
628 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
629 struct mlx5_ib_cq *recv_cq);
630 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
631 struct mlx5_ib_cq *recv_cq);
633 int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
634 struct mlx5_bfreg_info *bfregi, u32 bfregn,
637 unsigned int bfregs_per_sys_page;
638 u32 index_of_sys_page;
641 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
642 MLX5_NON_FP_BFREGS_PER_UAR;
643 index_of_sys_page = bfregn / bfregs_per_sys_page;
646 index_of_sys_page += bfregi->num_static_sys_pages;
648 if (index_of_sys_page >= bfregi->num_sys_pages)
651 if (bfregn > bfregi->num_dyn_bfregs ||
652 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
653 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
658 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
659 return bfregi->sys_pages[index_of_sys_page] + offset;
662 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
664 unsigned long addr, size_t size,
665 struct ib_umem **umem,
666 int *npages, int *page_shift, int *ncont,
671 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
673 mlx5_ib_dbg(dev, "umem_get failed\n");
674 return PTR_ERR(*umem);
677 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
679 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
681 mlx5_ib_warn(dev, "bad offset\n");
685 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
686 addr, size, *npages, *page_shift, *ncont, *offset);
691 ib_umem_release(*umem);
697 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
698 struct mlx5_ib_rwq *rwq)
700 struct mlx5_ib_ucontext *context;
702 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
703 atomic_dec(&dev->delay_drop.rqs_cnt);
705 context = to_mucontext(pd->uobject->context);
706 mlx5_ib_db_unmap_user(context, &rwq->db);
708 ib_umem_release(rwq->umem);
711 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
712 struct mlx5_ib_rwq *rwq,
713 struct mlx5_ib_create_wq *ucmd)
715 struct mlx5_ib_ucontext *context;
725 context = to_mucontext(pd->uobject->context);
726 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
727 rwq->buf_size, 0, 0);
728 if (IS_ERR(rwq->umem)) {
729 mlx5_ib_dbg(dev, "umem_get failed\n");
730 err = PTR_ERR(rwq->umem);
734 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
736 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
737 &rwq->rq_page_offset);
739 mlx5_ib_warn(dev, "bad offset\n");
743 rwq->rq_num_pas = ncont;
744 rwq->page_shift = page_shift;
745 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
746 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
748 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
749 (unsigned long long)ucmd->buf_addr, rwq->buf_size,
750 npages, page_shift, ncont, offset);
752 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
754 mlx5_ib_dbg(dev, "map failed\n");
758 rwq->create_type = MLX5_WQ_USER;
762 ib_umem_release(rwq->umem);
766 static int adjust_bfregn(struct mlx5_ib_dev *dev,
767 struct mlx5_bfreg_info *bfregi, int bfregn)
769 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
770 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
773 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
774 struct mlx5_ib_qp *qp, struct ib_udata *udata,
775 struct ib_qp_init_attr *attr,
777 struct mlx5_ib_create_qp_resp *resp, int *inlen,
778 struct mlx5_ib_qp_base *base)
780 struct mlx5_ib_ucontext *context;
781 struct mlx5_ib_create_qp ucmd;
782 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
793 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
795 mlx5_ib_dbg(dev, "copy failed\n");
799 context = to_mucontext(pd->uobject->context);
800 if (ucmd.flags & MLX5_QP_FLAG_BFREG_INDEX) {
801 uar_index = bfregn_to_uar_index(dev, &context->bfregi,
802 ucmd.bfreg_index, true);
806 bfregn = MLX5_IB_INVALID_BFREG;
807 } else if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) {
809 * TBD: should come from the verbs when we have the API
811 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
812 bfregn = MLX5_CROSS_CHANNEL_BFREG;
815 bfregn = alloc_bfreg(dev, &context->bfregi);
820 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
821 if (bfregn != MLX5_IB_INVALID_BFREG)
822 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
826 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
827 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
829 err = set_user_buf_size(dev, qp, &ucmd, base, attr);
833 if (ucmd.buf_addr && ubuffer->buf_size) {
834 ubuffer->buf_addr = ucmd.buf_addr;
835 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
837 &ubuffer->umem, &npages, &page_shift,
842 ubuffer->umem = NULL;
845 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
846 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
847 *in = kvzalloc(*inlen, GFP_KERNEL);
853 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
855 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
857 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
859 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
860 MLX5_SET(qpc, qpc, page_offset, offset);
862 MLX5_SET(qpc, qpc, uar_page, uar_index);
863 if (bfregn != MLX5_IB_INVALID_BFREG)
864 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
866 resp->bfreg_index = MLX5_IB_INVALID_BFREG;
869 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
871 mlx5_ib_dbg(dev, "map failed\n");
875 err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
877 mlx5_ib_dbg(dev, "copy failed\n");
880 qp->create_type = MLX5_QP_USER;
885 mlx5_ib_db_unmap_user(context, &qp->db);
892 ib_umem_release(ubuffer->umem);
895 if (bfregn != MLX5_IB_INVALID_BFREG)
896 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
900 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
901 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base)
903 struct mlx5_ib_ucontext *context;
905 context = to_mucontext(pd->uobject->context);
906 mlx5_ib_db_unmap_user(context, &qp->db);
907 if (base->ubuffer.umem)
908 ib_umem_release(base->ubuffer.umem);
911 * Free only the BFREGs which are handled by the kernel.
912 * BFREGs of UARs allocated dynamically are handled by user.
914 if (qp->bfregn != MLX5_IB_INVALID_BFREG)
915 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
918 static int create_kernel_qp(struct mlx5_ib_dev *dev,
919 struct ib_qp_init_attr *init_attr,
920 struct mlx5_ib_qp *qp,
921 u32 **in, int *inlen,
922 struct mlx5_ib_qp_base *base)
928 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
929 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
930 IB_QP_CREATE_IPOIB_UD_LSO |
931 IB_QP_CREATE_NETIF_QP |
932 mlx5_ib_create_qp_sqpn_qp1()))
935 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
936 qp->bf.bfreg = &dev->fp_bfreg;
938 qp->bf.bfreg = &dev->bfreg;
940 /* We need to divide by two since each register is comprised of
941 * two buffers of identical size, namely odd and even
943 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
944 uar_index = qp->bf.bfreg->index;
946 err = calc_sq_size(dev, init_attr, qp);
948 mlx5_ib_dbg(dev, "err %d\n", err);
953 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
954 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
956 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
958 mlx5_ib_dbg(dev, "err %d\n", err);
962 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
963 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
964 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
965 *in = kvzalloc(*inlen, GFP_KERNEL);
971 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
972 MLX5_SET(qpc, qpc, uar_page, uar_index);
973 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
975 /* Set "fast registration enabled" for all kernel QPs */
976 MLX5_SET(qpc, qpc, fre, 1);
977 MLX5_SET(qpc, qpc, rlky, 1);
979 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
980 MLX5_SET(qpc, qpc, deth_sqpn, 1);
981 qp->flags |= MLX5_IB_QP_SQPN_QP1;
984 mlx5_fill_page_array(&qp->buf,
985 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
987 err = mlx5_db_alloc(dev->mdev, &qp->db);
989 mlx5_ib_dbg(dev, "err %d\n", err);
993 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
994 sizeof(*qp->sq.wrid), GFP_KERNEL);
995 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
996 sizeof(*qp->sq.wr_data), GFP_KERNEL);
997 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
998 sizeof(*qp->rq.wrid), GFP_KERNEL);
999 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
1000 sizeof(*qp->sq.w_list), GFP_KERNEL);
1001 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
1002 sizeof(*qp->sq.wqe_head), GFP_KERNEL);
1004 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
1005 !qp->sq.w_list || !qp->sq.wqe_head) {
1009 qp->create_type = MLX5_QP_KERNEL;
1014 kvfree(qp->sq.wqe_head);
1015 kvfree(qp->sq.w_list);
1016 kvfree(qp->sq.wrid);
1017 kvfree(qp->sq.wr_data);
1018 kvfree(qp->rq.wrid);
1019 mlx5_db_free(dev->mdev, &qp->db);
1025 mlx5_buf_free(dev->mdev, &qp->buf);
1029 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1031 kvfree(qp->sq.wqe_head);
1032 kvfree(qp->sq.w_list);
1033 kvfree(qp->sq.wrid);
1034 kvfree(qp->sq.wr_data);
1035 kvfree(qp->rq.wrid);
1036 mlx5_db_free(dev->mdev, &qp->db);
1037 mlx5_buf_free(dev->mdev, &qp->buf);
1040 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
1042 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1043 (attr->qp_type == MLX5_IB_QPT_DCI) ||
1044 (attr->qp_type == IB_QPT_XRC_INI))
1046 else if (!qp->has_rq)
1047 return MLX5_ZERO_LEN_RQ;
1049 return MLX5_NON_ZERO_RQ;
1052 static int is_connected(enum ib_qp_type qp_type)
1054 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1060 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1061 struct mlx5_ib_qp *qp,
1062 struct mlx5_ib_sq *sq, u32 tdn)
1064 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1065 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1067 MLX5_SET(tisc, tisc, transport_domain, tdn);
1068 if (qp->flags & MLX5_IB_QP_UNDERLAY)
1069 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1071 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1074 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1075 struct mlx5_ib_sq *sq)
1077 mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1080 static void destroy_flow_rule_vport_sq(struct mlx5_ib_dev *dev,
1081 struct mlx5_ib_sq *sq)
1084 mlx5_del_flow_rules(sq->flow_rule);
1087 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1088 struct mlx5_ib_sq *sq, void *qpin,
1091 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1095 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1104 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1105 &sq->ubuffer.umem, &npages, &page_shift,
1110 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1111 in = kvzalloc(inlen, GFP_KERNEL);
1117 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1118 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1119 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1120 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
1121 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1122 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1123 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1124 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1125 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1126 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1127 MLX5_CAP_ETH(dev->mdev, swp))
1128 MLX5_SET(sqc, sqc, allow_swp, 1);
1130 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1131 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1132 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1133 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1134 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1135 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1136 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1137 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1138 MLX5_SET(wq, wq, page_offset, offset);
1140 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1141 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1143 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1150 err = create_flow_rule_vport_sq(dev, sq);
1157 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1160 ib_umem_release(sq->ubuffer.umem);
1161 sq->ubuffer.umem = NULL;
1166 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1167 struct mlx5_ib_sq *sq)
1169 destroy_flow_rule_vport_sq(dev, sq);
1170 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1171 ib_umem_release(sq->ubuffer.umem);
1174 static size_t get_rq_pas_size(void *qpc)
1176 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1177 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1178 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1179 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1180 u32 po_quanta = 1 << (log_page_size - 6);
1181 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1182 u32 page_size = 1 << log_page_size;
1183 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1184 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1186 return rq_num_pas * sizeof(u64);
1189 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1190 struct mlx5_ib_rq *rq, void *qpin,
1193 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1199 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1200 size_t rq_pas_size = get_rq_pas_size(qpc);
1204 if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas))
1207 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1208 in = kvzalloc(inlen, GFP_KERNEL);
1212 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1213 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1214 MLX5_SET(rqc, rqc, vsd, 1);
1215 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1216 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1217 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1218 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1219 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1221 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1222 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1224 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1225 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1226 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1227 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1228 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1229 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1230 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1231 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1232 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1233 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1235 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1236 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1237 memcpy(pas, qp_pas, rq_pas_size);
1239 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1246 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1247 struct mlx5_ib_rq *rq)
1249 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1252 static bool tunnel_offload_supported(struct mlx5_core_dev *dev)
1254 return (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) ||
1255 MLX5_CAP_ETH(dev, tunnel_stateless_gre) ||
1256 MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx));
1259 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1260 struct mlx5_ib_rq *rq, u32 tdn,
1261 bool tunnel_offload_en)
1268 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1269 in = kvzalloc(inlen, GFP_KERNEL);
1273 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1274 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1275 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1276 MLX5_SET(tirc, tirc, transport_domain, tdn);
1277 if (tunnel_offload_en)
1278 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1281 MLX5_SET(tirc, tirc, self_lb_block,
1282 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_);
1284 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1291 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1292 struct mlx5_ib_rq *rq)
1294 mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1297 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1298 u32 *in, size_t inlen,
1301 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1302 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1303 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1304 struct ib_uobject *uobj = pd->uobject;
1305 struct ib_ucontext *ucontext = uobj->context;
1306 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1308 u32 tdn = mucontext->tdn;
1310 if (qp->sq.wqe_cnt) {
1311 err = create_raw_packet_qp_tis(dev, qp, sq, tdn);
1315 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1317 goto err_destroy_tis;
1319 sq->base.container_mibqp = qp;
1320 sq->base.mqp.event = mlx5_ib_qp_event;
1323 if (qp->rq.wqe_cnt) {
1324 rq->base.container_mibqp = qp;
1326 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING)
1327 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
1328 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING)
1329 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
1330 err = create_raw_packet_qp_rq(dev, rq, in, inlen);
1332 goto err_destroy_sq;
1335 err = create_raw_packet_qp_tir(dev, rq, tdn,
1336 qp->tunnel_offload_en);
1338 goto err_destroy_rq;
1341 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1347 destroy_raw_packet_qp_rq(dev, rq);
1349 if (!qp->sq.wqe_cnt)
1351 destroy_raw_packet_qp_sq(dev, sq);
1353 destroy_raw_packet_qp_tis(dev, sq);
1358 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1359 struct mlx5_ib_qp *qp)
1361 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1362 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1363 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1365 if (qp->rq.wqe_cnt) {
1366 destroy_raw_packet_qp_tir(dev, rq);
1367 destroy_raw_packet_qp_rq(dev, rq);
1370 if (qp->sq.wqe_cnt) {
1371 destroy_raw_packet_qp_sq(dev, sq);
1372 destroy_raw_packet_qp_tis(dev, sq);
1376 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1377 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1379 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1380 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1384 sq->doorbell = &qp->db;
1385 rq->doorbell = &qp->db;
1388 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1390 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1393 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1395 struct ib_qp_init_attr *init_attr,
1396 struct ib_udata *udata)
1398 struct ib_uobject *uobj = pd->uobject;
1399 struct ib_ucontext *ucontext = uobj->context;
1400 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1401 struct mlx5_ib_create_qp_resp resp = {};
1407 u32 selected_fields = 0;
1409 size_t min_resp_len;
1410 u32 tdn = mucontext->tdn;
1411 struct mlx5_ib_create_qp_rss ucmd = {};
1412 size_t required_cmd_sz;
1414 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1417 if (init_attr->create_flags || init_attr->send_cq)
1420 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
1421 if (udata->outlen < min_resp_len)
1424 required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags);
1425 if (udata->inlen < required_cmd_sz) {
1426 mlx5_ib_dbg(dev, "invalid inlen\n");
1430 if (udata->inlen > sizeof(ucmd) &&
1431 !ib_is_udata_cleared(udata, sizeof(ucmd),
1432 udata->inlen - sizeof(ucmd))) {
1433 mlx5_ib_dbg(dev, "inlen is not supported\n");
1437 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1438 mlx5_ib_dbg(dev, "copy failed\n");
1442 if (ucmd.comp_mask) {
1443 mlx5_ib_dbg(dev, "invalid comp mask\n");
1447 if (ucmd.flags & ~MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1448 mlx5_ib_dbg(dev, "invalid flags\n");
1452 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS &&
1453 !tunnel_offload_supported(dev->mdev)) {
1454 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n");
1458 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1459 !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
1460 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1464 err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
1466 mlx5_ib_dbg(dev, "copy failed\n");
1470 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1471 in = kvzalloc(inlen, GFP_KERNEL);
1475 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1476 MLX5_SET(tirc, tirc, disp_type,
1477 MLX5_TIRC_DISP_TYPE_INDIRECT);
1478 MLX5_SET(tirc, tirc, indirect_table,
1479 init_attr->rwq_ind_tbl->ind_tbl_num);
1480 MLX5_SET(tirc, tirc, transport_domain, tdn);
1482 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1484 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1485 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1487 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER)
1488 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1490 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1492 switch (ucmd.rx_hash_function) {
1493 case MLX5_RX_HASH_FUNC_TOEPLITZ:
1495 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1496 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1498 if (len != ucmd.rx_key_len) {
1503 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1504 memcpy(rss_key, ucmd.rx_hash_key, len);
1512 if (!ucmd.rx_hash_fields_mask) {
1513 /* special case when this TIR serves as steering entry without hashing */
1514 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1520 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1521 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1522 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1523 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1528 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1529 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1530 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1531 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1532 MLX5_L3_PROT_TYPE_IPV4);
1533 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1534 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1535 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1536 MLX5_L3_PROT_TYPE_IPV6);
1538 outer_l4 = ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1539 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) << 0 |
1540 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1541 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) << 1 |
1542 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2;
1544 /* Check that only one l4 protocol is set */
1545 if (outer_l4 & (outer_l4 - 1)) {
1550 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1551 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1552 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1553 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1554 MLX5_L4_PROT_TYPE_TCP);
1555 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1556 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1557 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1558 MLX5_L4_PROT_TYPE_UDP);
1560 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1561 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1562 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1564 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1565 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1566 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1568 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1569 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1570 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1572 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1573 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1574 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1576 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI)
1577 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI;
1579 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1583 MLX5_SET(tirc, tirc, self_lb_block,
1584 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_);
1586 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1592 /* qpn is reserved for that QP */
1593 qp->trans_qp.base.mqp.qpn = 0;
1594 qp->flags |= MLX5_IB_QP_RSS;
1602 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1603 struct ib_qp_init_attr *init_attr,
1604 struct ib_udata *udata, struct mlx5_ib_qp *qp)
1606 struct mlx5_ib_resources *devr = &dev->devr;
1607 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1608 struct mlx5_core_dev *mdev = dev->mdev;
1609 struct mlx5_ib_create_qp_resp resp = {};
1610 struct mlx5_ib_cq *send_cq;
1611 struct mlx5_ib_cq *recv_cq;
1612 unsigned long flags;
1613 u32 uidx = MLX5_IB_DEFAULT_UIDX;
1614 struct mlx5_ib_create_qp ucmd;
1615 struct mlx5_ib_qp_base *base;
1621 mutex_init(&qp->mutex);
1622 spin_lock_init(&qp->sq.lock);
1623 spin_lock_init(&qp->rq.lock);
1625 mlx5_st = to_mlx5_st(init_attr->qp_type);
1629 if (init_attr->rwq_ind_tbl) {
1633 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1637 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1638 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1639 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1642 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1646 if (init_attr->create_flags &
1647 (IB_QP_CREATE_CROSS_CHANNEL |
1648 IB_QP_CREATE_MANAGED_SEND |
1649 IB_QP_CREATE_MANAGED_RECV)) {
1650 if (!MLX5_CAP_GEN(mdev, cd)) {
1651 mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1654 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1655 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1656 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1657 qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1658 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1659 qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1662 if (init_attr->qp_type == IB_QPT_UD &&
1663 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1664 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1665 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1669 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1670 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1671 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1674 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1675 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1676 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1679 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1682 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1683 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1685 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) {
1686 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1687 MLX5_CAP_ETH(dev->mdev, vlan_cap)) ||
1688 (init_attr->qp_type != IB_QPT_RAW_PACKET))
1690 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING;
1693 if (pd && pd->uobject) {
1694 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1695 mlx5_ib_dbg(dev, "copy failed\n");
1699 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1700 &ucmd, udata->inlen, &uidx);
1704 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1705 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1706 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1707 if (init_attr->qp_type != IB_QPT_RAW_PACKET ||
1708 !tunnel_offload_supported(mdev)) {
1709 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n");
1712 qp->tunnel_offload_en = true;
1715 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) {
1716 if (init_attr->qp_type != IB_QPT_UD ||
1717 (MLX5_CAP_GEN(dev->mdev, port_type) !=
1718 MLX5_CAP_PORT_TYPE_IB) ||
1719 !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) {
1720 mlx5_ib_dbg(dev, "Source QP option isn't supported\n");
1724 qp->flags |= MLX5_IB_QP_UNDERLAY;
1725 qp->underlay_qpn = init_attr->source_qpn;
1728 qp->wq_sig = !!wq_signature;
1731 base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1732 qp->flags & MLX5_IB_QP_UNDERLAY) ?
1733 &qp->raw_packet_qp.rq.base :
1736 qp->has_rq = qp_has_rq(init_attr);
1737 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1738 qp, (pd && pd->uobject) ? &ucmd : NULL);
1740 mlx5_ib_dbg(dev, "err %d\n", err);
1747 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1748 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1749 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1750 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1751 mlx5_ib_dbg(dev, "invalid rq params\n");
1754 if (ucmd.sq_wqe_count > max_wqes) {
1755 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
1756 ucmd.sq_wqe_count, max_wqes);
1759 if (init_attr->create_flags &
1760 mlx5_ib_create_qp_sqpn_qp1()) {
1761 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1764 err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1765 &resp, &inlen, base);
1767 mlx5_ib_dbg(dev, "err %d\n", err);
1769 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1772 mlx5_ib_dbg(dev, "err %d\n", err);
1778 in = kvzalloc(inlen, GFP_KERNEL);
1782 qp->create_type = MLX5_QP_EMPTY;
1785 if (is_sqp(init_attr->qp_type))
1786 qp->port = init_attr->port_num;
1788 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1790 MLX5_SET(qpc, qpc, st, mlx5_st);
1791 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1793 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
1794 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
1796 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1800 MLX5_SET(qpc, qpc, wq_signature, 1);
1802 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1803 MLX5_SET(qpc, qpc, block_lb_mc, 1);
1805 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
1806 MLX5_SET(qpc, qpc, cd_master, 1);
1807 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
1808 MLX5_SET(qpc, qpc, cd_slave_send, 1);
1809 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
1810 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
1812 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1816 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1817 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1820 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1822 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
1824 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1826 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1828 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1832 if (qp->rq.wqe_cnt) {
1833 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1834 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
1837 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
1839 if (qp->sq.wqe_cnt) {
1840 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
1842 MLX5_SET(qpc, qpc, no_sq, 1);
1843 if (init_attr->srq &&
1844 init_attr->srq->srq_type == IB_SRQT_TM)
1845 MLX5_SET(qpc, qpc, offload_type,
1846 MLX5_QPC_OFFLOAD_TYPE_RNDV);
1849 /* Set default resources */
1850 switch (init_attr->qp_type) {
1851 case IB_QPT_XRC_TGT:
1852 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1853 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1854 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1855 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
1857 case IB_QPT_XRC_INI:
1858 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1859 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1860 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1863 if (init_attr->srq) {
1864 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1865 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
1867 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1868 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
1872 if (init_attr->send_cq)
1873 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
1875 if (init_attr->recv_cq)
1876 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
1878 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
1880 /* 0xffffff means we ask to work with cqe version 0 */
1881 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
1882 MLX5_SET(qpc, qpc, user_index, uidx);
1884 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1885 if (init_attr->qp_type == IB_QPT_UD &&
1886 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
1887 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1888 qp->flags |= MLX5_IB_QP_LSO;
1891 if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) {
1892 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
1893 mlx5_ib_dbg(dev, "scatter end padding is not supported\n");
1896 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1897 MLX5_SET(qpc, qpc, end_padding_mode,
1898 MLX5_WQ_END_PAD_MODE_ALIGN);
1900 qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING;
1909 if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1910 qp->flags & MLX5_IB_QP_UNDERLAY) {
1911 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1912 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1913 err = create_raw_packet_qp(dev, qp, in, inlen, pd);
1915 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1919 mlx5_ib_dbg(dev, "create qp failed\n");
1925 base->container_mibqp = qp;
1926 base->mqp.event = mlx5_ib_qp_event;
1928 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1929 &send_cq, &recv_cq);
1930 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1931 mlx5_ib_lock_cqs(send_cq, recv_cq);
1932 /* Maintain device to QPs access, needed for further handling via reset
1935 list_add_tail(&qp->qps_list, &dev->qp_list);
1936 /* Maintain CQ to QPs access, needed for further handling via reset flow
1939 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1941 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1942 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1943 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1948 if (qp->create_type == MLX5_QP_USER)
1949 destroy_qp_user(dev, pd, qp, base);
1950 else if (qp->create_type == MLX5_QP_KERNEL)
1951 destroy_qp_kernel(dev, qp);
1958 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1959 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1963 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1964 spin_lock(&send_cq->lock);
1965 spin_lock_nested(&recv_cq->lock,
1966 SINGLE_DEPTH_NESTING);
1967 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1968 spin_lock(&send_cq->lock);
1969 __acquire(&recv_cq->lock);
1971 spin_lock(&recv_cq->lock);
1972 spin_lock_nested(&send_cq->lock,
1973 SINGLE_DEPTH_NESTING);
1976 spin_lock(&send_cq->lock);
1977 __acquire(&recv_cq->lock);
1979 } else if (recv_cq) {
1980 spin_lock(&recv_cq->lock);
1981 __acquire(&send_cq->lock);
1983 __acquire(&send_cq->lock);
1984 __acquire(&recv_cq->lock);
1988 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1989 __releases(&send_cq->lock) __releases(&recv_cq->lock)
1993 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1994 spin_unlock(&recv_cq->lock);
1995 spin_unlock(&send_cq->lock);
1996 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1997 __release(&recv_cq->lock);
1998 spin_unlock(&send_cq->lock);
2000 spin_unlock(&send_cq->lock);
2001 spin_unlock(&recv_cq->lock);
2004 __release(&recv_cq->lock);
2005 spin_unlock(&send_cq->lock);
2007 } else if (recv_cq) {
2008 __release(&send_cq->lock);
2009 spin_unlock(&recv_cq->lock);
2011 __release(&recv_cq->lock);
2012 __release(&send_cq->lock);
2016 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
2018 return to_mpd(qp->ibqp.pd);
2021 static void get_cqs(enum ib_qp_type qp_type,
2022 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
2023 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
2026 case IB_QPT_XRC_TGT:
2030 case MLX5_IB_QPT_REG_UMR:
2031 case IB_QPT_XRC_INI:
2032 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2037 case MLX5_IB_QPT_HW_GSI:
2041 case IB_QPT_RAW_IPV6:
2042 case IB_QPT_RAW_ETHERTYPE:
2043 case IB_QPT_RAW_PACKET:
2044 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2045 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
2056 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2057 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2058 u8 lag_tx_affinity);
2060 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
2062 struct mlx5_ib_cq *send_cq, *recv_cq;
2063 struct mlx5_ib_qp_base *base;
2064 unsigned long flags;
2067 if (qp->ibqp.rwq_ind_tbl) {
2068 destroy_rss_raw_qp_tir(dev, qp);
2072 base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2073 qp->flags & MLX5_IB_QP_UNDERLAY) ?
2074 &qp->raw_packet_qp.rq.base :
2077 if (qp->state != IB_QPS_RESET) {
2078 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET &&
2079 !(qp->flags & MLX5_IB_QP_UNDERLAY)) {
2080 err = mlx5_core_qp_modify(dev->mdev,
2081 MLX5_CMD_OP_2RST_QP, 0,
2084 struct mlx5_modify_raw_qp_param raw_qp_param = {
2085 .operation = MLX5_CMD_OP_2RST_QP
2088 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
2091 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
2095 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2096 &send_cq, &recv_cq);
2098 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2099 mlx5_ib_lock_cqs(send_cq, recv_cq);
2100 /* del from lists under both locks above to protect reset flow paths */
2101 list_del(&qp->qps_list);
2103 list_del(&qp->cq_send_list);
2106 list_del(&qp->cq_recv_list);
2108 if (qp->create_type == MLX5_QP_KERNEL) {
2109 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2110 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2111 if (send_cq != recv_cq)
2112 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2115 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2116 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2118 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2119 qp->flags & MLX5_IB_QP_UNDERLAY) {
2120 destroy_raw_packet_qp(dev, qp);
2122 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
2124 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2128 if (qp->create_type == MLX5_QP_KERNEL)
2129 destroy_qp_kernel(dev, qp);
2130 else if (qp->create_type == MLX5_QP_USER)
2131 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base);
2134 static const char *ib_qp_type_str(enum ib_qp_type type)
2138 return "IB_QPT_SMI";
2140 return "IB_QPT_GSI";
2147 case IB_QPT_RAW_IPV6:
2148 return "IB_QPT_RAW_IPV6";
2149 case IB_QPT_RAW_ETHERTYPE:
2150 return "IB_QPT_RAW_ETHERTYPE";
2151 case IB_QPT_XRC_INI:
2152 return "IB_QPT_XRC_INI";
2153 case IB_QPT_XRC_TGT:
2154 return "IB_QPT_XRC_TGT";
2155 case IB_QPT_RAW_PACKET:
2156 return "IB_QPT_RAW_PACKET";
2157 case MLX5_IB_QPT_REG_UMR:
2158 return "MLX5_IB_QPT_REG_UMR";
2160 return "IB_QPT_DRIVER";
2163 return "Invalid QP type";
2167 static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd,
2168 struct ib_qp_init_attr *attr,
2169 struct mlx5_ib_create_qp *ucmd)
2171 struct mlx5_ib_qp *qp;
2173 u32 uidx = MLX5_IB_DEFAULT_UIDX;
2176 if (!attr->srq || !attr->recv_cq)
2177 return ERR_PTR(-EINVAL);
2179 err = get_qp_user_index(to_mucontext(pd->uobject->context),
2180 ucmd, sizeof(*ucmd), &uidx);
2182 return ERR_PTR(err);
2184 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2186 return ERR_PTR(-ENOMEM);
2188 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL);
2194 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
2195 qp->qp_sub_type = MLX5_IB_QPT_DCT;
2196 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn);
2197 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn);
2198 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn);
2199 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key);
2200 MLX5_SET(dctc, dctc, user_index, uidx);
2202 qp->state = IB_QPS_RESET;
2207 return ERR_PTR(err);
2210 static int set_mlx_qp_type(struct mlx5_ib_dev *dev,
2211 struct ib_qp_init_attr *init_attr,
2212 struct mlx5_ib_create_qp *ucmd,
2213 struct ib_udata *udata)
2215 enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI };
2221 if (udata->inlen < sizeof(*ucmd)) {
2222 mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n");
2225 err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd));
2229 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) {
2230 init_attr->qp_type = MLX5_IB_QPT_DCI;
2232 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) {
2233 init_attr->qp_type = MLX5_IB_QPT_DCT;
2235 mlx5_ib_dbg(dev, "Invalid QP flags\n");
2240 if (!MLX5_CAP_GEN(dev->mdev, dct)) {
2241 mlx5_ib_dbg(dev, "DC transport is not supported\n");
2248 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
2249 struct ib_qp_init_attr *verbs_init_attr,
2250 struct ib_udata *udata)
2252 struct mlx5_ib_dev *dev;
2253 struct mlx5_ib_qp *qp;
2256 struct ib_qp_init_attr mlx_init_attr;
2257 struct ib_qp_init_attr *init_attr = verbs_init_attr;
2260 dev = to_mdev(pd->device);
2262 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2264 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2265 return ERR_PTR(-EINVAL);
2266 } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2267 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2268 return ERR_PTR(-EINVAL);
2272 /* being cautious here */
2273 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2274 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2275 pr_warn("%s: no PD for transport %s\n", __func__,
2276 ib_qp_type_str(init_attr->qp_type));
2277 return ERR_PTR(-EINVAL);
2279 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2282 if (init_attr->qp_type == IB_QPT_DRIVER) {
2283 struct mlx5_ib_create_qp ucmd;
2285 init_attr = &mlx_init_attr;
2286 memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr));
2287 err = set_mlx_qp_type(dev, init_attr, &ucmd, udata);
2289 return ERR_PTR(err);
2291 if (init_attr->qp_type == MLX5_IB_QPT_DCI) {
2292 if (init_attr->cap.max_recv_wr ||
2293 init_attr->cap.max_recv_sge) {
2294 mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n");
2295 return ERR_PTR(-EINVAL);
2298 return mlx5_ib_create_dct(pd, init_attr, &ucmd);
2302 switch (init_attr->qp_type) {
2303 case IB_QPT_XRC_TGT:
2304 case IB_QPT_XRC_INI:
2305 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
2306 mlx5_ib_dbg(dev, "XRC not supported\n");
2307 return ERR_PTR(-ENOSYS);
2309 init_attr->recv_cq = NULL;
2310 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2311 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2312 init_attr->send_cq = NULL;
2316 case IB_QPT_RAW_PACKET:
2321 case MLX5_IB_QPT_HW_GSI:
2322 case MLX5_IB_QPT_REG_UMR:
2323 case MLX5_IB_QPT_DCI:
2324 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2326 return ERR_PTR(-ENOMEM);
2328 err = create_qp_common(dev, pd, init_attr, udata, qp);
2330 mlx5_ib_dbg(dev, "create_qp_common failed\n");
2332 return ERR_PTR(err);
2335 if (is_qp0(init_attr->qp_type))
2336 qp->ibqp.qp_num = 0;
2337 else if (is_qp1(init_attr->qp_type))
2338 qp->ibqp.qp_num = 1;
2340 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2342 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
2343 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2344 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2345 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
2347 qp->trans_qp.xrcdn = xrcdn;
2352 return mlx5_ib_gsi_create_qp(pd, init_attr);
2354 case IB_QPT_RAW_IPV6:
2355 case IB_QPT_RAW_ETHERTYPE:
2358 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2359 init_attr->qp_type);
2360 /* Don't support raw QPs */
2361 return ERR_PTR(-EINVAL);
2364 if (verbs_init_attr->qp_type == IB_QPT_DRIVER)
2365 qp->qp_sub_type = init_attr->qp_type;
2370 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp)
2372 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device);
2374 if (mqp->state == IB_QPS_RTR) {
2377 err = mlx5_core_destroy_dct(dev->mdev, &mqp->dct.mdct);
2379 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err);
2389 int mlx5_ib_destroy_qp(struct ib_qp *qp)
2391 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2392 struct mlx5_ib_qp *mqp = to_mqp(qp);
2394 if (unlikely(qp->qp_type == IB_QPT_GSI))
2395 return mlx5_ib_gsi_destroy_qp(qp);
2397 if (mqp->qp_sub_type == MLX5_IB_QPT_DCT)
2398 return mlx5_ib_destroy_dct(mqp);
2400 destroy_qp_common(dev, mqp);
2407 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2410 u32 hw_access_flags = 0;
2414 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2415 dest_rd_atomic = attr->max_dest_rd_atomic;
2417 dest_rd_atomic = qp->trans_qp.resp_depth;
2419 if (attr_mask & IB_QP_ACCESS_FLAGS)
2420 access_flags = attr->qp_access_flags;
2422 access_flags = qp->trans_qp.atomic_rd_en;
2424 if (!dest_rd_atomic)
2425 access_flags &= IB_ACCESS_REMOTE_WRITE;
2427 if (access_flags & IB_ACCESS_REMOTE_READ)
2428 hw_access_flags |= MLX5_QP_BIT_RRE;
2429 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2430 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2431 if (access_flags & IB_ACCESS_REMOTE_WRITE)
2432 hw_access_flags |= MLX5_QP_BIT_RWE;
2434 return cpu_to_be32(hw_access_flags);
2438 MLX5_PATH_FLAG_FL = 1 << 0,
2439 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
2440 MLX5_PATH_FLAG_COUNTER = 1 << 2,
2443 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2445 if (rate == IB_RATE_PORT_CURRENT)
2448 if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS)
2451 while (rate != IB_RATE_PORT_CURRENT &&
2452 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2453 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2456 return rate ? rate + MLX5_STAT_RATE_OFFSET : rate;
2459 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2460 struct mlx5_ib_sq *sq, u8 sl)
2467 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2468 in = kvzalloc(inlen, GFP_KERNEL);
2472 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2474 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2475 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2477 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2484 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2485 struct mlx5_ib_sq *sq, u8 tx_affinity)
2492 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2493 in = kvzalloc(inlen, GFP_KERNEL);
2497 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2499 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2500 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2502 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2509 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2510 const struct rdma_ah_attr *ah,
2511 struct mlx5_qp_path *path, u8 port, int attr_mask,
2512 u32 path_flags, const struct ib_qp_attr *attr,
2515 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
2517 enum ib_gid_type gid_type;
2518 u8 ah_flags = rdma_ah_get_ah_flags(ah);
2519 u8 sl = rdma_ah_get_sl(ah);
2521 if (attr_mask & IB_QP_PKEY_INDEX)
2522 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2525 if (ah_flags & IB_AH_GRH) {
2526 if (grh->sgid_index >=
2527 dev->mdev->port_caps[port - 1].gid_table_len) {
2528 pr_err("sgid_index (%u) too large. max is %d\n",
2530 dev->mdev->port_caps[port - 1].gid_table_len);
2535 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
2536 if (!(ah_flags & IB_AH_GRH))
2539 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
2540 if (qp->ibqp.qp_type == IB_QPT_RC ||
2541 qp->ibqp.qp_type == IB_QPT_UC ||
2542 qp->ibqp.qp_type == IB_QPT_XRC_INI ||
2543 qp->ibqp.qp_type == IB_QPT_XRC_TGT)
2545 mlx5_get_roce_udp_sport(dev, ah->grh.sgid_attr);
2546 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
2547 gid_type = ah->grh.sgid_attr->gid_type;
2548 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
2549 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
2551 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2553 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2554 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
2555 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
2556 if (ah_flags & IB_AH_GRH)
2557 path->grh_mlid |= 1 << 7;
2558 path->dci_cfi_prio_sl = sl & 0xf;
2561 if (ah_flags & IB_AH_GRH) {
2562 path->mgid_index = grh->sgid_index;
2563 path->hop_limit = grh->hop_limit;
2564 path->tclass_flowlabel =
2565 cpu_to_be32((grh->traffic_class << 20) |
2567 memcpy(path->rgid, grh->dgid.raw, 16);
2570 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
2573 path->static_rate = err;
2576 if (attr_mask & IB_QP_TIMEOUT)
2577 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
2579 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2580 return modify_raw_packet_eth_prio(dev->mdev,
2581 &qp->raw_packet_qp.sq,
2587 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2588 [MLX5_QP_STATE_INIT] = {
2589 [MLX5_QP_STATE_INIT] = {
2590 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2591 MLX5_QP_OPTPAR_RAE |
2592 MLX5_QP_OPTPAR_RWE |
2593 MLX5_QP_OPTPAR_PKEY_INDEX |
2594 MLX5_QP_OPTPAR_PRI_PORT,
2595 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2596 MLX5_QP_OPTPAR_PKEY_INDEX |
2597 MLX5_QP_OPTPAR_PRI_PORT,
2598 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2599 MLX5_QP_OPTPAR_Q_KEY |
2600 MLX5_QP_OPTPAR_PRI_PORT,
2601 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE |
2602 MLX5_QP_OPTPAR_RAE |
2603 MLX5_QP_OPTPAR_RWE |
2604 MLX5_QP_OPTPAR_PKEY_INDEX |
2605 MLX5_QP_OPTPAR_PRI_PORT,
2607 [MLX5_QP_STATE_RTR] = {
2608 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2609 MLX5_QP_OPTPAR_RRE |
2610 MLX5_QP_OPTPAR_RAE |
2611 MLX5_QP_OPTPAR_RWE |
2612 MLX5_QP_OPTPAR_PKEY_INDEX,
2613 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2614 MLX5_QP_OPTPAR_RWE |
2615 MLX5_QP_OPTPAR_PKEY_INDEX,
2616 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2617 MLX5_QP_OPTPAR_Q_KEY,
2618 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
2619 MLX5_QP_OPTPAR_Q_KEY,
2620 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2621 MLX5_QP_OPTPAR_RRE |
2622 MLX5_QP_OPTPAR_RAE |
2623 MLX5_QP_OPTPAR_RWE |
2624 MLX5_QP_OPTPAR_PKEY_INDEX,
2627 [MLX5_QP_STATE_RTR] = {
2628 [MLX5_QP_STATE_RTS] = {
2629 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2630 MLX5_QP_OPTPAR_RRE |
2631 MLX5_QP_OPTPAR_RAE |
2632 MLX5_QP_OPTPAR_RWE |
2633 MLX5_QP_OPTPAR_PM_STATE |
2634 MLX5_QP_OPTPAR_RNR_TIMEOUT,
2635 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2636 MLX5_QP_OPTPAR_RWE |
2637 MLX5_QP_OPTPAR_PM_STATE,
2638 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2639 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2640 MLX5_QP_OPTPAR_RRE |
2641 MLX5_QP_OPTPAR_RAE |
2642 MLX5_QP_OPTPAR_RWE |
2643 MLX5_QP_OPTPAR_PM_STATE |
2644 MLX5_QP_OPTPAR_RNR_TIMEOUT,
2647 [MLX5_QP_STATE_RTS] = {
2648 [MLX5_QP_STATE_RTS] = {
2649 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2650 MLX5_QP_OPTPAR_RAE |
2651 MLX5_QP_OPTPAR_RWE |
2652 MLX5_QP_OPTPAR_RNR_TIMEOUT |
2653 MLX5_QP_OPTPAR_PM_STATE |
2654 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2655 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2656 MLX5_QP_OPTPAR_PM_STATE |
2657 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2658 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
2659 MLX5_QP_OPTPAR_SRQN |
2660 MLX5_QP_OPTPAR_CQN_RCV,
2661 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE |
2662 MLX5_QP_OPTPAR_RAE |
2663 MLX5_QP_OPTPAR_RWE |
2664 MLX5_QP_OPTPAR_RNR_TIMEOUT |
2665 MLX5_QP_OPTPAR_PM_STATE |
2666 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2669 [MLX5_QP_STATE_SQER] = {
2670 [MLX5_QP_STATE_RTS] = {
2671 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2672 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
2673 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
2674 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
2675 MLX5_QP_OPTPAR_RWE |
2676 MLX5_QP_OPTPAR_RAE |
2678 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
2679 MLX5_QP_OPTPAR_RWE |
2680 MLX5_QP_OPTPAR_RAE |
2686 static int ib_nr_to_mlx5_nr(int ib_mask)
2691 case IB_QP_CUR_STATE:
2693 case IB_QP_EN_SQD_ASYNC_NOTIFY:
2695 case IB_QP_ACCESS_FLAGS:
2696 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2698 case IB_QP_PKEY_INDEX:
2699 return MLX5_QP_OPTPAR_PKEY_INDEX;
2701 return MLX5_QP_OPTPAR_PRI_PORT;
2703 return MLX5_QP_OPTPAR_Q_KEY;
2705 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2706 MLX5_QP_OPTPAR_PRI_PORT;
2707 case IB_QP_PATH_MTU:
2710 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2711 case IB_QP_RETRY_CNT:
2712 return MLX5_QP_OPTPAR_RETRY_COUNT;
2713 case IB_QP_RNR_RETRY:
2714 return MLX5_QP_OPTPAR_RNR_RETRY;
2717 case IB_QP_MAX_QP_RD_ATOMIC:
2718 return MLX5_QP_OPTPAR_SRA_MAX;
2719 case IB_QP_ALT_PATH:
2720 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2721 case IB_QP_MIN_RNR_TIMER:
2722 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2725 case IB_QP_MAX_DEST_RD_ATOMIC:
2726 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2727 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2728 case IB_QP_PATH_MIG_STATE:
2729 return MLX5_QP_OPTPAR_PM_STATE;
2732 case IB_QP_DEST_QPN:
2738 static int ib_mask_to_mlx5_opt(int ib_mask)
2743 for (i = 0; i < 8 * sizeof(int); i++) {
2744 if ((1 << i) & ib_mask)
2745 result |= ib_nr_to_mlx5_nr(1 << i);
2751 static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2752 struct mlx5_ib_rq *rq, int new_state,
2753 const struct mlx5_modify_raw_qp_param *raw_qp_param)
2760 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2761 in = kvzalloc(inlen, GFP_KERNEL);
2765 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2767 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2768 MLX5_SET(rqc, rqc, state, new_state);
2770 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2771 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
2772 MLX5_SET64(modify_rq_in, in, modify_bitmask,
2773 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
2774 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2776 pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n",
2780 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
2784 rq->state = new_state;
2791 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
2792 struct mlx5_ib_sq *sq,
2794 const struct mlx5_modify_raw_qp_param *raw_qp_param)
2796 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
2797 struct mlx5_rate_limit old_rl = ibqp->rl;
2798 struct mlx5_rate_limit new_rl = old_rl;
2799 bool new_rate_added = false;
2806 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2807 in = kvzalloc(inlen, GFP_KERNEL);
2811 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2813 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2814 MLX5_SET(sqc, sqc, state, new_state);
2816 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
2817 if (new_state != MLX5_SQC_STATE_RDY)
2818 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
2821 new_rl = raw_qp_param->rl;
2824 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) {
2826 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl);
2828 pr_err("Failed configuring rate limit(err %d): \
2829 rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
2830 err, new_rl.rate, new_rl.max_burst_sz,
2831 new_rl.typical_pkt_sz);
2835 new_rate_added = true;
2838 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
2839 /* index 0 means no limit */
2840 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
2843 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
2845 /* Remove new rate from table if failed */
2847 mlx5_rl_remove_rate(dev, &new_rl);
2851 /* Only remove the old rate after new rate was set */
2852 if ((old_rl.rate && !mlx5_rl_are_equal(&old_rl, &new_rl)) ||
2853 (new_state != MLX5_SQC_STATE_RDY)) {
2854 mlx5_rl_remove_rate(dev, &old_rl);
2855 if (new_state != MLX5_SQC_STATE_RDY)
2856 memset(&new_rl, 0, sizeof(new_rl));
2860 sq->state = new_state;
2867 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2868 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2871 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2872 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2873 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
2874 int modify_rq = !!qp->rq.wqe_cnt;
2875 int modify_sq = !!qp->sq.wqe_cnt;
2880 switch (raw_qp_param->operation) {
2881 case MLX5_CMD_OP_RST2INIT_QP:
2882 rq_state = MLX5_RQC_STATE_RDY;
2883 sq_state = MLX5_SQC_STATE_RDY;
2885 case MLX5_CMD_OP_2ERR_QP:
2886 rq_state = MLX5_RQC_STATE_ERR;
2887 sq_state = MLX5_SQC_STATE_ERR;
2889 case MLX5_CMD_OP_2RST_QP:
2890 rq_state = MLX5_RQC_STATE_RST;
2891 sq_state = MLX5_SQC_STATE_RST;
2893 case MLX5_CMD_OP_RTR2RTS_QP:
2894 case MLX5_CMD_OP_RTS2RTS_QP:
2895 if (raw_qp_param->set_mask ==
2896 MLX5_RAW_QP_RATE_LIMIT) {
2898 sq_state = sq->state;
2900 return raw_qp_param->set_mask ? -EINVAL : 0;
2903 case MLX5_CMD_OP_INIT2INIT_QP:
2904 case MLX5_CMD_OP_INIT2RTR_QP:
2905 if (raw_qp_param->set_mask)
2915 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param);
2922 err = modify_raw_packet_tx_affinity(dev->mdev, sq,
2928 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, raw_qp_param);
2934 static unsigned int get_tx_affinity(struct mlx5_ib_dev *dev,
2935 struct mlx5_ib_pd *pd,
2936 struct mlx5_ib_qp_base *qp_base,
2939 struct mlx5_ib_ucontext *ucontext = NULL;
2940 unsigned int tx_port_affinity;
2942 if (pd && pd->ibpd.uobject && pd->ibpd.uobject->context)
2943 ucontext = to_mucontext(pd->ibpd.uobject->context);
2946 tx_port_affinity = (unsigned int)atomic_add_return(
2947 1, &ucontext->tx_port_affinity) %
2950 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n",
2951 tx_port_affinity, qp_base->mqp.qpn, ucontext);
2954 (unsigned int)atomic_add_return(
2955 1, &dev->roce[port_num].tx_port_affinity) %
2958 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n",
2959 tx_port_affinity, qp_base->mqp.qpn);
2962 return tx_port_affinity;
2965 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2966 const struct ib_qp_attr *attr, int attr_mask,
2967 enum ib_qp_state cur_state, enum ib_qp_state new_state,
2968 const struct mlx5_ib_modify_qp *ucmd)
2970 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2971 [MLX5_QP_STATE_RST] = {
2972 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2973 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2974 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
2976 [MLX5_QP_STATE_INIT] = {
2977 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2978 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2979 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
2980 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
2982 [MLX5_QP_STATE_RTR] = {
2983 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2984 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2985 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
2987 [MLX5_QP_STATE_RTS] = {
2988 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2989 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2990 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
2992 [MLX5_QP_STATE_SQD] = {
2993 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2994 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2996 [MLX5_QP_STATE_SQER] = {
2997 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2998 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2999 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
3001 [MLX5_QP_STATE_ERR] = {
3002 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3003 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3007 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3008 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3009 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
3010 struct mlx5_ib_cq *send_cq, *recv_cq;
3011 struct mlx5_qp_context *context;
3012 struct mlx5_ib_pd *pd;
3013 struct mlx5_ib_port *mibport = NULL;
3014 enum mlx5_qp_state mlx5_cur, mlx5_new;
3015 enum mlx5_qp_optpar optpar;
3021 mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ?
3022 qp->qp_sub_type : ibqp->qp_type);
3026 context = kzalloc(sizeof(*context), GFP_KERNEL);
3031 context->flags = cpu_to_be32(mlx5_st << 16);
3033 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
3034 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3036 switch (attr->path_mig_state) {
3037 case IB_MIG_MIGRATED:
3038 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3041 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
3044 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
3049 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
3050 if ((ibqp->qp_type == IB_QPT_RC) ||
3051 (ibqp->qp_type == IB_QPT_UD &&
3052 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
3053 (ibqp->qp_type == IB_QPT_UC) ||
3054 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
3055 (ibqp->qp_type == IB_QPT_XRC_INI) ||
3056 (ibqp->qp_type == IB_QPT_XRC_TGT)) {
3057 if (mlx5_lag_is_active(dev->mdev)) {
3058 u8 p = mlx5_core_native_port_num(dev->mdev);
3059 tx_affinity = get_tx_affinity(dev, pd, base, p);
3060 context->flags |= cpu_to_be32(tx_affinity << 24);
3065 if (is_sqp(ibqp->qp_type)) {
3066 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
3067 } else if ((ibqp->qp_type == IB_QPT_UD &&
3068 !(qp->flags & MLX5_IB_QP_UNDERLAY)) ||
3069 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
3070 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
3071 } else if (attr_mask & IB_QP_PATH_MTU) {
3072 if (attr->path_mtu < IB_MTU_256 ||
3073 attr->path_mtu > IB_MTU_4096) {
3074 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
3078 context->mtu_msgmax = (attr->path_mtu << 5) |
3079 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
3082 if (attr_mask & IB_QP_DEST_QPN)
3083 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
3085 if (attr_mask & IB_QP_PKEY_INDEX)
3086 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
3088 /* todo implement counter_index functionality */
3090 if (is_sqp(ibqp->qp_type))
3091 context->pri_path.port = qp->port;
3093 if (attr_mask & IB_QP_PORT)
3094 context->pri_path.port = attr->port_num;
3096 if (attr_mask & IB_QP_AV) {
3097 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
3098 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
3099 attr_mask, 0, attr, false);
3104 if (attr_mask & IB_QP_TIMEOUT)
3105 context->pri_path.ackto_lt |= attr->timeout << 3;
3107 if (attr_mask & IB_QP_ALT_PATH) {
3108 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
3111 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
3117 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
3118 &send_cq, &recv_cq);
3120 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
3121 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
3122 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
3123 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
3125 if (attr_mask & IB_QP_RNR_RETRY)
3126 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
3128 if (attr_mask & IB_QP_RETRY_CNT)
3129 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
3131 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
3132 if (attr->max_rd_atomic)
3134 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
3137 if (attr_mask & IB_QP_SQ_PSN)
3138 context->next_send_psn = cpu_to_be32(attr->sq_psn);
3140 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
3141 if (attr->max_dest_rd_atomic)
3143 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
3146 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
3147 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
3149 if (attr_mask & IB_QP_MIN_RNR_TIMER)
3150 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
3152 if (attr_mask & IB_QP_RQ_PSN)
3153 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
3155 if (attr_mask & IB_QP_QKEY)
3156 context->qkey = cpu_to_be32(attr->qkey);
3158 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3159 context->db_rec_addr = cpu_to_be64(qp->db.dma);
3161 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3162 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
3165 /* Underlay port should be used - index 0 function per port */
3166 if (qp->flags & MLX5_IB_QP_UNDERLAY)
3169 mibport = &dev->port[port_num];
3170 context->qp_counter_set_usr_page |=
3171 cpu_to_be32((u32)(mibport->cnts.set_id) << 24);
3174 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3175 context->sq_crq_size |= cpu_to_be16(1 << 4);
3177 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
3178 context->deth_sqpn = cpu_to_be32(1);
3180 mlx5_cur = to_mlx5_state(cur_state);
3181 mlx5_new = to_mlx5_state(new_state);
3183 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
3184 !optab[mlx5_cur][mlx5_new]) {
3189 op = optab[mlx5_cur][mlx5_new];
3190 optpar = ib_mask_to_mlx5_opt(attr_mask);
3191 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
3193 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
3194 qp->flags & MLX5_IB_QP_UNDERLAY) {
3195 struct mlx5_modify_raw_qp_param raw_qp_param = {};
3197 raw_qp_param.operation = op;
3198 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3199 raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id;
3200 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
3203 if (attr_mask & IB_QP_RATE_LIMIT) {
3204 raw_qp_param.rl.rate = attr->rate_limit;
3206 if (ucmd->burst_info.max_burst_sz) {
3207 if (attr->rate_limit &&
3208 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) {
3209 raw_qp_param.rl.max_burst_sz =
3210 ucmd->burst_info.max_burst_sz;
3217 if (ucmd->burst_info.typical_pkt_sz) {
3218 if (attr->rate_limit &&
3219 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) {
3220 raw_qp_param.rl.typical_pkt_sz =
3221 ucmd->burst_info.typical_pkt_sz;
3228 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
3231 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
3233 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
3240 qp->state = new_state;
3242 if (attr_mask & IB_QP_ACCESS_FLAGS)
3243 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
3244 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3245 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
3246 if (attr_mask & IB_QP_PORT)
3247 qp->port = attr->port_num;
3248 if (attr_mask & IB_QP_ALT_PATH)
3249 qp->trans_qp.alt_port = attr->alt_port_num;
3252 * If we moved a kernel QP to RESET, clean up all old CQ
3253 * entries and reinitialize the QP.
3255 if (new_state == IB_QPS_RESET &&
3256 !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) {
3257 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
3258 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
3259 if (send_cq != recv_cq)
3260 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
3266 qp->sq.cur_post = 0;
3267 qp->sq.last_poll = 0;
3268 qp->db.db[MLX5_RCV_DBR] = 0;
3269 qp->db.db[MLX5_SND_DBR] = 0;
3277 static inline bool is_valid_mask(int mask, int req, int opt)
3279 if ((mask & req) != req)
3282 if (mask & ~(req | opt))
3288 /* check valid transition for driver QP types
3289 * for now the only QP type that this function supports is DCI
3291 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state,
3292 enum ib_qp_attr_mask attr_mask)
3294 int req = IB_QP_STATE;
3297 if (new_state == IB_QPS_RESET) {
3298 return is_valid_mask(attr_mask, req, opt);
3299 } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3300 req |= IB_QP_PKEY_INDEX | IB_QP_PORT;
3301 return is_valid_mask(attr_mask, req, opt);
3302 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3303 opt = IB_QP_PKEY_INDEX | IB_QP_PORT;
3304 return is_valid_mask(attr_mask, req, opt);
3305 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3306 req |= IB_QP_PATH_MTU;
3307 opt = IB_QP_PKEY_INDEX;
3308 return is_valid_mask(attr_mask, req, opt);
3309 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3310 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY |
3311 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN;
3312 opt = IB_QP_MIN_RNR_TIMER;
3313 return is_valid_mask(attr_mask, req, opt);
3314 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) {
3315 opt = IB_QP_MIN_RNR_TIMER;
3316 return is_valid_mask(attr_mask, req, opt);
3317 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) {
3318 return is_valid_mask(attr_mask, req, opt);
3323 /* mlx5_ib_modify_dct: modify a DCT QP
3324 * valid transitions are:
3325 * RESET to INIT: must set access_flags, pkey_index and port
3326 * INIT to RTR : must set min_rnr_timer, tclass, flow_label,
3327 * mtu, gid_index and hop_limit
3328 * Other transitions and attributes are illegal
3330 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3331 int attr_mask, struct ib_udata *udata)
3333 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3334 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3335 enum ib_qp_state cur_state, new_state;
3337 int required = IB_QP_STATE;
3340 if (!(attr_mask & IB_QP_STATE))
3343 cur_state = qp->state;
3344 new_state = attr->qp_state;
3346 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
3347 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3348 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT;
3349 if (!is_valid_mask(attr_mask, required, 0))
3352 if (attr->port_num == 0 ||
3353 attr->port_num > dev->num_ports) {
3354 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3355 attr->port_num, dev->num_ports);
3358 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
3359 MLX5_SET(dctc, dctc, rre, 1);
3360 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
3361 MLX5_SET(dctc, dctc, rwe, 1);
3362 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) {
3363 if (!mlx5_ib_dc_atomic_is_supported(dev))
3365 MLX5_SET(dctc, dctc, rae, 1);
3366 MLX5_SET(dctc, dctc, atomic_mode, MLX5_ATOMIC_MODE_DCT_CX);
3368 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index);
3369 MLX5_SET(dctc, dctc, port, attr->port_num);
3370 MLX5_SET(dctc, dctc, counter_set_id, dev->port[attr->port_num - 1].cnts.set_id);
3372 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3373 struct mlx5_ib_modify_qp_resp resp = {};
3374 u32 min_resp_len = offsetof(typeof(resp), dctn) +
3377 if (udata->outlen < min_resp_len)
3379 resp.response_length = min_resp_len;
3381 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU;
3382 if (!is_valid_mask(attr_mask, required, 0))
3384 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer);
3385 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class);
3386 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label);
3387 MLX5_SET(dctc, dctc, mtu, attr->path_mtu);
3388 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index);
3389 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit);
3390 if (attr->ah_attr.type == RDMA_AH_ATTR_TYPE_ROCE)
3391 MLX5_SET(dctc, dctc, eth_prio, attr->ah_attr.sl & 0x7);
3393 err = mlx5_core_create_dct(dev->mdev, &qp->dct.mdct, qp->dct.in,
3394 MLX5_ST_SZ_BYTES(create_dct_in));
3397 resp.dctn = qp->dct.mdct.mqp.qpn;
3398 err = ib_copy_to_udata(udata, &resp, resp.response_length);
3400 mlx5_core_destroy_dct(dev->mdev, &qp->dct.mdct);
3404 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state);
3408 qp->state = IB_QPS_ERR;
3410 qp->state = new_state;
3414 static int validate_rd_atomic(struct mlx5_ib_dev *dev, struct ib_qp_attr *attr,
3415 int attr_mask, enum ib_qp_type qp_type)
3420 if (qp_type == MLX5_IB_QPT_DCI) {
3421 log_max_ra_res = 1 << MLX5_CAP_GEN(dev->mdev,
3423 log_max_ra_req = 1 << MLX5_CAP_GEN(dev->mdev,
3426 log_max_ra_res = 1 << MLX5_CAP_GEN(dev->mdev,
3428 log_max_ra_req = 1 << MLX5_CAP_GEN(dev->mdev,
3432 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
3433 attr->max_rd_atomic > log_max_ra_res) {
3434 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
3435 attr->max_rd_atomic);
3439 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
3440 attr->max_dest_rd_atomic > log_max_ra_req) {
3441 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
3442 attr->max_dest_rd_atomic);
3448 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3449 int attr_mask, struct ib_udata *udata)
3451 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3452 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3453 struct mlx5_ib_modify_qp ucmd = {};
3454 enum ib_qp_type qp_type;
3455 enum ib_qp_state cur_state, new_state;
3456 size_t required_cmd_sz;
3459 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
3461 if (ibqp->rwq_ind_tbl)
3464 if (udata && udata->inlen) {
3465 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
3466 sizeof(ucmd.reserved);
3467 if (udata->inlen < required_cmd_sz)
3470 if (udata->inlen > sizeof(ucmd) &&
3471 !ib_is_udata_cleared(udata, sizeof(ucmd),
3472 udata->inlen - sizeof(ucmd)))
3475 if (ib_copy_from_udata(&ucmd, udata,
3476 min(udata->inlen, sizeof(ucmd))))
3479 if (ucmd.comp_mask ||
3480 memchr_inv(&ucmd.reserved, 0, sizeof(ucmd.reserved)) ||
3481 memchr_inv(&ucmd.burst_info.reserved, 0,
3482 sizeof(ucmd.burst_info.reserved)))
3486 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3487 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
3489 if (ibqp->qp_type == IB_QPT_DRIVER)
3490 qp_type = qp->qp_sub_type;
3492 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
3493 IB_QPT_GSI : ibqp->qp_type;
3495 if (qp_type == MLX5_IB_QPT_DCT)
3496 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata);
3498 mutex_lock(&qp->mutex);
3500 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
3501 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
3503 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
3504 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3505 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
3508 if (qp->flags & MLX5_IB_QP_UNDERLAY) {
3509 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
3510 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
3514 } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
3515 qp_type != MLX5_IB_QPT_DCI &&
3516 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
3517 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3518 cur_state, new_state, ibqp->qp_type, attr_mask);
3520 } else if (qp_type == MLX5_IB_QPT_DCI &&
3521 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) {
3522 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3523 cur_state, new_state, qp_type, attr_mask);
3527 if ((attr_mask & IB_QP_PORT) &&
3528 (attr->port_num == 0 ||
3529 attr->port_num > dev->num_ports)) {
3530 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3531 attr->port_num, dev->num_ports);
3535 if (attr_mask & IB_QP_PKEY_INDEX) {
3536 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3537 if (attr->pkey_index >=
3538 dev->mdev->port_caps[port - 1].pkey_table_len) {
3539 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
3545 if (!validate_rd_atomic(dev, attr, attr_mask, qp_type))
3548 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
3553 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state,
3557 mutex_unlock(&qp->mutex);
3561 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3563 struct mlx5_ib_cq *cq;
3566 cur = wq->head - wq->tail;
3567 if (likely(cur + nreq < wq->max_post))
3571 spin_lock(&cq->lock);
3572 cur = wq->head - wq->tail;
3573 spin_unlock(&cq->lock);
3575 return cur + nreq >= wq->max_post;
3578 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
3579 u64 remote_addr, u32 rkey)
3581 rseg->raddr = cpu_to_be64(remote_addr);
3582 rseg->rkey = cpu_to_be32(rkey);
3586 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
3587 const struct ib_send_wr *wr, void *qend,
3588 struct mlx5_ib_qp *qp, int *size)
3592 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
3594 if (wr->send_flags & IB_SEND_IP_CSUM)
3595 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
3596 MLX5_ETH_WQE_L4_CSUM;
3598 seg += sizeof(struct mlx5_wqe_eth_seg);
3599 *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
3601 if (wr->opcode == IB_WR_LSO) {
3602 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
3603 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr.start);
3604 u64 left, leftlen, copysz;
3605 void *pdata = ud_wr->header;
3608 eseg->mss = cpu_to_be16(ud_wr->mss);
3609 eseg->inline_hdr.sz = cpu_to_be16(left);
3612 * check if there is space till the end of queue, if yes,
3613 * copy all in one shot, otherwise copy till the end of queue,
3614 * rollback and than the copy the left
3616 leftlen = qend - (void *)eseg->inline_hdr.start;
3617 copysz = min_t(u64, leftlen, left);
3619 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
3621 if (likely(copysz > size_of_inl_hdr_start)) {
3622 seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
3623 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
3626 if (unlikely(copysz < left)) { /* the last wqe in the queue */
3627 seg = mlx5_get_send_wqe(qp, 0);
3630 memcpy(seg, pdata, left);
3631 seg += ALIGN(left, 16);
3632 *size += ALIGN(left, 16) / 16;
3639 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
3640 const struct ib_send_wr *wr)
3642 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
3643 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
3644 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
3647 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
3649 dseg->byte_count = cpu_to_be32(sg->length);
3650 dseg->lkey = cpu_to_be32(sg->lkey);
3651 dseg->addr = cpu_to_be64(sg->addr);
3654 static u64 get_xlt_octo(u64 bytes)
3656 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
3657 MLX5_IB_UMR_OCTOWORD;
3660 static __be64 frwr_mkey_mask(void)
3664 result = MLX5_MKEY_MASK_LEN |
3665 MLX5_MKEY_MASK_PAGE_SIZE |
3666 MLX5_MKEY_MASK_START_ADDR |
3667 MLX5_MKEY_MASK_EN_RINVAL |
3668 MLX5_MKEY_MASK_KEY |
3674 MLX5_MKEY_MASK_SMALL_FENCE |
3675 MLX5_MKEY_MASK_FREE;
3677 return cpu_to_be64(result);
3680 static __be64 sig_mkey_mask(void)
3684 result = MLX5_MKEY_MASK_LEN |
3685 MLX5_MKEY_MASK_PAGE_SIZE |
3686 MLX5_MKEY_MASK_START_ADDR |
3687 MLX5_MKEY_MASK_EN_SIGERR |
3688 MLX5_MKEY_MASK_EN_RINVAL |
3689 MLX5_MKEY_MASK_KEY |
3694 MLX5_MKEY_MASK_SMALL_FENCE |
3695 MLX5_MKEY_MASK_FREE |
3696 MLX5_MKEY_MASK_BSF_EN;
3698 return cpu_to_be64(result);
3701 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
3702 struct mlx5_ib_mr *mr, bool umr_inline)
3704 int size = mr->ndescs * mr->desc_size;
3706 memset(umr, 0, sizeof(*umr));
3708 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
3710 umr->flags |= MLX5_UMR_INLINE;
3711 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
3712 umr->mkey_mask = frwr_mkey_mask();
3715 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
3717 memset(umr, 0, sizeof(*umr));
3718 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
3719 umr->flags = MLX5_UMR_INLINE;
3722 static __be64 get_umr_enable_mr_mask(void)
3726 result = MLX5_MKEY_MASK_KEY |
3727 MLX5_MKEY_MASK_FREE;
3729 return cpu_to_be64(result);
3732 static __be64 get_umr_disable_mr_mask(void)
3736 result = MLX5_MKEY_MASK_FREE;
3738 return cpu_to_be64(result);
3741 static __be64 get_umr_update_translation_mask(void)
3745 result = MLX5_MKEY_MASK_LEN |
3746 MLX5_MKEY_MASK_PAGE_SIZE |
3747 MLX5_MKEY_MASK_START_ADDR;
3749 return cpu_to_be64(result);
3752 static __be64 get_umr_update_access_mask(int atomic)
3756 result = MLX5_MKEY_MASK_LR |
3762 result |= MLX5_MKEY_MASK_A;
3764 return cpu_to_be64(result);
3767 static __be64 get_umr_update_pd_mask(void)
3771 result = MLX5_MKEY_MASK_PD;
3773 return cpu_to_be64(result);
3776 static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask)
3778 if ((mask & MLX5_MKEY_MASK_PAGE_SIZE &&
3779 MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) ||
3780 (mask & MLX5_MKEY_MASK_A &&
3781 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled)))
3786 static int set_reg_umr_segment(struct mlx5_ib_dev *dev,
3787 struct mlx5_wqe_umr_ctrl_seg *umr,
3788 const struct ib_send_wr *wr, int atomic)
3790 const struct mlx5_umr_wr *umrwr = umr_wr(wr);
3792 memset(umr, 0, sizeof(*umr));
3794 if (!umrwr->ignore_free_state) {
3795 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3797 umr->flags = MLX5_UMR_CHECK_FREE;
3799 /* fail if not free */
3800 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
3803 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
3804 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
3805 u64 offset = get_xlt_octo(umrwr->offset);
3807 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
3808 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
3809 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
3811 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3812 umr->mkey_mask |= get_umr_update_translation_mask();
3813 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
3814 umr->mkey_mask |= get_umr_update_access_mask(atomic);
3815 umr->mkey_mask |= get_umr_update_pd_mask();
3817 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
3818 umr->mkey_mask |= get_umr_enable_mr_mask();
3819 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3820 umr->mkey_mask |= get_umr_disable_mr_mask();
3823 umr->flags |= MLX5_UMR_INLINE;
3825 return umr_check_mkey_mask(dev, be64_to_cpu(umr->mkey_mask));
3828 static u8 get_umr_flags(int acc)
3830 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
3831 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
3832 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
3833 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
3834 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
3837 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3838 struct mlx5_ib_mr *mr,
3839 u32 key, int access)
3841 int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3843 memset(seg, 0, sizeof(*seg));
3845 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
3846 seg->log2_page_size = ilog2(mr->ibmr.page_size);
3847 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
3848 /* KLMs take twice the size of MTTs */
3851 seg->flags = get_umr_flags(access) | mr->access_mode;
3852 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3853 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3854 seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3855 seg->len = cpu_to_be64(mr->ibmr.length);
3856 seg->xlt_oct_size = cpu_to_be32(ndescs);
3859 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
3861 memset(seg, 0, sizeof(*seg));
3862 seg->status = MLX5_MKEY_STATUS_FREE;
3865 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg,
3866 const struct ib_send_wr *wr)
3868 const struct mlx5_umr_wr *umrwr = umr_wr(wr);
3870 memset(seg, 0, sizeof(*seg));
3871 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3872 seg->status = MLX5_MKEY_STATUS_FREE;
3874 seg->flags = convert_access(umrwr->access_flags);
3876 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3877 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
3879 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
3881 seg->start_addr = cpu_to_be64(umrwr->virt_addr);
3882 seg->len = cpu_to_be64(umrwr->length);
3883 seg->log2_page_size = umrwr->page_shift;
3884 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
3885 mlx5_mkey_variant(umrwr->mkey));
3888 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3889 struct mlx5_ib_mr *mr,
3890 struct mlx5_ib_pd *pd)
3892 int bcount = mr->desc_size * mr->ndescs;
3894 dseg->addr = cpu_to_be64(mr->desc_map);
3895 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3896 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3899 static void set_reg_umr_inline_seg(void *seg, struct mlx5_ib_qp *qp,
3900 struct mlx5_ib_mr *mr, int mr_list_size)
3902 void *qend = qp->sq.qend;
3903 void *addr = mr->descs;
3906 if (unlikely(seg + mr_list_size > qend)) {
3908 memcpy(seg, addr, copy);
3910 mr_list_size -= copy;
3911 seg = mlx5_get_send_wqe(qp, 0);
3913 memcpy(seg, addr, mr_list_size);
3914 seg += mr_list_size;
3917 static __be32 send_ieth(const struct ib_send_wr *wr)
3919 switch (wr->opcode) {
3920 case IB_WR_SEND_WITH_IMM:
3921 case IB_WR_RDMA_WRITE_WITH_IMM:
3922 return wr->ex.imm_data;
3924 case IB_WR_SEND_WITH_INV:
3925 return cpu_to_be32(wr->ex.invalidate_rkey);
3932 static u8 calc_sig(void *wqe, int size)
3938 for (i = 0; i < size; i++)
3944 static u8 wq_sig(void *wqe)
3946 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3949 static int set_data_inl_seg(struct mlx5_ib_qp *qp, const struct ib_send_wr *wr,
3952 struct mlx5_wqe_inline_seg *seg;
3953 void *qend = qp->sq.qend;
3961 wqe += sizeof(*seg);
3962 for (i = 0; i < wr->num_sge; i++) {
3963 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3964 len = wr->sg_list[i].length;
3967 if (unlikely(inl > qp->max_inline_data))
3970 if (unlikely(wqe + len > qend)) {
3972 memcpy(wqe, addr, copy);
3975 wqe = mlx5_get_send_wqe(qp, 0);
3977 memcpy(wqe, addr, len);
3981 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3983 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3988 static u16 prot_field_size(enum ib_signature_type type)
3991 case IB_SIG_TYPE_T10_DIF:
3992 return MLX5_DIF_SIZE;
3998 static u8 bs_selector(int block_size)
4000 switch (block_size) {
4001 case 512: return 0x1;
4002 case 520: return 0x2;
4003 case 4096: return 0x3;
4004 case 4160: return 0x4;
4005 case 1073741824: return 0x5;
4010 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
4011 struct mlx5_bsf_inl *inl)
4013 /* Valid inline section and allow BSF refresh */
4014 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
4015 MLX5_BSF_REFRESH_DIF);
4016 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
4017 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
4018 /* repeating block */
4019 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
4020 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
4021 MLX5_DIF_CRC : MLX5_DIF_IPCS;
4023 if (domain->sig.dif.ref_remap)
4024 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
4026 if (domain->sig.dif.app_escape) {
4027 if (domain->sig.dif.ref_escape)
4028 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
4030 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
4033 inl->dif_app_bitmask_check =
4034 cpu_to_be16(domain->sig.dif.apptag_check_mask);
4037 static int mlx5_set_bsf(struct ib_mr *sig_mr,
4038 struct ib_sig_attrs *sig_attrs,
4039 struct mlx5_bsf *bsf, u32 data_size)
4041 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
4042 struct mlx5_bsf_basic *basic = &bsf->basic;
4043 struct ib_sig_domain *mem = &sig_attrs->mem;
4044 struct ib_sig_domain *wire = &sig_attrs->wire;
4046 memset(bsf, 0, sizeof(*bsf));
4048 /* Basic + Extended + Inline */
4049 basic->bsf_size_sbs = 1 << 7;
4050 /* Input domain check byte mask */
4051 basic->check_byte_mask = sig_attrs->check_mask;
4052 basic->raw_data_size = cpu_to_be32(data_size);
4055 switch (sig_attrs->mem.sig_type) {
4056 case IB_SIG_TYPE_NONE:
4058 case IB_SIG_TYPE_T10_DIF:
4059 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
4060 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
4061 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
4068 switch (sig_attrs->wire.sig_type) {
4069 case IB_SIG_TYPE_NONE:
4071 case IB_SIG_TYPE_T10_DIF:
4072 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
4073 mem->sig_type == wire->sig_type) {
4074 /* Same block structure */
4075 basic->bsf_size_sbs |= 1 << 4;
4076 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
4077 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
4078 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
4079 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
4080 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
4081 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
4083 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
4085 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
4086 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
4095 static int set_sig_data_segment(const struct ib_sig_handover_wr *wr,
4096 struct mlx5_ib_qp *qp, void **seg, int *size)
4098 struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
4099 struct ib_mr *sig_mr = wr->sig_mr;
4100 struct mlx5_bsf *bsf;
4101 u32 data_len = wr->wr.sg_list->length;
4102 u32 data_key = wr->wr.sg_list->lkey;
4103 u64 data_va = wr->wr.sg_list->addr;
4108 (data_key == wr->prot->lkey &&
4109 data_va == wr->prot->addr &&
4110 data_len == wr->prot->length)) {
4112 * Source domain doesn't contain signature information
4113 * or data and protection are interleaved in memory.
4114 * So need construct:
4115 * ------------------
4117 * ------------------
4119 * ------------------
4121 struct mlx5_klm *data_klm = *seg;
4123 data_klm->bcount = cpu_to_be32(data_len);
4124 data_klm->key = cpu_to_be32(data_key);
4125 data_klm->va = cpu_to_be64(data_va);
4126 wqe_size = ALIGN(sizeof(*data_klm), 64);
4129 * Source domain contains signature information
4130 * So need construct a strided block format:
4131 * ---------------------------
4132 * | stride_block_ctrl |
4133 * ---------------------------
4135 * ---------------------------
4137 * ---------------------------
4139 * ---------------------------
4141 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
4142 struct mlx5_stride_block_entry *data_sentry;
4143 struct mlx5_stride_block_entry *prot_sentry;
4144 u32 prot_key = wr->prot->lkey;
4145 u64 prot_va = wr->prot->addr;
4146 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
4150 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
4151 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
4153 prot_size = prot_field_size(sig_attrs->mem.sig_type);
4155 pr_err("Bad block size given: %u\n", block_size);
4158 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
4160 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
4161 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
4162 sblock_ctrl->num_entries = cpu_to_be16(2);
4164 data_sentry->bcount = cpu_to_be16(block_size);
4165 data_sentry->key = cpu_to_be32(data_key);
4166 data_sentry->va = cpu_to_be64(data_va);
4167 data_sentry->stride = cpu_to_be16(block_size);
4169 prot_sentry->bcount = cpu_to_be16(prot_size);
4170 prot_sentry->key = cpu_to_be32(prot_key);
4171 prot_sentry->va = cpu_to_be64(prot_va);
4172 prot_sentry->stride = cpu_to_be16(prot_size);
4174 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
4175 sizeof(*prot_sentry), 64);
4179 *size += wqe_size / 16;
4180 if (unlikely((*seg == qp->sq.qend)))
4181 *seg = mlx5_get_send_wqe(qp, 0);
4184 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
4188 *seg += sizeof(*bsf);
4189 *size += sizeof(*bsf) / 16;
4190 if (unlikely((*seg == qp->sq.qend)))
4191 *seg = mlx5_get_send_wqe(qp, 0);
4196 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
4197 const struct ib_sig_handover_wr *wr, u32 size,
4198 u32 length, u32 pdn)
4200 struct ib_mr *sig_mr = wr->sig_mr;
4201 u32 sig_key = sig_mr->rkey;
4202 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
4204 memset(seg, 0, sizeof(*seg));
4206 seg->flags = get_umr_flags(wr->access_flags) |
4207 MLX5_MKC_ACCESS_MODE_KLMS;
4208 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
4209 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
4210 MLX5_MKEY_BSF_EN | pdn);
4211 seg->len = cpu_to_be64(length);
4212 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
4213 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
4216 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
4219 memset(umr, 0, sizeof(*umr));
4221 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
4222 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
4223 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
4224 umr->mkey_mask = sig_mkey_mask();
4228 static int set_sig_umr_wr(const struct ib_send_wr *send_wr,
4229 struct mlx5_ib_qp *qp, void **seg, int *size)
4231 const struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
4232 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
4233 u32 pdn = get_pd(qp)->pdn;
4235 int region_len, ret;
4237 if (unlikely(wr->wr.num_sge != 1) ||
4238 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
4239 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
4240 unlikely(!sig_mr->sig->sig_status_checked))
4243 /* length of the protected region, data + protection */
4244 region_len = wr->wr.sg_list->length;
4246 (wr->prot->lkey != wr->wr.sg_list->lkey ||
4247 wr->prot->addr != wr->wr.sg_list->addr ||
4248 wr->prot->length != wr->wr.sg_list->length))
4249 region_len += wr->prot->length;
4252 * KLM octoword size - if protection was provided
4253 * then we use strided block format (3 octowords),
4254 * else we use single KLM (1 octoword)
4256 xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm);
4258 set_sig_umr_segment(*seg, xlt_size);
4259 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4260 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4261 if (unlikely((*seg == qp->sq.qend)))
4262 *seg = mlx5_get_send_wqe(qp, 0);
4264 set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn);
4265 *seg += sizeof(struct mlx5_mkey_seg);
4266 *size += sizeof(struct mlx5_mkey_seg) / 16;
4267 if (unlikely((*seg == qp->sq.qend)))
4268 *seg = mlx5_get_send_wqe(qp, 0);
4270 ret = set_sig_data_segment(wr, qp, seg, size);
4274 sig_mr->sig->sig_status_checked = false;
4278 static int set_psv_wr(struct ib_sig_domain *domain,
4279 u32 psv_idx, void **seg, int *size)
4281 struct mlx5_seg_set_psv *psv_seg = *seg;
4283 memset(psv_seg, 0, sizeof(*psv_seg));
4284 psv_seg->psv_num = cpu_to_be32(psv_idx);
4285 switch (domain->sig_type) {
4286 case IB_SIG_TYPE_NONE:
4288 case IB_SIG_TYPE_T10_DIF:
4289 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
4290 domain->sig.dif.app_tag);
4291 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
4294 pr_err("Bad signature type (%d) is given.\n",
4299 *seg += sizeof(*psv_seg);
4300 *size += sizeof(*psv_seg) / 16;
4305 static int set_reg_wr(struct mlx5_ib_qp *qp,
4306 const struct ib_reg_wr *wr,
4307 void **seg, int *size)
4309 struct mlx5_ib_mr *mr = to_mmr(wr->mr);
4310 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
4311 int mr_list_size = mr->ndescs * mr->desc_size;
4312 bool umr_inline = mr_list_size <= MLX5_IB_SQ_UMR_INLINE_THRESHOLD;
4314 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
4315 mlx5_ib_warn(to_mdev(qp->ibqp.device),
4316 "Invalid IB_SEND_INLINE send flag\n");
4320 set_reg_umr_seg(*seg, mr, umr_inline);
4321 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4322 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4323 if (unlikely((*seg == qp->sq.qend)))
4324 *seg = mlx5_get_send_wqe(qp, 0);
4326 set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
4327 *seg += sizeof(struct mlx5_mkey_seg);
4328 *size += sizeof(struct mlx5_mkey_seg) / 16;
4329 if (unlikely((*seg == qp->sq.qend)))
4330 *seg = mlx5_get_send_wqe(qp, 0);
4333 set_reg_umr_inline_seg(*seg, qp, mr, mr_list_size);
4334 *size += get_xlt_octo(mr_list_size);
4336 set_reg_data_seg(*seg, mr, pd);
4337 *seg += sizeof(struct mlx5_wqe_data_seg);
4338 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
4343 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
4345 set_linv_umr_seg(*seg);
4346 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4347 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4348 if (unlikely((*seg == qp->sq.qend)))
4349 *seg = mlx5_get_send_wqe(qp, 0);
4350 set_linv_mkey_seg(*seg);
4351 *seg += sizeof(struct mlx5_mkey_seg);
4352 *size += sizeof(struct mlx5_mkey_seg) / 16;
4353 if (unlikely((*seg == qp->sq.qend)))
4354 *seg = mlx5_get_send_wqe(qp, 0);
4357 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
4363 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
4364 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
4365 if ((i & 0xf) == 0) {
4366 void *buf = mlx5_get_send_wqe(qp, tidx);
4367 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
4371 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
4372 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
4373 be32_to_cpu(p[j + 3]));
4377 static int __begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4378 struct mlx5_wqe_ctrl_seg **ctrl,
4379 const struct ib_send_wr *wr, unsigned *idx,
4380 int *size, int nreq, bool send_signaled, bool solicited)
4382 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
4385 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
4386 *seg = mlx5_get_send_wqe(qp, *idx);
4388 *(uint32_t *)(*seg + 8) = 0;
4389 (*ctrl)->imm = send_ieth(wr);
4390 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
4391 (send_signaled ? MLX5_WQE_CTRL_CQ_UPDATE : 0) |
4392 (solicited ? MLX5_WQE_CTRL_SOLICITED : 0);
4394 *seg += sizeof(**ctrl);
4395 *size = sizeof(**ctrl) / 16;
4400 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4401 struct mlx5_wqe_ctrl_seg **ctrl,
4402 const struct ib_send_wr *wr, unsigned *idx,
4403 int *size, int nreq)
4405 return __begin_wqe(qp, seg, ctrl, wr, idx, size, nreq,
4406 wr->send_flags & IB_SEND_SIGNALED,
4407 wr->send_flags & IB_SEND_SOLICITED);
4410 static void finish_wqe(struct mlx5_ib_qp *qp,
4411 struct mlx5_wqe_ctrl_seg *ctrl,
4412 u8 size, unsigned idx, u64 wr_id,
4413 int nreq, u8 fence, u32 mlx5_opcode)
4417 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
4418 mlx5_opcode | ((u32)opmod << 24));
4419 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
4420 ctrl->fm_ce_se |= fence;
4421 if (unlikely(qp->wq_sig))
4422 ctrl->signature = wq_sig(ctrl);
4424 qp->sq.wrid[idx] = wr_id;
4425 qp->sq.w_list[idx].opcode = mlx5_opcode;
4426 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
4427 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
4428 qp->sq.w_list[idx].next = qp->sq.cur_post;
4431 static int _mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
4432 const struct ib_send_wr **bad_wr, bool drain)
4434 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
4435 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4436 struct mlx5_core_dev *mdev = dev->mdev;
4437 struct mlx5_ib_qp *qp;
4438 struct mlx5_ib_mr *mr;
4439 struct mlx5_wqe_data_seg *dpseg;
4440 struct mlx5_wqe_xrc_seg *xrc;
4442 int uninitialized_var(size);
4444 unsigned long flags;
4454 if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
4460 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4461 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
4467 spin_lock_irqsave(&qp->sq.lock, flags);
4469 for (nreq = 0; wr; nreq++, wr = wr->next) {
4470 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
4471 mlx5_ib_warn(dev, "\n");
4477 num_sge = wr->num_sge;
4478 if (unlikely(num_sge > qp->sq.max_gs)) {
4479 mlx5_ib_warn(dev, "\n");
4485 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
4487 mlx5_ib_warn(dev, "\n");
4493 if (wr->opcode == IB_WR_REG_MR) {
4494 fence = dev->umr_fence;
4495 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4497 if (wr->send_flags & IB_SEND_FENCE) {
4499 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
4501 fence = MLX5_FENCE_MODE_FENCE;
4503 fence = qp->next_fence;
4507 switch (ibqp->qp_type) {
4508 case IB_QPT_XRC_INI:
4510 seg += sizeof(*xrc);
4511 size += sizeof(*xrc) / 16;
4514 switch (wr->opcode) {
4515 case IB_WR_RDMA_READ:
4516 case IB_WR_RDMA_WRITE:
4517 case IB_WR_RDMA_WRITE_WITH_IMM:
4518 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4520 seg += sizeof(struct mlx5_wqe_raddr_seg);
4521 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4524 case IB_WR_ATOMIC_CMP_AND_SWP:
4525 case IB_WR_ATOMIC_FETCH_AND_ADD:
4526 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
4527 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
4532 case IB_WR_LOCAL_INV:
4533 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
4534 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
4535 set_linv_wr(qp, &seg, &size);
4540 qp->sq.wr_data[idx] = IB_WR_REG_MR;
4541 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
4542 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
4550 case IB_WR_REG_SIG_MR:
4551 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
4552 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
4554 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
4555 err = set_sig_umr_wr(wr, qp, &seg, &size);
4557 mlx5_ib_warn(dev, "\n");
4562 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4563 fence, MLX5_OPCODE_UMR);
4565 * SET_PSV WQEs are not signaled and solicited
4568 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
4569 &size, nreq, false, true);
4571 mlx5_ib_warn(dev, "\n");
4577 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
4578 mr->sig->psv_memory.psv_idx, &seg,
4581 mlx5_ib_warn(dev, "\n");
4586 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4587 fence, MLX5_OPCODE_SET_PSV);
4588 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
4589 &size, nreq, false, true);
4591 mlx5_ib_warn(dev, "\n");
4597 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
4598 mr->sig->psv_wire.psv_idx, &seg,
4601 mlx5_ib_warn(dev, "\n");
4606 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4607 fence, MLX5_OPCODE_SET_PSV);
4608 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4618 switch (wr->opcode) {
4619 case IB_WR_RDMA_WRITE:
4620 case IB_WR_RDMA_WRITE_WITH_IMM:
4621 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4623 seg += sizeof(struct mlx5_wqe_raddr_seg);
4624 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4633 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
4634 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
4640 case MLX5_IB_QPT_HW_GSI:
4641 set_datagram_seg(seg, wr);
4642 seg += sizeof(struct mlx5_wqe_datagram_seg);
4643 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4644 if (unlikely((seg == qend)))
4645 seg = mlx5_get_send_wqe(qp, 0);
4648 set_datagram_seg(seg, wr);
4649 seg += sizeof(struct mlx5_wqe_datagram_seg);
4650 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4652 if (unlikely((seg == qend)))
4653 seg = mlx5_get_send_wqe(qp, 0);
4655 /* handle qp that supports ud offload */
4656 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
4657 struct mlx5_wqe_eth_pad *pad;
4660 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4661 seg += sizeof(struct mlx5_wqe_eth_pad);
4662 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
4664 seg = set_eth_seg(seg, wr, qend, qp, &size);
4666 if (unlikely((seg == qend)))
4667 seg = mlx5_get_send_wqe(qp, 0);
4670 case MLX5_IB_QPT_REG_UMR:
4671 if (wr->opcode != MLX5_IB_WR_UMR) {
4673 mlx5_ib_warn(dev, "bad opcode\n");
4676 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
4677 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
4678 err = set_reg_umr_segment(dev, seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
4681 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4682 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4683 if (unlikely((seg == qend)))
4684 seg = mlx5_get_send_wqe(qp, 0);
4685 set_reg_mkey_segment(seg, wr);
4686 seg += sizeof(struct mlx5_mkey_seg);
4687 size += sizeof(struct mlx5_mkey_seg) / 16;
4688 if (unlikely((seg == qend)))
4689 seg = mlx5_get_send_wqe(qp, 0);
4696 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
4697 int uninitialized_var(sz);
4699 err = set_data_inl_seg(qp, wr, seg, &sz);
4700 if (unlikely(err)) {
4701 mlx5_ib_warn(dev, "\n");
4708 for (i = 0; i < num_sge; i++) {
4709 if (unlikely(dpseg == qend)) {
4710 seg = mlx5_get_send_wqe(qp, 0);
4713 if (likely(wr->sg_list[i].length)) {
4714 set_data_ptr_seg(dpseg, wr->sg_list + i);
4715 size += sizeof(struct mlx5_wqe_data_seg) / 16;
4721 qp->next_fence = next_fence;
4722 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, fence,
4723 mlx5_ib_opcode[wr->opcode]);
4726 dump_wqe(qp, idx, size);
4731 qp->sq.head += nreq;
4733 /* Make sure that descriptors are written before
4734 * updating doorbell record and ringing the doorbell
4738 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4740 /* Make sure doorbell record is visible to the HCA before
4741 * we hit doorbell */
4744 /* currently we support only regular doorbells */
4745 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL);
4746 /* Make sure doorbells don't leak out of SQ spinlock
4747 * and reach the HCA out of order.
4750 bf->offset ^= bf->buf_size;
4753 spin_unlock_irqrestore(&qp->sq.lock, flags);
4758 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
4759 const struct ib_send_wr **bad_wr)
4761 return _mlx5_ib_post_send(ibqp, wr, bad_wr, false);
4764 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4766 sig->signature = calc_sig(sig, size);
4769 static int _mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
4770 const struct ib_recv_wr **bad_wr, bool drain)
4772 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4773 struct mlx5_wqe_data_seg *scat;
4774 struct mlx5_rwqe_sig *sig;
4775 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4776 struct mlx5_core_dev *mdev = dev->mdev;
4777 unsigned long flags;
4783 if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
4789 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4790 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4792 spin_lock_irqsave(&qp->rq.lock, flags);
4794 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4796 for (nreq = 0; wr; nreq++, wr = wr->next) {
4797 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4803 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4809 scat = get_recv_wqe(qp, ind);
4813 for (i = 0; i < wr->num_sge; i++)
4814 set_data_ptr_seg(scat + i, wr->sg_list + i);
4816 if (i < qp->rq.max_gs) {
4817 scat[i].byte_count = 0;
4818 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
4823 sig = (struct mlx5_rwqe_sig *)scat;
4824 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4827 qp->rq.wrid[ind] = wr->wr_id;
4829 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4834 qp->rq.head += nreq;
4836 /* Make sure that descriptors are written before
4841 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4844 spin_unlock_irqrestore(&qp->rq.lock, flags);
4849 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
4850 const struct ib_recv_wr **bad_wr)
4852 return _mlx5_ib_post_recv(ibqp, wr, bad_wr, false);
4855 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4857 switch (mlx5_state) {
4858 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
4859 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
4860 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
4861 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
4862 case MLX5_QP_STATE_SQ_DRAINING:
4863 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
4864 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
4865 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
4870 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4872 switch (mlx5_mig_state) {
4873 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
4874 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
4875 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
4880 static int to_ib_qp_access_flags(int mlx5_flags)
4884 if (mlx5_flags & MLX5_QP_BIT_RRE)
4885 ib_flags |= IB_ACCESS_REMOTE_READ;
4886 if (mlx5_flags & MLX5_QP_BIT_RWE)
4887 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4888 if (mlx5_flags & MLX5_QP_BIT_RAE)
4889 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4894 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
4895 struct rdma_ah_attr *ah_attr,
4896 struct mlx5_qp_path *path)
4899 memset(ah_attr, 0, sizeof(*ah_attr));
4901 if (!path->port || path->port > ibdev->num_ports)
4904 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port);
4906 rdma_ah_set_port_num(ah_attr, path->port);
4907 rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf);
4909 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
4910 rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f);
4911 rdma_ah_set_static_rate(ah_attr,
4912 path->static_rate ? path->static_rate - 5 : 0);
4914 if (path->grh_mlid & (1 << 7) ||
4915 ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE) {
4916 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel);
4918 rdma_ah_set_grh(ah_attr, NULL,
4922 (tc_fl >> 20) & 0xff);
4923 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
4927 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4928 struct mlx5_ib_sq *sq,
4933 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state);
4936 sq->state = *sq_state;
4942 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4943 struct mlx5_ib_rq *rq,
4951 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
4952 out = kvzalloc(inlen, GFP_KERNEL);
4956 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4960 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4961 *rq_state = MLX5_GET(rqc, rqc, state);
4962 rq->state = *rq_state;
4969 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4970 struct mlx5_ib_qp *qp, u8 *qp_state)
4972 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4973 [MLX5_RQC_STATE_RST] = {
4974 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4975 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4976 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
4977 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
4979 [MLX5_RQC_STATE_RDY] = {
4980 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4981 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4982 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
4983 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
4985 [MLX5_RQC_STATE_ERR] = {
4986 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4987 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4988 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
4989 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
4991 [MLX5_RQ_STATE_NA] = {
4992 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4993 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4994 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
4995 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
4999 *qp_state = sqrq_trans[rq_state][sq_state];
5001 if (*qp_state == MLX5_QP_STATE_BAD) {
5002 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
5003 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
5004 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
5008 if (*qp_state == MLX5_QP_STATE)
5009 *qp_state = qp->state;
5014 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
5015 struct mlx5_ib_qp *qp,
5016 u8 *raw_packet_qp_state)
5018 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
5019 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
5020 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
5022 u8 sq_state = MLX5_SQ_STATE_NA;
5023 u8 rq_state = MLX5_RQ_STATE_NA;
5025 if (qp->sq.wqe_cnt) {
5026 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
5031 if (qp->rq.wqe_cnt) {
5032 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
5037 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
5038 raw_packet_qp_state);
5041 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
5042 struct ib_qp_attr *qp_attr)
5044 int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
5045 struct mlx5_qp_context *context;
5050 outb = kzalloc(outlen, GFP_KERNEL);
5054 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
5059 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
5060 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
5062 mlx5_state = be32_to_cpu(context->flags) >> 28;
5064 qp->state = to_ib_qp_state(mlx5_state);
5065 qp_attr->path_mtu = context->mtu_msgmax >> 5;
5066 qp_attr->path_mig_state =
5067 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
5068 qp_attr->qkey = be32_to_cpu(context->qkey);
5069 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
5070 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
5071 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
5072 qp_attr->qp_access_flags =
5073 to_ib_qp_access_flags(be32_to_cpu(context->params2));
5075 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
5076 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
5077 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
5078 qp_attr->alt_pkey_index =
5079 be16_to_cpu(context->alt_path.pkey_index);
5080 qp_attr->alt_port_num =
5081 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
5084 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
5085 qp_attr->port_num = context->pri_path.port;
5087 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
5088 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
5090 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
5092 qp_attr->max_dest_rd_atomic =
5093 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
5094 qp_attr->min_rnr_timer =
5095 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
5096 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
5097 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
5098 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
5099 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
5106 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp,
5107 struct ib_qp_attr *qp_attr, int qp_attr_mask,
5108 struct ib_qp_init_attr *qp_init_attr)
5110 struct mlx5_core_dct *dct = &mqp->dct.mdct;
5112 u32 access_flags = 0;
5113 int outlen = MLX5_ST_SZ_BYTES(query_dct_out);
5116 int supported_mask = IB_QP_STATE |
5117 IB_QP_ACCESS_FLAGS |
5119 IB_QP_MIN_RNR_TIMER |
5124 if (qp_attr_mask & ~supported_mask)
5126 if (mqp->state != IB_QPS_RTR)
5129 out = kzalloc(outlen, GFP_KERNEL);
5133 err = mlx5_core_dct_query(dev->mdev, dct, out, outlen);
5137 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry);
5139 if (qp_attr_mask & IB_QP_STATE)
5140 qp_attr->qp_state = IB_QPS_RTR;
5142 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
5143 if (MLX5_GET(dctc, dctc, rre))
5144 access_flags |= IB_ACCESS_REMOTE_READ;
5145 if (MLX5_GET(dctc, dctc, rwe))
5146 access_flags |= IB_ACCESS_REMOTE_WRITE;
5147 if (MLX5_GET(dctc, dctc, rae))
5148 access_flags |= IB_ACCESS_REMOTE_ATOMIC;
5149 qp_attr->qp_access_flags = access_flags;
5152 if (qp_attr_mask & IB_QP_PORT)
5153 qp_attr->port_num = MLX5_GET(dctc, dctc, port);
5154 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER)
5155 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak);
5156 if (qp_attr_mask & IB_QP_AV) {
5157 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass);
5158 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label);
5159 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index);
5160 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit);
5162 if (qp_attr_mask & IB_QP_PATH_MTU)
5163 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu);
5164 if (qp_attr_mask & IB_QP_PKEY_INDEX)
5165 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index);
5171 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
5172 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
5174 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5175 struct mlx5_ib_qp *qp = to_mqp(ibqp);
5177 u8 raw_packet_qp_state;
5179 if (ibqp->rwq_ind_tbl)
5182 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5183 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
5186 /* Not all of output fields are applicable, make sure to zero them */
5187 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
5188 memset(qp_attr, 0, sizeof(*qp_attr));
5190 if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT))
5191 return mlx5_ib_dct_query_qp(dev, qp, qp_attr,
5192 qp_attr_mask, qp_init_attr);
5194 mutex_lock(&qp->mutex);
5196 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
5197 qp->flags & MLX5_IB_QP_UNDERLAY) {
5198 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
5201 qp->state = raw_packet_qp_state;
5202 qp_attr->port_num = 1;
5204 err = query_qp_attr(dev, qp, qp_attr);
5209 qp_attr->qp_state = qp->state;
5210 qp_attr->cur_qp_state = qp_attr->qp_state;
5211 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
5212 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
5214 if (!ibqp->uobject) {
5215 qp_attr->cap.max_send_wr = qp->sq.max_post;
5216 qp_attr->cap.max_send_sge = qp->sq.max_gs;
5217 qp_init_attr->qp_context = ibqp->qp_context;
5219 qp_attr->cap.max_send_wr = 0;
5220 qp_attr->cap.max_send_sge = 0;
5223 qp_init_attr->qp_type = ibqp->qp_type;
5224 qp_init_attr->recv_cq = ibqp->recv_cq;
5225 qp_init_attr->send_cq = ibqp->send_cq;
5226 qp_init_attr->srq = ibqp->srq;
5227 qp_attr->cap.max_inline_data = qp->max_inline_data;
5229 qp_init_attr->cap = qp_attr->cap;
5231 qp_init_attr->create_flags = 0;
5232 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
5233 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
5235 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
5236 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
5237 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
5238 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
5239 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
5240 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
5241 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
5242 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
5244 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
5245 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
5248 mutex_unlock(&qp->mutex);
5252 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
5253 struct ib_ucontext *context,
5254 struct ib_udata *udata)
5256 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5257 struct mlx5_ib_xrcd *xrcd;
5260 if (!MLX5_CAP_GEN(dev->mdev, xrc))
5261 return ERR_PTR(-ENOSYS);
5263 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
5265 return ERR_PTR(-ENOMEM);
5267 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
5270 return ERR_PTR(-ENOMEM);
5273 return &xrcd->ibxrcd;
5276 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
5278 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
5279 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
5282 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
5284 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
5290 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
5292 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
5293 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
5294 struct ib_event event;
5296 if (rwq->ibwq.event_handler) {
5297 event.device = rwq->ibwq.device;
5298 event.element.wq = &rwq->ibwq;
5300 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
5301 event.event = IB_EVENT_WQ_FATAL;
5304 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
5308 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
5312 static int set_delay_drop(struct mlx5_ib_dev *dev)
5316 mutex_lock(&dev->delay_drop.lock);
5317 if (dev->delay_drop.activate)
5320 err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout);
5324 dev->delay_drop.activate = true;
5326 mutex_unlock(&dev->delay_drop.lock);
5329 atomic_inc(&dev->delay_drop.rqs_cnt);
5333 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
5334 struct ib_wq_init_attr *init_attr)
5336 struct mlx5_ib_dev *dev;
5337 int has_net_offloads;
5345 dev = to_mdev(pd->device);
5347 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
5348 in = kvzalloc(inlen, GFP_KERNEL);
5352 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
5353 MLX5_SET(rqc, rqc, mem_rq_type,
5354 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
5355 MLX5_SET(rqc, rqc, user_index, rwq->user_index);
5356 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
5357 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
5358 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
5359 wq = MLX5_ADDR_OF(rqc, rqc, wq);
5360 MLX5_SET(wq, wq, wq_type,
5361 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
5362 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
5363 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5364 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
5365 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n");
5369 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
5372 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
5373 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
5374 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
5375 MLX5_SET(wq, wq, log_wqe_stride_size,
5376 rwq->single_stride_log_num_of_bytes -
5377 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
5378 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides -
5379 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES);
5381 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
5382 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
5383 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
5384 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
5385 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
5386 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
5387 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
5388 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5389 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5390 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
5395 MLX5_SET(rqc, rqc, vsd, 1);
5397 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
5398 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
5399 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
5403 MLX5_SET(rqc, rqc, scatter_fcs, 1);
5405 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5406 if (!(dev->ib_dev.attrs.raw_packet_caps &
5407 IB_RAW_PACKET_CAP_DELAY_DROP)) {
5408 mlx5_ib_dbg(dev, "Delay drop is not supported\n");
5412 MLX5_SET(rqc, rqc, delay_drop_en, 1);
5414 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
5415 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
5416 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
5417 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5418 err = set_delay_drop(dev);
5420 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
5422 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5424 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
5432 static int set_user_rq_size(struct mlx5_ib_dev *dev,
5433 struct ib_wq_init_attr *wq_init_attr,
5434 struct mlx5_ib_create_wq *ucmd,
5435 struct mlx5_ib_rwq *rwq)
5437 /* Sanity check RQ size before proceeding */
5438 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
5441 if (!ucmd->rq_wqe_count)
5444 rwq->wqe_count = ucmd->rq_wqe_count;
5445 rwq->wqe_shift = ucmd->rq_wqe_shift;
5446 if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size))
5449 rwq->log_rq_stride = rwq->wqe_shift;
5450 rwq->log_rq_size = ilog2(rwq->wqe_count);
5454 static int prepare_user_rq(struct ib_pd *pd,
5455 struct ib_wq_init_attr *init_attr,
5456 struct ib_udata *udata,
5457 struct mlx5_ib_rwq *rwq)
5459 struct mlx5_ib_dev *dev = to_mdev(pd->device);
5460 struct mlx5_ib_create_wq ucmd = {};
5462 size_t required_cmd_sz;
5464 required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes)
5465 + sizeof(ucmd.single_stride_log_num_of_bytes);
5466 if (udata->inlen < required_cmd_sz) {
5467 mlx5_ib_dbg(dev, "invalid inlen\n");
5471 if (udata->inlen > sizeof(ucmd) &&
5472 !ib_is_udata_cleared(udata, sizeof(ucmd),
5473 udata->inlen - sizeof(ucmd))) {
5474 mlx5_ib_dbg(dev, "inlen is not supported\n");
5478 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
5479 mlx5_ib_dbg(dev, "copy failed\n");
5483 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
5484 mlx5_ib_dbg(dev, "invalid comp mask\n");
5486 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
5487 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
5488 mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
5491 if ((ucmd.single_stride_log_num_of_bytes <
5492 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
5493 (ucmd.single_stride_log_num_of_bytes >
5494 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
5495 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
5496 ucmd.single_stride_log_num_of_bytes,
5497 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
5498 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
5501 if ((ucmd.single_wqe_log_num_of_strides >
5502 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
5503 (ucmd.single_wqe_log_num_of_strides <
5504 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) {
5505 mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n",
5506 ucmd.single_wqe_log_num_of_strides,
5507 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
5508 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
5511 rwq->single_stride_log_num_of_bytes =
5512 ucmd.single_stride_log_num_of_bytes;
5513 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
5514 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
5515 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
5518 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
5520 mlx5_ib_dbg(dev, "err %d\n", err);
5524 err = create_user_rq(dev, pd, rwq, &ucmd);
5526 mlx5_ib_dbg(dev, "err %d\n", err);
5531 rwq->user_index = ucmd.user_index;
5535 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
5536 struct ib_wq_init_attr *init_attr,
5537 struct ib_udata *udata)
5539 struct mlx5_ib_dev *dev;
5540 struct mlx5_ib_rwq *rwq;
5541 struct mlx5_ib_create_wq_resp resp = {};
5542 size_t min_resp_len;
5546 return ERR_PTR(-ENOSYS);
5548 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5549 if (udata->outlen && udata->outlen < min_resp_len)
5550 return ERR_PTR(-EINVAL);
5552 if (!capable(CAP_SYS_RAWIO) &&
5553 init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP)
5554 return ERR_PTR(-EPERM);
5556 dev = to_mdev(pd->device);
5557 switch (init_attr->wq_type) {
5559 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
5561 return ERR_PTR(-ENOMEM);
5562 err = prepare_user_rq(pd, init_attr, udata, rwq);
5565 err = create_rq(rwq, pd, init_attr);
5570 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
5571 init_attr->wq_type);
5572 return ERR_PTR(-EINVAL);
5575 rwq->ibwq.wq_num = rwq->core_qp.qpn;
5576 rwq->ibwq.state = IB_WQS_RESET;
5577 if (udata->outlen) {
5578 resp.response_length = offsetof(typeof(resp), response_length) +
5579 sizeof(resp.response_length);
5580 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5585 rwq->core_qp.event = mlx5_ib_wq_event;
5586 rwq->ibwq.event_handler = init_attr->event_handler;
5590 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5592 destroy_user_rq(dev, pd, rwq);
5595 return ERR_PTR(err);
5598 int mlx5_ib_destroy_wq(struct ib_wq *wq)
5600 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5601 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5603 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5604 destroy_user_rq(dev, wq->pd, rwq);
5610 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
5611 struct ib_rwq_ind_table_init_attr *init_attr,
5612 struct ib_udata *udata)
5614 struct mlx5_ib_dev *dev = to_mdev(device);
5615 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
5616 int sz = 1 << init_attr->log_ind_tbl_size;
5617 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
5618 size_t min_resp_len;
5625 if (udata->inlen > 0 &&
5626 !ib_is_udata_cleared(udata, 0,
5628 return ERR_PTR(-EOPNOTSUPP);
5630 if (init_attr->log_ind_tbl_size >
5631 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
5632 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
5633 init_attr->log_ind_tbl_size,
5634 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
5635 return ERR_PTR(-EINVAL);
5638 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5639 if (udata->outlen && udata->outlen < min_resp_len)
5640 return ERR_PTR(-EINVAL);
5642 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
5644 return ERR_PTR(-ENOMEM);
5646 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
5647 in = kvzalloc(inlen, GFP_KERNEL);
5653 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
5655 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5656 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
5658 for (i = 0; i < sz; i++)
5659 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
5661 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
5667 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
5668 if (udata->outlen) {
5669 resp.response_length = offsetof(typeof(resp), response_length) +
5670 sizeof(resp.response_length);
5671 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5676 return &rwq_ind_tbl->ib_rwq_ind_tbl;
5679 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
5682 return ERR_PTR(err);
5685 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
5687 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
5688 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
5690 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
5696 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
5697 u32 wq_attr_mask, struct ib_udata *udata)
5699 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5700 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5701 struct mlx5_ib_modify_wq ucmd = {};
5702 size_t required_cmd_sz;
5710 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
5711 if (udata->inlen < required_cmd_sz)
5714 if (udata->inlen > sizeof(ucmd) &&
5715 !ib_is_udata_cleared(udata, sizeof(ucmd),
5716 udata->inlen - sizeof(ucmd)))
5719 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
5722 if (ucmd.comp_mask || ucmd.reserved)
5725 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
5726 in = kvzalloc(inlen, GFP_KERNEL);
5730 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
5732 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
5733 wq_attr->curr_wq_state : wq->state;
5734 wq_state = (wq_attr_mask & IB_WQ_STATE) ?
5735 wq_attr->wq_state : curr_wq_state;
5736 if (curr_wq_state == IB_WQS_ERR)
5737 curr_wq_state = MLX5_RQC_STATE_ERR;
5738 if (wq_state == IB_WQS_ERR)
5739 wq_state = MLX5_RQC_STATE_ERR;
5740 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
5741 MLX5_SET(rqc, rqc, state, wq_state);
5743 if (wq_attr_mask & IB_WQ_FLAGS) {
5744 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5745 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
5746 MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5747 mlx5_ib_dbg(dev, "VLAN offloads are not "
5752 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5753 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
5754 MLX5_SET(rqc, rqc, vsd,
5755 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
5758 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5759 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n");
5765 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
5766 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
5767 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5768 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
5769 MLX5_SET(rqc, rqc, counter_set_id,
5770 dev->port->cnts.set_id);
5772 pr_info_once("%s: Receive WQ counters are not supported on current FW\n",
5776 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
5778 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
5785 struct mlx5_ib_drain_cqe {
5787 struct completion done;
5790 static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
5792 struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
5793 struct mlx5_ib_drain_cqe,
5796 complete(&cqe->done);
5799 /* This function returns only once the drained WR was completed */
5800 static void handle_drain_completion(struct ib_cq *cq,
5801 struct mlx5_ib_drain_cqe *sdrain,
5802 struct mlx5_ib_dev *dev)
5804 struct mlx5_core_dev *mdev = dev->mdev;
5806 if (cq->poll_ctx == IB_POLL_DIRECT) {
5807 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
5808 ib_process_cq_direct(cq, -1);
5812 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5813 struct mlx5_ib_cq *mcq = to_mcq(cq);
5814 bool triggered = false;
5815 unsigned long flags;
5817 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
5818 /* Make sure that the CQ handler won't run if wasn't run yet */
5819 if (!mcq->mcq.reset_notify_added)
5820 mcq->mcq.reset_notify_added = 1;
5823 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
5826 /* Wait for any scheduled/running task to be ended */
5827 switch (cq->poll_ctx) {
5828 case IB_POLL_SOFTIRQ:
5829 irq_poll_disable(&cq->iop);
5830 irq_poll_enable(&cq->iop);
5832 case IB_POLL_WORKQUEUE:
5833 cancel_work_sync(&cq->work);
5840 /* Run the CQ handler - this makes sure that the drain WR will
5841 * be processed if wasn't processed yet.
5843 mcq->mcq.comp(&mcq->mcq);
5846 wait_for_completion(&sdrain->done);
5849 void mlx5_ib_drain_sq(struct ib_qp *qp)
5851 struct ib_cq *cq = qp->send_cq;
5852 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
5853 struct mlx5_ib_drain_cqe sdrain;
5854 const struct ib_send_wr *bad_swr;
5855 struct ib_rdma_wr swr = {
5858 { .wr_cqe = &sdrain.cqe, },
5859 .opcode = IB_WR_RDMA_WRITE,
5863 struct mlx5_ib_dev *dev = to_mdev(qp->device);
5864 struct mlx5_core_dev *mdev = dev->mdev;
5866 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
5867 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5868 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
5872 sdrain.cqe.done = mlx5_ib_drain_qp_done;
5873 init_completion(&sdrain.done);
5875 ret = _mlx5_ib_post_send(qp, &swr.wr, &bad_swr, true);
5877 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
5881 handle_drain_completion(cq, &sdrain, dev);
5884 void mlx5_ib_drain_rq(struct ib_qp *qp)
5886 struct ib_cq *cq = qp->recv_cq;
5887 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
5888 struct mlx5_ib_drain_cqe rdrain;
5889 struct ib_recv_wr rwr = {};
5890 const struct ib_recv_wr *bad_rwr;
5892 struct mlx5_ib_dev *dev = to_mdev(qp->device);
5893 struct mlx5_core_dev *mdev = dev->mdev;
5895 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
5896 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5897 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
5901 rwr.wr_cqe = &rdrain.cqe;
5902 rdrain.cqe.done = mlx5_ib_drain_qp_done;
5903 init_completion(&rdrain.done);
5905 ret = _mlx5_ib_post_recv(qp, &rwr, &bad_rwr, true);
5907 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
5911 handle_drain_completion(cq, &rdrain, dev);