drivers/infiniband/hw/mlx5/qp.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34 #include <rdma/ib_umem.h>
  35 #include <rdma/ib_cache.h>
  36 #include <rdma/ib_user_verbs.h>
  37 #include "mlx5_ib.h"
  38
  39 /* not supported currently */
  40 static int wq_signature;
  41
  42 enum {
  43         MLX5_IB_ACK_REQ_FREQ    = 8,
  44 };
  45
  46 enum {
  47         MLX5_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  48         MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  49         MLX5_IB_LINK_TYPE_IB            = 0,
  50         MLX5_IB_LINK_TYPE_ETH           = 1
  51 };
  52
  53 enum {
  54         MLX5_IB_SQ_STRIDE       = 6,
  55 };
  56
  57 static const u32 mlx5_ib_opcode[] = {
  58         [IB_WR_SEND]                            = MLX5_OPCODE_SEND,
  59         [IB_WR_LSO]                             = MLX5_OPCODE_LSO,
  60         [IB_WR_SEND_WITH_IMM]                   = MLX5_OPCODE_SEND_IMM,
  61         [IB_WR_RDMA_WRITE]                      = MLX5_OPCODE_RDMA_WRITE,
  62         [IB_WR_RDMA_WRITE_WITH_IMM]             = MLX5_OPCODE_RDMA_WRITE_IMM,
  63         [IB_WR_RDMA_READ]                       = MLX5_OPCODE_RDMA_READ,
  64         [IB_WR_ATOMIC_CMP_AND_SWP]              = MLX5_OPCODE_ATOMIC_CS,
  65         [IB_WR_ATOMIC_FETCH_AND_ADD]            = MLX5_OPCODE_ATOMIC_FA,
  66         [IB_WR_SEND_WITH_INV]                   = MLX5_OPCODE_SEND_INVAL,
  67         [IB_WR_LOCAL_INV]                       = MLX5_OPCODE_UMR,
  68         [IB_WR_REG_MR]                          = MLX5_OPCODE_UMR,
  69         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = MLX5_OPCODE_ATOMIC_MASKED_CS,
  70         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = MLX5_OPCODE_ATOMIC_MASKED_FA,
  71         [MLX5_IB_WR_UMR]                        = MLX5_OPCODE_UMR,
  72 };
  73
  74 struct mlx5_wqe_eth_pad {
  75         u8 rsvd0[16];
  76 };
  77
  78 enum raw_qp_set_mask_map {
  79         MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID         = 1UL << 0,
  80 };
  81
  82 struct mlx5_modify_raw_qp_param {
  83         u16 operation;
  84
  85         u32 set_mask; /* raw_qp_set_mask_map */
  86         u8 rq_q_ctr_id;
  87 };
  88
  89 static void get_cqs(enum ib_qp_type qp_type,
  90                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
  91                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
  92
  93 static int is_qp0(enum ib_qp_type qp_type)
  94 {
  95         return qp_type == IB_QPT_SMI;
  96 }
  97
  98 static int is_sqp(enum ib_qp_type qp_type)
  99 {
 100         return is_qp0(qp_type) || is_qp1(qp_type);
 101 }
 102
 103 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
 104 {
 105         return mlx5_buf_offset(&qp->buf, offset);
 106 }
 107
 108 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
 109 {
 110         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 111 }
 112
 113 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
 114 {
 115         return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
 116 }
 117
 118 /**
 119  * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
 120  *
 121  * @qp: QP to copy from.
 122  * @send: copy from the send queue when non-zero, use the receive queue
 123  *        otherwise.
 124  * @wqe_index:  index to start copying from. For send work queues, the
 125  *              wqe_index is in units of MLX5_SEND_WQE_BB.
 126  *              For receive work queue, it is the number of work queue
 127  *              element in the queue.
 128  * @buffer: destination buffer.
 129  * @length: maximum number of bytes to copy.
 130  *
 131  * Copies at least a single WQE, but may copy more data.
 132  *
 133  * Return: the number of bytes copied, or an error code.
 134  */
 135 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
 136                           void *buffer, u32 length,
 137                           struct mlx5_ib_qp_base *base)
 138 {
 139         struct ib_device *ibdev = qp->ibqp.device;
 140         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 141         struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
 142         size_t offset;
 143         size_t wq_end;
 144         struct ib_umem *umem = base->ubuffer.umem;
 145         u32 first_copy_length;
 146         int wqe_length;
 147         int ret;
 148
 149         if (wq->wqe_cnt == 0) {
 150                 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
 151                             qp->ibqp.qp_type);
 152                 return -EINVAL;
 153         }
 154
 155         offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
 156         wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
 157
 158         if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
 159                 return -EINVAL;
 160
 161         if (offset > umem->length ||
 162             (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
 163                 return -EINVAL;
 164
 165         first_copy_length = min_t(u32, offset + length, wq_end) - offset;
 166         ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
 167         if (ret)
 168                 return ret;
 169
 170         if (send) {
 171                 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
 172                 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
 173
 174                 wqe_length = ds * MLX5_WQE_DS_UNITS;
 175         } else {
 176                 wqe_length = 1 << wq->wqe_shift;
 177         }
 178
 179         if (wqe_length <= first_copy_length)
 180                 return first_copy_length;
 181
 182         ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
 183                                 wqe_length - first_copy_length);
 184         if (ret)
 185                 return ret;
 186
 187         return wqe_length;
 188 }
 189
 190 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
 191 {
 192         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 193         struct ib_event event;
 194
 195         if (type == MLX5_EVENT_TYPE_PATH_MIG) {
 196                 /* This event is only valid for trans_qps */
 197                 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
 198         }
 199
 200         if (ibqp->event_handler) {
 201                 event.device     = ibqp->device;
 202                 event.element.qp = ibqp;
 203                 switch (type) {
 204                 case MLX5_EVENT_TYPE_PATH_MIG:
 205                         event.event = IB_EVENT_PATH_MIG;
 206                         break;
 207                 case MLX5_EVENT_TYPE_COMM_EST:
 208                         event.event = IB_EVENT_COMM_EST;
 209                         break;
 210                 case MLX5_EVENT_TYPE_SQ_DRAINED:
 211                         event.event = IB_EVENT_SQ_DRAINED;
 212                         break;
 213                 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 214                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 215                         break;
 216                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 217                         event.event = IB_EVENT_QP_FATAL;
 218                         break;
 219                 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 220                         event.event = IB_EVENT_PATH_MIG_ERR;
 221                         break;
 222                 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 223                         event.event = IB_EVENT_QP_REQ_ERR;
 224                         break;
 225                 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 226                         event.event = IB_EVENT_QP_ACCESS_ERR;
 227                         break;
 228                 default:
 229                         pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
 230                         return;
 231                 }
 232
 233                 ibqp->event_handler(&event, ibqp->qp_context);
 234         }
 235 }
 236
 237 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
 238                        int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
 239 {
 240         int wqe_size;
 241         int wq_size;
 242
 243         /* Sanity check RQ size before proceeding */
 244         if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
 245                 return -EINVAL;
 246
 247         if (!has_rq) {
 248                 qp->rq.max_gs = 0;
 249                 qp->rq.wqe_cnt = 0;
 250                 qp->rq.wqe_shift = 0;
 251                 cap->max_recv_wr = 0;
 252                 cap->max_recv_sge = 0;
 253         } else {
 254                 if (ucmd) {
 255                         qp->rq.wqe_cnt = ucmd->rq_wqe_count;
 256                         if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift))
 257                                 return -EINVAL;
 258                         qp->rq.wqe_shift = ucmd->rq_wqe_shift;
 259                         if ((1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) < qp->wq_sig)
 260                                 return -EINVAL;
 261                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 262                         qp->rq.max_post = qp->rq.wqe_cnt;
 263                 } else {
 264                         wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
 265                         wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
 266                         wqe_size = roundup_pow_of_two(wqe_size);
 267                         wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
 268                         wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
 269                         qp->rq.wqe_cnt = wq_size / wqe_size;
 270                         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
 271                                 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
 272                                             wqe_size,
 273                                             MLX5_CAP_GEN(dev->mdev,
 274                                                          max_wqe_sz_rq));
 275                                 return -EINVAL;
 276                         }
 277                         qp->rq.wqe_shift = ilog2(wqe_size);
 278                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 279                         qp->rq.max_post = qp->rq.wqe_cnt;
 280                 }
 281         }
 282
 283         return 0;
 284 }
 285
 286 static int sq_overhead(struct ib_qp_init_attr *attr)
 287 {
 288         int size = 0;
 289
 290         switch (attr->qp_type) {
 291         case IB_QPT_XRC_INI:
 292                 size += sizeof(struct mlx5_wqe_xrc_seg);
 293                 /* fall through */
 294         case IB_QPT_RC:
 295                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 296                         max(sizeof(struct mlx5_wqe_atomic_seg) +
 297                             sizeof(struct mlx5_wqe_raddr_seg),
 298                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 299                             sizeof(struct mlx5_mkey_seg));
 300                 break;
 301
 302         case IB_QPT_XRC_TGT:
 303                 return 0;
 304
 305         case IB_QPT_UC:
 306                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 307                         max(sizeof(struct mlx5_wqe_raddr_seg),
 308                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 309                             sizeof(struct mlx5_mkey_seg));
 310                 break;
 311
 312         case IB_QPT_UD:
 313                 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 314                         size += sizeof(struct mlx5_wqe_eth_pad) +
 315                                 sizeof(struct mlx5_wqe_eth_seg);
 316                 /* fall through */
 317         case IB_QPT_SMI:
 318         case MLX5_IB_QPT_HW_GSI:
 319                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 320                         sizeof(struct mlx5_wqe_datagram_seg);
 321                 break;
 322
 323         case MLX5_IB_QPT_REG_UMR:
 324                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 325                         sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 326                         sizeof(struct mlx5_mkey_seg);
 327                 break;
 328
 329         default:
 330                 return -EINVAL;
 331         }
 332
 333         return size;
 334 }
 335
 336 static int calc_send_wqe(struct ib_qp_init_attr *attr)
 337 {
 338         int inl_size = 0;
 339         int size;
 340
 341         size = sq_overhead(attr);
 342         if (size < 0)
 343                 return size;
 344
 345         if (attr->cap.max_inline_data) {
 346                 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
 347                         attr->cap.max_inline_data;
 348         }
 349
 350         size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
 351         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
 352             ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
 353                         return MLX5_SIG_WQE_SIZE;
 354         else
 355                 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
 356 }
 357
 358 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
 359 {
 360         int max_sge;
 361
 362         if (attr->qp_type == IB_QPT_RC)
 363                 max_sge = (min_t(int, wqe_size, 512) -
 364                            sizeof(struct mlx5_wqe_ctrl_seg) -
 365                            sizeof(struct mlx5_wqe_raddr_seg)) /
 366                         sizeof(struct mlx5_wqe_data_seg);
 367         else if (attr->qp_type == IB_QPT_XRC_INI)
 368                 max_sge = (min_t(int, wqe_size, 512) -
 369                            sizeof(struct mlx5_wqe_ctrl_seg) -
 370                            sizeof(struct mlx5_wqe_xrc_seg) -
 371                            sizeof(struct mlx5_wqe_raddr_seg)) /
 372                         sizeof(struct mlx5_wqe_data_seg);
 373         else
 374                 max_sge = (wqe_size - sq_overhead(attr)) /
 375                         sizeof(struct mlx5_wqe_data_seg);
 376
 377         return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
 378                      sizeof(struct mlx5_wqe_data_seg));
 379 }
 380
 381 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
 382                         struct mlx5_ib_qp *qp)
 383 {
 384         int wqe_size;
 385         int wq_size;
 386
 387         if (!attr->cap.max_send_wr)
 388                 return 0;
 389
 390         wqe_size = calc_send_wqe(attr);
 391         mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
 392         if (wqe_size < 0)
 393                 return wqe_size;
 394
 395         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 396                 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
 397                             wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 398                 return -EINVAL;
 399         }
 400
 401         qp->max_inline_data = wqe_size - sq_overhead(attr) -
 402                               sizeof(struct mlx5_wqe_inline_seg);
 403         attr->cap.max_inline_data = qp->max_inline_data;
 404
 405         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
 406                 qp->signature_en = true;
 407
 408         wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
 409         qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
 410         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 411                 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n",
 412                             qp->sq.wqe_cnt,
 413                             1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 414                 return -ENOMEM;
 415         }
 416         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 417         qp->sq.max_gs = get_send_sge(attr, wqe_size);
 418         if (qp->sq.max_gs < attr->cap.max_send_sge)
 419                 return -ENOMEM;
 420
 421         attr->cap.max_send_sge = qp->sq.max_gs;
 422         qp->sq.max_post = wq_size / wqe_size;
 423         attr->cap.max_send_wr = qp->sq.max_post;
 424
 425         return wq_size;
 426 }
 427
 428 static int set_user_buf_size(struct mlx5_ib_dev *dev,
 429                             struct mlx5_ib_qp *qp,
 430                             struct mlx5_ib_create_qp *ucmd,
 431                             struct mlx5_ib_qp_base *base,
 432                             struct ib_qp_init_attr *attr)
 433 {
 434         int desc_sz = 1 << qp->sq.wqe_shift;
 435
 436         if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 437                 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
 438                              desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 439                 return -EINVAL;
 440         }
 441
 442         if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
 443                 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
 444                              ucmd->sq_wqe_count, ucmd->sq_wqe_count);
 445                 return -EINVAL;
 446         }
 447
 448         qp->sq.wqe_cnt = ucmd->sq_wqe_count;
 449
 450         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 451                 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
 452                              qp->sq.wqe_cnt,
 453                              1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 454                 return -EINVAL;
 455         }
 456
 457         if (attr->qp_type == IB_QPT_RAW_PACKET) {
 458                 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 459                 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
 460         } else {
 461                 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 462                                          (qp->sq.wqe_cnt << 6);
 463         }
 464
 465         return 0;
 466 }
 467
 468 static int qp_has_rq(struct ib_qp_init_attr *attr)
 469 {
 470         if (attr->qp_type == IB_QPT_XRC_INI ||
 471             attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
 472             attr->qp_type == MLX5_IB_QPT_REG_UMR ||
 473             !attr->cap.max_recv_wr)
 474                 return 0;
 475
 476         return 1;
 477 }
 478
 479 static int first_med_uuar(void)
 480 {
 481         return 1;
 482 }
 483
 484 static int next_uuar(int n)
 485 {
 486         n++;
 487
 488         while (((n % 4) & 2))
 489                 n++;
 490
 491         return n;
 492 }
 493
 494 static int num_med_uuar(struct mlx5_uuar_info *uuari)
 495 {
 496         int n;
 497
 498         n = uuari->num_uars * MLX5_NON_FP_BF_REGS_PER_PAGE -
 499                 uuari->num_low_latency_uuars - 1;
 500
 501         return n >= 0 ? n : 0;
 502 }
 503
 504 static int max_uuari(struct mlx5_uuar_info *uuari)
 505 {
 506         return uuari->num_uars * 4;
 507 }
 508
 509 static int first_hi_uuar(struct mlx5_uuar_info *uuari)
 510 {
 511         int med;
 512         int i;
 513         int t;
 514
 515         med = num_med_uuar(uuari);
 516         for (t = 0, i = first_med_uuar();; i = next_uuar(i)) {
 517                 t++;
 518                 if (t == med)
 519                         return next_uuar(i);
 520         }
 521
 522         return 0;
 523 }
 524
 525 static int alloc_high_class_uuar(struct mlx5_uuar_info *uuari)
 526 {
 527         int i;
 528
 529         for (i = first_hi_uuar(uuari); i < max_uuari(uuari); i = next_uuar(i)) {
 530                 if (!test_bit(i, uuari->bitmap)) {
 531                         set_bit(i, uuari->bitmap);
 532                         uuari->count[i]++;
 533                         return i;
 534                 }
 535         }
 536
 537         return -ENOMEM;
 538 }
 539
 540 static int alloc_med_class_uuar(struct mlx5_uuar_info *uuari)
 541 {
 542         int minidx = first_med_uuar();
 543         int i;
 544
 545         for (i = first_med_uuar(); i < first_hi_uuar(uuari); i = next_uuar(i)) {
 546                 if (uuari->count[i] < uuari->count[minidx])
 547                         minidx = i;
 548         }
 549
 550         uuari->count[minidx]++;
 551         return minidx;
 552 }
 553
 554 static int alloc_uuar(struct mlx5_uuar_info *uuari,
 555                       enum mlx5_ib_latency_class lat)
 556 {
 557         int uuarn = -EINVAL;
 558
 559         mutex_lock(&uuari->lock);
 560         switch (lat) {
 561         case MLX5_IB_LATENCY_CLASS_LOW:
 562                 uuarn = 0;
 563                 uuari->count[uuarn]++;
 564                 break;
 565
 566         case MLX5_IB_LATENCY_CLASS_MEDIUM:
 567                 if (uuari->ver < 2)
 568                         uuarn = -ENOMEM;
 569                 else
 570                         uuarn = alloc_med_class_uuar(uuari);
 571                 break;
 572
 573         case MLX5_IB_LATENCY_CLASS_HIGH:
 574                 if (uuari->ver < 2)
 575                         uuarn = -ENOMEM;
 576                 else
 577                         uuarn = alloc_high_class_uuar(uuari);
 578                 break;
 579
 580         case MLX5_IB_LATENCY_CLASS_FAST_PATH:
 581                 uuarn = 2;
 582                 break;
 583         }
 584         mutex_unlock(&uuari->lock);
 585
 586         return uuarn;
 587 }
 588
 589 static void free_med_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
 590 {
 591         clear_bit(uuarn, uuari->bitmap);
 592         --uuari->count[uuarn];
 593 }
 594
 595 static void free_high_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
 596 {
 597         clear_bit(uuarn, uuari->bitmap);
 598         --uuari->count[uuarn];
 599 }
 600
 601 static void free_uuar(struct mlx5_uuar_info *uuari, int uuarn)
 602 {
 603         int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE;
 604         int high_uuar = nuuars - uuari->num_low_latency_uuars;
 605
 606         mutex_lock(&uuari->lock);
 607         if (uuarn == 0) {
 608                 --uuari->count[uuarn];
 609                 goto out;
 610         }
 611
 612         if (uuarn < high_uuar) {
 613                 free_med_class_uuar(uuari, uuarn);
 614                 goto out;
 615         }
 616
 617         free_high_class_uuar(uuari, uuarn);
 618
 619 out:
 620         mutex_unlock(&uuari->lock);
 621 }
 622
 623 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
 624 {
 625         switch (state) {
 626         case IB_QPS_RESET:      return MLX5_QP_STATE_RST;
 627         case IB_QPS_INIT:       return MLX5_QP_STATE_INIT;
 628         case IB_QPS_RTR:        return MLX5_QP_STATE_RTR;
 629         case IB_QPS_RTS:        return MLX5_QP_STATE_RTS;
 630         case IB_QPS_SQD:        return MLX5_QP_STATE_SQD;
 631         case IB_QPS_SQE:        return MLX5_QP_STATE_SQER;
 632         case IB_QPS_ERR:        return MLX5_QP_STATE_ERR;
 633         default:                return -1;
 634         }
 635 }
 636
 637 static int to_mlx5_st(enum ib_qp_type type)
 638 {
 639         switch (type) {
 640         case IB_QPT_RC:                 return MLX5_QP_ST_RC;
 641         case IB_QPT_UC:                 return MLX5_QP_ST_UC;
 642         case IB_QPT_UD:                 return MLX5_QP_ST_UD;
 643         case MLX5_IB_QPT_REG_UMR:       return MLX5_QP_ST_REG_UMR;
 644         case IB_QPT_XRC_INI:
 645         case IB_QPT_XRC_TGT:            return MLX5_QP_ST_XRC;
 646         case IB_QPT_SMI:                return MLX5_QP_ST_QP0;
 647         case MLX5_IB_QPT_HW_GSI:        return MLX5_QP_ST_QP1;
 648         case IB_QPT_RAW_IPV6:           return MLX5_QP_ST_RAW_IPV6;
 649         case IB_QPT_RAW_PACKET:
 650         case IB_QPT_RAW_ETHERTYPE:      return MLX5_QP_ST_RAW_ETHERTYPE;
 651         case IB_QPT_MAX:
 652         default:                return -EINVAL;
 653         }
 654 }
 655
 656 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
 657                              struct mlx5_ib_cq *recv_cq);
 658 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
 659                                struct mlx5_ib_cq *recv_cq);
 660
 661 static int uuarn_to_uar_index(struct mlx5_uuar_info *uuari, int uuarn)
 662 {
 663         return uuari->uars[uuarn / MLX5_BF_REGS_PER_PAGE].index;
 664 }
 665
 666 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
 667                             struct ib_pd *pd,
 668                             unsigned long addr, size_t size,
 669                             struct ib_umem **umem,
 670                             int *npages, int *page_shift, int *ncont,
 671                             u32 *offset)
 672 {
 673         int err;
 674
 675         *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
 676         if (IS_ERR(*umem)) {
 677                 mlx5_ib_dbg(dev, "umem_get failed\n");
 678                 return PTR_ERR(*umem);
 679         }
 680
 681         mlx5_ib_cont_pages(*umem, addr, npages, page_shift, ncont, NULL);
 682
 683         err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
 684         if (err) {
 685                 mlx5_ib_warn(dev, "bad offset\n");
 686                 goto err_umem;
 687         }
 688
 689         mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
 690                     addr, size, *npages, *page_shift, *ncont, *offset);
 691
 692         return 0;
 693
 694 err_umem:
 695         ib_umem_release(*umem);
 696         *umem = NULL;
 697
 698         return err;
 699 }
 700
 701 static void destroy_user_rq(struct ib_pd *pd, struct mlx5_ib_rwq *rwq)
 702 {
 703         struct mlx5_ib_ucontext *context;
 704
 705         context = to_mucontext(pd->uobject->context);
 706         mlx5_ib_db_unmap_user(context, &rwq->db);
 707         if (rwq->umem)
 708                 ib_umem_release(rwq->umem);
 709 }
 710
 711 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 712                           struct mlx5_ib_rwq *rwq,
 713                           struct mlx5_ib_create_wq *ucmd)
 714 {
 715         struct mlx5_ib_ucontext *context;
 716         int page_shift = 0;
 717         int npages;
 718         u32 offset = 0;
 719         int ncont = 0;
 720         int err;
 721
 722         if (!ucmd->buf_addr)
 723                 return -EINVAL;
 724
 725         context = to_mucontext(pd->uobject->context);
 726         rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
 727                                rwq->buf_size, 0, 0);
 728         if (IS_ERR(rwq->umem)) {
 729                 mlx5_ib_dbg(dev, "umem_get failed\n");
 730                 err = PTR_ERR(rwq->umem);
 731                 return err;
 732         }
 733
 734         mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, &npages, &page_shift,
 735                            &ncont, NULL);
 736         err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
 737                                      &rwq->rq_page_offset);
 738         if (err) {
 739                 mlx5_ib_warn(dev, "bad offset\n");
 740                 goto err_umem;
 741         }
 742
 743         rwq->rq_num_pas = ncont;
 744         rwq->page_shift = page_shift;
 745         rwq->log_page_size =  page_shift - MLX5_ADAPTER_PAGE_SHIFT;
 746         rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
 747
 748         mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
 749                     (unsigned long long)ucmd->buf_addr, rwq->buf_size,
 750                     npages, page_shift, ncont, offset);
 751
 752         err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
 753         if (err) {
 754                 mlx5_ib_dbg(dev, "map failed\n");
 755                 goto err_umem;
 756         }
 757
 758         rwq->create_type = MLX5_WQ_USER;
 759         return 0;
 760
 761 err_umem:
 762         ib_umem_release(rwq->umem);
 763         return err;
 764 }
 765
 766 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 767                           struct mlx5_ib_qp *qp, struct ib_udata *udata,
 768                           struct ib_qp_init_attr *attr,
 769                           u32 **in,
 770                           struct mlx5_ib_create_qp_resp *resp, int *inlen,
 771                           struct mlx5_ib_qp_base *base)
 772 {
 773         struct mlx5_ib_ucontext *context;
 774         struct mlx5_ib_create_qp ucmd;
 775         struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
 776         int page_shift = 0;
 777         int uar_index;
 778         int npages;
 779         u32 offset = 0;
 780         int uuarn;
 781         int ncont = 0;
 782         __be64 *pas;
 783         void *qpc;
 784         int err;
 785
 786         err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
 787         if (err) {
 788                 mlx5_ib_dbg(dev, "copy failed\n");
 789                 return err;
 790         }
 791
 792         context = to_mucontext(pd->uobject->context);
 793         /*
 794          * TBD: should come from the verbs when we have the API
 795          */
 796         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
 797                 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
 798                 uuarn = MLX5_CROSS_CHANNEL_UUAR;
 799         else {
 800                 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_HIGH);
 801                 if (uuarn < 0) {
 802                         mlx5_ib_dbg(dev, "failed to allocate low latency UUAR\n");
 803                         mlx5_ib_dbg(dev, "reverting to medium latency\n");
 804                         uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_MEDIUM);
 805                         if (uuarn < 0) {
 806                                 mlx5_ib_dbg(dev, "failed to allocate medium latency UUAR\n");
 807                                 mlx5_ib_dbg(dev, "reverting to high latency\n");
 808                                 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_LOW);
 809                                 if (uuarn < 0) {
 810                                         mlx5_ib_warn(dev, "uuar allocation failed\n");
 811                                         return uuarn;
 812                                 }
 813                         }
 814                 }
 815         }
 816
 817         uar_index = uuarn_to_uar_index(&context->uuari, uuarn);
 818         mlx5_ib_dbg(dev, "uuarn 0x%x, uar_index 0x%x\n", uuarn, uar_index);
 819
 820         qp->rq.offset = 0;
 821         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 822         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 823
 824         err = set_user_buf_size(dev, qp, &ucmd, base, attr);
 825         if (err)
 826                 goto err_uuar;
 827
 828         if (ucmd.buf_addr && ubuffer->buf_size) {
 829                 ubuffer->buf_addr = ucmd.buf_addr;
 830                 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
 831                                        ubuffer->buf_size,
 832                                        &ubuffer->umem, &npages, &page_shift,
 833                                        &ncont, &offset);
 834                 if (err)
 835                         goto err_uuar;
 836         } else {
 837                 ubuffer->umem = NULL;
 838         }
 839
 840         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
 841                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
 842         *in = mlx5_vzalloc(*inlen);
 843         if (!*in) {
 844                 err = -ENOMEM;
 845                 goto err_umem;
 846         }
 847
 848         pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
 849         if (ubuffer->umem)
 850                 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
 851
 852         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
 853
 854         MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
 855         MLX5_SET(qpc, qpc, page_offset, offset);
 856
 857         MLX5_SET(qpc, qpc, uar_page, uar_index);
 858         resp->uuar_index = uuarn;
 859         qp->uuarn = uuarn;
 860
 861         err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
 862         if (err) {
 863                 mlx5_ib_dbg(dev, "map failed\n");
 864                 goto err_free;
 865         }
 866
 867         err = ib_copy_to_udata(udata, resp, sizeof(*resp));
 868         if (err) {
 869                 mlx5_ib_dbg(dev, "copy failed\n");
 870                 goto err_unmap;
 871         }
 872         qp->create_type = MLX5_QP_USER;
 873
 874         return 0;
 875
 876 err_unmap:
 877         mlx5_ib_db_unmap_user(context, &qp->db);
 878
 879 err_free:
 880         kvfree(*in);
 881
 882 err_umem:
 883         if (ubuffer->umem)
 884                 ib_umem_release(ubuffer->umem);
 885
 886 err_uuar:
 887         free_uuar(&context->uuari, uuarn);
 888         return err;
 889 }
 890
 891 static void destroy_qp_user(struct ib_pd *pd, struct mlx5_ib_qp *qp,
 892                             struct mlx5_ib_qp_base *base)
 893 {
 894         struct mlx5_ib_ucontext *context;
 895
 896         context = to_mucontext(pd->uobject->context);
 897         mlx5_ib_db_unmap_user(context, &qp->db);
 898         if (base->ubuffer.umem)
 899                 ib_umem_release(base->ubuffer.umem);
 900         free_uuar(&context->uuari, qp->uuarn);
 901 }
 902
 903 static int create_kernel_qp(struct mlx5_ib_dev *dev,
 904                             struct ib_qp_init_attr *init_attr,
 905                             struct mlx5_ib_qp *qp,
 906                             u32 **in, int *inlen,
 907                             struct mlx5_ib_qp_base *base)
 908 {
 909         enum mlx5_ib_latency_class lc = MLX5_IB_LATENCY_CLASS_LOW;
 910         struct mlx5_uuar_info *uuari;
 911         int uar_index;
 912         void *qpc;
 913         int uuarn;
 914         int err;
 915
 916         uuari = &dev->mdev->priv.uuari;
 917         if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
 918                                         IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
 919                                         IB_QP_CREATE_IPOIB_UD_LSO |
 920                                         mlx5_ib_create_qp_sqpn_qp1()))
 921                 return -EINVAL;
 922
 923         if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
 924                 lc = MLX5_IB_LATENCY_CLASS_FAST_PATH;
 925
 926         uuarn = alloc_uuar(uuari, lc);
 927         if (uuarn < 0) {
 928                 mlx5_ib_dbg(dev, "\n");
 929                 return -ENOMEM;
 930         }
 931
 932         qp->bf = &uuari->bfs[uuarn];
 933         uar_index = qp->bf->uar->index;
 934
 935         err = calc_sq_size(dev, init_attr, qp);
 936         if (err < 0) {
 937                 mlx5_ib_dbg(dev, "err %d\n", err);
 938                 goto err_uuar;
 939         }
 940
 941         qp->rq.offset = 0;
 942         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 943         base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
 944
 945         err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
 946         if (err) {
 947                 mlx5_ib_dbg(dev, "err %d\n", err);
 948                 goto err_uuar;
 949         }
 950
 951         qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
 952         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
 953                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
 954         *in = mlx5_vzalloc(*inlen);
 955         if (!*in) {
 956                 err = -ENOMEM;
 957                 goto err_buf;
 958         }
 959
 960         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
 961         MLX5_SET(qpc, qpc, uar_page, uar_index);
 962         MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
 963
 964         /* Set "fast registration enabled" for all kernel QPs */
 965         MLX5_SET(qpc, qpc, fre, 1);
 966         MLX5_SET(qpc, qpc, rlky, 1);
 967
 968         if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
 969                 MLX5_SET(qpc, qpc, deth_sqpn, 1);
 970                 qp->flags |= MLX5_IB_QP_SQPN_QP1;
 971         }
 972
 973         mlx5_fill_page_array(&qp->buf,
 974                              (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
 975
 976         err = mlx5_db_alloc(dev->mdev, &qp->db);
 977         if (err) {
 978                 mlx5_ib_dbg(dev, "err %d\n", err);
 979                 goto err_free;
 980         }
 981
 982         qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL);
 983         qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL);
 984         qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL);
 985         qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL);
 986         qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL);
 987
 988         if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
 989             !qp->sq.w_list || !qp->sq.wqe_head) {
 990                 err = -ENOMEM;
 991                 goto err_wrid;
 992         }
 993         qp->create_type = MLX5_QP_KERNEL;
 994
 995         return 0;
 996
 997 err_wrid:
 998         mlx5_db_free(dev->mdev, &qp->db);
 999         kfree(qp->sq.wqe_head);
1000         kfree(qp->sq.w_list);
1001         kfree(qp->sq.wrid);
1002         kfree(qp->sq.wr_data);
1003         kfree(qp->rq.wrid);
1004
1005 err_free:
1006         kvfree(*in);
1007
1008 err_buf:
1009         mlx5_buf_free(dev->mdev, &qp->buf);
1010
1011 err_uuar:
1012         free_uuar(&dev->mdev->priv.uuari, uuarn);
1013         return err;
1014 }
1015
1016 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1017 {
1018         mlx5_db_free(dev->mdev, &qp->db);
1019         kfree(qp->sq.wqe_head);
1020         kfree(qp->sq.w_list);
1021         kfree(qp->sq.wrid);
1022         kfree(qp->sq.wr_data);
1023         kfree(qp->rq.wrid);
1024         mlx5_buf_free(dev->mdev, &qp->buf);
1025         free_uuar(&dev->mdev->priv.uuari, qp->bf->uuarn);
1026 }
1027
1028 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
1029 {
1030         if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1031             (attr->qp_type == IB_QPT_XRC_INI))
1032                 return MLX5_SRQ_RQ;
1033         else if (!qp->has_rq)
1034                 return MLX5_ZERO_LEN_RQ;
1035         else
1036                 return MLX5_NON_ZERO_RQ;
1037 }
1038
1039 static int is_connected(enum ib_qp_type qp_type)
1040 {
1041         if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1042                 return 1;
1043
1044         return 0;
1045 }
1046
1047 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1048                                     struct mlx5_ib_sq *sq, u32 tdn)
1049 {
1050         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1051         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1052
1053         MLX5_SET(tisc, tisc, transport_domain, tdn);
1054         return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1055 }
1056
1057 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1058                                       struct mlx5_ib_sq *sq)
1059 {
1060         mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1061 }
1062
1063 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1064                                    struct mlx5_ib_sq *sq, void *qpin,
1065                                    struct ib_pd *pd)
1066 {
1067         struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1068         __be64 *pas;
1069         void *in;
1070         void *sqc;
1071         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1072         void *wq;
1073         int inlen;
1074         int err;
1075         int page_shift = 0;
1076         int npages;
1077         int ncont = 0;
1078         u32 offset = 0;
1079
1080         err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1081                                &sq->ubuffer.umem, &npages, &page_shift,
1082                                &ncont, &offset);
1083         if (err)
1084                 return err;
1085
1086         inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1087         in = mlx5_vzalloc(inlen);
1088         if (!in) {
1089                 err = -ENOMEM;
1090                 goto err_umem;
1091         }
1092
1093         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1094         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1095         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1096         MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1097         MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1098         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1099         MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1100
1101         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1102         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1103         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1104         MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1105         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1106         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1107         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1108         MLX5_SET(wq, wq, log_wq_pg_sz,  page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1109         MLX5_SET(wq, wq, page_offset, offset);
1110
1111         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1112         mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1113
1114         err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1115
1116         kvfree(in);
1117
1118         if (err)
1119                 goto err_umem;
1120
1121         return 0;
1122
1123 err_umem:
1124         ib_umem_release(sq->ubuffer.umem);
1125         sq->ubuffer.umem = NULL;
1126
1127         return err;
1128 }
1129
1130 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1131                                      struct mlx5_ib_sq *sq)
1132 {
1133         mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1134         ib_umem_release(sq->ubuffer.umem);
1135 }
1136
1137 static size_t get_rq_pas_size(void *qpc)
1138 {
1139         u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1140         u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1141         u32 log_rq_size   = MLX5_GET(qpc, qpc, log_rq_size);
1142         u32 page_offset   = MLX5_GET(qpc, qpc, page_offset);
1143         u32 po_quanta     = 1 << (log_page_size - 6);
1144         u32 rq_sz         = 1 << (log_rq_size + 4 + log_rq_stride);
1145         u32 page_size     = 1 << log_page_size;
1146         u32 rq_sz_po      = rq_sz + (page_offset * po_quanta);
1147         u32 rq_num_pas    = (rq_sz_po + page_size - 1) / page_size;
1148
1149         return rq_num_pas * sizeof(u64);
1150 }
1151
1152 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1153                                    struct mlx5_ib_rq *rq, void *qpin,
1154                                    size_t qpinlen)
1155 {
1156         struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1157         __be64 *pas;
1158         __be64 *qp_pas;
1159         void *in;
1160         void *rqc;
1161         void *wq;
1162         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1163         size_t rq_pas_size = get_rq_pas_size(qpc);
1164         size_t inlen;
1165         int err;
1166
1167         if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas))
1168                 return -EINVAL;
1169
1170         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1171         in = mlx5_vzalloc(inlen);
1172         if (!in)
1173                 return -ENOMEM;
1174
1175         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1176         MLX5_SET(rqc, rqc, vsd, 1);
1177         MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1178         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1179         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1180         MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1181         MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1182
1183         if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1184                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1185
1186         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1187         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1188         MLX5_SET(wq, wq, end_padding_mode,
1189                  MLX5_GET(qpc, qpc, end_padding_mode));
1190         MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1191         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1192         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1193         MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1194         MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1195         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1196
1197         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1198         qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1199         memcpy(pas, qp_pas, rq_pas_size);
1200
1201         err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1202
1203         kvfree(in);
1204
1205         return err;
1206 }
1207
1208 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1209                                      struct mlx5_ib_rq *rq)
1210 {
1211         mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1212 }
1213
1214 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1215                                     struct mlx5_ib_rq *rq, u32 tdn)
1216 {
1217         u32 *in;
1218         void *tirc;
1219         int inlen;
1220         int err;
1221
1222         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1223         in = mlx5_vzalloc(inlen);
1224         if (!in)
1225                 return -ENOMEM;
1226
1227         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1228         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1229         MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1230         MLX5_SET(tirc, tirc, transport_domain, tdn);
1231
1232         err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1233
1234         kvfree(in);
1235
1236         return err;
1237 }
1238
1239 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1240                                       struct mlx5_ib_rq *rq)
1241 {
1242         mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1243 }
1244
1245 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1246                                 u32 *in, size_t inlen,
1247                                 struct ib_pd *pd)
1248 {
1249         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1250         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1251         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1252         struct ib_uobject *uobj = pd->uobject;
1253         struct ib_ucontext *ucontext = uobj->context;
1254         struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1255         int err;
1256         u32 tdn = mucontext->tdn;
1257
1258         if (qp->sq.wqe_cnt) {
1259                 err = create_raw_packet_qp_tis(dev, sq, tdn);
1260                 if (err)
1261                         return err;
1262
1263                 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1264                 if (err)
1265                         goto err_destroy_tis;
1266
1267                 sq->base.container_mibqp = qp;
1268         }
1269
1270         if (qp->rq.wqe_cnt) {
1271                 rq->base.container_mibqp = qp;
1272
1273                 err = create_raw_packet_qp_rq(dev, rq, in, inlen);
1274                 if (err)
1275                         goto err_destroy_sq;
1276
1277
1278                 err = create_raw_packet_qp_tir(dev, rq, tdn);
1279                 if (err)
1280                         goto err_destroy_rq;
1281         }
1282
1283         qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1284                                                      rq->base.mqp.qpn;
1285
1286         return 0;
1287
1288 err_destroy_rq:
1289         destroy_raw_packet_qp_rq(dev, rq);
1290 err_destroy_sq:
1291         if (!qp->sq.wqe_cnt)
1292                 return err;
1293         destroy_raw_packet_qp_sq(dev, sq);
1294 err_destroy_tis:
1295         destroy_raw_packet_qp_tis(dev, sq);
1296
1297         return err;
1298 }
1299
1300 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1301                                   struct mlx5_ib_qp *qp)
1302 {
1303         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1304         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1305         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1306
1307         if (qp->rq.wqe_cnt) {
1308                 destroy_raw_packet_qp_tir(dev, rq);
1309                 destroy_raw_packet_qp_rq(dev, rq);
1310         }
1311
1312         if (qp->sq.wqe_cnt) {
1313                 destroy_raw_packet_qp_sq(dev, sq);
1314                 destroy_raw_packet_qp_tis(dev, sq);
1315         }
1316 }
1317
1318 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1319                                     struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1320 {
1321         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1322         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1323
1324         sq->sq = &qp->sq;
1325         rq->rq = &qp->rq;
1326         sq->doorbell = &qp->db;
1327         rq->doorbell = &qp->db;
1328 }
1329
1330 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1331 {
1332         mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1333 }
1334
1335 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1336                                  struct ib_pd *pd,
1337                                  struct ib_qp_init_attr *init_attr,
1338                                  struct ib_udata *udata)
1339 {
1340         struct ib_uobject *uobj = pd->uobject;
1341         struct ib_ucontext *ucontext = uobj->context;
1342         struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1343         struct mlx5_ib_create_qp_resp resp = {};
1344         int inlen;
1345         int err;
1346         u32 *in;
1347         void *tirc;
1348         void *hfso;
1349         u32 selected_fields = 0;
1350         size_t min_resp_len;
1351         u32 tdn = mucontext->tdn;
1352         struct mlx5_ib_create_qp_rss ucmd = {};
1353         size_t required_cmd_sz;
1354
1355         if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1356                 return -EOPNOTSUPP;
1357
1358         if (init_attr->create_flags || init_attr->send_cq)
1359                 return -EINVAL;
1360
1361         min_resp_len = offsetof(typeof(resp), uuar_index) + sizeof(resp.uuar_index);
1362         if (udata->outlen < min_resp_len)
1363                 return -EINVAL;
1364
1365         required_cmd_sz = offsetof(typeof(ucmd), reserved1) + sizeof(ucmd.reserved1);
1366         if (udata->inlen < required_cmd_sz) {
1367                 mlx5_ib_dbg(dev, "invalid inlen\n");
1368                 return -EINVAL;
1369         }
1370
1371         if (udata->inlen > sizeof(ucmd) &&
1372             !ib_is_udata_cleared(udata, sizeof(ucmd),
1373                                  udata->inlen - sizeof(ucmd))) {
1374                 mlx5_ib_dbg(dev, "inlen is not supported\n");
1375                 return -EOPNOTSUPP;
1376         }
1377
1378         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1379                 mlx5_ib_dbg(dev, "copy failed\n");
1380                 return -EFAULT;
1381         }
1382
1383         if (ucmd.comp_mask) {
1384                 mlx5_ib_dbg(dev, "invalid comp mask\n");
1385                 return -EOPNOTSUPP;
1386         }
1387
1388         if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)) || ucmd.reserved1) {
1389                 mlx5_ib_dbg(dev, "invalid reserved\n");
1390                 return -EOPNOTSUPP;
1391         }
1392
1393         err = ib_copy_to_udata(udata, &resp, min_resp_len);
1394         if (err) {
1395                 mlx5_ib_dbg(dev, "copy failed\n");
1396                 return -EINVAL;
1397         }
1398
1399         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1400         in = mlx5_vzalloc(inlen);
1401         if (!in)
1402                 return -ENOMEM;
1403
1404         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1405         MLX5_SET(tirc, tirc, disp_type,
1406                  MLX5_TIRC_DISP_TYPE_INDIRECT);
1407         MLX5_SET(tirc, tirc, indirect_table,
1408                  init_attr->rwq_ind_tbl->ind_tbl_num);
1409         MLX5_SET(tirc, tirc, transport_domain, tdn);
1410
1411         hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1412         switch (ucmd.rx_hash_function) {
1413         case MLX5_RX_HASH_FUNC_TOEPLITZ:
1414         {
1415                 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1416                 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1417
1418                 if (len != ucmd.rx_key_len) {
1419                         err = -EINVAL;
1420                         goto err;
1421                 }
1422
1423                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1424                 memcpy(rss_key, ucmd.rx_hash_key, len);
1425                 break;
1426         }
1427         default:
1428                 err = -EOPNOTSUPP;
1429                 goto err;
1430         }
1431
1432         if (!ucmd.rx_hash_fields_mask) {
1433                 /* special case when this TIR serves as steering entry without hashing */
1434                 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1435                         goto create_tir;
1436                 err = -EINVAL;
1437                 goto err;
1438         }
1439
1440         if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1441              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1442              ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1443              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1444                 err = -EINVAL;
1445                 goto err;
1446         }
1447
1448         /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1449         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1450             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1451                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1452                          MLX5_L3_PROT_TYPE_IPV4);
1453         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1454                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1455                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1456                          MLX5_L3_PROT_TYPE_IPV6);
1457
1458         if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1459              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) &&
1460              ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1461              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) {
1462                 err = -EINVAL;
1463                 goto err;
1464         }
1465
1466         /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1467         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1468             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1469                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1470                          MLX5_L4_PROT_TYPE_TCP);
1471         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1472                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1473                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1474                          MLX5_L4_PROT_TYPE_UDP);
1475
1476         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1477             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1478                 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1479
1480         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1481             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1482                 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1483
1484         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1485             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1486                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1487
1488         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1489             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1490                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1491
1492         MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1493
1494 create_tir:
1495         err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1496
1497         if (err)
1498                 goto err;
1499
1500         kvfree(in);
1501         /* qpn is reserved for that QP */
1502         qp->trans_qp.base.mqp.qpn = 0;
1503         qp->flags |= MLX5_IB_QP_RSS;
1504         return 0;
1505
1506 err:
1507         kvfree(in);
1508         return err;
1509 }
1510
1511 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1512                             struct ib_qp_init_attr *init_attr,
1513                             struct ib_udata *udata, struct mlx5_ib_qp *qp)
1514 {
1515         struct mlx5_ib_resources *devr = &dev->devr;
1516         int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1517         struct mlx5_core_dev *mdev = dev->mdev;
1518         struct mlx5_ib_create_qp_resp resp;
1519         struct mlx5_ib_cq *send_cq;
1520         struct mlx5_ib_cq *recv_cq;
1521         unsigned long flags;
1522         u32 uidx = MLX5_IB_DEFAULT_UIDX;
1523         struct mlx5_ib_create_qp ucmd;
1524         struct mlx5_ib_qp_base *base;
1525         int mlx5_st;
1526         void *qpc;
1527         u32 *in;
1528         int err;
1529
1530         base = init_attr->qp_type == IB_QPT_RAW_PACKET ?
1531                &qp->raw_packet_qp.rq.base :
1532                &qp->trans_qp.base;
1533
1534         if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1535                 mlx5_ib_odp_create_qp(qp);
1536
1537         mutex_init(&qp->mutex);
1538         spin_lock_init(&qp->sq.lock);
1539         spin_lock_init(&qp->rq.lock);
1540
1541         mlx5_st = to_mlx5_st(init_attr->qp_type);
1542         if (mlx5_st < 0)
1543                 return -EINVAL;
1544
1545         if (init_attr->rwq_ind_tbl) {
1546                 if (!udata)
1547                         return -ENOSYS;
1548
1549                 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1550                 return err;
1551         }
1552
1553         if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1554                 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1555                         mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1556                         return -EINVAL;
1557                 } else {
1558                         qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1559                 }
1560         }
1561
1562         if (init_attr->create_flags &
1563                         (IB_QP_CREATE_CROSS_CHANNEL |
1564                          IB_QP_CREATE_MANAGED_SEND |
1565                          IB_QP_CREATE_MANAGED_RECV)) {
1566                 if (!MLX5_CAP_GEN(mdev, cd)) {
1567                         mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1568                         return -EINVAL;
1569                 }
1570                 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1571                         qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1572                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1573                         qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1574                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1575                         qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1576         }
1577
1578         if (init_attr->qp_type == IB_QPT_UD &&
1579             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1580                 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1581                         mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1582                         return -EOPNOTSUPP;
1583                 }
1584
1585         if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1586                 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1587                         mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1588                         return -EOPNOTSUPP;
1589                 }
1590                 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1591                     !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1592                         mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1593                         return -EOPNOTSUPP;
1594                 }
1595                 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1596         }
1597
1598         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1599                 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1600
1601         if (pd && pd->uobject) {
1602                 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1603                         mlx5_ib_dbg(dev, "copy failed\n");
1604                         return -EFAULT;
1605                 }
1606
1607                 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1608                                         &ucmd, udata->inlen, &uidx);
1609                 if (err)
1610                         return err;
1611
1612                 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1613                 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1614         } else {
1615                 qp->wq_sig = !!wq_signature;
1616         }
1617
1618         qp->has_rq = qp_has_rq(init_attr);
1619         err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1620                           qp, (pd && pd->uobject) ? &ucmd : NULL);
1621         if (err) {
1622                 mlx5_ib_dbg(dev, "err %d\n", err);
1623                 return err;
1624         }
1625
1626         if (pd) {
1627                 if (pd->uobject) {
1628                         __u32 max_wqes =
1629                                 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1630                         mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1631                         if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1632                             ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1633                                 mlx5_ib_dbg(dev, "invalid rq params\n");
1634                                 return -EINVAL;
1635                         }
1636                         if (ucmd.sq_wqe_count > max_wqes) {
1637                                 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
1638                                             ucmd.sq_wqe_count, max_wqes);
1639                                 return -EINVAL;
1640                         }
1641                         if (init_attr->create_flags &
1642                             mlx5_ib_create_qp_sqpn_qp1()) {
1643                                 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1644                                 return -EINVAL;
1645                         }
1646                         err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1647                                              &resp, &inlen, base);
1648                         if (err)
1649                                 mlx5_ib_dbg(dev, "err %d\n", err);
1650                 } else {
1651                         err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1652                                                base);
1653                         if (err)
1654                                 mlx5_ib_dbg(dev, "err %d\n", err);
1655                 }
1656
1657                 if (err)
1658                         return err;
1659         } else {
1660                 in = mlx5_vzalloc(inlen);
1661                 if (!in)
1662                         return -ENOMEM;
1663
1664                 qp->create_type = MLX5_QP_EMPTY;
1665         }
1666
1667         if (is_sqp(init_attr->qp_type))
1668                 qp->port = init_attr->port_num;
1669
1670         qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1671
1672         MLX5_SET(qpc, qpc, st, mlx5_st);
1673         MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1674
1675         if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
1676                 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
1677         else
1678                 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1679
1680
1681         if (qp->wq_sig)
1682                 MLX5_SET(qpc, qpc, wq_signature, 1);
1683
1684         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1685                 MLX5_SET(qpc, qpc, block_lb_mc, 1);
1686
1687         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
1688                 MLX5_SET(qpc, qpc, cd_master, 1);
1689         if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
1690                 MLX5_SET(qpc, qpc, cd_slave_send, 1);
1691         if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
1692                 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
1693
1694         if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1695                 int rcqe_sz;
1696                 int scqe_sz;
1697
1698                 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1699                 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1700
1701                 if (rcqe_sz == 128)
1702                         MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1703                 else
1704                         MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
1705
1706                 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1707                         if (scqe_sz == 128)
1708                                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1709                         else
1710                                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1711                 }
1712         }
1713
1714         if (qp->rq.wqe_cnt) {
1715                 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1716                 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
1717         }
1718
1719         MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
1720
1721         if (qp->sq.wqe_cnt)
1722                 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
1723         else
1724                 MLX5_SET(qpc, qpc, no_sq, 1);
1725
1726         /* Set default resources */
1727         switch (init_attr->qp_type) {
1728         case IB_QPT_XRC_TGT:
1729                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1730                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1731                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1732                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
1733                 break;
1734         case IB_QPT_XRC_INI:
1735                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1736                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1737                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1738                 break;
1739         default:
1740                 if (init_attr->srq) {
1741                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1742                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
1743                 } else {
1744                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1745                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
1746                 }
1747         }
1748
1749         if (init_attr->send_cq)
1750                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
1751
1752         if (init_attr->recv_cq)
1753                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
1754
1755         MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
1756
1757         /* 0xffffff means we ask to work with cqe version 0 */
1758         if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
1759                 MLX5_SET(qpc, qpc, user_index, uidx);
1760
1761         /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1762         if (init_attr->qp_type == IB_QPT_UD &&
1763             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
1764                 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1765                 qp->flags |= MLX5_IB_QP_LSO;
1766         }
1767
1768         if (inlen < 0) {
1769                 err = -EINVAL;
1770                 goto err;
1771         }
1772
1773         if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1774                 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1775                 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1776                 err = create_raw_packet_qp(dev, qp, in, inlen, pd);
1777         } else {
1778                 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1779         }
1780
1781         if (err) {
1782                 mlx5_ib_dbg(dev, "create qp failed\n");
1783                 goto err_create;
1784         }
1785
1786         kvfree(in);
1787
1788         base->container_mibqp = qp;
1789         base->mqp.event = mlx5_ib_qp_event;
1790
1791         get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1792                 &send_cq, &recv_cq);
1793         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1794         mlx5_ib_lock_cqs(send_cq, recv_cq);
1795         /* Maintain device to QPs access, needed for further handling via reset
1796          * flow
1797          */
1798         list_add_tail(&qp->qps_list, &dev->qp_list);
1799         /* Maintain CQ to QPs access, needed for further handling via reset flow
1800          */
1801         if (send_cq)
1802                 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1803         if (recv_cq)
1804                 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1805         mlx5_ib_unlock_cqs(send_cq, recv_cq);
1806         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1807
1808         return 0;
1809
1810 err_create:
1811         if (qp->create_type == MLX5_QP_USER)
1812                 destroy_qp_user(pd, qp, base);
1813         else if (qp->create_type == MLX5_QP_KERNEL)
1814                 destroy_qp_kernel(dev, qp);
1815
1816 err:
1817         kvfree(in);
1818         return err;
1819 }
1820
1821 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1822         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1823 {
1824         if (send_cq) {
1825                 if (recv_cq) {
1826                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
1827                                 spin_lock(&send_cq->lock);
1828                                 spin_lock_nested(&recv_cq->lock,
1829                                                  SINGLE_DEPTH_NESTING);
1830                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1831                                 spin_lock(&send_cq->lock);
1832                                 __acquire(&recv_cq->lock);
1833                         } else {
1834                                 spin_lock(&recv_cq->lock);
1835                                 spin_lock_nested(&send_cq->lock,
1836                                                  SINGLE_DEPTH_NESTING);
1837                         }
1838                 } else {
1839                         spin_lock(&send_cq->lock);
1840                         __acquire(&recv_cq->lock);
1841                 }
1842         } else if (recv_cq) {
1843                 spin_lock(&recv_cq->lock);
1844                 __acquire(&send_cq->lock);
1845         } else {
1846                 __acquire(&send_cq->lock);
1847                 __acquire(&recv_cq->lock);
1848         }
1849 }
1850
1851 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1852         __releases(&send_cq->lock) __releases(&recv_cq->lock)
1853 {
1854         if (send_cq) {
1855                 if (recv_cq) {
1856                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
1857                                 spin_unlock(&recv_cq->lock);
1858                                 spin_unlock(&send_cq->lock);
1859                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1860                                 __release(&recv_cq->lock);
1861                                 spin_unlock(&send_cq->lock);
1862                         } else {
1863                                 spin_unlock(&send_cq->lock);
1864                                 spin_unlock(&recv_cq->lock);
1865                         }
1866                 } else {
1867                         __release(&recv_cq->lock);
1868                         spin_unlock(&send_cq->lock);
1869                 }
1870         } else if (recv_cq) {
1871                 __release(&send_cq->lock);
1872                 spin_unlock(&recv_cq->lock);
1873         } else {
1874                 __release(&recv_cq->lock);
1875                 __release(&send_cq->lock);
1876         }
1877 }
1878
1879 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1880 {
1881         return to_mpd(qp->ibqp.pd);
1882 }
1883
1884 static void get_cqs(enum ib_qp_type qp_type,
1885                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
1886                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1887 {
1888         switch (qp_type) {
1889         case IB_QPT_XRC_TGT:
1890                 *send_cq = NULL;
1891                 *recv_cq = NULL;
1892                 break;
1893         case MLX5_IB_QPT_REG_UMR:
1894         case IB_QPT_XRC_INI:
1895                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1896                 *recv_cq = NULL;
1897                 break;
1898
1899         case IB_QPT_SMI:
1900         case MLX5_IB_QPT_HW_GSI:
1901         case IB_QPT_RC:
1902         case IB_QPT_UC:
1903         case IB_QPT_UD:
1904         case IB_QPT_RAW_IPV6:
1905         case IB_QPT_RAW_ETHERTYPE:
1906         case IB_QPT_RAW_PACKET:
1907                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1908                 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
1909                 break;
1910
1911         case IB_QPT_MAX:
1912         default:
1913                 *send_cq = NULL;
1914                 *recv_cq = NULL;
1915                 break;
1916         }
1917 }
1918
1919 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1920                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
1921                                 u8 lag_tx_affinity);
1922
1923 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1924 {
1925         struct mlx5_ib_cq *send_cq, *recv_cq;
1926         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
1927         unsigned long flags;
1928         int err;
1929
1930         if (qp->ibqp.rwq_ind_tbl) {
1931                 destroy_rss_raw_qp_tir(dev, qp);
1932                 return;
1933         }
1934
1935         base = qp->ibqp.qp_type == IB_QPT_RAW_PACKET ?
1936                &qp->raw_packet_qp.rq.base :
1937                &qp->trans_qp.base;
1938
1939         if (qp->state != IB_QPS_RESET) {
1940                 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET) {
1941                         mlx5_ib_qp_disable_pagefaults(qp);
1942                         err = mlx5_core_qp_modify(dev->mdev,
1943                                                   MLX5_CMD_OP_2RST_QP, 0,
1944                                                   NULL, &base->mqp);
1945                 } else {
1946                         struct mlx5_modify_raw_qp_param raw_qp_param = {
1947                                 .operation = MLX5_CMD_OP_2RST_QP
1948                         };
1949
1950                         err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
1951                 }
1952                 if (err)
1953                         mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
1954                                      base->mqp.qpn);
1955         }
1956
1957         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
1958                 &send_cq, &recv_cq);
1959
1960         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1961         mlx5_ib_lock_cqs(send_cq, recv_cq);
1962         /* del from lists under both locks above to protect reset flow paths */
1963         list_del(&qp->qps_list);
1964         if (send_cq)
1965                 list_del(&qp->cq_send_list);
1966
1967         if (recv_cq)
1968                 list_del(&qp->cq_recv_list);
1969
1970         if (qp->create_type == MLX5_QP_KERNEL) {
1971                 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
1972                                    qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1973                 if (send_cq != recv_cq)
1974                         __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
1975                                            NULL);
1976         }
1977         mlx5_ib_unlock_cqs(send_cq, recv_cq);
1978         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1979
1980         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
1981                 destroy_raw_packet_qp(dev, qp);
1982         } else {
1983                 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
1984                 if (err)
1985                         mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
1986                                      base->mqp.qpn);
1987         }
1988
1989         if (qp->create_type == MLX5_QP_KERNEL)
1990                 destroy_qp_kernel(dev, qp);
1991         else if (qp->create_type == MLX5_QP_USER)
1992                 destroy_qp_user(&get_pd(qp)->ibpd, qp, base);
1993 }
1994
1995 static const char *ib_qp_type_str(enum ib_qp_type type)
1996 {
1997         switch (type) {
1998         case IB_QPT_SMI:
1999                 return "IB_QPT_SMI";
2000         case IB_QPT_GSI:
2001                 return "IB_QPT_GSI";
2002         case IB_QPT_RC:
2003                 return "IB_QPT_RC";
2004         case IB_QPT_UC:
2005                 return "IB_QPT_UC";
2006         case IB_QPT_UD:
2007                 return "IB_QPT_UD";
2008         case IB_QPT_RAW_IPV6:
2009                 return "IB_QPT_RAW_IPV6";
2010         case IB_QPT_RAW_ETHERTYPE:
2011                 return "IB_QPT_RAW_ETHERTYPE";
2012         case IB_QPT_XRC_INI:
2013                 return "IB_QPT_XRC_INI";
2014         case IB_QPT_XRC_TGT:
2015                 return "IB_QPT_XRC_TGT";
2016         case IB_QPT_RAW_PACKET:
2017                 return "IB_QPT_RAW_PACKET";
2018         case MLX5_IB_QPT_REG_UMR:
2019                 return "MLX5_IB_QPT_REG_UMR";
2020         case IB_QPT_MAX:
2021         default:
2022                 return "Invalid QP type";
2023         }
2024 }
2025
2026 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
2027                                 struct ib_qp_init_attr *init_attr,
2028                                 struct ib_udata *udata)
2029 {
2030         struct mlx5_ib_dev *dev;
2031         struct mlx5_ib_qp *qp;
2032         u16 xrcdn = 0;
2033         int err;
2034
2035         if (pd) {
2036                 dev = to_mdev(pd->device);
2037
2038                 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2039                         if (!pd->uobject) {
2040                                 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2041                                 return ERR_PTR(-EINVAL);
2042                         } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2043                                 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2044                                 return ERR_PTR(-EINVAL);
2045                         }
2046                 }
2047         } else {
2048                 /* being cautious here */
2049                 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2050                     init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2051                         pr_warn("%s: no PD for transport %s\n", __func__,
2052                                 ib_qp_type_str(init_attr->qp_type));
2053                         return ERR_PTR(-EINVAL);
2054                 }
2055                 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2056         }
2057
2058         switch (init_attr->qp_type) {
2059         case IB_QPT_XRC_TGT:
2060         case IB_QPT_XRC_INI:
2061                 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
2062                         mlx5_ib_dbg(dev, "XRC not supported\n");
2063                         return ERR_PTR(-ENOSYS);
2064                 }
2065                 init_attr->recv_cq = NULL;
2066                 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2067                         xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2068                         init_attr->send_cq = NULL;
2069                 }
2070
2071                 /* fall through */
2072         case IB_QPT_RAW_PACKET:
2073         case IB_QPT_RC:
2074         case IB_QPT_UC:
2075         case IB_QPT_UD:
2076         case IB_QPT_SMI:
2077         case MLX5_IB_QPT_HW_GSI:
2078         case MLX5_IB_QPT_REG_UMR:
2079                 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2080                 if (!qp)
2081                         return ERR_PTR(-ENOMEM);
2082
2083                 err = create_qp_common(dev, pd, init_attr, udata, qp);
2084                 if (err) {
2085                         mlx5_ib_dbg(dev, "create_qp_common failed\n");
2086                         kfree(qp);
2087                         return ERR_PTR(err);
2088                 }
2089
2090                 if (is_qp0(init_attr->qp_type))
2091                         qp->ibqp.qp_num = 0;
2092                 else if (is_qp1(init_attr->qp_type))
2093                         qp->ibqp.qp_num = 1;
2094                 else
2095                         qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2096
2097                 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
2098                             qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2099                             init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2100                             init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
2101
2102                 qp->trans_qp.xrcdn = xrcdn;
2103
2104                 break;
2105
2106         case IB_QPT_GSI:
2107                 return mlx5_ib_gsi_create_qp(pd, init_attr);
2108
2109         case IB_QPT_RAW_IPV6:
2110         case IB_QPT_RAW_ETHERTYPE:
2111         case IB_QPT_MAX:
2112         default:
2113                 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2114                             init_attr->qp_type);
2115                 /* Don't support raw QPs */
2116                 return ERR_PTR(-EINVAL);
2117         }
2118
2119         return &qp->ibqp;
2120 }
2121
2122 int mlx5_ib_destroy_qp(struct ib_qp *qp)
2123 {
2124         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2125         struct mlx5_ib_qp *mqp = to_mqp(qp);
2126
2127         if (unlikely(qp->qp_type == IB_QPT_GSI))
2128                 return mlx5_ib_gsi_destroy_qp(qp);
2129
2130         destroy_qp_common(dev, mqp);
2131
2132         kfree(mqp);
2133
2134         return 0;
2135 }
2136
2137 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2138                                    int attr_mask)
2139 {
2140         u32 hw_access_flags = 0;
2141         u8 dest_rd_atomic;
2142         u32 access_flags;
2143
2144         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2145                 dest_rd_atomic = attr->max_dest_rd_atomic;
2146         else
2147                 dest_rd_atomic = qp->trans_qp.resp_depth;
2148
2149         if (attr_mask & IB_QP_ACCESS_FLAGS)
2150                 access_flags = attr->qp_access_flags;
2151         else
2152                 access_flags = qp->trans_qp.atomic_rd_en;
2153
2154         if (!dest_rd_atomic)
2155                 access_flags &= IB_ACCESS_REMOTE_WRITE;
2156
2157         if (access_flags & IB_ACCESS_REMOTE_READ)
2158                 hw_access_flags |= MLX5_QP_BIT_RRE;
2159         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2160                 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2161         if (access_flags & IB_ACCESS_REMOTE_WRITE)
2162                 hw_access_flags |= MLX5_QP_BIT_RWE;
2163
2164         return cpu_to_be32(hw_access_flags);
2165 }
2166
2167 enum {
2168         MLX5_PATH_FLAG_FL       = 1 << 0,
2169         MLX5_PATH_FLAG_FREE_AR  = 1 << 1,
2170         MLX5_PATH_FLAG_COUNTER  = 1 << 2,
2171 };
2172
2173 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2174 {
2175         if (rate == IB_RATE_PORT_CURRENT)
2176                 return 0;
2177
2178         if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS)
2179                 return -EINVAL;
2180
2181         while (rate != IB_RATE_PORT_CURRENT &&
2182                !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2183                  MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2184                 --rate;
2185
2186         return rate ? rate + MLX5_STAT_RATE_OFFSET : rate;
2187 }
2188
2189 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2190                                       struct mlx5_ib_sq *sq, u8 sl)
2191 {
2192         void *in;
2193         void *tisc;
2194         int inlen;
2195         int err;
2196
2197         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2198         in = mlx5_vzalloc(inlen);
2199         if (!in)
2200                 return -ENOMEM;
2201
2202         MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2203
2204         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2205         MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2206
2207         err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2208
2209         kvfree(in);
2210
2211         return err;
2212 }
2213
2214 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2215                                          struct mlx5_ib_sq *sq, u8 tx_affinity)
2216 {
2217         void *in;
2218         void *tisc;
2219         int inlen;
2220         int err;
2221
2222         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2223         in = mlx5_vzalloc(inlen);
2224         if (!in)
2225                 return -ENOMEM;
2226
2227         MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2228
2229         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2230         MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2231
2232         err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2233
2234         kvfree(in);
2235
2236         return err;
2237 }
2238
2239 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2240                          const struct ib_ah_attr *ah,
2241                          struct mlx5_qp_path *path, u8 port, int attr_mask,
2242                          u32 path_flags, const struct ib_qp_attr *attr,
2243                          bool alt)
2244 {
2245         enum rdma_link_layer ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2246         int err;
2247         enum ib_gid_type gid_type;
2248
2249         if (attr_mask & IB_QP_PKEY_INDEX)
2250                 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2251                                                      attr->pkey_index);
2252
2253         if (ah->ah_flags & IB_AH_GRH) {
2254                 if (ah->grh.sgid_index >=
2255                     dev->mdev->port_caps[port - 1].gid_table_len) {
2256                         pr_err("sgid_index (%u) too large. max is %d\n",
2257                                ah->grh.sgid_index,
2258                                dev->mdev->port_caps[port - 1].gid_table_len);
2259                         return -EINVAL;
2260                 }
2261         }
2262
2263         if (ll == IB_LINK_LAYER_ETHERNET) {
2264                 if (!(ah->ah_flags & IB_AH_GRH))
2265                         return -EINVAL;
2266                 err = mlx5_get_roce_gid_type(dev, port, ah->grh.sgid_index,
2267                                              &gid_type);
2268                 if (err)
2269                         return err;
2270                 memcpy(path->rmac, ah->dmac, sizeof(ah->dmac));
2271                 path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
2272                                                           ah->grh.sgid_index);
2273                 path->dci_cfi_prio_sl = (ah->sl & 0x7) << 4;
2274                 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
2275                         path->ecn_dscp = (ah->grh.traffic_class >> 2) & 0x3f;
2276         } else {
2277                 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2278                 path->fl_free_ar |=
2279                         (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2280                 path->rlid = cpu_to_be16(ah->dlid);
2281                 path->grh_mlid = ah->src_path_bits & 0x7f;
2282                 if (ah->ah_flags & IB_AH_GRH)
2283                         path->grh_mlid  |= 1 << 7;
2284                 path->dci_cfi_prio_sl = ah->sl & 0xf;
2285         }
2286
2287         if (ah->ah_flags & IB_AH_GRH) {
2288                 path->mgid_index = ah->grh.sgid_index;
2289                 path->hop_limit  = ah->grh.hop_limit;
2290                 path->tclass_flowlabel =
2291                         cpu_to_be32((ah->grh.traffic_class << 20) |
2292                                     (ah->grh.flow_label));
2293                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
2294         }
2295
2296         err = ib_rate_to_mlx5(dev, ah->static_rate);
2297         if (err < 0)
2298                 return err;
2299         path->static_rate = err;
2300         path->port = port;
2301
2302         if (attr_mask & IB_QP_TIMEOUT)
2303                 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
2304
2305         if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2306                 return modify_raw_packet_eth_prio(dev->mdev,
2307                                                   &qp->raw_packet_qp.sq,
2308                                                   ah->sl & 0xf);
2309
2310         return 0;
2311 }
2312
2313 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2314         [MLX5_QP_STATE_INIT] = {
2315                 [MLX5_QP_STATE_INIT] = {
2316                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
2317                                           MLX5_QP_OPTPAR_RAE            |
2318                                           MLX5_QP_OPTPAR_RWE            |
2319                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2320                                           MLX5_QP_OPTPAR_PRI_PORT,
2321                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
2322                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2323                                           MLX5_QP_OPTPAR_PRI_PORT,
2324                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2325                                           MLX5_QP_OPTPAR_Q_KEY          |
2326                                           MLX5_QP_OPTPAR_PRI_PORT,
2327                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE           |
2328                                           MLX5_QP_OPTPAR_RAE            |
2329                                           MLX5_QP_OPTPAR_RWE            |
2330                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2331                                           MLX5_QP_OPTPAR_PRI_PORT,
2332                 },
2333                 [MLX5_QP_STATE_RTR] = {
2334                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2335                                           MLX5_QP_OPTPAR_RRE            |
2336                                           MLX5_QP_OPTPAR_RAE            |
2337                                           MLX5_QP_OPTPAR_RWE            |
2338                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2339                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2340                                           MLX5_QP_OPTPAR_RWE            |
2341                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2342                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2343                                           MLX5_QP_OPTPAR_Q_KEY,
2344                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX    |
2345                                            MLX5_QP_OPTPAR_Q_KEY,
2346                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2347                                           MLX5_QP_OPTPAR_RRE            |
2348                                           MLX5_QP_OPTPAR_RAE            |
2349                                           MLX5_QP_OPTPAR_RWE            |
2350                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2351                 },
2352         },
2353         [MLX5_QP_STATE_RTR] = {
2354                 [MLX5_QP_STATE_RTS] = {
2355                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2356                                           MLX5_QP_OPTPAR_RRE            |
2357                                           MLX5_QP_OPTPAR_RAE            |
2358                                           MLX5_QP_OPTPAR_RWE            |
2359                                           MLX5_QP_OPTPAR_PM_STATE       |
2360                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
2361                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2362                                           MLX5_QP_OPTPAR_RWE            |
2363                                           MLX5_QP_OPTPAR_PM_STATE,
2364                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2365                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2366                                           MLX5_QP_OPTPAR_RRE            |
2367                                           MLX5_QP_OPTPAR_RAE            |
2368                                           MLX5_QP_OPTPAR_RWE            |
2369                                           MLX5_QP_OPTPAR_PM_STATE       |
2370                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
2371                 },
2372         },
2373         [MLX5_QP_STATE_RTS] = {
2374                 [MLX5_QP_STATE_RTS] = {
2375                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
2376                                           MLX5_QP_OPTPAR_RAE            |
2377                                           MLX5_QP_OPTPAR_RWE            |
2378                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
2379                                           MLX5_QP_OPTPAR_PM_STATE       |
2380                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2381                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
2382                                           MLX5_QP_OPTPAR_PM_STATE       |
2383                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2384                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY          |
2385                                           MLX5_QP_OPTPAR_SRQN           |
2386                                           MLX5_QP_OPTPAR_CQN_RCV,
2387                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE           |
2388                                           MLX5_QP_OPTPAR_RAE            |
2389                                           MLX5_QP_OPTPAR_RWE            |
2390                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
2391                                           MLX5_QP_OPTPAR_PM_STATE       |
2392                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2393                 },
2394         },
2395         [MLX5_QP_STATE_SQER] = {
2396                 [MLX5_QP_STATE_RTS] = {
2397                         [MLX5_QP_ST_UD]  = MLX5_QP_OPTPAR_Q_KEY,
2398                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
2399                         [MLX5_QP_ST_UC]  = MLX5_QP_OPTPAR_RWE,
2400                         [MLX5_QP_ST_RC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT   |
2401                                            MLX5_QP_OPTPAR_RWE           |
2402                                            MLX5_QP_OPTPAR_RAE           |
2403                                            MLX5_QP_OPTPAR_RRE,
2404                         [MLX5_QP_ST_XRC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT  |
2405                                            MLX5_QP_OPTPAR_RWE           |
2406                                            MLX5_QP_OPTPAR_RAE           |
2407                                            MLX5_QP_OPTPAR_RRE,
2408                 },
2409         },
2410 };
2411
2412 static int ib_nr_to_mlx5_nr(int ib_mask)
2413 {
2414         switch (ib_mask) {
2415         case IB_QP_STATE:
2416                 return 0;
2417         case IB_QP_CUR_STATE:
2418                 return 0;
2419         case IB_QP_EN_SQD_ASYNC_NOTIFY:
2420                 return 0;
2421         case IB_QP_ACCESS_FLAGS:
2422                 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2423                         MLX5_QP_OPTPAR_RAE;
2424         case IB_QP_PKEY_INDEX:
2425                 return MLX5_QP_OPTPAR_PKEY_INDEX;
2426         case IB_QP_PORT:
2427                 return MLX5_QP_OPTPAR_PRI_PORT;
2428         case IB_QP_QKEY:
2429                 return MLX5_QP_OPTPAR_Q_KEY;
2430         case IB_QP_AV:
2431                 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2432                         MLX5_QP_OPTPAR_PRI_PORT;
2433         case IB_QP_PATH_MTU:
2434                 return 0;
2435         case IB_QP_TIMEOUT:
2436                 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2437         case IB_QP_RETRY_CNT:
2438                 return MLX5_QP_OPTPAR_RETRY_COUNT;
2439         case IB_QP_RNR_RETRY:
2440                 return MLX5_QP_OPTPAR_RNR_RETRY;
2441         case IB_QP_RQ_PSN:
2442                 return 0;
2443         case IB_QP_MAX_QP_RD_ATOMIC:
2444                 return MLX5_QP_OPTPAR_SRA_MAX;
2445         case IB_QP_ALT_PATH:
2446                 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2447         case IB_QP_MIN_RNR_TIMER:
2448                 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2449         case IB_QP_SQ_PSN:
2450                 return 0;
2451         case IB_QP_MAX_DEST_RD_ATOMIC:
2452                 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2453                         MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2454         case IB_QP_PATH_MIG_STATE:
2455                 return MLX5_QP_OPTPAR_PM_STATE;
2456         case IB_QP_CAP:
2457                 return 0;
2458         case IB_QP_DEST_QPN:
2459                 return 0;
2460         }
2461         return 0;
2462 }
2463
2464 static int ib_mask_to_mlx5_opt(int ib_mask)
2465 {
2466         int result = 0;
2467         int i;
2468
2469         for (i = 0; i < 8 * sizeof(int); i++) {
2470                 if ((1 << i) & ib_mask)
2471                         result |= ib_nr_to_mlx5_nr(1 << i);
2472         }
2473
2474         return result;
2475 }
2476
2477 static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2478                                    struct mlx5_ib_rq *rq, int new_state,
2479                                    const struct mlx5_modify_raw_qp_param *raw_qp_param)
2480 {
2481         void *in;
2482         void *rqc;
2483         int inlen;
2484         int err;
2485
2486         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2487         in = mlx5_vzalloc(inlen);
2488         if (!in)
2489                 return -ENOMEM;
2490
2491         MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2492
2493         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2494         MLX5_SET(rqc, rqc, state, new_state);
2495
2496         if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2497                 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
2498                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
2499                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID);
2500                         MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2501                 } else
2502                         pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n",
2503                                      dev->ib_dev.name);
2504         }
2505
2506         err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
2507         if (err)
2508                 goto out;
2509
2510         rq->state = new_state;
2511
2512 out:
2513         kvfree(in);
2514         return err;
2515 }
2516
2517 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
2518                                    struct mlx5_ib_sq *sq, int new_state)
2519 {
2520         void *in;
2521         void *sqc;
2522         int inlen;
2523         int err;
2524
2525         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2526         in = mlx5_vzalloc(inlen);
2527         if (!in)
2528                 return -ENOMEM;
2529
2530         MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2531
2532         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2533         MLX5_SET(sqc, sqc, state, new_state);
2534
2535         err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
2536         if (err)
2537                 goto out;
2538
2539         sq->state = new_state;
2540
2541 out:
2542         kvfree(in);
2543         return err;
2544 }
2545
2546 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2547                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2548                                 u8 tx_affinity)
2549 {
2550         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2551         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2552         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
2553         int rq_state;
2554         int sq_state;
2555         int err;
2556
2557         switch (raw_qp_param->operation) {
2558         case MLX5_CMD_OP_RST2INIT_QP:
2559                 rq_state = MLX5_RQC_STATE_RDY;
2560                 sq_state = MLX5_SQC_STATE_RDY;
2561                 break;
2562         case MLX5_CMD_OP_2ERR_QP:
2563                 rq_state = MLX5_RQC_STATE_ERR;
2564                 sq_state = MLX5_SQC_STATE_ERR;
2565                 break;
2566         case MLX5_CMD_OP_2RST_QP:
2567                 rq_state = MLX5_RQC_STATE_RST;
2568                 sq_state = MLX5_SQC_STATE_RST;
2569                 break;
2570         case MLX5_CMD_OP_INIT2INIT_QP:
2571         case MLX5_CMD_OP_INIT2RTR_QP:
2572         case MLX5_CMD_OP_RTR2RTS_QP:
2573         case MLX5_CMD_OP_RTS2RTS_QP:
2574                 if (raw_qp_param->set_mask)
2575                         return -EINVAL;
2576                 else
2577                         return 0;
2578         default:
2579                 WARN_ON(1);
2580                 return -EINVAL;
2581         }
2582
2583         if (qp->rq.wqe_cnt) {
2584                 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param);
2585                 if (err)
2586                         return err;
2587         }
2588
2589         if (qp->sq.wqe_cnt) {
2590                 if (tx_affinity) {
2591                         err = modify_raw_packet_tx_affinity(dev->mdev, sq,
2592                                                             tx_affinity);
2593                         if (err)
2594                                 return err;
2595                 }
2596
2597                 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state);
2598         }
2599
2600         return 0;
2601 }
2602
2603 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2604                                const struct ib_qp_attr *attr, int attr_mask,
2605                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
2606 {
2607         static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2608                 [MLX5_QP_STATE_RST] = {
2609                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2610                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2611                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_RST2INIT_QP,
2612                 },
2613                 [MLX5_QP_STATE_INIT]  = {
2614                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2615                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2616                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_INIT2INIT_QP,
2617                         [MLX5_QP_STATE_RTR]     = MLX5_CMD_OP_INIT2RTR_QP,
2618                 },
2619                 [MLX5_QP_STATE_RTR]   = {
2620                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2621                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2622                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTR2RTS_QP,
2623                 },
2624                 [MLX5_QP_STATE_RTS]   = {
2625                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2626                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2627                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTS2RTS_QP,
2628                 },
2629                 [MLX5_QP_STATE_SQD] = {
2630                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2631                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2632                 },
2633                 [MLX5_QP_STATE_SQER] = {
2634                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2635                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2636                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_SQERR2RTS_QP,
2637                 },
2638                 [MLX5_QP_STATE_ERR] = {
2639                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2640                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2641                 }
2642         };
2643
2644         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2645         struct mlx5_ib_qp *qp = to_mqp(ibqp);
2646         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
2647         struct mlx5_ib_cq *send_cq, *recv_cq;
2648         struct mlx5_qp_context *context;
2649         struct mlx5_ib_pd *pd;
2650         struct mlx5_ib_port *mibport = NULL;
2651         enum mlx5_qp_state mlx5_cur, mlx5_new;
2652         enum mlx5_qp_optpar optpar;
2653         int sqd_event;
2654         int mlx5_st;
2655         int err;
2656         u16 op;
2657         u8 tx_affinity = 0;
2658
2659         context = kzalloc(sizeof(*context), GFP_KERNEL);
2660         if (!context)
2661                 return -ENOMEM;
2662
2663         err = to_mlx5_st(ibqp->qp_type);
2664         if (err < 0) {
2665                 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type);
2666                 goto out;
2667         }
2668
2669         context->flags = cpu_to_be32(err << 16);
2670
2671         if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2672                 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2673         } else {
2674                 switch (attr->path_mig_state) {
2675                 case IB_MIG_MIGRATED:
2676                         context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2677                         break;
2678                 case IB_MIG_REARM:
2679                         context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2680                         break;
2681                 case IB_MIG_ARMED:
2682                         context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2683                         break;
2684                 }
2685         }
2686
2687         if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2688                 if ((ibqp->qp_type == IB_QPT_RC) ||
2689                     (ibqp->qp_type == IB_QPT_UD &&
2690                      !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
2691                     (ibqp->qp_type == IB_QPT_UC) ||
2692                     (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2693                     (ibqp->qp_type == IB_QPT_XRC_INI) ||
2694                     (ibqp->qp_type == IB_QPT_XRC_TGT)) {
2695                         if (mlx5_lag_is_active(dev->mdev)) {
2696                                 tx_affinity = (unsigned int)atomic_add_return(1,
2697                                                 &dev->roce.next_port) %
2698                                                 MLX5_MAX_PORTS + 1;
2699                                 context->flags |= cpu_to_be32(tx_affinity << 24);
2700                         }
2701                 }
2702         }
2703
2704         if (is_sqp(ibqp->qp_type)) {
2705                 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
2706         } else if (ibqp->qp_type == IB_QPT_UD ||
2707                    ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
2708                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
2709         } else if (attr_mask & IB_QP_PATH_MTU) {
2710                 if (attr->path_mtu < IB_MTU_256 ||
2711                     attr->path_mtu > IB_MTU_4096) {
2712                         mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
2713                         err = -EINVAL;
2714                         goto out;
2715                 }
2716                 context->mtu_msgmax = (attr->path_mtu << 5) |
2717                                       (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
2718         }
2719
2720         if (attr_mask & IB_QP_DEST_QPN)
2721                 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
2722
2723         if (attr_mask & IB_QP_PKEY_INDEX)
2724                 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
2725
2726         /* todo implement counter_index functionality */
2727
2728         if (is_sqp(ibqp->qp_type))
2729                 context->pri_path.port = qp->port;
2730
2731         if (attr_mask & IB_QP_PORT)
2732                 context->pri_path.port = attr->port_num;
2733
2734         if (attr_mask & IB_QP_AV) {
2735                 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
2736                                     attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
2737                                     attr_mask, 0, attr, false);
2738                 if (err)
2739                         goto out;
2740         }
2741
2742         if (attr_mask & IB_QP_TIMEOUT)
2743                 context->pri_path.ackto_lt |= attr->timeout << 3;
2744
2745         if (attr_mask & IB_QP_ALT_PATH) {
2746                 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
2747                                     &context->alt_path,
2748                                     attr->alt_port_num,
2749                                     attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
2750                                     0, attr, true);
2751                 if (err)
2752                         goto out;
2753         }
2754
2755         pd = get_pd(qp);
2756         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2757                 &send_cq, &recv_cq);
2758
2759         context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
2760         context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
2761         context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
2762         context->params1  = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
2763
2764         if (attr_mask & IB_QP_RNR_RETRY)
2765                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2766
2767         if (attr_mask & IB_QP_RETRY_CNT)
2768                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2769
2770         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2771                 if (attr->max_rd_atomic)
2772                         context->params1 |=
2773                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2774         }
2775
2776         if (attr_mask & IB_QP_SQ_PSN)
2777                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2778
2779         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2780                 if (attr->max_dest_rd_atomic)
2781                         context->params2 |=
2782                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2783         }
2784
2785         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
2786                 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
2787
2788         if (attr_mask & IB_QP_MIN_RNR_TIMER)
2789                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2790
2791         if (attr_mask & IB_QP_RQ_PSN)
2792                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2793
2794         if (attr_mask & IB_QP_QKEY)
2795                 context->qkey = cpu_to_be32(attr->qkey);
2796
2797         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2798                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2799
2800         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
2801             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
2802                 sqd_event = 1;
2803         else
2804                 sqd_event = 0;
2805
2806         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2807                 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
2808                                qp->port) - 1;
2809                 mibport = &dev->port[port_num];
2810                 context->qp_counter_set_usr_page |=
2811                         cpu_to_be32((u32)(mibport->q_cnt_id) << 24);
2812         }
2813
2814         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2815                 context->sq_crq_size |= cpu_to_be16(1 << 4);
2816
2817         if (qp->flags & MLX5_IB_QP_SQPN_QP1)
2818                 context->deth_sqpn = cpu_to_be32(1);
2819
2820         mlx5_cur = to_mlx5_state(cur_state);
2821         mlx5_new = to_mlx5_state(new_state);
2822         mlx5_st = to_mlx5_st(ibqp->qp_type);
2823         if (mlx5_st < 0)
2824                 goto out;
2825
2826         /* If moving to a reset or error state, we must disable page faults on
2827          * this QP and flush all current page faults. Otherwise a stale page
2828          * fault may attempt to work on this QP after it is reset and moved
2829          * again to RTS, and may cause the driver and the device to get out of
2830          * sync. */
2831         if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2832             (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR) &&
2833             (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
2834                 mlx5_ib_qp_disable_pagefaults(qp);
2835
2836         if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
2837             !optab[mlx5_cur][mlx5_new]) {
2838                 err = -EINVAL;
2839                 goto out;
2840         }
2841
2842         op = optab[mlx5_cur][mlx5_new];
2843         optpar = ib_mask_to_mlx5_opt(attr_mask);
2844         optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
2845
2846         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
2847                 struct mlx5_modify_raw_qp_param raw_qp_param = {};
2848
2849                 raw_qp_param.operation = op;
2850                 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2851                         raw_qp_param.rq_q_ctr_id = mibport->q_cnt_id;
2852                         raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
2853                 }
2854                 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
2855         } else {
2856                 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
2857                                           &base->mqp);
2858         }
2859
2860         if (err)
2861                 goto out;
2862
2863         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT &&
2864             (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
2865                 mlx5_ib_qp_enable_pagefaults(qp);
2866
2867         qp->state = new_state;
2868
2869         if (attr_mask & IB_QP_ACCESS_FLAGS)
2870                 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
2871         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2872                 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
2873         if (attr_mask & IB_QP_PORT)
2874                 qp->port = attr->port_num;
2875         if (attr_mask & IB_QP_ALT_PATH)
2876                 qp->trans_qp.alt_port = attr->alt_port_num;
2877
2878         /*
2879          * If we moved a kernel QP to RESET, clean up all old CQ
2880          * entries and reinitialize the QP.
2881          */
2882         if (new_state == IB_QPS_RESET &&
2883             !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) {
2884                 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2885                                  ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2886                 if (send_cq != recv_cq)
2887                         mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
2888
2889                 qp->rq.head = 0;
2890                 qp->rq.tail = 0;
2891                 qp->sq.head = 0;
2892                 qp->sq.tail = 0;
2893                 qp->sq.cur_post = 0;
2894                 qp->sq.last_poll = 0;
2895                 qp->db.db[MLX5_RCV_DBR] = 0;
2896                 qp->db.db[MLX5_SND_DBR] = 0;
2897         }
2898
2899 out:
2900         kfree(context);
2901         return err;
2902 }
2903
2904 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2905                       int attr_mask, struct ib_udata *udata)
2906 {
2907         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2908         struct mlx5_ib_qp *qp = to_mqp(ibqp);
2909         enum ib_qp_type qp_type;
2910         enum ib_qp_state cur_state, new_state;
2911         int err = -EINVAL;
2912         int port;
2913         enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
2914
2915         if (ibqp->rwq_ind_tbl)
2916                 return -ENOSYS;
2917
2918         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
2919                 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
2920
2921         qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
2922                 IB_QPT_GSI : ibqp->qp_type;
2923
2924         mutex_lock(&qp->mutex);
2925
2926         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2927         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2928
2929         if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
2930                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2931                 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
2932         }
2933
2934         if (qp_type != MLX5_IB_QPT_REG_UMR &&
2935             !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
2936                 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
2937                             cur_state, new_state, ibqp->qp_type, attr_mask);
2938                 goto out;
2939         }
2940
2941         if ((attr_mask & IB_QP_PORT) &&
2942             (attr->port_num == 0 ||
2943              attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) {
2944                 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
2945                             attr->port_num, dev->num_ports);
2946                 goto out;
2947         }
2948
2949         if (attr_mask & IB_QP_PKEY_INDEX) {
2950                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2951                 if (attr->pkey_index >=
2952                     dev->mdev->port_caps[port - 1].pkey_table_len) {
2953                         mlx5_ib_dbg(dev, "invalid pkey index %d\n",
2954                                     attr->pkey_index);
2955                         goto out;
2956                 }
2957         }
2958
2959         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2960             attr->max_rd_atomic >
2961             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
2962                 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
2963                             attr->max_rd_atomic);
2964                 goto out;
2965         }
2966
2967         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2968             attr->max_dest_rd_atomic >
2969             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
2970                 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
2971                             attr->max_dest_rd_atomic);
2972                 goto out;
2973         }
2974
2975         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2976                 err = 0;
2977                 goto out;
2978         }
2979
2980         err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2981
2982 out:
2983         mutex_unlock(&qp->mutex);
2984         return err;
2985 }
2986
2987 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2988 {
2989         struct mlx5_ib_cq *cq;
2990         unsigned cur;
2991
2992         cur = wq->head - wq->tail;
2993         if (likely(cur + nreq < wq->max_post))
2994                 return 0;
2995
2996         cq = to_mcq(ib_cq);
2997         spin_lock(&cq->lock);
2998         cur = wq->head - wq->tail;
2999         spin_unlock(&cq->lock);
3000
3001         return cur + nreq >= wq->max_post;
3002 }
3003
3004 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
3005                                           u64 remote_addr, u32 rkey)
3006 {
3007         rseg->raddr    = cpu_to_be64(remote_addr);
3008         rseg->rkey     = cpu_to_be32(rkey);
3009         rseg->reserved = 0;
3010 }
3011
3012 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
3013                          struct ib_send_wr *wr, void *qend,
3014                          struct mlx5_ib_qp *qp, int *size)
3015 {
3016         void *seg = eseg;
3017
3018         memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
3019
3020         if (wr->send_flags & IB_SEND_IP_CSUM)
3021                 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
3022                                  MLX5_ETH_WQE_L4_CSUM;
3023
3024         seg += sizeof(struct mlx5_wqe_eth_seg);
3025         *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
3026
3027         if (wr->opcode == IB_WR_LSO) {
3028                 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
3029                 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr_start);
3030                 u64 left, leftlen, copysz;
3031                 void *pdata = ud_wr->header;
3032
3033                 left = ud_wr->hlen;
3034                 eseg->mss = cpu_to_be16(ud_wr->mss);
3035                 eseg->inline_hdr_sz = cpu_to_be16(left);
3036
3037                 /*
3038                  * check if there is space till the end of queue, if yes,
3039                  * copy all in one shot, otherwise copy till the end of queue,
3040                  * rollback and than the copy the left
3041                  */
3042                 leftlen = qend - (void *)eseg->inline_hdr_start;
3043                 copysz = min_t(u64, leftlen, left);
3044
3045                 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
3046
3047                 if (likely(copysz > size_of_inl_hdr_start)) {
3048                         seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
3049                         *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
3050                 }
3051
3052                 if (unlikely(copysz < left)) { /* the last wqe in the queue */
3053                         seg = mlx5_get_send_wqe(qp, 0);
3054                         left -= copysz;
3055                         pdata += copysz;
3056                         memcpy(seg, pdata, left);
3057                         seg += ALIGN(left, 16);
3058                         *size += ALIGN(left, 16) / 16;
3059                 }
3060         }
3061
3062         return seg;
3063 }
3064
3065 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
3066                              struct ib_send_wr *wr)
3067 {
3068         memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
3069         dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
3070         dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
3071 }
3072
3073 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
3074 {
3075         dseg->byte_count = cpu_to_be32(sg->length);
3076         dseg->lkey       = cpu_to_be32(sg->lkey);
3077         dseg->addr       = cpu_to_be64(sg->addr);
3078 }
3079
3080 static __be16 get_klm_octo(int npages)
3081 {
3082         return cpu_to_be16(ALIGN(npages, 8) / 2);
3083 }
3084
3085 static __be64 frwr_mkey_mask(void)
3086 {
3087         u64 result;
3088
3089         result = MLX5_MKEY_MASK_LEN             |
3090                 MLX5_MKEY_MASK_PAGE_SIZE        |
3091                 MLX5_MKEY_MASK_START_ADDR       |
3092                 MLX5_MKEY_MASK_EN_RINVAL        |
3093                 MLX5_MKEY_MASK_KEY              |
3094                 MLX5_MKEY_MASK_LR               |
3095                 MLX5_MKEY_MASK_LW               |
3096                 MLX5_MKEY_MASK_RR               |
3097                 MLX5_MKEY_MASK_RW               |
3098                 MLX5_MKEY_MASK_A                |
3099                 MLX5_MKEY_MASK_SMALL_FENCE      |
3100                 MLX5_MKEY_MASK_FREE;
3101
3102         return cpu_to_be64(result);
3103 }
3104
3105 static __be64 sig_mkey_mask(void)
3106 {
3107         u64 result;
3108
3109         result = MLX5_MKEY_MASK_LEN             |
3110                 MLX5_MKEY_MASK_PAGE_SIZE        |
3111                 MLX5_MKEY_MASK_START_ADDR       |
3112                 MLX5_MKEY_MASK_EN_SIGERR        |
3113                 MLX5_MKEY_MASK_EN_RINVAL        |
3114                 MLX5_MKEY_MASK_KEY              |
3115                 MLX5_MKEY_MASK_LR               |
3116                 MLX5_MKEY_MASK_LW               |
3117                 MLX5_MKEY_MASK_RR               |
3118                 MLX5_MKEY_MASK_RW               |
3119                 MLX5_MKEY_MASK_SMALL_FENCE      |
3120                 MLX5_MKEY_MASK_FREE             |
3121                 MLX5_MKEY_MASK_BSF_EN;
3122
3123         return cpu_to_be64(result);
3124 }
3125
3126 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
3127                                 struct mlx5_ib_mr *mr)
3128 {
3129         int ndescs = mr->ndescs;
3130
3131         memset(umr, 0, sizeof(*umr));
3132
3133         if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
3134                 /* KLMs take twice the size of MTTs */
3135                 ndescs *= 2;
3136
3137         umr->flags = MLX5_UMR_CHECK_NOT_FREE;
3138         umr->klm_octowords = get_klm_octo(ndescs);
3139         umr->mkey_mask = frwr_mkey_mask();
3140 }
3141
3142 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
3143 {
3144         memset(umr, 0, sizeof(*umr));
3145         umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
3146         umr->flags = 1 << 7;
3147 }
3148
3149 static __be64 get_umr_reg_mr_mask(void)
3150 {
3151         u64 result;
3152
3153         result = MLX5_MKEY_MASK_LEN             |
3154                  MLX5_MKEY_MASK_PAGE_SIZE       |
3155                  MLX5_MKEY_MASK_START_ADDR      |
3156                  MLX5_MKEY_MASK_PD              |
3157                  MLX5_MKEY_MASK_LR              |
3158                  MLX5_MKEY_MASK_LW              |
3159                  MLX5_MKEY_MASK_KEY             |
3160                  MLX5_MKEY_MASK_RR              |
3161                  MLX5_MKEY_MASK_RW              |
3162                  MLX5_MKEY_MASK_A               |
3163                  MLX5_MKEY_MASK_FREE;
3164
3165         return cpu_to_be64(result);
3166 }
3167
3168 static __be64 get_umr_unreg_mr_mask(void)
3169 {
3170         u64 result;
3171
3172         result = MLX5_MKEY_MASK_FREE;
3173
3174         return cpu_to_be64(result);
3175 }
3176
3177 static __be64 get_umr_update_mtt_mask(void)
3178 {
3179         u64 result;
3180
3181         result = MLX5_MKEY_MASK_FREE;
3182
3183         return cpu_to_be64(result);
3184 }
3185
3186 static __be64 get_umr_update_translation_mask(void)
3187 {
3188         u64 result;
3189
3190         result = MLX5_MKEY_MASK_LEN |
3191                  MLX5_MKEY_MASK_PAGE_SIZE |
3192                  MLX5_MKEY_MASK_START_ADDR |
3193                  MLX5_MKEY_MASK_KEY |
3194                  MLX5_MKEY_MASK_FREE;
3195
3196         return cpu_to_be64(result);
3197 }
3198
3199 static __be64 get_umr_update_access_mask(void)
3200 {
3201         u64 result;
3202
3203         result = MLX5_MKEY_MASK_LW |
3204                  MLX5_MKEY_MASK_RR |
3205                  MLX5_MKEY_MASK_RW |
3206                  MLX5_MKEY_MASK_A |
3207                  MLX5_MKEY_MASK_KEY |
3208                  MLX5_MKEY_MASK_FREE;
3209
3210         return cpu_to_be64(result);
3211 }
3212
3213 static __be64 get_umr_update_pd_mask(void)
3214 {
3215         u64 result;
3216
3217         result = MLX5_MKEY_MASK_PD |
3218                  MLX5_MKEY_MASK_KEY |
3219                  MLX5_MKEY_MASK_FREE;
3220
3221         return cpu_to_be64(result);
3222 }
3223
3224 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3225                                 struct ib_send_wr *wr)
3226 {
3227         struct mlx5_umr_wr *umrwr = umr_wr(wr);
3228
3229         memset(umr, 0, sizeof(*umr));
3230
3231         if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3232                 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3233         else
3234                 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3235
3236         if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) {
3237                 umr->klm_octowords = get_klm_octo(umrwr->npages);
3238                 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT) {
3239                         umr->mkey_mask = get_umr_update_mtt_mask();
3240                         umr->bsf_octowords = get_klm_octo(umrwr->target.offset);
3241                         umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
3242                 }
3243                 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3244                         umr->mkey_mask |= get_umr_update_translation_mask();
3245                 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_ACCESS)
3246                         umr->mkey_mask |= get_umr_update_access_mask();
3247                 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD)
3248                         umr->mkey_mask |= get_umr_update_pd_mask();
3249                 if (!umr->mkey_mask)
3250                         umr->mkey_mask = get_umr_reg_mr_mask();
3251         } else {
3252                 umr->mkey_mask = get_umr_unreg_mr_mask();
3253         }
3254
3255         if (!wr->num_sge)
3256                 umr->flags |= MLX5_UMR_INLINE;
3257 }
3258
3259 static u8 get_umr_flags(int acc)
3260 {
3261         return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC       : 0) |
3262                (acc & IB_ACCESS_REMOTE_WRITE  ? MLX5_PERM_REMOTE_WRITE : 0) |
3263                (acc & IB_ACCESS_REMOTE_READ   ? MLX5_PERM_REMOTE_READ  : 0) |
3264                (acc & IB_ACCESS_LOCAL_WRITE   ? MLX5_PERM_LOCAL_WRITE  : 0) |
3265                 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
3266 }
3267
3268 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3269                              struct mlx5_ib_mr *mr,
3270                              u32 key, int access)
3271 {
3272         int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3273
3274         memset(seg, 0, sizeof(*seg));
3275
3276         if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
3277                 seg->log2_page_size = ilog2(mr->ibmr.page_size);
3278         else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
3279                 /* KLMs take twice the size of MTTs */
3280                 ndescs *= 2;
3281
3282         seg->flags = get_umr_flags(access) | mr->access_mode;
3283         seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3284         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3285         seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3286         seg->len = cpu_to_be64(mr->ibmr.length);
3287         seg->xlt_oct_size = cpu_to_be32(ndescs);
3288 }
3289
3290 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
3291 {
3292         memset(seg, 0, sizeof(*seg));
3293         seg->status = MLX5_MKEY_STATUS_FREE;
3294 }
3295
3296 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
3297 {
3298         struct mlx5_umr_wr *umrwr = umr_wr(wr);
3299
3300         memset(seg, 0, sizeof(*seg));
3301         if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) {
3302                 seg->status = MLX5_MKEY_STATUS_FREE;
3303                 return;
3304         }
3305
3306         seg->flags = convert_access(umrwr->access_flags);
3307         if (!(wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT)) {
3308                 if (umrwr->pd)
3309                         seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3310                 seg->start_addr = cpu_to_be64(umrwr->target.virt_addr);
3311         }
3312         seg->len = cpu_to_be64(umrwr->length);
3313         seg->log2_page_size = umrwr->page_shift;
3314         seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
3315                                        mlx5_mkey_variant(umrwr->mkey));
3316 }
3317
3318 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3319                              struct mlx5_ib_mr *mr,
3320                              struct mlx5_ib_pd *pd)
3321 {
3322         int bcount = mr->desc_size * mr->ndescs;
3323
3324         dseg->addr = cpu_to_be64(mr->desc_map);
3325         dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3326         dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3327 }
3328
3329 static __be32 send_ieth(struct ib_send_wr *wr)
3330 {
3331         switch (wr->opcode) {
3332         case IB_WR_SEND_WITH_IMM:
3333         case IB_WR_RDMA_WRITE_WITH_IMM:
3334                 return wr->ex.imm_data;
3335
3336         case IB_WR_SEND_WITH_INV:
3337                 return cpu_to_be32(wr->ex.invalidate_rkey);
3338
3339         default:
3340                 return 0;
3341         }
3342 }
3343
3344 static u8 calc_sig(void *wqe, int size)
3345 {
3346         u8 *p = wqe;
3347         u8 res = 0;
3348         int i;
3349
3350         for (i = 0; i < size; i++)
3351                 res ^= p[i];
3352
3353         return ~res;
3354 }
3355
3356 static u8 wq_sig(void *wqe)
3357 {
3358         return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3359 }
3360
3361 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
3362                             void *wqe, int *sz)
3363 {
3364         struct mlx5_wqe_inline_seg *seg;
3365         void *qend = qp->sq.qend;
3366         void *addr;
3367         int inl = 0;
3368         int copy;
3369         int len;
3370         int i;
3371
3372         seg = wqe;
3373         wqe += sizeof(*seg);
3374         for (i = 0; i < wr->num_sge; i++) {
3375                 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3376                 len  = wr->sg_list[i].length;
3377                 inl += len;
3378
3379                 if (unlikely(inl > qp->max_inline_data))
3380                         return -ENOMEM;
3381
3382                 if (unlikely(wqe + len > qend)) {
3383                         copy = qend - wqe;
3384                         memcpy(wqe, addr, copy);
3385                         addr += copy;
3386                         len -= copy;
3387                         wqe = mlx5_get_send_wqe(qp, 0);
3388                 }
3389                 memcpy(wqe, addr, len);
3390                 wqe += len;
3391         }
3392
3393         seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3394
3395         *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3396
3397         return 0;
3398 }
3399
3400 static u16 prot_field_size(enum ib_signature_type type)
3401 {
3402         switch (type) {
3403         case IB_SIG_TYPE_T10_DIF:
3404                 return MLX5_DIF_SIZE;
3405         default:
3406                 return 0;
3407         }
3408 }
3409
3410 static u8 bs_selector(int block_size)
3411 {
3412         switch (block_size) {
3413         case 512:           return 0x1;
3414         case 520:           return 0x2;
3415         case 4096:          return 0x3;
3416         case 4160:          return 0x4;
3417         case 1073741824:    return 0x5;
3418         default:            return 0;
3419         }
3420 }
3421
3422 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3423                               struct mlx5_bsf_inl *inl)
3424 {
3425         /* Valid inline section and allow BSF refresh */
3426         inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3427                                        MLX5_BSF_REFRESH_DIF);
3428         inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3429         inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
3430         /* repeating block */
3431         inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3432         inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3433                         MLX5_DIF_CRC : MLX5_DIF_IPCS;
3434
3435         if (domain->sig.dif.ref_remap)
3436                 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
3437
3438         if (domain->sig.dif.app_escape) {
3439                 if (domain->sig.dif.ref_escape)
3440                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
3441                 else
3442                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
3443         }
3444
3445         inl->dif_app_bitmask_check =
3446                 cpu_to_be16(domain->sig.dif.apptag_check_mask);
3447 }
3448
3449 static int mlx5_set_bsf(struct ib_mr *sig_mr,
3450                         struct ib_sig_attrs *sig_attrs,
3451                         struct mlx5_bsf *bsf, u32 data_size)
3452 {
3453         struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
3454         struct mlx5_bsf_basic *basic = &bsf->basic;
3455         struct ib_sig_domain *mem = &sig_attrs->mem;
3456         struct ib_sig_domain *wire = &sig_attrs->wire;
3457
3458         memset(bsf, 0, sizeof(*bsf));
3459
3460         /* Basic + Extended + Inline */
3461         basic->bsf_size_sbs = 1 << 7;
3462         /* Input domain check byte mask */
3463         basic->check_byte_mask = sig_attrs->check_mask;
3464         basic->raw_data_size = cpu_to_be32(data_size);
3465
3466         /* Memory domain */
3467         switch (sig_attrs->mem.sig_type) {
3468         case IB_SIG_TYPE_NONE:
3469                 break;
3470         case IB_SIG_TYPE_T10_DIF:
3471                 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
3472                 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
3473                 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
3474                 break;
3475         default:
3476                 return -EINVAL;
3477         }
3478
3479         /* Wire domain */
3480         switch (sig_attrs->wire.sig_type) {
3481         case IB_SIG_TYPE_NONE:
3482                 break;
3483         case IB_SIG_TYPE_T10_DIF:
3484                 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
3485                     mem->sig_type == wire->sig_type) {
3486                         /* Same block structure */
3487                         basic->bsf_size_sbs |= 1 << 4;
3488                         if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
3489                                 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
3490                         if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
3491                                 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
3492                         if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
3493                                 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
3494                 } else
3495                         basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
3496
3497                 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
3498                 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
3499                 break;
3500         default:
3501                 return -EINVAL;
3502         }
3503
3504         return 0;
3505 }
3506
3507 static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
3508                                 struct mlx5_ib_qp *qp, void **seg, int *size)
3509 {
3510         struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
3511         struct ib_mr *sig_mr = wr->sig_mr;
3512         struct mlx5_bsf *bsf;
3513         u32 data_len = wr->wr.sg_list->length;
3514         u32 data_key = wr->wr.sg_list->lkey;
3515         u64 data_va = wr->wr.sg_list->addr;
3516         int ret;
3517         int wqe_size;
3518
3519         if (!wr->prot ||
3520             (data_key == wr->prot->lkey &&
3521              data_va == wr->prot->addr &&
3522              data_len == wr->prot->length)) {
3523                 /**
3524                  * Source domain doesn't contain signature information
3525                  * or data and protection are interleaved in memory.
3526                  * So need construct:
3527                  *                  ------------------
3528                  *                 |     data_klm     |
3529                  *                  ------------------
3530                  *                 |       BSF        |
3531                  *                  ------------------
3532                  **/
3533                 struct mlx5_klm *data_klm = *seg;
3534
3535                 data_klm->bcount = cpu_to_be32(data_len);
3536                 data_klm->key = cpu_to_be32(data_key);
3537                 data_klm->va = cpu_to_be64(data_va);
3538                 wqe_size = ALIGN(sizeof(*data_klm), 64);
3539         } else {
3540                 /**
3541                  * Source domain contains signature information
3542                  * So need construct a strided block format:
3543                  *               ---------------------------
3544                  *              |     stride_block_ctrl     |
3545                  *               ---------------------------
3546                  *              |          data_klm         |
3547                  *               ---------------------------
3548                  *              |          prot_klm         |
3549                  *               ---------------------------
3550                  *              |             BSF           |
3551                  *               ---------------------------
3552                  **/
3553                 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
3554                 struct mlx5_stride_block_entry *data_sentry;
3555                 struct mlx5_stride_block_entry *prot_sentry;
3556                 u32 prot_key = wr->prot->lkey;
3557                 u64 prot_va = wr->prot->addr;
3558                 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
3559                 int prot_size;
3560
3561                 sblock_ctrl = *seg;
3562                 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
3563                 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
3564
3565                 prot_size = prot_field_size(sig_attrs->mem.sig_type);
3566                 if (!prot_size) {
3567                         pr_err("Bad block size given: %u\n", block_size);
3568                         return -EINVAL;
3569                 }
3570                 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
3571                                                             prot_size);
3572                 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
3573                 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
3574                 sblock_ctrl->num_entries = cpu_to_be16(2);
3575
3576                 data_sentry->bcount = cpu_to_be16(block_size);
3577                 data_sentry->key = cpu_to_be32(data_key);
3578                 data_sentry->va = cpu_to_be64(data_va);
3579                 data_sentry->stride = cpu_to_be16(block_size);
3580
3581                 prot_sentry->bcount = cpu_to_be16(prot_size);
3582                 prot_sentry->key = cpu_to_be32(prot_key);
3583                 prot_sentry->va = cpu_to_be64(prot_va);
3584                 prot_sentry->stride = cpu_to_be16(prot_size);
3585
3586                 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
3587                                  sizeof(*prot_sentry), 64);
3588         }
3589
3590         *seg += wqe_size;
3591         *size += wqe_size / 16;
3592         if (unlikely((*seg == qp->sq.qend)))
3593                 *seg = mlx5_get_send_wqe(qp, 0);
3594
3595         bsf = *seg;
3596         ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
3597         if (ret)
3598                 return -EINVAL;
3599
3600         *seg += sizeof(*bsf);
3601         *size += sizeof(*bsf) / 16;
3602         if (unlikely((*seg == qp->sq.qend)))
3603                 *seg = mlx5_get_send_wqe(qp, 0);
3604
3605         return 0;
3606 }
3607
3608 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
3609                                  struct ib_sig_handover_wr *wr, u32 nelements,
3610                                  u32 length, u32 pdn)
3611 {
3612         struct ib_mr *sig_mr = wr->sig_mr;
3613         u32 sig_key = sig_mr->rkey;
3614         u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
3615
3616         memset(seg, 0, sizeof(*seg));
3617
3618         seg->flags = get_umr_flags(wr->access_flags) |
3619                                    MLX5_MKC_ACCESS_MODE_KLMS;
3620         seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
3621         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
3622                                     MLX5_MKEY_BSF_EN | pdn);
3623         seg->len = cpu_to_be64(length);
3624         seg->xlt_oct_size = cpu_to_be32(be16_to_cpu(get_klm_octo(nelements)));
3625         seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
3626 }
3627
3628 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3629                                 u32 nelements)
3630 {
3631         memset(umr, 0, sizeof(*umr));
3632
3633         umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
3634         umr->klm_octowords = get_klm_octo(nelements);
3635         umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
3636         umr->mkey_mask = sig_mkey_mask();
3637 }
3638
3639
3640 static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
3641                           void **seg, int *size)
3642 {
3643         struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
3644         struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
3645         u32 pdn = get_pd(qp)->pdn;
3646         u32 klm_oct_size;
3647         int region_len, ret;
3648
3649         if (unlikely(wr->wr.num_sge != 1) ||
3650             unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
3651             unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
3652             unlikely(!sig_mr->sig->sig_status_checked))
3653                 return -EINVAL;
3654
3655         /* length of the protected region, data + protection */
3656         region_len = wr->wr.sg_list->length;
3657         if (wr->prot &&
3658             (wr->prot->lkey != wr->wr.sg_list->lkey  ||
3659              wr->prot->addr != wr->wr.sg_list->addr  ||
3660              wr->prot->length != wr->wr.sg_list->length))
3661                 region_len += wr->prot->length;
3662
3663         /**
3664          * KLM octoword size - if protection was provided
3665          * then we use strided block format (3 octowords),
3666          * else we use single KLM (1 octoword)
3667          **/
3668         klm_oct_size = wr->prot ? 3 : 1;
3669
3670         set_sig_umr_segment(*seg, klm_oct_size);
3671         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3672         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3673         if (unlikely((*seg == qp->sq.qend)))
3674                 *seg = mlx5_get_send_wqe(qp, 0);
3675
3676         set_sig_mkey_segment(*seg, wr, klm_oct_size, region_len, pdn);
3677         *seg += sizeof(struct mlx5_mkey_seg);
3678         *size += sizeof(struct mlx5_mkey_seg) / 16;
3679         if (unlikely((*seg == qp->sq.qend)))
3680                 *seg = mlx5_get_send_wqe(qp, 0);
3681
3682         ret = set_sig_data_segment(wr, qp, seg, size);
3683         if (ret)
3684                 return ret;
3685
3686         sig_mr->sig->sig_status_checked = false;
3687         return 0;
3688 }
3689
3690 static int set_psv_wr(struct ib_sig_domain *domain,
3691                       u32 psv_idx, void **seg, int *size)
3692 {
3693         struct mlx5_seg_set_psv *psv_seg = *seg;
3694
3695         memset(psv_seg, 0, sizeof(*psv_seg));
3696         psv_seg->psv_num = cpu_to_be32(psv_idx);
3697         switch (domain->sig_type) {
3698         case IB_SIG_TYPE_NONE:
3699                 break;
3700         case IB_SIG_TYPE_T10_DIF:
3701                 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
3702                                                      domain->sig.dif.app_tag);
3703                 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
3704                 break;
3705         default:
3706                 pr_err("Bad signature type given.\n");
3707                 return 1;
3708         }
3709
3710         *seg += sizeof(*psv_seg);
3711         *size += sizeof(*psv_seg) / 16;
3712
3713         return 0;
3714 }
3715
3716 static int set_reg_wr(struct mlx5_ib_qp *qp,
3717                       struct ib_reg_wr *wr,
3718                       void **seg, int *size)
3719 {
3720         struct mlx5_ib_mr *mr = to_mmr(wr->mr);
3721         struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
3722
3723         if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
3724                 mlx5_ib_warn(to_mdev(qp->ibqp.device),
3725                              "Invalid IB_SEND_INLINE send flag\n");
3726                 return -EINVAL;
3727         }
3728
3729         set_reg_umr_seg(*seg, mr);
3730         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3731         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3732         if (unlikely((*seg == qp->sq.qend)))
3733                 *seg = mlx5_get_send_wqe(qp, 0);
3734
3735         set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
3736         *seg += sizeof(struct mlx5_mkey_seg);
3737         *size += sizeof(struct mlx5_mkey_seg) / 16;
3738         if (unlikely((*seg == qp->sq.qend)))
3739                 *seg = mlx5_get_send_wqe(qp, 0);
3740
3741         set_reg_data_seg(*seg, mr, pd);
3742         *seg += sizeof(struct mlx5_wqe_data_seg);
3743         *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
3744
3745         return 0;
3746 }
3747
3748 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
3749 {
3750         set_linv_umr_seg(*seg);
3751         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3752         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3753         if (unlikely((*seg == qp->sq.qend)))
3754                 *seg = mlx5_get_send_wqe(qp, 0);
3755         set_linv_mkey_seg(*seg);
3756         *seg += sizeof(struct mlx5_mkey_seg);
3757         *size += sizeof(struct mlx5_mkey_seg) / 16;
3758         if (unlikely((*seg == qp->sq.qend)))
3759                 *seg = mlx5_get_send_wqe(qp, 0);
3760 }
3761
3762 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
3763 {
3764         __be32 *p = NULL;
3765         int tidx = idx;
3766         int i, j;
3767
3768         pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
3769         for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
3770                 if ((i & 0xf) == 0) {
3771                         void *buf = mlx5_get_send_wqe(qp, tidx);
3772                         tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
3773                         p = buf;
3774                         j = 0;
3775                 }
3776                 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
3777                          be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
3778                          be32_to_cpu(p[j + 3]));
3779         }
3780 }
3781
3782 static void mlx5_bf_copy(u64 __iomem *dst, u64 *src,
3783                          unsigned bytecnt, struct mlx5_ib_qp *qp)
3784 {
3785         while (bytecnt > 0) {
3786                 __iowrite64_copy(dst++, src++, 8);
3787                 __iowrite64_copy(dst++, src++, 8);
3788                 __iowrite64_copy(dst++, src++, 8);
3789                 __iowrite64_copy(dst++, src++, 8);
3790                 __iowrite64_copy(dst++, src++, 8);
3791                 __iowrite64_copy(dst++, src++, 8);
3792                 __iowrite64_copy(dst++, src++, 8);
3793                 __iowrite64_copy(dst++, src++, 8);
3794                 bytecnt -= 64;
3795                 if (unlikely(src == qp->sq.qend))
3796                         src = mlx5_get_send_wqe(qp, 0);
3797         }
3798 }
3799
3800 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
3801                      struct mlx5_wqe_ctrl_seg **ctrl,
3802                      struct ib_send_wr *wr, unsigned *idx,
3803                      int *size, int nreq)
3804 {
3805         if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
3806                 return -ENOMEM;
3807
3808         *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
3809         *seg = mlx5_get_send_wqe(qp, *idx);
3810         *ctrl = *seg;
3811         *(uint32_t *)(*seg + 8) = 0;
3812         (*ctrl)->imm = send_ieth(wr);
3813         (*ctrl)->fm_ce_se = qp->sq_signal_bits |
3814                 (wr->send_flags & IB_SEND_SIGNALED ?
3815                  MLX5_WQE_CTRL_CQ_UPDATE : 0) |
3816                 (wr->send_flags & IB_SEND_SOLICITED ?
3817                  MLX5_WQE_CTRL_SOLICITED : 0);
3818
3819         *seg += sizeof(**ctrl);
3820         *size = sizeof(**ctrl) / 16;
3821
3822         return 0;
3823 }
3824
3825 static void finish_wqe(struct mlx5_ib_qp *qp,
3826                        struct mlx5_wqe_ctrl_seg *ctrl,
3827                        u8 size, unsigned idx, u64 wr_id,
3828                        int nreq, u8 fence, u32 mlx5_opcode)
3829 {
3830         u8 opmod = 0;
3831
3832         ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
3833                                              mlx5_opcode | ((u32)opmod << 24));
3834         ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
3835         ctrl->fm_ce_se |= fence;
3836         if (unlikely(qp->wq_sig))
3837                 ctrl->signature = wq_sig(ctrl);
3838
3839         qp->sq.wrid[idx] = wr_id;
3840         qp->sq.w_list[idx].opcode = mlx5_opcode;
3841         qp->sq.wqe_head[idx] = qp->sq.head + nreq;
3842         qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
3843         qp->sq.w_list[idx].next = qp->sq.cur_post;
3844 }
3845
3846
3847 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3848                       struct ib_send_wr **bad_wr)
3849 {
3850         struct mlx5_wqe_ctrl_seg *ctrl = NULL;  /* compiler warning */
3851         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3852         struct mlx5_core_dev *mdev = dev->mdev;
3853         struct mlx5_ib_qp *qp;
3854         struct mlx5_ib_mr *mr;
3855         struct mlx5_wqe_data_seg *dpseg;
3856         struct mlx5_wqe_xrc_seg *xrc;
3857         struct mlx5_bf *bf;
3858         int uninitialized_var(size);
3859         void *qend;
3860         unsigned long flags;
3861         unsigned idx;
3862         int err = 0;
3863         int inl = 0;
3864         int num_sge;
3865         void *seg;
3866         int nreq;
3867         int i;
3868         u8 next_fence = 0;
3869         u8 fence;
3870
3871         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3872                 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
3873
3874         qp = to_mqp(ibqp);
3875         bf = qp->bf;
3876         qend = qp->sq.qend;
3877
3878         spin_lock_irqsave(&qp->sq.lock, flags);
3879
3880         if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
3881                 err = -EIO;
3882                 *bad_wr = wr;
3883                 nreq = 0;
3884                 goto out;
3885         }
3886
3887         for (nreq = 0; wr; nreq++, wr = wr->next) {
3888                 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
3889                         mlx5_ib_warn(dev, "\n");
3890                         err = -EINVAL;
3891                         *bad_wr = wr;
3892                         goto out;
3893                 }
3894
3895                 num_sge = wr->num_sge;
3896                 if (unlikely(num_sge > qp->sq.max_gs)) {
3897                         mlx5_ib_warn(dev, "\n");
3898                         err = -EINVAL;
3899                         *bad_wr = wr;
3900                         goto out;
3901                 }
3902
3903                 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
3904                 if (err) {
3905                         mlx5_ib_warn(dev, "\n");
3906                         err = -ENOMEM;
3907                         *bad_wr = wr;
3908                         goto out;
3909                 }
3910
3911                 if (wr->opcode == IB_WR_REG_MR) {
3912                         fence = dev->umr_fence;
3913                         next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3914                 } else  {
3915                         if (wr->send_flags & IB_SEND_FENCE) {
3916                                 if (qp->next_fence)
3917                                         fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
3918                                 else
3919                                         fence = MLX5_FENCE_MODE_FENCE;
3920                         } else {
3921                                 fence = qp->next_fence;
3922                         }
3923                 }
3924
3925                 switch (ibqp->qp_type) {
3926                 case IB_QPT_XRC_INI:
3927                         xrc = seg;
3928                         seg += sizeof(*xrc);
3929                         size += sizeof(*xrc) / 16;
3930                         /* fall through */
3931                 case IB_QPT_RC:
3932                         switch (wr->opcode) {
3933                         case IB_WR_RDMA_READ:
3934                         case IB_WR_RDMA_WRITE:
3935                         case IB_WR_RDMA_WRITE_WITH_IMM:
3936                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3937                                               rdma_wr(wr)->rkey);
3938                                 seg += sizeof(struct mlx5_wqe_raddr_seg);
3939                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3940                                 break;
3941
3942                         case IB_WR_ATOMIC_CMP_AND_SWP:
3943                         case IB_WR_ATOMIC_FETCH_AND_ADD:
3944                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
3945                                 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
3946                                 err = -ENOSYS;
3947                                 *bad_wr = wr;
3948                                 goto out;
3949
3950                         case IB_WR_LOCAL_INV:
3951                                 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
3952                                 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
3953                                 set_linv_wr(qp, &seg, &size);
3954                                 num_sge = 0;
3955                                 break;
3956
3957                         case IB_WR_REG_MR:
3958                                 qp->sq.wr_data[idx] = IB_WR_REG_MR;
3959                                 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
3960                                 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
3961                                 if (err) {
3962                                         *bad_wr = wr;
3963                                         goto out;
3964                                 }
3965                                 num_sge = 0;
3966                                 break;
3967
3968                         case IB_WR_REG_SIG_MR:
3969                                 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
3970                                 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
3971
3972                                 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
3973                                 err = set_sig_umr_wr(wr, qp, &seg, &size);
3974                                 if (err) {
3975                                         mlx5_ib_warn(dev, "\n");
3976                                         *bad_wr = wr;
3977                                         goto out;
3978                                 }
3979
3980                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
3981                                            fence, MLX5_OPCODE_UMR);
3982                                 /*
3983                                  * SET_PSV WQEs are not signaled and solicited
3984                                  * on error
3985                                  */
3986                                 wr->send_flags &= ~IB_SEND_SIGNALED;
3987                                 wr->send_flags |= IB_SEND_SOLICITED;
3988                                 err = begin_wqe(qp, &seg, &ctrl, wr,
3989                                                 &idx, &size, nreq);
3990                                 if (err) {
3991                                         mlx5_ib_warn(dev, "\n");
3992                                         err = -ENOMEM;
3993                                         *bad_wr = wr;
3994                                         goto out;
3995                                 }
3996
3997                                 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
3998                                                  mr->sig->psv_memory.psv_idx, &seg,
3999                                                  &size);
4000                                 if (err) {
4001                                         mlx5_ib_warn(dev, "\n");
4002                                         *bad_wr = wr;
4003                                         goto out;
4004                                 }
4005
4006                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4007                                            fence, MLX5_OPCODE_SET_PSV);
4008                                 err = begin_wqe(qp, &seg, &ctrl, wr,
4009                                                 &idx, &size, nreq);
4010                                 if (err) {
4011                                         mlx5_ib_warn(dev, "\n");
4012                                         err = -ENOMEM;
4013                                         *bad_wr = wr;
4014                                         goto out;
4015                                 }
4016
4017                                 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
4018                                                  mr->sig->psv_wire.psv_idx, &seg,
4019                                                  &size);
4020                                 if (err) {
4021                                         mlx5_ib_warn(dev, "\n");
4022                                         *bad_wr = wr;
4023                                         goto out;
4024                                 }
4025
4026                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4027                                            fence, MLX5_OPCODE_SET_PSV);
4028                                 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4029                                 num_sge = 0;
4030                                 goto skip_psv;
4031
4032                         default:
4033                                 break;
4034                         }
4035                         break;
4036
4037                 case IB_QPT_UC:
4038                         switch (wr->opcode) {
4039                         case IB_WR_RDMA_WRITE:
4040                         case IB_WR_RDMA_WRITE_WITH_IMM:
4041                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4042                                               rdma_wr(wr)->rkey);
4043                                 seg  += sizeof(struct mlx5_wqe_raddr_seg);
4044                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4045                                 break;
4046
4047                         default:
4048                                 break;
4049                         }
4050                         break;
4051
4052                 case IB_QPT_SMI:
4053                 case MLX5_IB_QPT_HW_GSI:
4054                         set_datagram_seg(seg, wr);
4055                         seg += sizeof(struct mlx5_wqe_datagram_seg);
4056                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4057                         if (unlikely((seg == qend)))
4058                                 seg = mlx5_get_send_wqe(qp, 0);
4059                         break;
4060                 case IB_QPT_UD:
4061                         set_datagram_seg(seg, wr);
4062                         seg += sizeof(struct mlx5_wqe_datagram_seg);
4063                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4064
4065                         if (unlikely((seg == qend)))
4066                                 seg = mlx5_get_send_wqe(qp, 0);
4067
4068                         /* handle qp that supports ud offload */
4069                         if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
4070                                 struct mlx5_wqe_eth_pad *pad;
4071
4072                                 pad = seg;
4073                                 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4074                                 seg += sizeof(struct mlx5_wqe_eth_pad);
4075                                 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
4076
4077                                 seg = set_eth_seg(seg, wr, qend, qp, &size);
4078
4079                                 if (unlikely((seg == qend)))
4080                                         seg = mlx5_get_send_wqe(qp, 0);
4081                         }
4082                         break;
4083                 case MLX5_IB_QPT_REG_UMR:
4084                         if (wr->opcode != MLX5_IB_WR_UMR) {
4085                                 err = -EINVAL;
4086                                 mlx5_ib_warn(dev, "bad opcode\n");
4087                                 goto out;
4088                         }
4089                         qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
4090                         ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
4091                         set_reg_umr_segment(seg, wr);
4092                         seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4093                         size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4094                         if (unlikely((seg == qend)))
4095                                 seg = mlx5_get_send_wqe(qp, 0);
4096                         set_reg_mkey_segment(seg, wr);
4097                         seg += sizeof(struct mlx5_mkey_seg);
4098                         size += sizeof(struct mlx5_mkey_seg) / 16;
4099                         if (unlikely((seg == qend)))
4100                                 seg = mlx5_get_send_wqe(qp, 0);
4101                         break;
4102
4103                 default:
4104                         break;
4105                 }
4106
4107                 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
4108                         int uninitialized_var(sz);
4109
4110                         err = set_data_inl_seg(qp, wr, seg, &sz);
4111                         if (unlikely(err)) {
4112                                 mlx5_ib_warn(dev, "\n");
4113                                 *bad_wr = wr;
4114                                 goto out;
4115                         }
4116                         inl = 1;
4117                         size += sz;
4118                 } else {
4119                         dpseg = seg;
4120                         for (i = 0; i < num_sge; i++) {
4121                                 if (unlikely(dpseg == qend)) {
4122                                         seg = mlx5_get_send_wqe(qp, 0);
4123                                         dpseg = seg;
4124                                 }
4125                                 if (likely(wr->sg_list[i].length)) {
4126                                         set_data_ptr_seg(dpseg, wr->sg_list + i);
4127                                         size += sizeof(struct mlx5_wqe_data_seg) / 16;
4128                                         dpseg++;
4129                                 }
4130                         }
4131                 }
4132
4133                 qp->next_fence = next_fence;
4134                 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, fence,
4135                            mlx5_ib_opcode[wr->opcode]);
4136 skip_psv:
4137                 if (0)
4138                         dump_wqe(qp, idx, size);
4139         }
4140
4141 out:
4142         if (likely(nreq)) {
4143                 qp->sq.head += nreq;
4144
4145                 /* Make sure that descriptors are written before
4146                  * updating doorbell record and ringing the doorbell
4147                  */
4148                 wmb();
4149
4150                 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4151
4152                 /* Make sure doorbell record is visible to the HCA before
4153                  * we hit doorbell */
4154                 wmb();
4155
4156                 if (bf->need_lock)
4157                         spin_lock(&bf->lock);
4158                 else
4159                         __acquire(&bf->lock);
4160
4161                 /* TBD enable WC */
4162                 if (0 && nreq == 1 && bf->uuarn && inl && size > 1 && size <= bf->buf_size / 16) {
4163                         mlx5_bf_copy(bf->reg + bf->offset, (u64 *)ctrl, ALIGN(size * 16, 64), qp);
4164                         /* wc_wmb(); */
4165                 } else {
4166                         mlx5_write64((__be32 *)ctrl, bf->regreg + bf->offset,
4167                                      MLX5_GET_DOORBELL_LOCK(&bf->lock32));
4168                         /* Make sure doorbells don't leak out of SQ spinlock
4169                          * and reach the HCA out of order.
4170                          */
4171                         mmiowb();
4172                 }
4173                 bf->offset ^= bf->buf_size;
4174                 if (bf->need_lock)
4175                         spin_unlock(&bf->lock);
4176                 else
4177                         __release(&bf->lock);
4178         }
4179
4180         spin_unlock_irqrestore(&qp->sq.lock, flags);
4181
4182         return err;
4183 }
4184
4185 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4186 {
4187         sig->signature = calc_sig(sig, size);
4188 }
4189
4190 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
4191                       struct ib_recv_wr **bad_wr)
4192 {
4193         struct mlx5_ib_qp *qp = to_mqp(ibqp);
4194         struct mlx5_wqe_data_seg *scat;
4195         struct mlx5_rwqe_sig *sig;
4196         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4197         struct mlx5_core_dev *mdev = dev->mdev;
4198         unsigned long flags;
4199         int err = 0;
4200         int nreq;
4201         int ind;
4202         int i;
4203
4204         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4205                 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4206
4207         spin_lock_irqsave(&qp->rq.lock, flags);
4208
4209         if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4210                 err = -EIO;
4211                 *bad_wr = wr;
4212                 nreq = 0;
4213                 goto out;
4214         }
4215
4216         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4217
4218         for (nreq = 0; wr; nreq++, wr = wr->next) {
4219                 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4220                         err = -ENOMEM;
4221                         *bad_wr = wr;
4222                         goto out;
4223                 }
4224
4225                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4226                         err = -EINVAL;
4227                         *bad_wr = wr;
4228                         goto out;
4229                 }
4230
4231                 scat = get_recv_wqe(qp, ind);
4232                 if (qp->wq_sig)
4233                         scat++;
4234
4235                 for (i = 0; i < wr->num_sge; i++)
4236                         set_data_ptr_seg(scat + i, wr->sg_list + i);
4237
4238                 if (i < qp->rq.max_gs) {
4239                         scat[i].byte_count = 0;
4240                         scat[i].lkey       = cpu_to_be32(MLX5_INVALID_LKEY);
4241                         scat[i].addr       = 0;
4242                 }
4243
4244                 if (qp->wq_sig) {
4245                         sig = (struct mlx5_rwqe_sig *)scat;
4246                         set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4247                 }
4248
4249                 qp->rq.wrid[ind] = wr->wr_id;
4250
4251                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4252         }
4253
4254 out:
4255         if (likely(nreq)) {
4256                 qp->rq.head += nreq;
4257
4258                 /* Make sure that descriptors are written before
4259                  * doorbell record.
4260                  */
4261                 wmb();
4262
4263                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4264         }
4265
4266         spin_unlock_irqrestore(&qp->rq.lock, flags);
4267
4268         return err;
4269 }
4270
4271 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4272 {
4273         switch (mlx5_state) {
4274         case MLX5_QP_STATE_RST:      return IB_QPS_RESET;
4275         case MLX5_QP_STATE_INIT:     return IB_QPS_INIT;
4276         case MLX5_QP_STATE_RTR:      return IB_QPS_RTR;
4277         case MLX5_QP_STATE_RTS:      return IB_QPS_RTS;
4278         case MLX5_QP_STATE_SQ_DRAINING:
4279         case MLX5_QP_STATE_SQD:      return IB_QPS_SQD;
4280         case MLX5_QP_STATE_SQER:     return IB_QPS_SQE;
4281         case MLX5_QP_STATE_ERR:      return IB_QPS_ERR;
4282         default:                     return -1;
4283         }
4284 }
4285
4286 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4287 {
4288         switch (mlx5_mig_state) {
4289         case MLX5_QP_PM_ARMED:          return IB_MIG_ARMED;
4290         case MLX5_QP_PM_REARM:          return IB_MIG_REARM;
4291         case MLX5_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
4292         default: return -1;
4293         }
4294 }
4295
4296 static int to_ib_qp_access_flags(int mlx5_flags)
4297 {
4298         int ib_flags = 0;
4299
4300         if (mlx5_flags & MLX5_QP_BIT_RRE)
4301                 ib_flags |= IB_ACCESS_REMOTE_READ;
4302         if (mlx5_flags & MLX5_QP_BIT_RWE)
4303                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4304         if (mlx5_flags & MLX5_QP_BIT_RAE)
4305                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4306
4307         return ib_flags;
4308 }
4309
4310 static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
4311                                 struct mlx5_qp_path *path)
4312 {
4313         struct mlx5_core_dev *dev = ibdev->mdev;
4314
4315         memset(ib_ah_attr, 0, sizeof(*ib_ah_attr));
4316         ib_ah_attr->port_num      = path->port;
4317
4318         if (ib_ah_attr->port_num == 0 ||
4319             ib_ah_attr->port_num > MLX5_CAP_GEN(dev, num_ports))
4320                 return;
4321
4322         ib_ah_attr->sl = path->dci_cfi_prio_sl & 0xf;
4323
4324         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
4325         ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f;
4326         ib_ah_attr->static_rate   = path->static_rate ? path->static_rate - 5 : 0;
4327         ib_ah_attr->ah_flags      = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0;
4328         if (ib_ah_attr->ah_flags) {
4329                 ib_ah_attr->grh.sgid_index = path->mgid_index;
4330                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
4331                 ib_ah_attr->grh.traffic_class =
4332                         (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
4333                 ib_ah_attr->grh.flow_label =
4334                         be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
4335                 memcpy(ib_ah_attr->grh.dgid.raw,
4336                        path->rgid, sizeof(ib_ah_attr->grh.dgid.raw));
4337         }
4338 }
4339
4340 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4341                                         struct mlx5_ib_sq *sq,
4342                                         u8 *sq_state)
4343 {
4344         void *out;
4345         void *sqc;
4346         int inlen;
4347         int err;
4348
4349         inlen = MLX5_ST_SZ_BYTES(query_sq_out);
4350         out = mlx5_vzalloc(inlen);
4351         if (!out)
4352                 return -ENOMEM;
4353
4354         err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out);
4355         if (err)
4356                 goto out;
4357
4358         sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context);
4359         *sq_state = MLX5_GET(sqc, sqc, state);
4360         sq->state = *sq_state;
4361
4362 out:
4363         kvfree(out);
4364         return err;
4365 }
4366
4367 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4368                                         struct mlx5_ib_rq *rq,
4369                                         u8 *rq_state)
4370 {
4371         void *out;
4372         void *rqc;
4373         int inlen;
4374         int err;
4375
4376         inlen = MLX5_ST_SZ_BYTES(query_rq_out);
4377         out = mlx5_vzalloc(inlen);
4378         if (!out)
4379                 return -ENOMEM;
4380
4381         err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4382         if (err)
4383                 goto out;
4384
4385         rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4386         *rq_state = MLX5_GET(rqc, rqc, state);
4387         rq->state = *rq_state;
4388
4389 out:
4390         kvfree(out);
4391         return err;
4392 }
4393
4394 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4395                                   struct mlx5_ib_qp *qp, u8 *qp_state)
4396 {
4397         static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4398                 [MLX5_RQC_STATE_RST] = {
4399                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
4400                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
4401                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE_BAD,
4402                         [MLX5_SQ_STATE_NA]      = IB_QPS_RESET,
4403                 },
4404                 [MLX5_RQC_STATE_RDY] = {
4405                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
4406                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
4407                         [MLX5_SQC_STATE_ERR]    = IB_QPS_SQE,
4408                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE,
4409                 },
4410                 [MLX5_RQC_STATE_ERR] = {
4411                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
4412                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
4413                         [MLX5_SQC_STATE_ERR]    = IB_QPS_ERR,
4414                         [MLX5_SQ_STATE_NA]      = IB_QPS_ERR,
4415                 },
4416                 [MLX5_RQ_STATE_NA] = {
4417                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
4418                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
4419                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE,
4420                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE_BAD,
4421                 },
4422         };
4423
4424         *qp_state = sqrq_trans[rq_state][sq_state];
4425
4426         if (*qp_state == MLX5_QP_STATE_BAD) {
4427                 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4428                      qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4429                      qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4430                 return -EINVAL;
4431         }
4432
4433         if (*qp_state == MLX5_QP_STATE)
4434                 *qp_state = qp->state;
4435
4436         return 0;
4437 }
4438
4439 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4440                                      struct mlx5_ib_qp *qp,
4441                                      u8 *raw_packet_qp_state)
4442 {
4443         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4444         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4445         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4446         int err;
4447         u8 sq_state = MLX5_SQ_STATE_NA;
4448         u8 rq_state = MLX5_RQ_STATE_NA;
4449
4450         if (qp->sq.wqe_cnt) {
4451                 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4452                 if (err)
4453                         return err;
4454         }
4455
4456         if (qp->rq.wqe_cnt) {
4457                 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4458                 if (err)
4459                         return err;
4460         }
4461
4462         return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4463                                       raw_packet_qp_state);
4464 }
4465
4466 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4467                          struct ib_qp_attr *qp_attr)
4468 {
4469         int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
4470         struct mlx5_qp_context *context;
4471         int mlx5_state;
4472         u32 *outb;
4473         int err = 0;
4474
4475         outb = kzalloc(outlen, GFP_KERNEL);
4476         if (!outb)
4477                 return -ENOMEM;
4478
4479         err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
4480                                  outlen);
4481         if (err)
4482                 goto out;
4483
4484         /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
4485         context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
4486
4487         mlx5_state = be32_to_cpu(context->flags) >> 28;
4488
4489         qp->state                    = to_ib_qp_state(mlx5_state);
4490         qp_attr->path_mtu            = context->mtu_msgmax >> 5;
4491         qp_attr->path_mig_state      =
4492                 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
4493         qp_attr->qkey                = be32_to_cpu(context->qkey);
4494         qp_attr->rq_psn              = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
4495         qp_attr->sq_psn              = be32_to_cpu(context->next_send_psn) & 0xffffff;
4496         qp_attr->dest_qp_num         = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
4497         qp_attr->qp_access_flags     =
4498                 to_ib_qp_access_flags(be32_to_cpu(context->params2));
4499
4500         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4501                 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
4502                 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
4503                 qp_attr->alt_pkey_index =
4504                         be16_to_cpu(context->alt_path.pkey_index);
4505                 qp_attr->alt_port_num   = qp_attr->alt_ah_attr.port_num;
4506         }
4507
4508         qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
4509         qp_attr->port_num = context->pri_path.port;
4510
4511         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4512         qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
4513
4514         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
4515
4516         qp_attr->max_dest_rd_atomic =
4517                 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
4518         qp_attr->min_rnr_timer      =
4519                 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
4520         qp_attr->timeout            = context->pri_path.ackto_lt >> 3;
4521         qp_attr->retry_cnt          = (be32_to_cpu(context->params1) >> 16) & 0x7;
4522         qp_attr->rnr_retry          = (be32_to_cpu(context->params1) >> 13) & 0x7;
4523         qp_attr->alt_timeout        = context->alt_path.ackto_lt >> 3;
4524
4525 out:
4526         kfree(outb);
4527         return err;
4528 }
4529
4530 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4531                      int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4532 {
4533         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4534         struct mlx5_ib_qp *qp = to_mqp(ibqp);
4535         int err = 0;
4536         u8 raw_packet_qp_state;
4537
4538         if (ibqp->rwq_ind_tbl)
4539                 return -ENOSYS;
4540
4541         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4542                 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4543                                             qp_init_attr);
4544
4545 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4546         /*
4547          * Wait for any outstanding page faults, in case the user frees memory
4548          * based upon this query's result.
4549          */
4550         flush_workqueue(mlx5_ib_page_fault_wq);
4551 #endif
4552
4553         mutex_lock(&qp->mutex);
4554
4555         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
4556                 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4557                 if (err)
4558                         goto out;
4559                 qp->state = raw_packet_qp_state;
4560                 qp_attr->port_num = 1;
4561         } else {
4562                 err = query_qp_attr(dev, qp, qp_attr);
4563                 if (err)
4564                         goto out;
4565         }
4566
4567         qp_attr->qp_state            = qp->state;
4568         qp_attr->cur_qp_state        = qp_attr->qp_state;
4569         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
4570         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
4571
4572         if (!ibqp->uobject) {
4573                 qp_attr->cap.max_send_wr  = qp->sq.max_post;
4574                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
4575                 qp_init_attr->qp_context = ibqp->qp_context;
4576         } else {
4577                 qp_attr->cap.max_send_wr  = 0;
4578                 qp_attr->cap.max_send_sge = 0;
4579         }
4580
4581         qp_init_attr->qp_type = ibqp->qp_type;
4582         qp_init_attr->recv_cq = ibqp->recv_cq;
4583         qp_init_attr->send_cq = ibqp->send_cq;
4584         qp_init_attr->srq = ibqp->srq;
4585         qp_attr->cap.max_inline_data = qp->max_inline_data;
4586
4587         qp_init_attr->cap            = qp_attr->cap;
4588
4589         qp_init_attr->create_flags = 0;
4590         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4591                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4592
4593         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
4594                 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
4595         if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
4596                 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
4597         if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
4598                 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
4599         if (qp->flags & MLX5_IB_QP_SQPN_QP1)
4600                 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
4601
4602         qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
4603                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4604
4605 out:
4606         mutex_unlock(&qp->mutex);
4607         return err;
4608 }
4609
4610 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
4611                                           struct ib_ucontext *context,
4612                                           struct ib_udata *udata)
4613 {
4614         struct mlx5_ib_dev *dev = to_mdev(ibdev);
4615         struct mlx5_ib_xrcd *xrcd;
4616         int err;
4617
4618         if (!MLX5_CAP_GEN(dev->mdev, xrc))
4619                 return ERR_PTR(-ENOSYS);
4620
4621         xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
4622         if (!xrcd)
4623                 return ERR_PTR(-ENOMEM);
4624
4625         err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
4626         if (err) {
4627                 kfree(xrcd);
4628                 return ERR_PTR(-ENOMEM);
4629         }
4630
4631         return &xrcd->ibxrcd;
4632 }
4633
4634 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
4635 {
4636         struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
4637         u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
4638         int err;
4639
4640         err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
4641         if (err)
4642                 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
4643
4644         kfree(xrcd);
4645         return 0;
4646 }
4647
4648 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
4649 {
4650         struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
4651         struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
4652         struct ib_event event;
4653
4654         if (rwq->ibwq.event_handler) {
4655                 event.device     = rwq->ibwq.device;
4656                 event.element.wq = &rwq->ibwq;
4657                 switch (type) {
4658                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
4659                         event.event = IB_EVENT_WQ_FATAL;
4660                         break;
4661                 default:
4662                         mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
4663                         return;
4664                 }
4665
4666                 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
4667         }
4668 }
4669
4670 static int  create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
4671                       struct ib_wq_init_attr *init_attr)
4672 {
4673         struct mlx5_ib_dev *dev;
4674         __be64 *rq_pas0;
4675         void *in;
4676         void *rqc;
4677         void *wq;
4678         int inlen;
4679         int err;
4680
4681         dev = to_mdev(pd->device);
4682
4683         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
4684         in = mlx5_vzalloc(inlen);
4685         if (!in)
4686                 return -ENOMEM;
4687
4688         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
4689         MLX5_SET(rqc,  rqc, mem_rq_type,
4690                  MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
4691         MLX5_SET(rqc, rqc, user_index, rwq->user_index);
4692         MLX5_SET(rqc,  rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
4693         MLX5_SET(rqc,  rqc, state, MLX5_RQC_STATE_RST);
4694         MLX5_SET(rqc,  rqc, flush_in_error_en, 1);
4695         wq = MLX5_ADDR_OF(rqc, rqc, wq);
4696         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
4697         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
4698         MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
4699         MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
4700         MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
4701         MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
4702         MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
4703         MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
4704         MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4705         rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
4706         mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
4707         err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
4708         kvfree(in);
4709         return err;
4710 }
4711
4712 static int set_user_rq_size(struct mlx5_ib_dev *dev,
4713                             struct ib_wq_init_attr *wq_init_attr,
4714                             struct mlx5_ib_create_wq *ucmd,
4715                             struct mlx5_ib_rwq *rwq)
4716 {
4717         /* Sanity check RQ size before proceeding */
4718         if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
4719                 return -EINVAL;
4720
4721         if (!ucmd->rq_wqe_count)
4722                 return -EINVAL;
4723
4724         rwq->wqe_count = ucmd->rq_wqe_count;
4725         rwq->wqe_shift = ucmd->rq_wqe_shift;
4726         rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift);
4727         rwq->log_rq_stride = rwq->wqe_shift;
4728         rwq->log_rq_size = ilog2(rwq->wqe_count);
4729         return 0;
4730 }
4731
4732 static int prepare_user_rq(struct ib_pd *pd,
4733                            struct ib_wq_init_attr *init_attr,
4734                            struct ib_udata *udata,
4735                            struct mlx5_ib_rwq *rwq)
4736 {
4737         struct mlx5_ib_dev *dev = to_mdev(pd->device);
4738         struct mlx5_ib_create_wq ucmd = {};
4739         int err;
4740         size_t required_cmd_sz;
4741
4742         required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4743         if (udata->inlen < required_cmd_sz) {
4744                 mlx5_ib_dbg(dev, "invalid inlen\n");
4745                 return -EINVAL;
4746         }
4747
4748         if (udata->inlen > sizeof(ucmd) &&
4749             !ib_is_udata_cleared(udata, sizeof(ucmd),
4750                                  udata->inlen - sizeof(ucmd))) {
4751                 mlx5_ib_dbg(dev, "inlen is not supported\n");
4752                 return -EOPNOTSUPP;
4753         }
4754
4755         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
4756                 mlx5_ib_dbg(dev, "copy failed\n");
4757                 return -EFAULT;
4758         }
4759
4760         if (ucmd.comp_mask) {
4761                 mlx5_ib_dbg(dev, "invalid comp mask\n");
4762                 return -EOPNOTSUPP;
4763         }
4764
4765         if (ucmd.reserved) {
4766                 mlx5_ib_dbg(dev, "invalid reserved\n");
4767                 return -EOPNOTSUPP;
4768         }
4769
4770         err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
4771         if (err) {
4772                 mlx5_ib_dbg(dev, "err %d\n", err);
4773                 return err;
4774         }
4775
4776         err = create_user_rq(dev, pd, rwq, &ucmd);
4777         if (err) {
4778                 mlx5_ib_dbg(dev, "err %d\n", err);
4779                 if (err)
4780                         return err;
4781         }
4782
4783         rwq->user_index = ucmd.user_index;
4784         return 0;
4785 }
4786
4787 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
4788                                 struct ib_wq_init_attr *init_attr,
4789                                 struct ib_udata *udata)
4790 {
4791         struct mlx5_ib_dev *dev;
4792         struct mlx5_ib_rwq *rwq;
4793         struct mlx5_ib_create_wq_resp resp = {};
4794         size_t min_resp_len;
4795         int err;
4796
4797         if (!udata)
4798                 return ERR_PTR(-ENOSYS);
4799
4800         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4801         if (udata->outlen && udata->outlen < min_resp_len)
4802                 return ERR_PTR(-EINVAL);
4803
4804         dev = to_mdev(pd->device);
4805         switch (init_attr->wq_type) {
4806         case IB_WQT_RQ:
4807                 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
4808                 if (!rwq)
4809                         return ERR_PTR(-ENOMEM);
4810                 err = prepare_user_rq(pd, init_attr, udata, rwq);
4811                 if (err)
4812                         goto err;
4813                 err = create_rq(rwq, pd, init_attr);
4814                 if (err)
4815                         goto err_user_rq;
4816                 break;
4817         default:
4818                 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
4819                             init_attr->wq_type);
4820                 return ERR_PTR(-EINVAL);
4821         }
4822
4823         rwq->ibwq.wq_num = rwq->core_qp.qpn;
4824         rwq->ibwq.state = IB_WQS_RESET;
4825         if (udata->outlen) {
4826                 resp.response_length = offsetof(typeof(resp), response_length) +
4827                                 sizeof(resp.response_length);
4828                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4829                 if (err)
4830                         goto err_copy;
4831         }
4832
4833         rwq->core_qp.event = mlx5_ib_wq_event;
4834         rwq->ibwq.event_handler = init_attr->event_handler;
4835         return &rwq->ibwq;
4836
4837 err_copy:
4838         mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
4839 err_user_rq:
4840         destroy_user_rq(pd, rwq);
4841 err:
4842         kfree(rwq);
4843         return ERR_PTR(err);
4844 }
4845
4846 int mlx5_ib_destroy_wq(struct ib_wq *wq)
4847 {
4848         struct mlx5_ib_dev *dev = to_mdev(wq->device);
4849         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4850
4851         mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
4852         destroy_user_rq(wq->pd, rwq);
4853         kfree(rwq);
4854
4855         return 0;
4856 }
4857
4858 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
4859                                                       struct ib_rwq_ind_table_init_attr *init_attr,
4860                                                       struct ib_udata *udata)
4861 {
4862         struct mlx5_ib_dev *dev = to_mdev(device);
4863         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
4864         int sz = 1 << init_attr->log_ind_tbl_size;
4865         struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
4866         size_t min_resp_len;
4867         int inlen;
4868         int err;
4869         int i;
4870         u32 *in;
4871         void *rqtc;
4872
4873         if (udata->inlen > 0 &&
4874             !ib_is_udata_cleared(udata, 0,
4875                                  udata->inlen))
4876                 return ERR_PTR(-EOPNOTSUPP);
4877
4878         if (init_attr->log_ind_tbl_size >
4879             MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
4880                 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
4881                             init_attr->log_ind_tbl_size,
4882                             MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
4883                 return ERR_PTR(-EINVAL);
4884         }
4885
4886         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4887         if (udata->outlen && udata->outlen < min_resp_len)
4888                 return ERR_PTR(-EINVAL);
4889
4890         rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
4891         if (!rwq_ind_tbl)
4892                 return ERR_PTR(-ENOMEM);
4893
4894         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
4895         in = mlx5_vzalloc(inlen);
4896         if (!in) {
4897                 err = -ENOMEM;
4898                 goto err;
4899         }
4900
4901         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
4902
4903         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
4904         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
4905
4906         for (i = 0; i < sz; i++)
4907                 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
4908
4909         err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
4910         kvfree(in);
4911
4912         if (err)
4913                 goto err;
4914
4915         rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
4916         if (udata->outlen) {
4917                 resp.response_length = offsetof(typeof(resp), response_length) +
4918                                         sizeof(resp.response_length);
4919                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4920                 if (err)
4921                         goto err_copy;
4922         }
4923
4924         return &rwq_ind_tbl->ib_rwq_ind_tbl;
4925
4926 err_copy:
4927         mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4928 err:
4929         kfree(rwq_ind_tbl);
4930         return ERR_PTR(err);
4931 }
4932
4933 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
4934 {
4935         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
4936         struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
4937
4938         mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4939
4940         kfree(rwq_ind_tbl);
4941         return 0;
4942 }
4943
4944 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
4945                       u32 wq_attr_mask, struct ib_udata *udata)
4946 {
4947         struct mlx5_ib_dev *dev = to_mdev(wq->device);
4948         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4949         struct mlx5_ib_modify_wq ucmd = {};
4950         size_t required_cmd_sz;
4951         int curr_wq_state;
4952         int wq_state;
4953         int inlen;
4954         int err;
4955         void *rqc;
4956         void *in;
4957
4958         required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4959         if (udata->inlen < required_cmd_sz)
4960                 return -EINVAL;
4961
4962         if (udata->inlen > sizeof(ucmd) &&
4963             !ib_is_udata_cleared(udata, sizeof(ucmd),
4964                                  udata->inlen - sizeof(ucmd)))
4965                 return -EOPNOTSUPP;
4966
4967         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4968                 return -EFAULT;
4969
4970         if (ucmd.comp_mask || ucmd.reserved)
4971                 return -EOPNOTSUPP;
4972
4973         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
4974         in = mlx5_vzalloc(inlen);
4975         if (!in)
4976                 return -ENOMEM;
4977
4978         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
4979
4980         curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
4981                 wq_attr->curr_wq_state : wq->state;
4982         wq_state = (wq_attr_mask & IB_WQ_STATE) ?
4983                 wq_attr->wq_state : curr_wq_state;
4984         if (curr_wq_state == IB_WQS_ERR)
4985                 curr_wq_state = MLX5_RQC_STATE_ERR;
4986         if (wq_state == IB_WQS_ERR)
4987                 wq_state = MLX5_RQC_STATE_ERR;
4988         MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
4989         MLX5_SET(rqc, rqc, state, wq_state);
4990
4991         err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
4992         kvfree(in);
4993         if (!err)
4994                 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
4995
4996         return err;
4997 }