drivers/infiniband/hw/mlx5/qp.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34 #include <rdma/ib_umem.h>
  35 #include "mlx5_ib.h"
  36 #include "user.h"
  37
  38 /* not supported currently */
  39 static int wq_signature;
  40
  41 enum {
  42         MLX5_IB_ACK_REQ_FREQ    = 8,
  43 };
  44
  45 enum {
  46         MLX5_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  47         MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  48         MLX5_IB_LINK_TYPE_IB            = 0,
  49         MLX5_IB_LINK_TYPE_ETH           = 1
  50 };
  51
  52 enum {
  53         MLX5_IB_SQ_STRIDE       = 6,
  54         MLX5_IB_CACHE_LINE_SIZE = 64,
  55 };
  56
  57 static const u32 mlx5_ib_opcode[] = {
  58         [IB_WR_SEND]                            = MLX5_OPCODE_SEND,
  59         [IB_WR_SEND_WITH_IMM]                   = MLX5_OPCODE_SEND_IMM,
  60         [IB_WR_RDMA_WRITE]                      = MLX5_OPCODE_RDMA_WRITE,
  61         [IB_WR_RDMA_WRITE_WITH_IMM]             = MLX5_OPCODE_RDMA_WRITE_IMM,
  62         [IB_WR_RDMA_READ]                       = MLX5_OPCODE_RDMA_READ,
  63         [IB_WR_ATOMIC_CMP_AND_SWP]              = MLX5_OPCODE_ATOMIC_CS,
  64         [IB_WR_ATOMIC_FETCH_AND_ADD]            = MLX5_OPCODE_ATOMIC_FA,
  65         [IB_WR_SEND_WITH_INV]                   = MLX5_OPCODE_SEND_INVAL,
  66         [IB_WR_LOCAL_INV]                       = MLX5_OPCODE_UMR,
  67         [IB_WR_REG_MR]                          = MLX5_OPCODE_UMR,
  68         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = MLX5_OPCODE_ATOMIC_MASKED_CS,
  69         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = MLX5_OPCODE_ATOMIC_MASKED_FA,
  70         [MLX5_IB_WR_UMR]                        = MLX5_OPCODE_UMR,
  71 };
  72
  73
  74 static int is_qp0(enum ib_qp_type qp_type)
  75 {
  76         return qp_type == IB_QPT_SMI;
  77 }
  78
  79 static int is_sqp(enum ib_qp_type qp_type)
  80 {
  81         return is_qp0(qp_type) || is_qp1(qp_type);
  82 }
  83
  84 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
  85 {
  86         return mlx5_buf_offset(&qp->buf, offset);
  87 }
  88
  89 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
  90 {
  91         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
  92 }
  93
  94 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
  95 {
  96         return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
  97 }
  98
  99 /**
 100  * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
 101  *
 102  * @qp: QP to copy from.
 103  * @send: copy from the send queue when non-zero, use the receive queue
 104  *        otherwise.
 105  * @wqe_index:  index to start copying from. For send work queues, the
 106  *              wqe_index is in units of MLX5_SEND_WQE_BB.
 107  *              For receive work queue, it is the number of work queue
 108  *              element in the queue.
 109  * @buffer: destination buffer.
 110  * @length: maximum number of bytes to copy.
 111  *
 112  * Copies at least a single WQE, but may copy more data.
 113  *
 114  * Return: the number of bytes copied, or an error code.
 115  */
 116 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
 117                           void *buffer, u32 length)
 118 {
 119         struct ib_device *ibdev = qp->ibqp.device;
 120         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 121         struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
 122         size_t offset;
 123         size_t wq_end;
 124         struct ib_umem *umem = qp->umem;
 125         u32 first_copy_length;
 126         int wqe_length;
 127         int ret;
 128
 129         if (wq->wqe_cnt == 0) {
 130                 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
 131                             qp->ibqp.qp_type);
 132                 return -EINVAL;
 133         }
 134
 135         offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
 136         wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
 137
 138         if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
 139                 return -EINVAL;
 140
 141         if (offset > umem->length ||
 142             (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
 143                 return -EINVAL;
 144
 145         first_copy_length = min_t(u32, offset + length, wq_end) - offset;
 146         ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
 147         if (ret)
 148                 return ret;
 149
 150         if (send) {
 151                 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
 152                 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
 153
 154                 wqe_length = ds * MLX5_WQE_DS_UNITS;
 155         } else {
 156                 wqe_length = 1 << wq->wqe_shift;
 157         }
 158
 159         if (wqe_length <= first_copy_length)
 160                 return first_copy_length;
 161
 162         ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
 163                                 wqe_length - first_copy_length);
 164         if (ret)
 165                 return ret;
 166
 167         return wqe_length;
 168 }
 169
 170 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
 171 {
 172         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 173         struct ib_event event;
 174
 175         if (type == MLX5_EVENT_TYPE_PATH_MIG)
 176                 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
 177
 178         if (ibqp->event_handler) {
 179                 event.device     = ibqp->device;
 180                 event.element.qp = ibqp;
 181                 switch (type) {
 182                 case MLX5_EVENT_TYPE_PATH_MIG:
 183                         event.event = IB_EVENT_PATH_MIG;
 184                         break;
 185                 case MLX5_EVENT_TYPE_COMM_EST:
 186                         event.event = IB_EVENT_COMM_EST;
 187                         break;
 188                 case MLX5_EVENT_TYPE_SQ_DRAINED:
 189                         event.event = IB_EVENT_SQ_DRAINED;
 190                         break;
 191                 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 192                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 193                         break;
 194                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 195                         event.event = IB_EVENT_QP_FATAL;
 196                         break;
 197                 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 198                         event.event = IB_EVENT_PATH_MIG_ERR;
 199                         break;
 200                 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 201                         event.event = IB_EVENT_QP_REQ_ERR;
 202                         break;
 203                 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 204                         event.event = IB_EVENT_QP_ACCESS_ERR;
 205                         break;
 206                 default:
 207                         pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
 208                         return;
 209                 }
 210
 211                 ibqp->event_handler(&event, ibqp->qp_context);
 212         }
 213 }
 214
 215 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
 216                        int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
 217 {
 218         int wqe_size;
 219         int wq_size;
 220
 221         /* Sanity check RQ size before proceeding */
 222         if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
 223                 return -EINVAL;
 224
 225         if (!has_rq) {
 226                 qp->rq.max_gs = 0;
 227                 qp->rq.wqe_cnt = 0;
 228                 qp->rq.wqe_shift = 0;
 229                 cap->max_recv_wr = 0;
 230                 cap->max_recv_sge = 0;
 231         } else {
 232                 if (ucmd) {
 233                         qp->rq.wqe_cnt = ucmd->rq_wqe_count;
 234                         if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift))
 235                                 return -EINVAL;
 236                         qp->rq.wqe_shift = ucmd->rq_wqe_shift;
 237                         if ((1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) < qp->wq_sig)
 238                                 return -EINVAL;
 239                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 240                         qp->rq.max_post = qp->rq.wqe_cnt;
 241                 } else {
 242                         wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
 243                         wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
 244                         wqe_size = roundup_pow_of_two(wqe_size);
 245                         wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
 246                         wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
 247                         qp->rq.wqe_cnt = wq_size / wqe_size;
 248                         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
 249                                 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
 250                                             wqe_size,
 251                                             MLX5_CAP_GEN(dev->mdev,
 252                                                          max_wqe_sz_rq));
 253                                 return -EINVAL;
 254                         }
 255                         qp->rq.wqe_shift = ilog2(wqe_size);
 256                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 257                         qp->rq.max_post = qp->rq.wqe_cnt;
 258                 }
 259         }
 260
 261         return 0;
 262 }
 263
 264 static int sq_overhead(enum ib_qp_type qp_type)
 265 {
 266         int size = 0;
 267
 268         switch (qp_type) {
 269         case IB_QPT_XRC_INI:
 270                 size += sizeof(struct mlx5_wqe_xrc_seg);
 271                 /* fall through */
 272         case IB_QPT_RC:
 273                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 274                         max(sizeof(struct mlx5_wqe_atomic_seg) +
 275                             sizeof(struct mlx5_wqe_raddr_seg),
 276                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 277                             sizeof(struct mlx5_mkey_seg));
 278                 break;
 279
 280         case IB_QPT_XRC_TGT:
 281                 return 0;
 282
 283         case IB_QPT_UC:
 284                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 285                         max(sizeof(struct mlx5_wqe_raddr_seg),
 286                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 287                             sizeof(struct mlx5_mkey_seg));
 288                 break;
 289
 290         case IB_QPT_UD:
 291         case IB_QPT_SMI:
 292         case IB_QPT_GSI:
 293                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 294                         sizeof(struct mlx5_wqe_datagram_seg);
 295                 break;
 296
 297         case MLX5_IB_QPT_REG_UMR:
 298                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 299                         sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 300                         sizeof(struct mlx5_mkey_seg);
 301                 break;
 302
 303         default:
 304                 return -EINVAL;
 305         }
 306
 307         return size;
 308 }
 309
 310 static int calc_send_wqe(struct ib_qp_init_attr *attr)
 311 {
 312         int inl_size = 0;
 313         int size;
 314
 315         size = sq_overhead(attr->qp_type);
 316         if (size < 0)
 317                 return size;
 318
 319         if (attr->cap.max_inline_data) {
 320                 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
 321                         attr->cap.max_inline_data;
 322         }
 323
 324         size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
 325         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
 326             ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
 327                         return MLX5_SIG_WQE_SIZE;
 328         else
 329                 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
 330 }
 331
 332 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
 333                         struct mlx5_ib_qp *qp)
 334 {
 335         int wqe_size;
 336         int wq_size;
 337
 338         if (!attr->cap.max_send_wr)
 339                 return 0;
 340
 341         wqe_size = calc_send_wqe(attr);
 342         mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
 343         if (wqe_size < 0)
 344                 return wqe_size;
 345
 346         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 347                 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
 348                             wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 349                 return -EINVAL;
 350         }
 351
 352         qp->max_inline_data = wqe_size - sq_overhead(attr->qp_type) -
 353                 sizeof(struct mlx5_wqe_inline_seg);
 354         attr->cap.max_inline_data = qp->max_inline_data;
 355
 356         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
 357                 qp->signature_en = true;
 358
 359         wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
 360         qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
 361         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 362                 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n",
 363                             qp->sq.wqe_cnt,
 364                             1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 365                 return -ENOMEM;
 366         }
 367         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 368         qp->sq.max_gs = attr->cap.max_send_sge;
 369         qp->sq.max_post = wq_size / wqe_size;
 370         attr->cap.max_send_wr = qp->sq.max_post;
 371
 372         return wq_size;
 373 }
 374
 375 static int set_user_buf_size(struct mlx5_ib_dev *dev,
 376                             struct mlx5_ib_qp *qp,
 377                             struct mlx5_ib_create_qp *ucmd)
 378 {
 379         int desc_sz = 1 << qp->sq.wqe_shift;
 380
 381         if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 382                 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
 383                              desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 384                 return -EINVAL;
 385         }
 386
 387         if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
 388                 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
 389                              ucmd->sq_wqe_count, ucmd->sq_wqe_count);
 390                 return -EINVAL;
 391         }
 392
 393         qp->sq.wqe_cnt = ucmd->sq_wqe_count;
 394
 395         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 396                 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
 397                              qp->sq.wqe_cnt,
 398                              1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 399                 return -EINVAL;
 400         }
 401
 402         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 403                 (qp->sq.wqe_cnt << 6);
 404
 405         return 0;
 406 }
 407
 408 static int qp_has_rq(struct ib_qp_init_attr *attr)
 409 {
 410         if (attr->qp_type == IB_QPT_XRC_INI ||
 411             attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
 412             attr->qp_type == MLX5_IB_QPT_REG_UMR ||
 413             !attr->cap.max_recv_wr)
 414                 return 0;
 415
 416         return 1;
 417 }
 418
 419 static int first_med_uuar(void)
 420 {
 421         return 1;
 422 }
 423
 424 static int next_uuar(int n)
 425 {
 426         n++;
 427
 428         while (((n % 4) & 2))
 429                 n++;
 430
 431         return n;
 432 }
 433
 434 static int num_med_uuar(struct mlx5_uuar_info *uuari)
 435 {
 436         int n;
 437
 438         n = uuari->num_uars * MLX5_NON_FP_BF_REGS_PER_PAGE -
 439                 uuari->num_low_latency_uuars - 1;
 440
 441         return n >= 0 ? n : 0;
 442 }
 443
 444 static int max_uuari(struct mlx5_uuar_info *uuari)
 445 {
 446         return uuari->num_uars * 4;
 447 }
 448
 449 static int first_hi_uuar(struct mlx5_uuar_info *uuari)
 450 {
 451         int med;
 452         int i;
 453         int t;
 454
 455         med = num_med_uuar(uuari);
 456         for (t = 0, i = first_med_uuar();; i = next_uuar(i)) {
 457                 t++;
 458                 if (t == med)
 459                         return next_uuar(i);
 460         }
 461
 462         return 0;
 463 }
 464
 465 static int alloc_high_class_uuar(struct mlx5_uuar_info *uuari)
 466 {
 467         int i;
 468
 469         for (i = first_hi_uuar(uuari); i < max_uuari(uuari); i = next_uuar(i)) {
 470                 if (!test_bit(i, uuari->bitmap)) {
 471                         set_bit(i, uuari->bitmap);
 472                         uuari->count[i]++;
 473                         return i;
 474                 }
 475         }
 476
 477         return -ENOMEM;
 478 }
 479
 480 static int alloc_med_class_uuar(struct mlx5_uuar_info *uuari)
 481 {
 482         int minidx = first_med_uuar();
 483         int i;
 484
 485         for (i = first_med_uuar(); i < first_hi_uuar(uuari); i = next_uuar(i)) {
 486                 if (uuari->count[i] < uuari->count[minidx])
 487                         minidx = i;
 488         }
 489
 490         uuari->count[minidx]++;
 491         return minidx;
 492 }
 493
 494 static int alloc_uuar(struct mlx5_uuar_info *uuari,
 495                       enum mlx5_ib_latency_class lat)
 496 {
 497         int uuarn = -EINVAL;
 498
 499         mutex_lock(&uuari->lock);
 500         switch (lat) {
 501         case MLX5_IB_LATENCY_CLASS_LOW:
 502                 uuarn = 0;
 503                 uuari->count[uuarn]++;
 504                 break;
 505
 506         case MLX5_IB_LATENCY_CLASS_MEDIUM:
 507                 if (uuari->ver < 2)
 508                         uuarn = -ENOMEM;
 509                 else
 510                         uuarn = alloc_med_class_uuar(uuari);
 511                 break;
 512
 513         case MLX5_IB_LATENCY_CLASS_HIGH:
 514                 if (uuari->ver < 2)
 515                         uuarn = -ENOMEM;
 516                 else
 517                         uuarn = alloc_high_class_uuar(uuari);
 518                 break;
 519
 520         case MLX5_IB_LATENCY_CLASS_FAST_PATH:
 521                 uuarn = 2;
 522                 break;
 523         }
 524         mutex_unlock(&uuari->lock);
 525
 526         return uuarn;
 527 }
 528
 529 static void free_med_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
 530 {
 531         clear_bit(uuarn, uuari->bitmap);
 532         --uuari->count[uuarn];
 533 }
 534
 535 static void free_high_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
 536 {
 537         clear_bit(uuarn, uuari->bitmap);
 538         --uuari->count[uuarn];
 539 }
 540
 541 static void free_uuar(struct mlx5_uuar_info *uuari, int uuarn)
 542 {
 543         int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE;
 544         int high_uuar = nuuars - uuari->num_low_latency_uuars;
 545
 546         mutex_lock(&uuari->lock);
 547         if (uuarn == 0) {
 548                 --uuari->count[uuarn];
 549                 goto out;
 550         }
 551
 552         if (uuarn < high_uuar) {
 553                 free_med_class_uuar(uuari, uuarn);
 554                 goto out;
 555         }
 556
 557         free_high_class_uuar(uuari, uuarn);
 558
 559 out:
 560         mutex_unlock(&uuari->lock);
 561 }
 562
 563 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
 564 {
 565         switch (state) {
 566         case IB_QPS_RESET:      return MLX5_QP_STATE_RST;
 567         case IB_QPS_INIT:       return MLX5_QP_STATE_INIT;
 568         case IB_QPS_RTR:        return MLX5_QP_STATE_RTR;
 569         case IB_QPS_RTS:        return MLX5_QP_STATE_RTS;
 570         case IB_QPS_SQD:        return MLX5_QP_STATE_SQD;
 571         case IB_QPS_SQE:        return MLX5_QP_STATE_SQER;
 572         case IB_QPS_ERR:        return MLX5_QP_STATE_ERR;
 573         default:                return -1;
 574         }
 575 }
 576
 577 static int to_mlx5_st(enum ib_qp_type type)
 578 {
 579         switch (type) {
 580         case IB_QPT_RC:                 return MLX5_QP_ST_RC;
 581         case IB_QPT_UC:                 return MLX5_QP_ST_UC;
 582         case IB_QPT_UD:                 return MLX5_QP_ST_UD;
 583         case MLX5_IB_QPT_REG_UMR:       return MLX5_QP_ST_REG_UMR;
 584         case IB_QPT_XRC_INI:
 585         case IB_QPT_XRC_TGT:            return MLX5_QP_ST_XRC;
 586         case IB_QPT_SMI:                return MLX5_QP_ST_QP0;
 587         case IB_QPT_GSI:                return MLX5_QP_ST_QP1;
 588         case IB_QPT_RAW_IPV6:           return MLX5_QP_ST_RAW_IPV6;
 589         case IB_QPT_RAW_ETHERTYPE:      return MLX5_QP_ST_RAW_ETHERTYPE;
 590         case IB_QPT_RAW_PACKET:
 591         case IB_QPT_MAX:
 592         default:                return -EINVAL;
 593         }
 594 }
 595
 596 static int uuarn_to_uar_index(struct mlx5_uuar_info *uuari, int uuarn)
 597 {
 598         return uuari->uars[uuarn / MLX5_BF_REGS_PER_PAGE].index;
 599 }
 600
 601 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 602                           struct mlx5_ib_qp *qp, struct ib_udata *udata,
 603                           struct mlx5_create_qp_mbox_in **in,
 604                           struct mlx5_ib_create_qp_resp *resp, int *inlen)
 605 {
 606         struct mlx5_ib_ucontext *context;
 607         struct mlx5_ib_create_qp ucmd;
 608         int page_shift = 0;
 609         int uar_index;
 610         int npages;
 611         u32 offset = 0;
 612         int uuarn;
 613         int ncont = 0;
 614         int err;
 615
 616         err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
 617         if (err) {
 618                 mlx5_ib_dbg(dev, "copy failed\n");
 619                 return err;
 620         }
 621
 622         context = to_mucontext(pd->uobject->context);
 623         /*
 624          * TBD: should come from the verbs when we have the API
 625          */
 626         uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_HIGH);
 627         if (uuarn < 0) {
 628                 mlx5_ib_dbg(dev, "failed to allocate low latency UUAR\n");
 629                 mlx5_ib_dbg(dev, "reverting to medium latency\n");
 630                 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_MEDIUM);
 631                 if (uuarn < 0) {
 632                         mlx5_ib_dbg(dev, "failed to allocate medium latency UUAR\n");
 633                         mlx5_ib_dbg(dev, "reverting to high latency\n");
 634                         uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_LOW);
 635                         if (uuarn < 0) {
 636                                 mlx5_ib_warn(dev, "uuar allocation failed\n");
 637                                 return uuarn;
 638                         }
 639                 }
 640         }
 641
 642         uar_index = uuarn_to_uar_index(&context->uuari, uuarn);
 643         mlx5_ib_dbg(dev, "uuarn 0x%x, uar_index 0x%x\n", uuarn, uar_index);
 644
 645         qp->rq.offset = 0;
 646         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 647         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 648
 649         err = set_user_buf_size(dev, qp, &ucmd);
 650         if (err)
 651                 goto err_uuar;
 652
 653         if (ucmd.buf_addr && qp->buf_size) {
 654                 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
 655                                        qp->buf_size, 0, 0);
 656                 if (IS_ERR(qp->umem)) {
 657                         mlx5_ib_dbg(dev, "umem_get failed\n");
 658                         err = PTR_ERR(qp->umem);
 659                         goto err_uuar;
 660                 }
 661         } else {
 662                 qp->umem = NULL;
 663         }
 664
 665         if (qp->umem) {
 666                 mlx5_ib_cont_pages(qp->umem, ucmd.buf_addr, &npages, &page_shift,
 667                                    &ncont, NULL);
 668                 err = mlx5_ib_get_buf_offset(ucmd.buf_addr, page_shift, &offset);
 669                 if (err) {
 670                         mlx5_ib_warn(dev, "bad offset\n");
 671                         goto err_umem;
 672                 }
 673                 mlx5_ib_dbg(dev, "addr 0x%llx, size %d, npages %d, page_shift %d, ncont %d, offset %d\n",
 674                             ucmd.buf_addr, qp->buf_size, npages, page_shift, ncont, offset);
 675         }
 676
 677         *inlen = sizeof(**in) + sizeof(*(*in)->pas) * ncont;
 678         *in = mlx5_vzalloc(*inlen);
 679         if (!*in) {
 680                 err = -ENOMEM;
 681                 goto err_umem;
 682         }
 683         if (qp->umem)
 684                 mlx5_ib_populate_pas(dev, qp->umem, page_shift, (*in)->pas, 0);
 685         (*in)->ctx.log_pg_sz_remote_qpn =
 686                 cpu_to_be32((page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24);
 687         (*in)->ctx.params2 = cpu_to_be32(offset << 6);
 688
 689         (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index);
 690         resp->uuar_index = uuarn;
 691         qp->uuarn = uuarn;
 692
 693         err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
 694         if (err) {
 695                 mlx5_ib_dbg(dev, "map failed\n");
 696                 goto err_free;
 697         }
 698
 699         err = ib_copy_to_udata(udata, resp, sizeof(*resp));
 700         if (err) {
 701                 mlx5_ib_dbg(dev, "copy failed\n");
 702                 goto err_unmap;
 703         }
 704         qp->create_type = MLX5_QP_USER;
 705
 706         return 0;
 707
 708 err_unmap:
 709         mlx5_ib_db_unmap_user(context, &qp->db);
 710
 711 err_free:
 712         kvfree(*in);
 713
 714 err_umem:
 715         if (qp->umem)
 716                 ib_umem_release(qp->umem);
 717
 718 err_uuar:
 719         free_uuar(&context->uuari, uuarn);
 720         return err;
 721 }
 722
 723 static void destroy_qp_user(struct ib_pd *pd, struct mlx5_ib_qp *qp)
 724 {
 725         struct mlx5_ib_ucontext *context;
 726
 727         context = to_mucontext(pd->uobject->context);
 728         mlx5_ib_db_unmap_user(context, &qp->db);
 729         if (qp->umem)
 730                 ib_umem_release(qp->umem);
 731         free_uuar(&context->uuari, qp->uuarn);
 732 }
 733
 734 static int create_kernel_qp(struct mlx5_ib_dev *dev,
 735                             struct ib_qp_init_attr *init_attr,
 736                             struct mlx5_ib_qp *qp,
 737                             struct mlx5_create_qp_mbox_in **in, int *inlen)
 738 {
 739         enum mlx5_ib_latency_class lc = MLX5_IB_LATENCY_CLASS_LOW;
 740         struct mlx5_uuar_info *uuari;
 741         int uar_index;
 742         int uuarn;
 743         int err;
 744
 745         uuari = &dev->mdev->priv.uuari;
 746         if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN | IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK))
 747                 return -EINVAL;
 748
 749         if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
 750                 lc = MLX5_IB_LATENCY_CLASS_FAST_PATH;
 751
 752         uuarn = alloc_uuar(uuari, lc);
 753         if (uuarn < 0) {
 754                 mlx5_ib_dbg(dev, "\n");
 755                 return -ENOMEM;
 756         }
 757
 758         qp->bf = &uuari->bfs[uuarn];
 759         uar_index = qp->bf->uar->index;
 760
 761         err = calc_sq_size(dev, init_attr, qp);
 762         if (err < 0) {
 763                 mlx5_ib_dbg(dev, "err %d\n", err);
 764                 goto err_uuar;
 765         }
 766
 767         qp->rq.offset = 0;
 768         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 769         qp->buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
 770
 771         err = mlx5_buf_alloc(dev->mdev, qp->buf_size, &qp->buf);
 772         if (err) {
 773                 mlx5_ib_dbg(dev, "err %d\n", err);
 774                 goto err_uuar;
 775         }
 776
 777         qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
 778         *inlen = sizeof(**in) + sizeof(*(*in)->pas) * qp->buf.npages;
 779         *in = mlx5_vzalloc(*inlen);
 780         if (!*in) {
 781                 err = -ENOMEM;
 782                 goto err_buf;
 783         }
 784         (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index);
 785         (*in)->ctx.log_pg_sz_remote_qpn =
 786                 cpu_to_be32((qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24);
 787         /* Set "fast registration enabled" for all kernel QPs */
 788         (*in)->ctx.params1 |= cpu_to_be32(1 << 11);
 789         (*in)->ctx.sq_crq_size |= cpu_to_be16(1 << 4);
 790
 791         mlx5_fill_page_array(&qp->buf, (*in)->pas);
 792
 793         err = mlx5_db_alloc(dev->mdev, &qp->db);
 794         if (err) {
 795                 mlx5_ib_dbg(dev, "err %d\n", err);
 796                 goto err_free;
 797         }
 798
 799         qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL);
 800         qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL);
 801         qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL);
 802         qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL);
 803         qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL);
 804
 805         if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
 806             !qp->sq.w_list || !qp->sq.wqe_head) {
 807                 err = -ENOMEM;
 808                 goto err_wrid;
 809         }
 810         qp->create_type = MLX5_QP_KERNEL;
 811
 812         return 0;
 813
 814 err_wrid:
 815         mlx5_db_free(dev->mdev, &qp->db);
 816         kfree(qp->sq.wqe_head);
 817         kfree(qp->sq.w_list);
 818         kfree(qp->sq.wrid);
 819         kfree(qp->sq.wr_data);
 820         kfree(qp->rq.wrid);
 821
 822 err_free:
 823         kvfree(*in);
 824
 825 err_buf:
 826         mlx5_buf_free(dev->mdev, &qp->buf);
 827
 828 err_uuar:
 829         free_uuar(&dev->mdev->priv.uuari, uuarn);
 830         return err;
 831 }
 832
 833 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
 834 {
 835         mlx5_db_free(dev->mdev, &qp->db);
 836         kfree(qp->sq.wqe_head);
 837         kfree(qp->sq.w_list);
 838         kfree(qp->sq.wrid);
 839         kfree(qp->sq.wr_data);
 840         kfree(qp->rq.wrid);
 841         mlx5_buf_free(dev->mdev, &qp->buf);
 842         free_uuar(&dev->mdev->priv.uuari, qp->bf->uuarn);
 843 }
 844
 845 static __be32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
 846 {
 847         if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
 848             (attr->qp_type == IB_QPT_XRC_INI))
 849                 return cpu_to_be32(MLX5_SRQ_RQ);
 850         else if (!qp->has_rq)
 851                 return cpu_to_be32(MLX5_ZERO_LEN_RQ);
 852         else
 853                 return cpu_to_be32(MLX5_NON_ZERO_RQ);
 854 }
 855
 856 static int is_connected(enum ib_qp_type qp_type)
 857 {
 858         if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
 859                 return 1;
 860
 861         return 0;
 862 }
 863
 864 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 865                             struct ib_qp_init_attr *init_attr,
 866                             struct ib_udata *udata, struct mlx5_ib_qp *qp)
 867 {
 868         struct mlx5_ib_resources *devr = &dev->devr;
 869         struct mlx5_core_dev *mdev = dev->mdev;
 870         struct mlx5_ib_create_qp_resp resp;
 871         struct mlx5_create_qp_mbox_in *in;
 872         struct mlx5_ib_create_qp ucmd;
 873         int inlen = sizeof(*in);
 874         int err;
 875
 876         mlx5_ib_odp_create_qp(qp);
 877
 878         mutex_init(&qp->mutex);
 879         spin_lock_init(&qp->sq.lock);
 880         spin_lock_init(&qp->rq.lock);
 881
 882         if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
 883                 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
 884                         mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
 885                         return -EINVAL;
 886                 } else {
 887                         qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
 888                 }
 889         }
 890
 891         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
 892                 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
 893
 894         if (pd && pd->uobject) {
 895                 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
 896                         mlx5_ib_dbg(dev, "copy failed\n");
 897                         return -EFAULT;
 898                 }
 899
 900                 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
 901                 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
 902         } else {
 903                 qp->wq_sig = !!wq_signature;
 904         }
 905
 906         qp->has_rq = qp_has_rq(init_attr);
 907         err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
 908                           qp, (pd && pd->uobject) ? &ucmd : NULL);
 909         if (err) {
 910                 mlx5_ib_dbg(dev, "err %d\n", err);
 911                 return err;
 912         }
 913
 914         if (pd) {
 915                 if (pd->uobject) {
 916                         __u32 max_wqes =
 917                                 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 918                         mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
 919                         if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
 920                             ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
 921                                 mlx5_ib_dbg(dev, "invalid rq params\n");
 922                                 return -EINVAL;
 923                         }
 924                         if (ucmd.sq_wqe_count > max_wqes) {
 925                                 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
 926                                             ucmd.sq_wqe_count, max_wqes);
 927                                 return -EINVAL;
 928                         }
 929                         err = create_user_qp(dev, pd, qp, udata, &in, &resp, &inlen);
 930                         if (err)
 931                                 mlx5_ib_dbg(dev, "err %d\n", err);
 932                 } else {
 933                         err = create_kernel_qp(dev, init_attr, qp, &in, &inlen);
 934                         if (err)
 935                                 mlx5_ib_dbg(dev, "err %d\n", err);
 936                 }
 937
 938                 if (err)
 939                         return err;
 940         } else {
 941                 in = mlx5_vzalloc(sizeof(*in));
 942                 if (!in)
 943                         return -ENOMEM;
 944
 945                 qp->create_type = MLX5_QP_EMPTY;
 946         }
 947
 948         if (is_sqp(init_attr->qp_type))
 949                 qp->port = init_attr->port_num;
 950
 951         in->ctx.flags = cpu_to_be32(to_mlx5_st(init_attr->qp_type) << 16 |
 952                                     MLX5_QP_PM_MIGRATED << 11);
 953
 954         if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
 955                 in->ctx.flags_pd = cpu_to_be32(to_mpd(pd ? pd : devr->p0)->pdn);
 956         else
 957                 in->ctx.flags_pd = cpu_to_be32(MLX5_QP_LAT_SENSITIVE);
 958
 959         if (qp->wq_sig)
 960                 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_ENABLE_SIG);
 961
 962         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
 963                 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_BLOCK_MCAST);
 964
 965         if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
 966                 int rcqe_sz;
 967                 int scqe_sz;
 968
 969                 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
 970                 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
 971
 972                 if (rcqe_sz == 128)
 973                         in->ctx.cs_res = MLX5_RES_SCAT_DATA64_CQE;
 974                 else
 975                         in->ctx.cs_res = MLX5_RES_SCAT_DATA32_CQE;
 976
 977                 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
 978                         if (scqe_sz == 128)
 979                                 in->ctx.cs_req = MLX5_REQ_SCAT_DATA64_CQE;
 980                         else
 981                                 in->ctx.cs_req = MLX5_REQ_SCAT_DATA32_CQE;
 982                 }
 983         }
 984
 985         if (qp->rq.wqe_cnt) {
 986                 in->ctx.rq_size_stride = (qp->rq.wqe_shift - 4);
 987                 in->ctx.rq_size_stride |= ilog2(qp->rq.wqe_cnt) << 3;
 988         }
 989
 990         in->ctx.rq_type_srqn = get_rx_type(qp, init_attr);
 991
 992         if (qp->sq.wqe_cnt)
 993                 in->ctx.sq_crq_size |= cpu_to_be16(ilog2(qp->sq.wqe_cnt) << 11);
 994         else
 995                 in->ctx.sq_crq_size |= cpu_to_be16(0x8000);
 996
 997         /* Set default resources */
 998         switch (init_attr->qp_type) {
 999         case IB_QPT_XRC_TGT:
1000                 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
1001                 in->ctx.cqn_send = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
1002                 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
1003                 in->ctx.xrcd = cpu_to_be32(to_mxrcd(init_attr->xrcd)->xrcdn);
1004                 break;
1005         case IB_QPT_XRC_INI:
1006                 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
1007                 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn);
1008                 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
1009                 break;
1010         default:
1011                 if (init_attr->srq) {
1012                         in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x0)->xrcdn);
1013                         in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(init_attr->srq)->msrq.srqn);
1014                 } else {
1015                         in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn);
1016                         in->ctx.rq_type_srqn |=
1017                                 cpu_to_be32(to_msrq(devr->s1)->msrq.srqn);
1018                 }
1019         }
1020
1021         if (init_attr->send_cq)
1022                 in->ctx.cqn_send = cpu_to_be32(to_mcq(init_attr->send_cq)->mcq.cqn);
1023
1024         if (init_attr->recv_cq)
1025                 in->ctx.cqn_recv = cpu_to_be32(to_mcq(init_attr->recv_cq)->mcq.cqn);
1026
1027         in->ctx.db_rec_addr = cpu_to_be64(qp->db.dma);
1028
1029         err = mlx5_core_create_qp(dev->mdev, &qp->mqp, in, inlen);
1030         if (err) {
1031                 mlx5_ib_dbg(dev, "create qp failed\n");
1032                 goto err_create;
1033         }
1034
1035         kvfree(in);
1036         /* Hardware wants QPN written in big-endian order (after
1037          * shifting) for send doorbell.  Precompute this value to save
1038          * a little bit when posting sends.
1039          */
1040         qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
1041
1042         qp->mqp.event = mlx5_ib_qp_event;
1043
1044         return 0;
1045
1046 err_create:
1047         if (qp->create_type == MLX5_QP_USER)
1048                 destroy_qp_user(pd, qp);
1049         else if (qp->create_type == MLX5_QP_KERNEL)
1050                 destroy_qp_kernel(dev, qp);
1051
1052         kvfree(in);
1053         return err;
1054 }
1055
1056 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1057         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1058 {
1059         if (send_cq) {
1060                 if (recv_cq) {
1061                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
1062                                 spin_lock_irq(&send_cq->lock);
1063                                 spin_lock_nested(&recv_cq->lock,
1064                                                  SINGLE_DEPTH_NESTING);
1065                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1066                                 spin_lock_irq(&send_cq->lock);
1067                                 __acquire(&recv_cq->lock);
1068                         } else {
1069                                 spin_lock_irq(&recv_cq->lock);
1070                                 spin_lock_nested(&send_cq->lock,
1071                                                  SINGLE_DEPTH_NESTING);
1072                         }
1073                 } else {
1074                         spin_lock_irq(&send_cq->lock);
1075                         __acquire(&recv_cq->lock);
1076                 }
1077         } else if (recv_cq) {
1078                 spin_lock_irq(&recv_cq->lock);
1079                 __acquire(&send_cq->lock);
1080         } else {
1081                 __acquire(&send_cq->lock);
1082                 __acquire(&recv_cq->lock);
1083         }
1084 }
1085
1086 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1087         __releases(&send_cq->lock) __releases(&recv_cq->lock)
1088 {
1089         if (send_cq) {
1090                 if (recv_cq) {
1091                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
1092                                 spin_unlock(&recv_cq->lock);
1093                                 spin_unlock_irq(&send_cq->lock);
1094                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1095                                 __release(&recv_cq->lock);
1096                                 spin_unlock_irq(&send_cq->lock);
1097                         } else {
1098                                 spin_unlock(&send_cq->lock);
1099                                 spin_unlock_irq(&recv_cq->lock);
1100                         }
1101                 } else {
1102                         __release(&recv_cq->lock);
1103                         spin_unlock_irq(&send_cq->lock);
1104                 }
1105         } else if (recv_cq) {
1106                 __release(&send_cq->lock);
1107                 spin_unlock_irq(&recv_cq->lock);
1108         } else {
1109                 __release(&recv_cq->lock);
1110                 __release(&send_cq->lock);
1111         }
1112 }
1113
1114 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1115 {
1116         return to_mpd(qp->ibqp.pd);
1117 }
1118
1119 static void get_cqs(struct mlx5_ib_qp *qp,
1120                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1121 {
1122         switch (qp->ibqp.qp_type) {
1123         case IB_QPT_XRC_TGT:
1124                 *send_cq = NULL;
1125                 *recv_cq = NULL;
1126                 break;
1127         case MLX5_IB_QPT_REG_UMR:
1128         case IB_QPT_XRC_INI:
1129                 *send_cq = to_mcq(qp->ibqp.send_cq);
1130                 *recv_cq = NULL;
1131                 break;
1132
1133         case IB_QPT_SMI:
1134         case IB_QPT_GSI:
1135         case IB_QPT_RC:
1136         case IB_QPT_UC:
1137         case IB_QPT_UD:
1138         case IB_QPT_RAW_IPV6:
1139         case IB_QPT_RAW_ETHERTYPE:
1140                 *send_cq = to_mcq(qp->ibqp.send_cq);
1141                 *recv_cq = to_mcq(qp->ibqp.recv_cq);
1142                 break;
1143
1144         case IB_QPT_RAW_PACKET:
1145         case IB_QPT_MAX:
1146         default:
1147                 *send_cq = NULL;
1148                 *recv_cq = NULL;
1149                 break;
1150         }
1151 }
1152
1153 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1154 {
1155         struct mlx5_ib_cq *send_cq, *recv_cq;
1156         struct mlx5_modify_qp_mbox_in *in;
1157         int err;
1158
1159         in = kzalloc(sizeof(*in), GFP_KERNEL);
1160         if (!in)
1161                 return;
1162
1163         if (qp->state != IB_QPS_RESET) {
1164                 mlx5_ib_qp_disable_pagefaults(qp);
1165                 if (mlx5_core_qp_modify(dev->mdev, to_mlx5_state(qp->state),
1166                                         MLX5_QP_STATE_RST, in, 0, &qp->mqp))
1167                         mlx5_ib_warn(dev, "mlx5_ib: modify QP %06x to RESET failed\n",
1168                                      qp->mqp.qpn);
1169         }
1170
1171         get_cqs(qp, &send_cq, &recv_cq);
1172
1173         if (qp->create_type == MLX5_QP_KERNEL) {
1174                 mlx5_ib_lock_cqs(send_cq, recv_cq);
1175                 __mlx5_ib_cq_clean(recv_cq, qp->mqp.qpn,
1176                                    qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1177                 if (send_cq != recv_cq)
1178                         __mlx5_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1179                 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1180         }
1181
1182         err = mlx5_core_destroy_qp(dev->mdev, &qp->mqp);
1183         if (err)
1184                 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", qp->mqp.qpn);
1185         kfree(in);
1186
1187
1188         if (qp->create_type == MLX5_QP_KERNEL)
1189                 destroy_qp_kernel(dev, qp);
1190         else if (qp->create_type == MLX5_QP_USER)
1191                 destroy_qp_user(&get_pd(qp)->ibpd, qp);
1192 }
1193
1194 static const char *ib_qp_type_str(enum ib_qp_type type)
1195 {
1196         switch (type) {
1197         case IB_QPT_SMI:
1198                 return "IB_QPT_SMI";
1199         case IB_QPT_GSI:
1200                 return "IB_QPT_GSI";
1201         case IB_QPT_RC:
1202                 return "IB_QPT_RC";
1203         case IB_QPT_UC:
1204                 return "IB_QPT_UC";
1205         case IB_QPT_UD:
1206                 return "IB_QPT_UD";
1207         case IB_QPT_RAW_IPV6:
1208                 return "IB_QPT_RAW_IPV6";
1209         case IB_QPT_RAW_ETHERTYPE:
1210                 return "IB_QPT_RAW_ETHERTYPE";
1211         case IB_QPT_XRC_INI:
1212                 return "IB_QPT_XRC_INI";
1213         case IB_QPT_XRC_TGT:
1214                 return "IB_QPT_XRC_TGT";
1215         case IB_QPT_RAW_PACKET:
1216                 return "IB_QPT_RAW_PACKET";
1217         case MLX5_IB_QPT_REG_UMR:
1218                 return "MLX5_IB_QPT_REG_UMR";
1219         case IB_QPT_MAX:
1220         default:
1221                 return "Invalid QP type";
1222         }
1223 }
1224
1225 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1226                                 struct ib_qp_init_attr *init_attr,
1227                                 struct ib_udata *udata)
1228 {
1229         struct mlx5_ib_dev *dev;
1230         struct mlx5_ib_qp *qp;
1231         u16 xrcdn = 0;
1232         int err;
1233
1234         if (pd) {
1235                 dev = to_mdev(pd->device);
1236         } else {
1237                 /* being cautious here */
1238                 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
1239                     init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
1240                         pr_warn("%s: no PD for transport %s\n", __func__,
1241                                 ib_qp_type_str(init_attr->qp_type));
1242                         return ERR_PTR(-EINVAL);
1243                 }
1244                 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
1245         }
1246
1247         switch (init_attr->qp_type) {
1248         case IB_QPT_XRC_TGT:
1249         case IB_QPT_XRC_INI:
1250                 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
1251                         mlx5_ib_dbg(dev, "XRC not supported\n");
1252                         return ERR_PTR(-ENOSYS);
1253                 }
1254                 init_attr->recv_cq = NULL;
1255                 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
1256                         xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1257                         init_attr->send_cq = NULL;
1258                 }
1259
1260                 /* fall through */
1261         case IB_QPT_RC:
1262         case IB_QPT_UC:
1263         case IB_QPT_UD:
1264         case IB_QPT_SMI:
1265         case IB_QPT_GSI:
1266         case MLX5_IB_QPT_REG_UMR:
1267                 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1268                 if (!qp)
1269                         return ERR_PTR(-ENOMEM);
1270
1271                 err = create_qp_common(dev, pd, init_attr, udata, qp);
1272                 if (err) {
1273                         mlx5_ib_dbg(dev, "create_qp_common failed\n");
1274                         kfree(qp);
1275                         return ERR_PTR(err);
1276                 }
1277
1278                 if (is_qp0(init_attr->qp_type))
1279                         qp->ibqp.qp_num = 0;
1280                 else if (is_qp1(init_attr->qp_type))
1281                         qp->ibqp.qp_num = 1;
1282                 else
1283                         qp->ibqp.qp_num = qp->mqp.qpn;
1284
1285                 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
1286                             qp->ibqp.qp_num, qp->mqp.qpn, to_mcq(init_attr->recv_cq)->mcq.cqn,
1287                             to_mcq(init_attr->send_cq)->mcq.cqn);
1288
1289                 qp->xrcdn = xrcdn;
1290
1291                 break;
1292
1293         case IB_QPT_RAW_IPV6:
1294         case IB_QPT_RAW_ETHERTYPE:
1295         case IB_QPT_RAW_PACKET:
1296         case IB_QPT_MAX:
1297         default:
1298                 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
1299                             init_attr->qp_type);
1300                 /* Don't support raw QPs */
1301                 return ERR_PTR(-EINVAL);
1302         }
1303
1304         return &qp->ibqp;
1305 }
1306
1307 int mlx5_ib_destroy_qp(struct ib_qp *qp)
1308 {
1309         struct mlx5_ib_dev *dev = to_mdev(qp->device);
1310         struct mlx5_ib_qp *mqp = to_mqp(qp);
1311
1312         destroy_qp_common(dev, mqp);
1313
1314         kfree(mqp);
1315
1316         return 0;
1317 }
1318
1319 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
1320                                    int attr_mask)
1321 {
1322         u32 hw_access_flags = 0;
1323         u8 dest_rd_atomic;
1324         u32 access_flags;
1325
1326         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1327                 dest_rd_atomic = attr->max_dest_rd_atomic;
1328         else
1329                 dest_rd_atomic = qp->resp_depth;
1330
1331         if (attr_mask & IB_QP_ACCESS_FLAGS)
1332                 access_flags = attr->qp_access_flags;
1333         else
1334                 access_flags = qp->atomic_rd_en;
1335
1336         if (!dest_rd_atomic)
1337                 access_flags &= IB_ACCESS_REMOTE_WRITE;
1338
1339         if (access_flags & IB_ACCESS_REMOTE_READ)
1340                 hw_access_flags |= MLX5_QP_BIT_RRE;
1341         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1342                 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
1343         if (access_flags & IB_ACCESS_REMOTE_WRITE)
1344                 hw_access_flags |= MLX5_QP_BIT_RWE;
1345
1346         return cpu_to_be32(hw_access_flags);
1347 }
1348
1349 enum {
1350         MLX5_PATH_FLAG_FL       = 1 << 0,
1351         MLX5_PATH_FLAG_FREE_AR  = 1 << 1,
1352         MLX5_PATH_FLAG_COUNTER  = 1 << 2,
1353 };
1354
1355 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
1356 {
1357         if (rate == IB_RATE_PORT_CURRENT)
1358                 return 0;
1359
1360         if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS)
1361                 return -EINVAL;
1362
1363         while (rate != IB_RATE_PORT_CURRENT &&
1364                !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
1365                  MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
1366                 --rate;
1367
1368         return rate ? rate + MLX5_STAT_RATE_OFFSET : rate;
1369 }
1370
1371 static int mlx5_set_path(struct mlx5_ib_dev *dev, const struct ib_ah_attr *ah,
1372                          struct mlx5_qp_path *path, u8 port, int attr_mask,
1373                          u32 path_flags, const struct ib_qp_attr *attr)
1374 {
1375         int err;
1376
1377         path->fl = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
1378         path->free_ar = (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x80 : 0;
1379
1380         if (attr_mask & IB_QP_PKEY_INDEX)
1381                 path->pkey_index = attr->pkey_index;
1382
1383         path->grh_mlid  = ah->src_path_bits & 0x7f;
1384         path->rlid      = cpu_to_be16(ah->dlid);
1385
1386         if (ah->ah_flags & IB_AH_GRH) {
1387                 if (ah->grh.sgid_index >=
1388                     dev->mdev->port_caps[port - 1].gid_table_len) {
1389                         pr_err("sgid_index (%u) too large. max is %d\n",
1390                                ah->grh.sgid_index,
1391                                dev->mdev->port_caps[port - 1].gid_table_len);
1392                         return -EINVAL;
1393                 }
1394                 path->grh_mlid |= 1 << 7;
1395                 path->mgid_index = ah->grh.sgid_index;
1396                 path->hop_limit  = ah->grh.hop_limit;
1397                 path->tclass_flowlabel =
1398                         cpu_to_be32((ah->grh.traffic_class << 20) |
1399                                     (ah->grh.flow_label));
1400                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1401         }
1402
1403         err = ib_rate_to_mlx5(dev, ah->static_rate);
1404         if (err < 0)
1405                 return err;
1406         path->static_rate = err;
1407         path->port = port;
1408
1409         if (attr_mask & IB_QP_TIMEOUT)
1410                 path->ackto_lt = attr->timeout << 3;
1411
1412         path->sl = ah->sl & 0xf;
1413
1414         return 0;
1415 }
1416
1417 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
1418         [MLX5_QP_STATE_INIT] = {
1419                 [MLX5_QP_STATE_INIT] = {
1420                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
1421                                           MLX5_QP_OPTPAR_RAE            |
1422                                           MLX5_QP_OPTPAR_RWE            |
1423                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
1424                                           MLX5_QP_OPTPAR_PRI_PORT,
1425                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
1426                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
1427                                           MLX5_QP_OPTPAR_PRI_PORT,
1428                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
1429                                           MLX5_QP_OPTPAR_Q_KEY          |
1430                                           MLX5_QP_OPTPAR_PRI_PORT,
1431                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE           |
1432                                           MLX5_QP_OPTPAR_RAE            |
1433                                           MLX5_QP_OPTPAR_RWE            |
1434                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
1435                                           MLX5_QP_OPTPAR_PRI_PORT,
1436                 },
1437                 [MLX5_QP_STATE_RTR] = {
1438                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
1439                                           MLX5_QP_OPTPAR_RRE            |
1440                                           MLX5_QP_OPTPAR_RAE            |
1441                                           MLX5_QP_OPTPAR_RWE            |
1442                                           MLX5_QP_OPTPAR_PKEY_INDEX,
1443                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
1444                                           MLX5_QP_OPTPAR_RWE            |
1445                                           MLX5_QP_OPTPAR_PKEY_INDEX,
1446                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
1447                                           MLX5_QP_OPTPAR_Q_KEY,
1448                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX    |
1449                                            MLX5_QP_OPTPAR_Q_KEY,
1450                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1451                                           MLX5_QP_OPTPAR_RRE            |
1452                                           MLX5_QP_OPTPAR_RAE            |
1453                                           MLX5_QP_OPTPAR_RWE            |
1454                                           MLX5_QP_OPTPAR_PKEY_INDEX,
1455                 },
1456         },
1457         [MLX5_QP_STATE_RTR] = {
1458                 [MLX5_QP_STATE_RTS] = {
1459                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
1460                                           MLX5_QP_OPTPAR_RRE            |
1461                                           MLX5_QP_OPTPAR_RAE            |
1462                                           MLX5_QP_OPTPAR_RWE            |
1463                                           MLX5_QP_OPTPAR_PM_STATE       |
1464                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
1465                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
1466                                           MLX5_QP_OPTPAR_RWE            |
1467                                           MLX5_QP_OPTPAR_PM_STATE,
1468                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
1469                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1470                                           MLX5_QP_OPTPAR_RRE            |
1471                                           MLX5_QP_OPTPAR_RAE            |
1472                                           MLX5_QP_OPTPAR_RWE            |
1473                                           MLX5_QP_OPTPAR_PM_STATE       |
1474                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
1475                 },
1476         },
1477         [MLX5_QP_STATE_RTS] = {
1478                 [MLX5_QP_STATE_RTS] = {
1479                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
1480                                           MLX5_QP_OPTPAR_RAE            |
1481                                           MLX5_QP_OPTPAR_RWE            |
1482                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
1483                                           MLX5_QP_OPTPAR_PM_STATE       |
1484                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
1485                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
1486                                           MLX5_QP_OPTPAR_PM_STATE       |
1487                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
1488                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY          |
1489                                           MLX5_QP_OPTPAR_SRQN           |
1490                                           MLX5_QP_OPTPAR_CQN_RCV,
1491                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE           |
1492                                           MLX5_QP_OPTPAR_RAE            |
1493                                           MLX5_QP_OPTPAR_RWE            |
1494                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
1495                                           MLX5_QP_OPTPAR_PM_STATE       |
1496                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
1497                 },
1498         },
1499         [MLX5_QP_STATE_SQER] = {
1500                 [MLX5_QP_STATE_RTS] = {
1501                         [MLX5_QP_ST_UD]  = MLX5_QP_OPTPAR_Q_KEY,
1502                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
1503                         [MLX5_QP_ST_UC]  = MLX5_QP_OPTPAR_RWE,
1504                         [MLX5_QP_ST_RC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT   |
1505                                            MLX5_QP_OPTPAR_RWE           |
1506                                            MLX5_QP_OPTPAR_RAE           |
1507                                            MLX5_QP_OPTPAR_RRE,
1508                         [MLX5_QP_ST_XRC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT  |
1509                                            MLX5_QP_OPTPAR_RWE           |
1510                                            MLX5_QP_OPTPAR_RAE           |
1511                                            MLX5_QP_OPTPAR_RRE,
1512                 },
1513         },
1514 };
1515
1516 static int ib_nr_to_mlx5_nr(int ib_mask)
1517 {
1518         switch (ib_mask) {
1519         case IB_QP_STATE:
1520                 return 0;
1521         case IB_QP_CUR_STATE:
1522                 return 0;
1523         case IB_QP_EN_SQD_ASYNC_NOTIFY:
1524                 return 0;
1525         case IB_QP_ACCESS_FLAGS:
1526                 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
1527                         MLX5_QP_OPTPAR_RAE;
1528         case IB_QP_PKEY_INDEX:
1529                 return MLX5_QP_OPTPAR_PKEY_INDEX;
1530         case IB_QP_PORT:
1531                 return MLX5_QP_OPTPAR_PRI_PORT;
1532         case IB_QP_QKEY:
1533                 return MLX5_QP_OPTPAR_Q_KEY;
1534         case IB_QP_AV:
1535                 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
1536                         MLX5_QP_OPTPAR_PRI_PORT;
1537         case IB_QP_PATH_MTU:
1538                 return 0;
1539         case IB_QP_TIMEOUT:
1540                 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
1541         case IB_QP_RETRY_CNT:
1542                 return MLX5_QP_OPTPAR_RETRY_COUNT;
1543         case IB_QP_RNR_RETRY:
1544                 return MLX5_QP_OPTPAR_RNR_RETRY;
1545         case IB_QP_RQ_PSN:
1546                 return 0;
1547         case IB_QP_MAX_QP_RD_ATOMIC:
1548                 return MLX5_QP_OPTPAR_SRA_MAX;
1549         case IB_QP_ALT_PATH:
1550                 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
1551         case IB_QP_MIN_RNR_TIMER:
1552                 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
1553         case IB_QP_SQ_PSN:
1554                 return 0;
1555         case IB_QP_MAX_DEST_RD_ATOMIC:
1556                 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
1557                         MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
1558         case IB_QP_PATH_MIG_STATE:
1559                 return MLX5_QP_OPTPAR_PM_STATE;
1560         case IB_QP_CAP:
1561                 return 0;
1562         case IB_QP_DEST_QPN:
1563                 return 0;
1564         }
1565         return 0;
1566 }
1567
1568 static int ib_mask_to_mlx5_opt(int ib_mask)
1569 {
1570         int result = 0;
1571         int i;
1572
1573         for (i = 0; i < 8 * sizeof(int); i++) {
1574                 if ((1 << i) & ib_mask)
1575                         result |= ib_nr_to_mlx5_nr(1 << i);
1576         }
1577
1578         return result;
1579 }
1580
1581 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
1582                                const struct ib_qp_attr *attr, int attr_mask,
1583                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
1584 {
1585         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1586         struct mlx5_ib_qp *qp = to_mqp(ibqp);
1587         struct mlx5_ib_cq *send_cq, *recv_cq;
1588         struct mlx5_qp_context *context;
1589         struct mlx5_modify_qp_mbox_in *in;
1590         struct mlx5_ib_pd *pd;
1591         enum mlx5_qp_state mlx5_cur, mlx5_new;
1592         enum mlx5_qp_optpar optpar;
1593         int sqd_event;
1594         int mlx5_st;
1595         int err;
1596
1597         in = kzalloc(sizeof(*in), GFP_KERNEL);
1598         if (!in)
1599                 return -ENOMEM;
1600
1601         context = &in->ctx;
1602         err = to_mlx5_st(ibqp->qp_type);
1603         if (err < 0)
1604                 goto out;
1605
1606         context->flags = cpu_to_be32(err << 16);
1607
1608         if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
1609                 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
1610         } else {
1611                 switch (attr->path_mig_state) {
1612                 case IB_MIG_MIGRATED:
1613                         context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
1614                         break;
1615                 case IB_MIG_REARM:
1616                         context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
1617                         break;
1618                 case IB_MIG_ARMED:
1619                         context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
1620                         break;
1621                 }
1622         }
1623
1624         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI) {
1625                 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
1626         } else if (ibqp->qp_type == IB_QPT_UD ||
1627                    ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
1628                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
1629         } else if (attr_mask & IB_QP_PATH_MTU) {
1630                 if (attr->path_mtu < IB_MTU_256 ||
1631                     attr->path_mtu > IB_MTU_4096) {
1632                         mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
1633                         err = -EINVAL;
1634                         goto out;
1635                 }
1636                 context->mtu_msgmax = (attr->path_mtu << 5) |
1637                                       (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
1638         }
1639
1640         if (attr_mask & IB_QP_DEST_QPN)
1641                 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
1642
1643         if (attr_mask & IB_QP_PKEY_INDEX)
1644                 context->pri_path.pkey_index = attr->pkey_index;
1645
1646         /* todo implement counter_index functionality */
1647
1648         if (is_sqp(ibqp->qp_type))
1649                 context->pri_path.port = qp->port;
1650
1651         if (attr_mask & IB_QP_PORT)
1652                 context->pri_path.port = attr->port_num;
1653
1654         if (attr_mask & IB_QP_AV) {
1655                 err = mlx5_set_path(dev, &attr->ah_attr, &context->pri_path,
1656                                     attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
1657                                     attr_mask, 0, attr);
1658                 if (err)
1659                         goto out;
1660         }
1661
1662         if (attr_mask & IB_QP_TIMEOUT)
1663                 context->pri_path.ackto_lt |= attr->timeout << 3;
1664
1665         if (attr_mask & IB_QP_ALT_PATH) {
1666                 err = mlx5_set_path(dev, &attr->alt_ah_attr, &context->alt_path,
1667                                     attr->alt_port_num, attr_mask, 0, attr);
1668                 if (err)
1669                         goto out;
1670         }
1671
1672         pd = get_pd(qp);
1673         get_cqs(qp, &send_cq, &recv_cq);
1674
1675         context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
1676         context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
1677         context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
1678         context->params1  = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
1679
1680         if (attr_mask & IB_QP_RNR_RETRY)
1681                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1682
1683         if (attr_mask & IB_QP_RETRY_CNT)
1684                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1685
1686         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1687                 if (attr->max_rd_atomic)
1688                         context->params1 |=
1689                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1690         }
1691
1692         if (attr_mask & IB_QP_SQ_PSN)
1693                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1694
1695         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1696                 if (attr->max_dest_rd_atomic)
1697                         context->params2 |=
1698                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1699         }
1700
1701         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
1702                 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
1703
1704         if (attr_mask & IB_QP_MIN_RNR_TIMER)
1705                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1706
1707         if (attr_mask & IB_QP_RQ_PSN)
1708                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1709
1710         if (attr_mask & IB_QP_QKEY)
1711                 context->qkey = cpu_to_be32(attr->qkey);
1712
1713         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1714                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1715
1716         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
1717             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1718                 sqd_event = 1;
1719         else
1720                 sqd_event = 0;
1721
1722         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1723                 context->sq_crq_size |= cpu_to_be16(1 << 4);
1724
1725
1726         mlx5_cur = to_mlx5_state(cur_state);
1727         mlx5_new = to_mlx5_state(new_state);
1728         mlx5_st = to_mlx5_st(ibqp->qp_type);
1729         if (mlx5_st < 0)
1730                 goto out;
1731
1732         /* If moving to a reset or error state, we must disable page faults on
1733          * this QP and flush all current page faults. Otherwise a stale page
1734          * fault may attempt to work on this QP after it is reset and moved
1735          * again to RTS, and may cause the driver and the device to get out of
1736          * sync. */
1737         if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
1738             (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
1739                 mlx5_ib_qp_disable_pagefaults(qp);
1740
1741         optpar = ib_mask_to_mlx5_opt(attr_mask);
1742         optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
1743         in->optparam = cpu_to_be32(optpar);
1744         err = mlx5_core_qp_modify(dev->mdev, to_mlx5_state(cur_state),
1745                                   to_mlx5_state(new_state), in, sqd_event,
1746                                   &qp->mqp);
1747         if (err)
1748                 goto out;
1749
1750         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1751                 mlx5_ib_qp_enable_pagefaults(qp);
1752
1753         qp->state = new_state;
1754
1755         if (attr_mask & IB_QP_ACCESS_FLAGS)
1756                 qp->atomic_rd_en = attr->qp_access_flags;
1757         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1758                 qp->resp_depth = attr->max_dest_rd_atomic;
1759         if (attr_mask & IB_QP_PORT)
1760                 qp->port = attr->port_num;
1761         if (attr_mask & IB_QP_ALT_PATH)
1762                 qp->alt_port = attr->alt_port_num;
1763
1764         /*
1765          * If we moved a kernel QP to RESET, clean up all old CQ
1766          * entries and reinitialize the QP.
1767          */
1768         if (new_state == IB_QPS_RESET && !ibqp->uobject) {
1769                 mlx5_ib_cq_clean(recv_cq, qp->mqp.qpn,
1770                                  ibqp->srq ? to_msrq(ibqp->srq) : NULL);
1771                 if (send_cq != recv_cq)
1772                         mlx5_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1773
1774                 qp->rq.head = 0;
1775                 qp->rq.tail = 0;
1776                 qp->sq.head = 0;
1777                 qp->sq.tail = 0;
1778                 qp->sq.cur_post = 0;
1779                 qp->sq.last_poll = 0;
1780                 qp->db.db[MLX5_RCV_DBR] = 0;
1781                 qp->db.db[MLX5_SND_DBR] = 0;
1782         }
1783
1784 out:
1785         kfree(in);
1786         return err;
1787 }
1788
1789 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1790                       int attr_mask, struct ib_udata *udata)
1791 {
1792         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1793         struct mlx5_ib_qp *qp = to_mqp(ibqp);
1794         enum ib_qp_state cur_state, new_state;
1795         int err = -EINVAL;
1796         int port;
1797
1798         mutex_lock(&qp->mutex);
1799
1800         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1801         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1802
1803         if (ibqp->qp_type != MLX5_IB_QPT_REG_UMR &&
1804             !ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask,
1805                                 IB_LINK_LAYER_UNSPECIFIED))
1806                 goto out;
1807
1808         if ((attr_mask & IB_QP_PORT) &&
1809             (attr->port_num == 0 ||
1810              attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)))
1811                 goto out;
1812
1813         if (attr_mask & IB_QP_PKEY_INDEX) {
1814                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1815                 if (attr->pkey_index >=
1816                     dev->mdev->port_caps[port - 1].pkey_table_len)
1817                         goto out;
1818         }
1819
1820         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1821             attr->max_rd_atomic >
1822             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp)))
1823                 goto out;
1824
1825         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1826             attr->max_dest_rd_atomic >
1827             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp)))
1828                 goto out;
1829
1830         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1831                 err = 0;
1832                 goto out;
1833         }
1834
1835         err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1836
1837 out:
1838         mutex_unlock(&qp->mutex);
1839         return err;
1840 }
1841
1842 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
1843 {
1844         struct mlx5_ib_cq *cq;
1845         unsigned cur;
1846
1847         cur = wq->head - wq->tail;
1848         if (likely(cur + nreq < wq->max_post))
1849                 return 0;
1850
1851         cq = to_mcq(ib_cq);
1852         spin_lock(&cq->lock);
1853         cur = wq->head - wq->tail;
1854         spin_unlock(&cq->lock);
1855
1856         return cur + nreq >= wq->max_post;
1857 }
1858
1859 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
1860                                           u64 remote_addr, u32 rkey)
1861 {
1862         rseg->raddr    = cpu_to_be64(remote_addr);
1863         rseg->rkey     = cpu_to_be32(rkey);
1864         rseg->reserved = 0;
1865 }
1866
1867 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
1868                              struct ib_send_wr *wr)
1869 {
1870         memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
1871         dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
1872         dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
1873 }
1874
1875 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
1876 {
1877         dseg->byte_count = cpu_to_be32(sg->length);
1878         dseg->lkey       = cpu_to_be32(sg->lkey);
1879         dseg->addr       = cpu_to_be64(sg->addr);
1880 }
1881
1882 static __be16 get_klm_octo(int npages)
1883 {
1884         return cpu_to_be16(ALIGN(npages, 8) / 2);
1885 }
1886
1887 static __be64 frwr_mkey_mask(void)
1888 {
1889         u64 result;
1890
1891         result = MLX5_MKEY_MASK_LEN             |
1892                 MLX5_MKEY_MASK_PAGE_SIZE        |
1893                 MLX5_MKEY_MASK_START_ADDR       |
1894                 MLX5_MKEY_MASK_EN_RINVAL        |
1895                 MLX5_MKEY_MASK_KEY              |
1896                 MLX5_MKEY_MASK_LR               |
1897                 MLX5_MKEY_MASK_LW               |
1898                 MLX5_MKEY_MASK_RR               |
1899                 MLX5_MKEY_MASK_RW               |
1900                 MLX5_MKEY_MASK_A                |
1901                 MLX5_MKEY_MASK_SMALL_FENCE      |
1902                 MLX5_MKEY_MASK_FREE;
1903
1904         return cpu_to_be64(result);
1905 }
1906
1907 static __be64 sig_mkey_mask(void)
1908 {
1909         u64 result;
1910
1911         result = MLX5_MKEY_MASK_LEN             |
1912                 MLX5_MKEY_MASK_PAGE_SIZE        |
1913                 MLX5_MKEY_MASK_START_ADDR       |
1914                 MLX5_MKEY_MASK_EN_SIGERR        |
1915                 MLX5_MKEY_MASK_EN_RINVAL        |
1916                 MLX5_MKEY_MASK_KEY              |
1917                 MLX5_MKEY_MASK_LR               |
1918                 MLX5_MKEY_MASK_LW               |
1919                 MLX5_MKEY_MASK_RR               |
1920                 MLX5_MKEY_MASK_RW               |
1921                 MLX5_MKEY_MASK_SMALL_FENCE      |
1922                 MLX5_MKEY_MASK_FREE             |
1923                 MLX5_MKEY_MASK_BSF_EN;
1924
1925         return cpu_to_be64(result);
1926 }
1927
1928 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
1929                                 struct mlx5_ib_mr *mr)
1930 {
1931         int ndescs = mr->ndescs;
1932
1933         memset(umr, 0, sizeof(*umr));
1934         umr->flags = MLX5_UMR_CHECK_NOT_FREE;
1935         umr->klm_octowords = get_klm_octo(ndescs);
1936         umr->mkey_mask = frwr_mkey_mask();
1937 }
1938
1939 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
1940 {
1941         memset(umr, 0, sizeof(*umr));
1942         umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
1943         umr->flags = 1 << 7;
1944 }
1945
1946 static __be64 get_umr_reg_mr_mask(void)
1947 {
1948         u64 result;
1949
1950         result = MLX5_MKEY_MASK_LEN             |
1951                  MLX5_MKEY_MASK_PAGE_SIZE       |
1952                  MLX5_MKEY_MASK_START_ADDR      |
1953                  MLX5_MKEY_MASK_PD              |
1954                  MLX5_MKEY_MASK_LR              |
1955                  MLX5_MKEY_MASK_LW              |
1956                  MLX5_MKEY_MASK_KEY             |
1957                  MLX5_MKEY_MASK_RR              |
1958                  MLX5_MKEY_MASK_RW              |
1959                  MLX5_MKEY_MASK_A               |
1960                  MLX5_MKEY_MASK_FREE;
1961
1962         return cpu_to_be64(result);
1963 }
1964
1965 static __be64 get_umr_unreg_mr_mask(void)
1966 {
1967         u64 result;
1968
1969         result = MLX5_MKEY_MASK_FREE;
1970
1971         return cpu_to_be64(result);
1972 }
1973
1974 static __be64 get_umr_update_mtt_mask(void)
1975 {
1976         u64 result;
1977
1978         result = MLX5_MKEY_MASK_FREE;
1979
1980         return cpu_to_be64(result);
1981 }
1982
1983 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
1984                                 struct ib_send_wr *wr)
1985 {
1986         struct mlx5_umr_wr *umrwr = umr_wr(wr);
1987
1988         memset(umr, 0, sizeof(*umr));
1989
1990         if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
1991                 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
1992         else
1993                 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
1994
1995         if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) {
1996                 umr->klm_octowords = get_klm_octo(umrwr->npages);
1997                 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT) {
1998                         umr->mkey_mask = get_umr_update_mtt_mask();
1999                         umr->bsf_octowords = get_klm_octo(umrwr->target.offset);
2000                         umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
2001                 } else {
2002                         umr->mkey_mask = get_umr_reg_mr_mask();
2003                 }
2004         } else {
2005                 umr->mkey_mask = get_umr_unreg_mr_mask();
2006         }
2007
2008         if (!wr->num_sge)
2009                 umr->flags |= MLX5_UMR_INLINE;
2010 }
2011
2012 static u8 get_umr_flags(int acc)
2013 {
2014         return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC       : 0) |
2015                (acc & IB_ACCESS_REMOTE_WRITE  ? MLX5_PERM_REMOTE_WRITE : 0) |
2016                (acc & IB_ACCESS_REMOTE_READ   ? MLX5_PERM_REMOTE_READ  : 0) |
2017                (acc & IB_ACCESS_LOCAL_WRITE   ? MLX5_PERM_LOCAL_WRITE  : 0) |
2018                 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
2019 }
2020
2021 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
2022                              struct mlx5_ib_mr *mr,
2023                              u32 key, int access)
2024 {
2025         int ndescs = ALIGN(mr->ndescs, 8) >> 1;
2026
2027         memset(seg, 0, sizeof(*seg));
2028         seg->flags = get_umr_flags(access) | MLX5_ACCESS_MODE_MTT;
2029         seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
2030         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
2031         seg->start_addr = cpu_to_be64(mr->ibmr.iova);
2032         seg->len = cpu_to_be64(mr->ibmr.length);
2033         seg->xlt_oct_size = cpu_to_be32(ndescs);
2034         seg->log2_page_size = ilog2(mr->ibmr.page_size);
2035 }
2036
2037 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
2038 {
2039         memset(seg, 0, sizeof(*seg));
2040         seg->status = MLX5_MKEY_STATUS_FREE;
2041 }
2042
2043 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
2044 {
2045         struct mlx5_umr_wr *umrwr = umr_wr(wr);
2046
2047         memset(seg, 0, sizeof(*seg));
2048         if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) {
2049                 seg->status = MLX5_MKEY_STATUS_FREE;
2050                 return;
2051         }
2052
2053         seg->flags = convert_access(umrwr->access_flags);
2054         if (!(wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT)) {
2055                 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
2056                 seg->start_addr = cpu_to_be64(umrwr->target.virt_addr);
2057         }
2058         seg->len = cpu_to_be64(umrwr->length);
2059         seg->log2_page_size = umrwr->page_shift;
2060         seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
2061                                        mlx5_mkey_variant(umrwr->mkey));
2062 }
2063
2064 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
2065                              struct mlx5_ib_mr *mr,
2066                              struct mlx5_ib_pd *pd)
2067 {
2068         int bcount = mr->desc_size * mr->ndescs;
2069
2070         dseg->addr = cpu_to_be64(mr->desc_map);
2071         dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
2072         dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
2073 }
2074
2075 static __be32 send_ieth(struct ib_send_wr *wr)
2076 {
2077         switch (wr->opcode) {
2078         case IB_WR_SEND_WITH_IMM:
2079         case IB_WR_RDMA_WRITE_WITH_IMM:
2080                 return wr->ex.imm_data;
2081
2082         case IB_WR_SEND_WITH_INV:
2083                 return cpu_to_be32(wr->ex.invalidate_rkey);
2084
2085         default:
2086                 return 0;
2087         }
2088 }
2089
2090 static u8 calc_sig(void *wqe, int size)
2091 {
2092         u8 *p = wqe;
2093         u8 res = 0;
2094         int i;
2095
2096         for (i = 0; i < size; i++)
2097                 res ^= p[i];
2098
2099         return ~res;
2100 }
2101
2102 static u8 wq_sig(void *wqe)
2103 {
2104         return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
2105 }
2106
2107 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
2108                             void *wqe, int *sz)
2109 {
2110         struct mlx5_wqe_inline_seg *seg;
2111         void *qend = qp->sq.qend;
2112         void *addr;
2113         int inl = 0;
2114         int copy;
2115         int len;
2116         int i;
2117
2118         seg = wqe;
2119         wqe += sizeof(*seg);
2120         for (i = 0; i < wr->num_sge; i++) {
2121                 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
2122                 len  = wr->sg_list[i].length;
2123                 inl += len;
2124
2125                 if (unlikely(inl > qp->max_inline_data))
2126                         return -ENOMEM;
2127
2128                 if (unlikely(wqe + len > qend)) {
2129                         copy = qend - wqe;
2130                         memcpy(wqe, addr, copy);
2131                         addr += copy;
2132                         len -= copy;
2133                         wqe = mlx5_get_send_wqe(qp, 0);
2134                 }
2135                 memcpy(wqe, addr, len);
2136                 wqe += len;
2137         }
2138
2139         seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
2140
2141         *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
2142
2143         return 0;
2144 }
2145
2146 static u16 prot_field_size(enum ib_signature_type type)
2147 {
2148         switch (type) {
2149         case IB_SIG_TYPE_T10_DIF:
2150                 return MLX5_DIF_SIZE;
2151         default:
2152                 return 0;
2153         }
2154 }
2155
2156 static u8 bs_selector(int block_size)
2157 {
2158         switch (block_size) {
2159         case 512:           return 0x1;
2160         case 520:           return 0x2;
2161         case 4096:          return 0x3;
2162         case 4160:          return 0x4;
2163         case 1073741824:    return 0x5;
2164         default:            return 0;
2165         }
2166 }
2167
2168 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
2169                               struct mlx5_bsf_inl *inl)
2170 {
2171         /* Valid inline section and allow BSF refresh */
2172         inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
2173                                        MLX5_BSF_REFRESH_DIF);
2174         inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
2175         inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
2176         /* repeating block */
2177         inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
2178         inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
2179                         MLX5_DIF_CRC : MLX5_DIF_IPCS;
2180
2181         if (domain->sig.dif.ref_remap)
2182                 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
2183
2184         if (domain->sig.dif.app_escape) {
2185                 if (domain->sig.dif.ref_escape)
2186                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
2187                 else
2188                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
2189         }
2190
2191         inl->dif_app_bitmask_check =
2192                 cpu_to_be16(domain->sig.dif.apptag_check_mask);
2193 }
2194
2195 static int mlx5_set_bsf(struct ib_mr *sig_mr,
2196                         struct ib_sig_attrs *sig_attrs,
2197                         struct mlx5_bsf *bsf, u32 data_size)
2198 {
2199         struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
2200         struct mlx5_bsf_basic *basic = &bsf->basic;
2201         struct ib_sig_domain *mem = &sig_attrs->mem;
2202         struct ib_sig_domain *wire = &sig_attrs->wire;
2203
2204         memset(bsf, 0, sizeof(*bsf));
2205
2206         /* Basic + Extended + Inline */
2207         basic->bsf_size_sbs = 1 << 7;
2208         /* Input domain check byte mask */
2209         basic->check_byte_mask = sig_attrs->check_mask;
2210         basic->raw_data_size = cpu_to_be32(data_size);
2211
2212         /* Memory domain */
2213         switch (sig_attrs->mem.sig_type) {
2214         case IB_SIG_TYPE_NONE:
2215                 break;
2216         case IB_SIG_TYPE_T10_DIF:
2217                 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
2218                 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
2219                 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
2220                 break;
2221         default:
2222                 return -EINVAL;
2223         }
2224
2225         /* Wire domain */
2226         switch (sig_attrs->wire.sig_type) {
2227         case IB_SIG_TYPE_NONE:
2228                 break;
2229         case IB_SIG_TYPE_T10_DIF:
2230                 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
2231                     mem->sig_type == wire->sig_type) {
2232                         /* Same block structure */
2233                         basic->bsf_size_sbs |= 1 << 4;
2234                         if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
2235                                 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
2236                         if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
2237                                 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
2238                         if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
2239                                 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
2240                 } else
2241                         basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
2242
2243                 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
2244                 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
2245                 break;
2246         default:
2247                 return -EINVAL;
2248         }
2249
2250         return 0;
2251 }
2252
2253 static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
2254                                 struct mlx5_ib_qp *qp, void **seg, int *size)
2255 {
2256         struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
2257         struct ib_mr *sig_mr = wr->sig_mr;
2258         struct mlx5_bsf *bsf;
2259         u32 data_len = wr->wr.sg_list->length;
2260         u32 data_key = wr->wr.sg_list->lkey;
2261         u64 data_va = wr->wr.sg_list->addr;
2262         int ret;
2263         int wqe_size;
2264
2265         if (!wr->prot ||
2266             (data_key == wr->prot->lkey &&
2267              data_va == wr->prot->addr &&
2268              data_len == wr->prot->length)) {
2269                 /**
2270                  * Source domain doesn't contain signature information
2271                  * or data and protection are interleaved in memory.
2272                  * So need construct:
2273                  *                  ------------------
2274                  *                 |     data_klm     |
2275                  *                  ------------------
2276                  *                 |       BSF        |
2277                  *                  ------------------
2278                  **/
2279                 struct mlx5_klm *data_klm = *seg;
2280
2281                 data_klm->bcount = cpu_to_be32(data_len);
2282                 data_klm->key = cpu_to_be32(data_key);
2283                 data_klm->va = cpu_to_be64(data_va);
2284                 wqe_size = ALIGN(sizeof(*data_klm), 64);
2285         } else {
2286                 /**
2287                  * Source domain contains signature information
2288                  * So need construct a strided block format:
2289                  *               ---------------------------
2290                  *              |     stride_block_ctrl     |
2291                  *               ---------------------------
2292                  *              |          data_klm         |
2293                  *               ---------------------------
2294                  *              |          prot_klm         |
2295                  *               ---------------------------
2296                  *              |             BSF           |
2297                  *               ---------------------------
2298                  **/
2299                 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
2300                 struct mlx5_stride_block_entry *data_sentry;
2301                 struct mlx5_stride_block_entry *prot_sentry;
2302                 u32 prot_key = wr->prot->lkey;
2303                 u64 prot_va = wr->prot->addr;
2304                 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
2305                 int prot_size;
2306
2307                 sblock_ctrl = *seg;
2308                 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
2309                 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
2310
2311                 prot_size = prot_field_size(sig_attrs->mem.sig_type);
2312                 if (!prot_size) {
2313                         pr_err("Bad block size given: %u\n", block_size);
2314                         return -EINVAL;
2315                 }
2316                 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
2317                                                             prot_size);
2318                 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
2319                 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
2320                 sblock_ctrl->num_entries = cpu_to_be16(2);
2321
2322                 data_sentry->bcount = cpu_to_be16(block_size);
2323                 data_sentry->key = cpu_to_be32(data_key);
2324                 data_sentry->va = cpu_to_be64(data_va);
2325                 data_sentry->stride = cpu_to_be16(block_size);
2326
2327                 prot_sentry->bcount = cpu_to_be16(prot_size);
2328                 prot_sentry->key = cpu_to_be32(prot_key);
2329                 prot_sentry->va = cpu_to_be64(prot_va);
2330                 prot_sentry->stride = cpu_to_be16(prot_size);
2331
2332                 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
2333                                  sizeof(*prot_sentry), 64);
2334         }
2335
2336         *seg += wqe_size;
2337         *size += wqe_size / 16;
2338         if (unlikely((*seg == qp->sq.qend)))
2339                 *seg = mlx5_get_send_wqe(qp, 0);
2340
2341         bsf = *seg;
2342         ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
2343         if (ret)
2344                 return -EINVAL;
2345
2346         *seg += sizeof(*bsf);
2347         *size += sizeof(*bsf) / 16;
2348         if (unlikely((*seg == qp->sq.qend)))
2349                 *seg = mlx5_get_send_wqe(qp, 0);
2350
2351         return 0;
2352 }
2353
2354 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
2355                                  struct ib_sig_handover_wr *wr, u32 nelements,
2356                                  u32 length, u32 pdn)
2357 {
2358         struct ib_mr *sig_mr = wr->sig_mr;
2359         u32 sig_key = sig_mr->rkey;
2360         u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
2361
2362         memset(seg, 0, sizeof(*seg));
2363
2364         seg->flags = get_umr_flags(wr->access_flags) |
2365                                    MLX5_ACCESS_MODE_KLM;
2366         seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
2367         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
2368                                     MLX5_MKEY_BSF_EN | pdn);
2369         seg->len = cpu_to_be64(length);
2370         seg->xlt_oct_size = cpu_to_be32(be16_to_cpu(get_klm_octo(nelements)));
2371         seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
2372 }
2373
2374 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
2375                                 u32 nelements)
2376 {
2377         memset(umr, 0, sizeof(*umr));
2378
2379         umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
2380         umr->klm_octowords = get_klm_octo(nelements);
2381         umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
2382         umr->mkey_mask = sig_mkey_mask();
2383 }
2384
2385
2386 static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
2387                           void **seg, int *size)
2388 {
2389         struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
2390         struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
2391         u32 pdn = get_pd(qp)->pdn;
2392         u32 klm_oct_size;
2393         int region_len, ret;
2394
2395         if (unlikely(wr->wr.num_sge != 1) ||
2396             unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
2397             unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
2398             unlikely(!sig_mr->sig->sig_status_checked))
2399                 return -EINVAL;
2400
2401         /* length of the protected region, data + protection */
2402         region_len = wr->wr.sg_list->length;
2403         if (wr->prot &&
2404             (wr->prot->lkey != wr->wr.sg_list->lkey  ||
2405              wr->prot->addr != wr->wr.sg_list->addr  ||
2406              wr->prot->length != wr->wr.sg_list->length))
2407                 region_len += wr->prot->length;
2408
2409         /**
2410          * KLM octoword size - if protection was provided
2411          * then we use strided block format (3 octowords),
2412          * else we use single KLM (1 octoword)
2413          **/
2414         klm_oct_size = wr->prot ? 3 : 1;
2415
2416         set_sig_umr_segment(*seg, klm_oct_size);
2417         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
2418         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
2419         if (unlikely((*seg == qp->sq.qend)))
2420                 *seg = mlx5_get_send_wqe(qp, 0);
2421
2422         set_sig_mkey_segment(*seg, wr, klm_oct_size, region_len, pdn);
2423         *seg += sizeof(struct mlx5_mkey_seg);
2424         *size += sizeof(struct mlx5_mkey_seg) / 16;
2425         if (unlikely((*seg == qp->sq.qend)))
2426                 *seg = mlx5_get_send_wqe(qp, 0);
2427
2428         ret = set_sig_data_segment(wr, qp, seg, size);
2429         if (ret)
2430                 return ret;
2431
2432         sig_mr->sig->sig_status_checked = false;
2433         return 0;
2434 }
2435
2436 static int set_psv_wr(struct ib_sig_domain *domain,
2437                       u32 psv_idx, void **seg, int *size)
2438 {
2439         struct mlx5_seg_set_psv *psv_seg = *seg;
2440
2441         memset(psv_seg, 0, sizeof(*psv_seg));
2442         psv_seg->psv_num = cpu_to_be32(psv_idx);
2443         switch (domain->sig_type) {
2444         case IB_SIG_TYPE_NONE:
2445                 break;
2446         case IB_SIG_TYPE_T10_DIF:
2447                 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
2448                                                      domain->sig.dif.app_tag);
2449                 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
2450                 break;
2451         default:
2452                 pr_err("Bad signature type given.\n");
2453                 return 1;
2454         }
2455
2456         *seg += sizeof(*psv_seg);
2457         *size += sizeof(*psv_seg) / 16;
2458
2459         return 0;
2460 }
2461
2462 static int set_reg_wr(struct mlx5_ib_qp *qp,
2463                       struct ib_reg_wr *wr,
2464                       void **seg, int *size)
2465 {
2466         struct mlx5_ib_mr *mr = to_mmr(wr->mr);
2467         struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
2468
2469         if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
2470                 mlx5_ib_warn(to_mdev(qp->ibqp.device),
2471                              "Invalid IB_SEND_INLINE send flag\n");
2472                 return -EINVAL;
2473         }
2474
2475         set_reg_umr_seg(*seg, mr);
2476         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
2477         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
2478         if (unlikely((*seg == qp->sq.qend)))
2479                 *seg = mlx5_get_send_wqe(qp, 0);
2480
2481         set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
2482         *seg += sizeof(struct mlx5_mkey_seg);
2483         *size += sizeof(struct mlx5_mkey_seg) / 16;
2484         if (unlikely((*seg == qp->sq.qend)))
2485                 *seg = mlx5_get_send_wqe(qp, 0);
2486
2487         set_reg_data_seg(*seg, mr, pd);
2488         *seg += sizeof(struct mlx5_wqe_data_seg);
2489         *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
2490
2491         return 0;
2492 }
2493
2494 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
2495 {
2496         set_linv_umr_seg(*seg);
2497         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
2498         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
2499         if (unlikely((*seg == qp->sq.qend)))
2500                 *seg = mlx5_get_send_wqe(qp, 0);
2501         set_linv_mkey_seg(*seg);
2502         *seg += sizeof(struct mlx5_mkey_seg);
2503         *size += sizeof(struct mlx5_mkey_seg) / 16;
2504         if (unlikely((*seg == qp->sq.qend)))
2505                 *seg = mlx5_get_send_wqe(qp, 0);
2506 }
2507
2508 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
2509 {
2510         __be32 *p = NULL;
2511         int tidx = idx;
2512         int i, j;
2513
2514         pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
2515         for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
2516                 if ((i & 0xf) == 0) {
2517                         void *buf = mlx5_get_send_wqe(qp, tidx);
2518                         tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
2519                         p = buf;
2520                         j = 0;
2521                 }
2522                 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
2523                          be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
2524                          be32_to_cpu(p[j + 3]));
2525         }
2526 }
2527
2528 static void mlx5_bf_copy(u64 __iomem *dst, u64 *src,
2529                          unsigned bytecnt, struct mlx5_ib_qp *qp)
2530 {
2531         while (bytecnt > 0) {
2532                 __iowrite64_copy(dst++, src++, 8);
2533                 __iowrite64_copy(dst++, src++, 8);
2534                 __iowrite64_copy(dst++, src++, 8);
2535                 __iowrite64_copy(dst++, src++, 8);
2536                 __iowrite64_copy(dst++, src++, 8);
2537                 __iowrite64_copy(dst++, src++, 8);
2538                 __iowrite64_copy(dst++, src++, 8);
2539                 __iowrite64_copy(dst++, src++, 8);
2540                 bytecnt -= 64;
2541                 if (unlikely(src == qp->sq.qend))
2542                         src = mlx5_get_send_wqe(qp, 0);
2543         }
2544 }
2545
2546 static u8 get_fence(u8 fence, struct ib_send_wr *wr)
2547 {
2548         if (unlikely(wr->opcode == IB_WR_LOCAL_INV &&
2549                      wr->send_flags & IB_SEND_FENCE))
2550                 return MLX5_FENCE_MODE_STRONG_ORDERING;
2551
2552         if (unlikely(fence)) {
2553                 if (wr->send_flags & IB_SEND_FENCE)
2554                         return MLX5_FENCE_MODE_SMALL_AND_FENCE;
2555                 else
2556                         return fence;
2557         } else if (unlikely(wr->send_flags & IB_SEND_FENCE)) {
2558                 return MLX5_FENCE_MODE_FENCE;
2559         }
2560
2561         return 0;
2562 }
2563
2564 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
2565                      struct mlx5_wqe_ctrl_seg **ctrl,
2566                      struct ib_send_wr *wr, unsigned *idx,
2567                      int *size, int nreq)
2568 {
2569         int err = 0;
2570
2571         if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) {
2572                 err = -ENOMEM;
2573                 return err;
2574         }
2575
2576         *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
2577         *seg = mlx5_get_send_wqe(qp, *idx);
2578         *ctrl = *seg;
2579         *(uint32_t *)(*seg + 8) = 0;
2580         (*ctrl)->imm = send_ieth(wr);
2581         (*ctrl)->fm_ce_se = qp->sq_signal_bits |
2582                 (wr->send_flags & IB_SEND_SIGNALED ?
2583                  MLX5_WQE_CTRL_CQ_UPDATE : 0) |
2584                 (wr->send_flags & IB_SEND_SOLICITED ?
2585                  MLX5_WQE_CTRL_SOLICITED : 0);
2586
2587         *seg += sizeof(**ctrl);
2588         *size = sizeof(**ctrl) / 16;
2589
2590         return err;
2591 }
2592
2593 static void finish_wqe(struct mlx5_ib_qp *qp,
2594                        struct mlx5_wqe_ctrl_seg *ctrl,
2595                        u8 size, unsigned idx, u64 wr_id,
2596                        int nreq, u8 fence, u8 next_fence,
2597                        u32 mlx5_opcode)
2598 {
2599         u8 opmod = 0;
2600
2601         ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
2602                                              mlx5_opcode | ((u32)opmod << 24));
2603         ctrl->qpn_ds = cpu_to_be32(size | (qp->mqp.qpn << 8));
2604         ctrl->fm_ce_se |= fence;
2605         qp->fm_cache = next_fence;
2606         if (unlikely(qp->wq_sig))
2607                 ctrl->signature = wq_sig(ctrl);
2608
2609         qp->sq.wrid[idx] = wr_id;
2610         qp->sq.w_list[idx].opcode = mlx5_opcode;
2611         qp->sq.wqe_head[idx] = qp->sq.head + nreq;
2612         qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
2613         qp->sq.w_list[idx].next = qp->sq.cur_post;
2614 }
2615
2616
2617 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2618                       struct ib_send_wr **bad_wr)
2619 {
2620         struct mlx5_wqe_ctrl_seg *ctrl = NULL;  /* compiler warning */
2621         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2622         struct mlx5_ib_qp *qp = to_mqp(ibqp);
2623         struct mlx5_ib_mr *mr;
2624         struct mlx5_wqe_data_seg *dpseg;
2625         struct mlx5_wqe_xrc_seg *xrc;
2626         struct mlx5_bf *bf = qp->bf;
2627         int uninitialized_var(size);
2628         void *qend = qp->sq.qend;
2629         unsigned long flags;
2630         unsigned idx;
2631         int err = 0;
2632         int inl = 0;
2633         int num_sge;
2634         void *seg;
2635         int nreq;
2636         int i;
2637         u8 next_fence = 0;
2638         u8 fence;
2639
2640         spin_lock_irqsave(&qp->sq.lock, flags);
2641
2642         for (nreq = 0; wr; nreq++, wr = wr->next) {
2643                 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
2644                         mlx5_ib_warn(dev, "\n");
2645                         err = -EINVAL;
2646                         *bad_wr = wr;
2647                         goto out;
2648                 }
2649
2650                 fence = qp->fm_cache;
2651                 num_sge = wr->num_sge;
2652                 if (unlikely(num_sge > qp->sq.max_gs)) {
2653                         mlx5_ib_warn(dev, "\n");
2654                         err = -ENOMEM;
2655                         *bad_wr = wr;
2656                         goto out;
2657                 }
2658
2659                 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
2660                 if (err) {
2661                         mlx5_ib_warn(dev, "\n");
2662                         err = -ENOMEM;
2663                         *bad_wr = wr;
2664                         goto out;
2665                 }
2666
2667                 switch (ibqp->qp_type) {
2668                 case IB_QPT_XRC_INI:
2669                         xrc = seg;
2670                         seg += sizeof(*xrc);
2671                         size += sizeof(*xrc) / 16;
2672                         /* fall through */
2673                 case IB_QPT_RC:
2674                         switch (wr->opcode) {
2675                         case IB_WR_RDMA_READ:
2676                         case IB_WR_RDMA_WRITE:
2677                         case IB_WR_RDMA_WRITE_WITH_IMM:
2678                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
2679                                               rdma_wr(wr)->rkey);
2680                                 seg += sizeof(struct mlx5_wqe_raddr_seg);
2681                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
2682                                 break;
2683
2684                         case IB_WR_ATOMIC_CMP_AND_SWP:
2685                         case IB_WR_ATOMIC_FETCH_AND_ADD:
2686                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
2687                                 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
2688                                 err = -ENOSYS;
2689                                 *bad_wr = wr;
2690                                 goto out;
2691
2692                         case IB_WR_LOCAL_INV:
2693                                 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
2694                                 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
2695                                 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
2696                                 set_linv_wr(qp, &seg, &size);
2697                                 num_sge = 0;
2698                                 break;
2699
2700                         case IB_WR_REG_MR:
2701                                 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
2702                                 qp->sq.wr_data[idx] = IB_WR_REG_MR;
2703                                 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
2704                                 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
2705                                 if (err) {
2706                                         *bad_wr = wr;
2707                                         goto out;
2708                                 }
2709                                 num_sge = 0;
2710                                 break;
2711
2712                         case IB_WR_REG_SIG_MR:
2713                                 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
2714                                 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
2715
2716                                 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
2717                                 err = set_sig_umr_wr(wr, qp, &seg, &size);
2718                                 if (err) {
2719                                         mlx5_ib_warn(dev, "\n");
2720                                         *bad_wr = wr;
2721                                         goto out;
2722                                 }
2723
2724                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
2725                                            nreq, get_fence(fence, wr),
2726                                            next_fence, MLX5_OPCODE_UMR);
2727                                 /*
2728                                  * SET_PSV WQEs are not signaled and solicited
2729                                  * on error
2730                                  */
2731                                 wr->send_flags &= ~IB_SEND_SIGNALED;
2732                                 wr->send_flags |= IB_SEND_SOLICITED;
2733                                 err = begin_wqe(qp, &seg, &ctrl, wr,
2734                                                 &idx, &size, nreq);
2735                                 if (err) {
2736                                         mlx5_ib_warn(dev, "\n");
2737                                         err = -ENOMEM;
2738                                         *bad_wr = wr;
2739                                         goto out;
2740                                 }
2741
2742                                 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
2743                                                  mr->sig->psv_memory.psv_idx, &seg,
2744                                                  &size);
2745                                 if (err) {
2746                                         mlx5_ib_warn(dev, "\n");
2747                                         *bad_wr = wr;
2748                                         goto out;
2749                                 }
2750
2751                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
2752                                            nreq, get_fence(fence, wr),
2753                                            next_fence, MLX5_OPCODE_SET_PSV);
2754                                 err = begin_wqe(qp, &seg, &ctrl, wr,
2755                                                 &idx, &size, nreq);
2756                                 if (err) {
2757                                         mlx5_ib_warn(dev, "\n");
2758                                         err = -ENOMEM;
2759                                         *bad_wr = wr;
2760                                         goto out;
2761                                 }
2762
2763                                 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
2764                                 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
2765                                                  mr->sig->psv_wire.psv_idx, &seg,
2766                                                  &size);
2767                                 if (err) {
2768                                         mlx5_ib_warn(dev, "\n");
2769                                         *bad_wr = wr;
2770                                         goto out;
2771                                 }
2772
2773                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
2774                                            nreq, get_fence(fence, wr),
2775                                            next_fence, MLX5_OPCODE_SET_PSV);
2776                                 num_sge = 0;
2777                                 goto skip_psv;
2778
2779                         default:
2780                                 break;
2781                         }
2782                         break;
2783
2784                 case IB_QPT_UC:
2785                         switch (wr->opcode) {
2786                         case IB_WR_RDMA_WRITE:
2787                         case IB_WR_RDMA_WRITE_WITH_IMM:
2788                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
2789                                               rdma_wr(wr)->rkey);
2790                                 seg  += sizeof(struct mlx5_wqe_raddr_seg);
2791                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
2792                                 break;
2793
2794                         default:
2795                                 break;
2796                         }
2797                         break;
2798
2799                 case IB_QPT_UD:
2800                 case IB_QPT_SMI:
2801                 case IB_QPT_GSI:
2802                         set_datagram_seg(seg, wr);
2803                         seg += sizeof(struct mlx5_wqe_datagram_seg);
2804                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
2805                         if (unlikely((seg == qend)))
2806                                 seg = mlx5_get_send_wqe(qp, 0);
2807                         break;
2808
2809                 case MLX5_IB_QPT_REG_UMR:
2810                         if (wr->opcode != MLX5_IB_WR_UMR) {
2811                                 err = -EINVAL;
2812                                 mlx5_ib_warn(dev, "bad opcode\n");
2813                                 goto out;
2814                         }
2815                         qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
2816                         ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
2817                         set_reg_umr_segment(seg, wr);
2818                         seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
2819                         size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
2820                         if (unlikely((seg == qend)))
2821                                 seg = mlx5_get_send_wqe(qp, 0);
2822                         set_reg_mkey_segment(seg, wr);
2823                         seg += sizeof(struct mlx5_mkey_seg);
2824                         size += sizeof(struct mlx5_mkey_seg) / 16;
2825                         if (unlikely((seg == qend)))
2826                                 seg = mlx5_get_send_wqe(qp, 0);
2827                         break;
2828
2829                 default:
2830                         break;
2831                 }
2832
2833                 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
2834                         int uninitialized_var(sz);
2835
2836                         err = set_data_inl_seg(qp, wr, seg, &sz);
2837                         if (unlikely(err)) {
2838                                 mlx5_ib_warn(dev, "\n");
2839                                 *bad_wr = wr;
2840                                 goto out;
2841                         }
2842                         inl = 1;
2843                         size += sz;
2844                 } else {
2845                         dpseg = seg;
2846                         for (i = 0; i < num_sge; i++) {
2847                                 if (unlikely(dpseg == qend)) {
2848                                         seg = mlx5_get_send_wqe(qp, 0);
2849                                         dpseg = seg;
2850                                 }
2851                                 if (likely(wr->sg_list[i].length)) {
2852                                         set_data_ptr_seg(dpseg, wr->sg_list + i);
2853                                         size += sizeof(struct mlx5_wqe_data_seg) / 16;
2854                                         dpseg++;
2855                                 }
2856                         }
2857                 }
2858
2859                 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
2860                            get_fence(fence, wr), next_fence,
2861                            mlx5_ib_opcode[wr->opcode]);
2862 skip_psv:
2863                 if (0)
2864                         dump_wqe(qp, idx, size);
2865         }
2866
2867 out:
2868         if (likely(nreq)) {
2869                 qp->sq.head += nreq;
2870
2871                 /* Make sure that descriptors are written before
2872                  * updating doorbell record and ringing the doorbell
2873                  */
2874                 wmb();
2875
2876                 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
2877
2878                 /* Make sure doorbell record is visible to the HCA before
2879                  * we hit doorbell */
2880                 wmb();
2881
2882                 if (bf->need_lock)
2883                         spin_lock(&bf->lock);
2884                 else
2885                         __acquire(&bf->lock);
2886
2887                 /* TBD enable WC */
2888                 if (0 && nreq == 1 && bf->uuarn && inl && size > 1 && size <= bf->buf_size / 16) {
2889                         mlx5_bf_copy(bf->reg + bf->offset, (u64 *)ctrl, ALIGN(size * 16, 64), qp);
2890                         /* wc_wmb(); */
2891                 } else {
2892                         mlx5_write64((__be32 *)ctrl, bf->regreg + bf->offset,
2893                                      MLX5_GET_DOORBELL_LOCK(&bf->lock32));
2894                         /* Make sure doorbells don't leak out of SQ spinlock
2895                          * and reach the HCA out of order.
2896                          */
2897                         mmiowb();
2898                 }
2899                 bf->offset ^= bf->buf_size;
2900                 if (bf->need_lock)
2901                         spin_unlock(&bf->lock);
2902                 else
2903                         __release(&bf->lock);
2904         }
2905
2906         spin_unlock_irqrestore(&qp->sq.lock, flags);
2907
2908         return err;
2909 }
2910
2911 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
2912 {
2913         sig->signature = calc_sig(sig, size);
2914 }
2915
2916 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2917                       struct ib_recv_wr **bad_wr)
2918 {
2919         struct mlx5_ib_qp *qp = to_mqp(ibqp);
2920         struct mlx5_wqe_data_seg *scat;
2921         struct mlx5_rwqe_sig *sig;
2922         unsigned long flags;
2923         int err = 0;
2924         int nreq;
2925         int ind;
2926         int i;
2927
2928         spin_lock_irqsave(&qp->rq.lock, flags);
2929
2930         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
2931
2932         for (nreq = 0; wr; nreq++, wr = wr->next) {
2933                 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2934                         err = -ENOMEM;
2935                         *bad_wr = wr;
2936                         goto out;
2937                 }
2938
2939                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2940                         err = -EINVAL;
2941                         *bad_wr = wr;
2942                         goto out;
2943                 }
2944
2945                 scat = get_recv_wqe(qp, ind);
2946                 if (qp->wq_sig)
2947                         scat++;
2948
2949                 for (i = 0; i < wr->num_sge; i++)
2950                         set_data_ptr_seg(scat + i, wr->sg_list + i);
2951
2952                 if (i < qp->rq.max_gs) {
2953                         scat[i].byte_count = 0;
2954                         scat[i].lkey       = cpu_to_be32(MLX5_INVALID_LKEY);
2955                         scat[i].addr       = 0;
2956                 }
2957
2958                 if (qp->wq_sig) {
2959                         sig = (struct mlx5_rwqe_sig *)scat;
2960                         set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
2961                 }
2962
2963                 qp->rq.wrid[ind] = wr->wr_id;
2964
2965                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
2966         }
2967
2968 out:
2969         if (likely(nreq)) {
2970                 qp->rq.head += nreq;
2971
2972                 /* Make sure that descriptors are written before
2973                  * doorbell record.
2974                  */
2975                 wmb();
2976
2977                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
2978         }
2979
2980         spin_unlock_irqrestore(&qp->rq.lock, flags);
2981
2982         return err;
2983 }
2984
2985 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
2986 {
2987         switch (mlx5_state) {
2988         case MLX5_QP_STATE_RST:      return IB_QPS_RESET;
2989         case MLX5_QP_STATE_INIT:     return IB_QPS_INIT;
2990         case MLX5_QP_STATE_RTR:      return IB_QPS_RTR;
2991         case MLX5_QP_STATE_RTS:      return IB_QPS_RTS;
2992         case MLX5_QP_STATE_SQ_DRAINING:
2993         case MLX5_QP_STATE_SQD:      return IB_QPS_SQD;
2994         case MLX5_QP_STATE_SQER:     return IB_QPS_SQE;
2995         case MLX5_QP_STATE_ERR:      return IB_QPS_ERR;
2996         default:                     return -1;
2997         }
2998 }
2999
3000 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
3001 {
3002         switch (mlx5_mig_state) {
3003         case MLX5_QP_PM_ARMED:          return IB_MIG_ARMED;
3004         case MLX5_QP_PM_REARM:          return IB_MIG_REARM;
3005         case MLX5_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
3006         default: return -1;
3007         }
3008 }
3009
3010 static int to_ib_qp_access_flags(int mlx5_flags)
3011 {
3012         int ib_flags = 0;
3013
3014         if (mlx5_flags & MLX5_QP_BIT_RRE)
3015                 ib_flags |= IB_ACCESS_REMOTE_READ;
3016         if (mlx5_flags & MLX5_QP_BIT_RWE)
3017                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
3018         if (mlx5_flags & MLX5_QP_BIT_RAE)
3019                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3020
3021         return ib_flags;
3022 }
3023
3024 static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
3025                                 struct mlx5_qp_path *path)
3026 {
3027         struct mlx5_core_dev *dev = ibdev->mdev;
3028
3029         memset(ib_ah_attr, 0, sizeof(*ib_ah_attr));
3030         ib_ah_attr->port_num      = path->port;
3031
3032         if (ib_ah_attr->port_num == 0 ||
3033             ib_ah_attr->port_num > MLX5_CAP_GEN(dev, num_ports))
3034                 return;
3035
3036         ib_ah_attr->sl = path->sl & 0xf;
3037
3038         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
3039         ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f;
3040         ib_ah_attr->static_rate   = path->static_rate ? path->static_rate - 5 : 0;
3041         ib_ah_attr->ah_flags      = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0;
3042         if (ib_ah_attr->ah_flags) {
3043                 ib_ah_attr->grh.sgid_index = path->mgid_index;
3044                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
3045                 ib_ah_attr->grh.traffic_class =
3046                         (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
3047                 ib_ah_attr->grh.flow_label =
3048                         be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
3049                 memcpy(ib_ah_attr->grh.dgid.raw,
3050                        path->rgid, sizeof(ib_ah_attr->grh.dgid.raw));
3051         }
3052 }
3053
3054 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
3055                      struct ib_qp_init_attr *qp_init_attr)
3056 {
3057         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3058         struct mlx5_ib_qp *qp = to_mqp(ibqp);
3059         struct mlx5_query_qp_mbox_out *outb;
3060         struct mlx5_qp_context *context;
3061         int mlx5_state;
3062         int err = 0;
3063
3064 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
3065         /*
3066          * Wait for any outstanding page faults, in case the user frees memory
3067          * based upon this query's result.
3068          */
3069         flush_workqueue(mlx5_ib_page_fault_wq);
3070 #endif
3071
3072         mutex_lock(&qp->mutex);
3073         outb = kzalloc(sizeof(*outb), GFP_KERNEL);
3074         if (!outb) {
3075                 err = -ENOMEM;
3076                 goto out;
3077         }
3078         context = &outb->ctx;
3079         err = mlx5_core_qp_query(dev->mdev, &qp->mqp, outb, sizeof(*outb));
3080         if (err)
3081                 goto out_free;
3082
3083         mlx5_state = be32_to_cpu(context->flags) >> 28;
3084
3085         qp->state                    = to_ib_qp_state(mlx5_state);
3086         qp_attr->qp_state            = qp->state;
3087         qp_attr->path_mtu            = context->mtu_msgmax >> 5;
3088         qp_attr->path_mig_state      =
3089                 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
3090         qp_attr->qkey                = be32_to_cpu(context->qkey);
3091         qp_attr->rq_psn              = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
3092         qp_attr->sq_psn              = be32_to_cpu(context->next_send_psn) & 0xffffff;
3093         qp_attr->dest_qp_num         = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
3094         qp_attr->qp_access_flags     =
3095                 to_ib_qp_access_flags(be32_to_cpu(context->params2));
3096
3097         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
3098                 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
3099                 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
3100                 qp_attr->alt_pkey_index = context->alt_path.pkey_index & 0x7f;
3101                 qp_attr->alt_port_num   = qp_attr->alt_ah_attr.port_num;
3102         }
3103
3104         qp_attr->pkey_index = context->pri_path.pkey_index & 0x7f;
3105         qp_attr->port_num = context->pri_path.port;
3106
3107         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
3108         qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
3109
3110         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
3111
3112         qp_attr->max_dest_rd_atomic =
3113                 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
3114         qp_attr->min_rnr_timer      =
3115                 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
3116         qp_attr->timeout            = context->pri_path.ackto_lt >> 3;
3117         qp_attr->retry_cnt          = (be32_to_cpu(context->params1) >> 16) & 0x7;
3118         qp_attr->rnr_retry          = (be32_to_cpu(context->params1) >> 13) & 0x7;
3119         qp_attr->alt_timeout        = context->alt_path.ackto_lt >> 3;
3120         qp_attr->cur_qp_state        = qp_attr->qp_state;
3121         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
3122         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
3123
3124         if (!ibqp->uobject) {
3125                 qp_attr->cap.max_send_wr  = qp->sq.max_post;
3126                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
3127                 qp_init_attr->qp_context = ibqp->qp_context;
3128         } else {
3129                 qp_attr->cap.max_send_wr  = 0;
3130                 qp_attr->cap.max_send_sge = 0;
3131         }
3132
3133         qp_init_attr->qp_type = ibqp->qp_type;
3134         qp_init_attr->recv_cq = ibqp->recv_cq;
3135         qp_init_attr->send_cq = ibqp->send_cq;
3136         qp_init_attr->srq = ibqp->srq;
3137         qp_attr->cap.max_inline_data = qp->max_inline_data;
3138
3139         qp_init_attr->cap            = qp_attr->cap;
3140
3141         qp_init_attr->create_flags = 0;
3142         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
3143                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
3144
3145         qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
3146                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
3147
3148 out_free:
3149         kfree(outb);
3150
3151 out:
3152         mutex_unlock(&qp->mutex);
3153         return err;
3154 }
3155
3156 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
3157                                           struct ib_ucontext *context,
3158                                           struct ib_udata *udata)
3159 {
3160         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3161         struct mlx5_ib_xrcd *xrcd;
3162         int err;
3163
3164         if (!MLX5_CAP_GEN(dev->mdev, xrc))
3165                 return ERR_PTR(-ENOSYS);
3166
3167         xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
3168         if (!xrcd)
3169                 return ERR_PTR(-ENOMEM);
3170
3171         err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
3172         if (err) {
3173                 kfree(xrcd);
3174                 return ERR_PTR(-ENOMEM);
3175         }
3176
3177         return &xrcd->ibxrcd;
3178 }
3179
3180 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
3181 {
3182         struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
3183         u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
3184         int err;
3185
3186         err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
3187         if (err)
3188                 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
3189
3190         kfree(xrcd);
3191         return 0;
3192 }