1 /* This file is part of the Emulex RoCE Device Driver for
2 * RoCE (RDMA over Converged Ethernet) adapters.
3 * Copyright (C) 2012-2015 Emulex. All rights reserved.
4 * EMULEX and SLI are trademarks of Emulex.
7 * This software is available to you under a choice of one of two licenses.
8 * You may choose to be licensed under the terms of the GNU General Public
9 * License (GPL) Version 2, available from the file COPYING in the main
10 * directory of this source tree, or the BSD license below:
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
16 * - Redistributions of source code must retain the above copyright notice,
17 * this list of conditions and the following disclaimer.
19 * - Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the distribution.
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 * Contact Information:
36 * linux-drivers@emulex.com
40 * Costa Mesa, CA 92626
43 #include <linux/sched.h>
44 #include <linux/interrupt.h>
45 #include <linux/log2.h>
46 #include <linux/dma-mapping.h>
47 #include <linux/if_ether.h>
49 #include <rdma/ib_verbs.h>
50 #include <rdma/ib_user_verbs.h>
51 #include <rdma/ib_cache.h>
54 #include "ocrdma_hw.h"
55 #include "ocrdma_verbs.h"
56 #include "ocrdma_ah.h"
59 OCRDMA_MBX_STATUS_FAILED = 1,
60 OCRDMA_MBX_STATUS_ILLEGAL_FIELD = 3,
61 OCRDMA_MBX_STATUS_OOR = 100,
62 OCRDMA_MBX_STATUS_INVALID_PD = 101,
63 OCRDMA_MBX_STATUS_PD_INUSE = 102,
64 OCRDMA_MBX_STATUS_INVALID_CQ = 103,
65 OCRDMA_MBX_STATUS_INVALID_QP = 104,
66 OCRDMA_MBX_STATUS_INVALID_LKEY = 105,
67 OCRDMA_MBX_STATUS_ORD_EXCEEDS = 106,
68 OCRDMA_MBX_STATUS_IRD_EXCEEDS = 107,
69 OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS = 108,
70 OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS = 109,
71 OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS = 110,
72 OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS = 111,
73 OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS = 112,
74 OCRDMA_MBX_STATUS_INVALID_STATE_CHANGE = 113,
75 OCRDMA_MBX_STATUS_MW_BOUND = 114,
76 OCRDMA_MBX_STATUS_INVALID_VA = 115,
77 OCRDMA_MBX_STATUS_INVALID_LENGTH = 116,
78 OCRDMA_MBX_STATUS_INVALID_FBO = 117,
79 OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS = 118,
80 OCRDMA_MBX_STATUS_INVALID_PBE_SIZE = 119,
81 OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY = 120,
82 OCRDMA_MBX_STATUS_INVALID_PBL_SHIFT = 121,
83 OCRDMA_MBX_STATUS_INVALID_SRQ_ID = 129,
84 OCRDMA_MBX_STATUS_SRQ_ERROR = 133,
85 OCRDMA_MBX_STATUS_RQE_EXCEEDS = 134,
86 OCRDMA_MBX_STATUS_MTU_EXCEEDS = 135,
87 OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS = 136,
88 OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS = 137,
89 OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS = 138,
90 OCRDMA_MBX_STATUS_QP_BOUND = 130,
91 OCRDMA_MBX_STATUS_INVALID_CHANGE = 139,
92 OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP = 140,
93 OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER = 141,
94 OCRDMA_MBX_STATUS_MW_STILL_BOUND = 142,
95 OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID = 143,
96 OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS = 144
99 enum additional_status {
100 OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES = 22
104 OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES = 1,
105 OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER = 2,
106 OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES = 3,
107 OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING = 4,
108 OCRDMA_MBX_CQE_STATUS_DMA_FAILED = 5
111 static inline void *ocrdma_get_eqe(struct ocrdma_eq *eq)
113 return eq->q.va + (eq->q.tail * sizeof(struct ocrdma_eqe));
116 static inline void ocrdma_eq_inc_tail(struct ocrdma_eq *eq)
118 eq->q.tail = (eq->q.tail + 1) & (OCRDMA_EQ_LEN - 1);
121 static inline void *ocrdma_get_mcqe(struct ocrdma_dev *dev)
123 struct ocrdma_mcqe *cqe = (struct ocrdma_mcqe *)
124 (dev->mq.cq.va + (dev->mq.cq.tail * sizeof(struct ocrdma_mcqe)));
126 if (!(le32_to_cpu(cqe->valid_ae_cmpl_cons) & OCRDMA_MCQE_VALID_MASK))
131 static inline void ocrdma_mcq_inc_tail(struct ocrdma_dev *dev)
133 dev->mq.cq.tail = (dev->mq.cq.tail + 1) & (OCRDMA_MQ_CQ_LEN - 1);
136 static inline struct ocrdma_mqe *ocrdma_get_mqe(struct ocrdma_dev *dev)
138 return dev->mq.sq.va + (dev->mq.sq.head * sizeof(struct ocrdma_mqe));
141 static inline void ocrdma_mq_inc_head(struct ocrdma_dev *dev)
143 dev->mq.sq.head = (dev->mq.sq.head + 1) & (OCRDMA_MQ_LEN - 1);
146 static inline void *ocrdma_get_mqe_rsp(struct ocrdma_dev *dev)
148 return dev->mq.sq.va + (dev->mqe_ctx.tag * sizeof(struct ocrdma_mqe));
151 enum ib_qp_state get_ibqp_state(enum ocrdma_qp_state qps)
156 case OCRDMA_QPS_INIT:
163 case OCRDMA_QPS_SQ_DRAINING:
173 static enum ocrdma_qp_state get_ocrdma_qp_state(enum ib_qp_state qps)
177 return OCRDMA_QPS_RST;
179 return OCRDMA_QPS_INIT;
181 return OCRDMA_QPS_RTR;
183 return OCRDMA_QPS_RTS;
185 return OCRDMA_QPS_SQD;
187 return OCRDMA_QPS_SQE;
189 return OCRDMA_QPS_ERR;
191 return OCRDMA_QPS_ERR;
194 static int ocrdma_get_mbx_errno(u32 status)
197 u8 mbox_status = (status & OCRDMA_MBX_RSP_STATUS_MASK) >>
198 OCRDMA_MBX_RSP_STATUS_SHIFT;
199 u8 add_status = (status & OCRDMA_MBX_RSP_ASTATUS_MASK) >>
200 OCRDMA_MBX_RSP_ASTATUS_SHIFT;
202 switch (mbox_status) {
203 case OCRDMA_MBX_STATUS_OOR:
204 case OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS:
208 case OCRDMA_MBX_STATUS_INVALID_PD:
209 case OCRDMA_MBX_STATUS_INVALID_CQ:
210 case OCRDMA_MBX_STATUS_INVALID_SRQ_ID:
211 case OCRDMA_MBX_STATUS_INVALID_QP:
212 case OCRDMA_MBX_STATUS_INVALID_CHANGE:
213 case OCRDMA_MBX_STATUS_MTU_EXCEEDS:
214 case OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER:
215 case OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID:
216 case OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS:
217 case OCRDMA_MBX_STATUS_ILLEGAL_FIELD:
218 case OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY:
219 case OCRDMA_MBX_STATUS_INVALID_LKEY:
220 case OCRDMA_MBX_STATUS_INVALID_VA:
221 case OCRDMA_MBX_STATUS_INVALID_LENGTH:
222 case OCRDMA_MBX_STATUS_INVALID_FBO:
223 case OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS:
224 case OCRDMA_MBX_STATUS_INVALID_PBE_SIZE:
225 case OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP:
226 case OCRDMA_MBX_STATUS_SRQ_ERROR:
227 case OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS:
231 case OCRDMA_MBX_STATUS_PD_INUSE:
232 case OCRDMA_MBX_STATUS_QP_BOUND:
233 case OCRDMA_MBX_STATUS_MW_STILL_BOUND:
234 case OCRDMA_MBX_STATUS_MW_BOUND:
238 case OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS:
239 case OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS:
240 case OCRDMA_MBX_STATUS_RQE_EXCEEDS:
241 case OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS:
242 case OCRDMA_MBX_STATUS_ORD_EXCEEDS:
243 case OCRDMA_MBX_STATUS_IRD_EXCEEDS:
244 case OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS:
245 case OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS:
246 case OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS:
250 case OCRDMA_MBX_STATUS_FAILED:
251 switch (add_status) {
252 case OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES:
265 char *port_speed_string(struct ocrdma_dev *dev)
268 u16 speeds_supported;
270 speeds_supported = dev->phy.fixed_speeds_supported |
271 dev->phy.auto_speeds_supported;
272 if (speeds_supported & OCRDMA_PHY_SPEED_40GBPS)
274 else if (speeds_supported & OCRDMA_PHY_SPEED_10GBPS)
276 else if (speeds_supported & OCRDMA_PHY_SPEED_1GBPS)
282 static int ocrdma_get_mbx_cqe_errno(u16 cqe_status)
284 int err_num = -EINVAL;
286 switch (cqe_status) {
287 case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES:
290 case OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER:
293 case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES:
294 case OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING:
297 case OCRDMA_MBX_CQE_STATUS_DMA_FAILED:
305 void ocrdma_ring_cq_db(struct ocrdma_dev *dev, u16 cq_id, bool armed,
306 bool solicited, u16 cqe_popped)
308 u32 val = cq_id & OCRDMA_DB_CQ_RING_ID_MASK;
310 val |= ((cq_id & OCRDMA_DB_CQ_RING_ID_EXT_MASK) <<
311 OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT);
314 val |= (1 << OCRDMA_DB_CQ_REARM_SHIFT);
316 val |= (1 << OCRDMA_DB_CQ_SOLICIT_SHIFT);
317 val |= (cqe_popped << OCRDMA_DB_CQ_NUM_POPPED_SHIFT);
318 iowrite32(val, dev->nic_info.db + OCRDMA_DB_CQ_OFFSET);
321 static void ocrdma_ring_mq_db(struct ocrdma_dev *dev)
325 val |= dev->mq.sq.id & OCRDMA_MQ_ID_MASK;
326 val |= 1 << OCRDMA_MQ_NUM_MQE_SHIFT;
327 iowrite32(val, dev->nic_info.db + OCRDMA_DB_MQ_OFFSET);
330 static void ocrdma_ring_eq_db(struct ocrdma_dev *dev, u16 eq_id,
331 bool arm, bool clear_int, u16 num_eqe)
335 val |= eq_id & OCRDMA_EQ_ID_MASK;
336 val |= ((eq_id & OCRDMA_EQ_ID_EXT_MASK) << OCRDMA_EQ_ID_EXT_MASK_SHIFT);
338 val |= (1 << OCRDMA_REARM_SHIFT);
340 val |= (1 << OCRDMA_EQ_CLR_SHIFT);
341 val |= (1 << OCRDMA_EQ_TYPE_SHIFT);
342 val |= (num_eqe << OCRDMA_NUM_EQE_SHIFT);
343 iowrite32(val, dev->nic_info.db + OCRDMA_DB_EQ_OFFSET);
346 static void ocrdma_init_mch(struct ocrdma_mbx_hdr *cmd_hdr,
347 u8 opcode, u8 subsys, u32 cmd_len)
349 cmd_hdr->subsys_op = (opcode | (subsys << OCRDMA_MCH_SUBSYS_SHIFT));
350 cmd_hdr->timeout = 20; /* seconds */
351 cmd_hdr->cmd_len = cmd_len - sizeof(struct ocrdma_mbx_hdr);
354 static void *ocrdma_init_emb_mqe(u8 opcode, u32 cmd_len)
356 struct ocrdma_mqe *mqe;
358 mqe = kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL);
361 mqe->hdr.spcl_sge_cnt_emb |=
362 (OCRDMA_MQE_EMBEDDED << OCRDMA_MQE_HDR_EMB_SHIFT) &
363 OCRDMA_MQE_HDR_EMB_MASK;
364 mqe->hdr.pyld_len = cmd_len - sizeof(struct ocrdma_mqe_hdr);
366 ocrdma_init_mch(&mqe->u.emb_req.mch, opcode, OCRDMA_SUBSYS_ROCE,
371 static void ocrdma_free_q(struct ocrdma_dev *dev, struct ocrdma_queue_info *q)
373 dma_free_coherent(&dev->nic_info.pdev->dev, q->size, q->va, q->dma);
376 static int ocrdma_alloc_q(struct ocrdma_dev *dev,
377 struct ocrdma_queue_info *q, u16 len, u16 entry_size)
379 memset(q, 0, sizeof(*q));
381 q->entry_size = entry_size;
382 q->size = len * entry_size;
383 q->va = dma_alloc_coherent(&dev->nic_info.pdev->dev, q->size,
384 &q->dma, GFP_KERNEL);
387 memset(q->va, 0, q->size);
391 static void ocrdma_build_q_pages(struct ocrdma_pa *q_pa, int cnt,
392 dma_addr_t host_pa, int hw_page_size)
396 for (i = 0; i < cnt; i++) {
397 q_pa[i].lo = (u32) (host_pa & 0xffffffff);
398 q_pa[i].hi = (u32) upper_32_bits(host_pa);
399 host_pa += hw_page_size;
403 static int ocrdma_mbx_delete_q(struct ocrdma_dev *dev,
404 struct ocrdma_queue_info *q, int queue_type)
408 struct ocrdma_delete_q_req *cmd = dev->mbx_cmd;
410 switch (queue_type) {
412 opcode = OCRDMA_CMD_DELETE_MQ;
415 opcode = OCRDMA_CMD_DELETE_CQ;
418 opcode = OCRDMA_CMD_DELETE_EQ;
423 memset(cmd, 0, sizeof(*cmd));
424 ocrdma_init_mch(&cmd->req, opcode, OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
427 status = be_roce_mcc_cmd(dev->nic_info.netdev,
428 cmd, sizeof(*cmd), NULL, NULL);
434 static int ocrdma_mbx_create_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
437 struct ocrdma_create_eq_req *cmd = dev->mbx_cmd;
438 struct ocrdma_create_eq_rsp *rsp = dev->mbx_cmd;
440 memset(cmd, 0, sizeof(*cmd));
441 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_EQ, OCRDMA_SUBSYS_COMMON,
444 cmd->req.rsvd_version = 2;
446 cmd->valid = OCRDMA_CREATE_EQ_VALID;
447 cmd->cnt = 4 << OCRDMA_CREATE_EQ_CNT_SHIFT;
449 ocrdma_build_q_pages(&cmd->pa[0], cmd->num_pages, eq->q.dma,
451 status = be_roce_mcc_cmd(dev->nic_info.netdev, cmd, sizeof(*cmd), NULL,
454 eq->q.id = rsp->vector_eqid & 0xffff;
455 eq->vector = (rsp->vector_eqid >> 16) & 0xffff;
456 eq->q.created = true;
461 static int ocrdma_create_eq(struct ocrdma_dev *dev,
462 struct ocrdma_eq *eq, u16 q_len)
466 status = ocrdma_alloc_q(dev, &eq->q, OCRDMA_EQ_LEN,
467 sizeof(struct ocrdma_eqe));
471 status = ocrdma_mbx_create_eq(dev, eq);
475 ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
479 ocrdma_free_q(dev, &eq->q);
483 int ocrdma_get_irq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
487 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX)
488 irq = dev->nic_info.pdev->irq;
490 irq = dev->nic_info.msix.vector_list[eq->vector];
494 static void _ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
497 ocrdma_mbx_delete_q(dev, &eq->q, QTYPE_EQ);
498 ocrdma_free_q(dev, &eq->q);
502 static void ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
506 /* disarm EQ so that interrupts are not generated
507 * during freeing and EQ delete is in progress.
509 ocrdma_ring_eq_db(dev, eq->q.id, false, false, 0);
511 irq = ocrdma_get_irq(dev, eq);
513 _ocrdma_destroy_eq(dev, eq);
516 static void ocrdma_destroy_eqs(struct ocrdma_dev *dev)
520 for (i = 0; i < dev->eq_cnt; i++)
521 ocrdma_destroy_eq(dev, &dev->eq_tbl[i]);
524 static int ocrdma_mbx_mq_cq_create(struct ocrdma_dev *dev,
525 struct ocrdma_queue_info *cq,
526 struct ocrdma_queue_info *eq)
528 struct ocrdma_create_cq_cmd *cmd = dev->mbx_cmd;
529 struct ocrdma_create_cq_cmd_rsp *rsp = dev->mbx_cmd;
532 memset(cmd, 0, sizeof(*cmd));
533 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_CQ,
534 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
536 cmd->req.rsvd_version = OCRDMA_CREATE_CQ_VER2;
537 cmd->pgsz_pgcnt = (cq->size / OCRDMA_MIN_Q_PAGE_SIZE) <<
538 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
539 cmd->pgsz_pgcnt |= PAGES_4K_SPANNED(cq->va, cq->size);
541 cmd->ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
543 cmd->pdid_cqecnt = cq->size / sizeof(struct ocrdma_mcqe);
545 ocrdma_build_q_pages(&cmd->pa[0], cq->size / OCRDMA_MIN_Q_PAGE_SIZE,
546 cq->dma, PAGE_SIZE_4K);
547 status = be_roce_mcc_cmd(dev->nic_info.netdev,
548 cmd, sizeof(*cmd), NULL, NULL);
550 cq->id = (u16) (rsp->cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
556 static u32 ocrdma_encoded_q_len(int q_len)
558 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
560 if (len_encoded == 16)
565 static int ocrdma_mbx_create_mq(struct ocrdma_dev *dev,
566 struct ocrdma_queue_info *mq,
567 struct ocrdma_queue_info *cq)
569 int num_pages, status;
570 struct ocrdma_create_mq_req *cmd = dev->mbx_cmd;
571 struct ocrdma_create_mq_rsp *rsp = dev->mbx_cmd;
572 struct ocrdma_pa *pa;
574 memset(cmd, 0, sizeof(*cmd));
575 num_pages = PAGES_4K_SPANNED(mq->va, mq->size);
577 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_MQ_EXT,
578 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
579 cmd->req.rsvd_version = 1;
580 cmd->cqid_pages = num_pages;
581 cmd->cqid_pages |= (cq->id << OCRDMA_CREATE_MQ_CQ_ID_SHIFT);
582 cmd->async_cqid_valid = OCRDMA_CREATE_MQ_ASYNC_CQ_VALID;
584 cmd->async_event_bitmap = BIT(OCRDMA_ASYNC_GRP5_EVE_CODE);
585 cmd->async_event_bitmap |= BIT(OCRDMA_ASYNC_RDMA_EVE_CODE);
586 /* Request link events on this MQ. */
587 cmd->async_event_bitmap |= BIT(OCRDMA_ASYNC_LINK_EVE_CODE);
589 cmd->async_cqid_ringsize = cq->id;
590 cmd->async_cqid_ringsize |= (ocrdma_encoded_q_len(mq->len) <<
591 OCRDMA_CREATE_MQ_RING_SIZE_SHIFT);
592 cmd->valid = OCRDMA_CREATE_MQ_VALID;
595 ocrdma_build_q_pages(pa, num_pages, mq->dma, PAGE_SIZE_4K);
596 status = be_roce_mcc_cmd(dev->nic_info.netdev,
597 cmd, sizeof(*cmd), NULL, NULL);
605 static int ocrdma_create_mq(struct ocrdma_dev *dev)
609 /* Alloc completion queue for Mailbox queue */
610 status = ocrdma_alloc_q(dev, &dev->mq.cq, OCRDMA_MQ_CQ_LEN,
611 sizeof(struct ocrdma_mcqe));
615 dev->eq_tbl[0].cq_cnt++;
616 status = ocrdma_mbx_mq_cq_create(dev, &dev->mq.cq, &dev->eq_tbl[0].q);
620 memset(&dev->mqe_ctx, 0, sizeof(dev->mqe_ctx));
621 init_waitqueue_head(&dev->mqe_ctx.cmd_wait);
622 mutex_init(&dev->mqe_ctx.lock);
624 /* Alloc Mailbox queue */
625 status = ocrdma_alloc_q(dev, &dev->mq.sq, OCRDMA_MQ_LEN,
626 sizeof(struct ocrdma_mqe));
629 status = ocrdma_mbx_create_mq(dev, &dev->mq.sq, &dev->mq.cq);
632 ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, 0);
636 ocrdma_free_q(dev, &dev->mq.sq);
638 ocrdma_mbx_delete_q(dev, &dev->mq.cq, QTYPE_CQ);
640 ocrdma_free_q(dev, &dev->mq.cq);
645 static void ocrdma_destroy_mq(struct ocrdma_dev *dev)
647 struct ocrdma_queue_info *mbxq, *cq;
649 /* mqe_ctx lock synchronizes with any other pending cmds. */
650 mutex_lock(&dev->mqe_ctx.lock);
653 ocrdma_mbx_delete_q(dev, mbxq, QTYPE_MCCQ);
654 ocrdma_free_q(dev, mbxq);
656 mutex_unlock(&dev->mqe_ctx.lock);
660 ocrdma_mbx_delete_q(dev, cq, QTYPE_CQ);
661 ocrdma_free_q(dev, cq);
665 static void ocrdma_process_qpcat_error(struct ocrdma_dev *dev,
666 struct ocrdma_qp *qp)
668 enum ib_qp_state new_ib_qps = IB_QPS_ERR;
669 enum ib_qp_state old_ib_qps;
673 ocrdma_qp_state_change(qp, new_ib_qps, &old_ib_qps);
676 static void ocrdma_dispatch_ibevent(struct ocrdma_dev *dev,
677 struct ocrdma_ae_mcqe *cqe)
679 struct ocrdma_qp *qp = NULL;
680 struct ocrdma_cq *cq = NULL;
681 struct ib_event ib_evt;
686 int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
687 OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
688 u16 qpid = cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPID_MASK;
689 u16 cqid = cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQID_MASK;
692 * Some FW version returns wrong qp or cq ids in CQEs.
693 * Checking whether the IDs are valid
696 if (cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPVALID) {
697 if (qpid < dev->attr.max_qp)
698 qp = dev->qp_tbl[qpid];
700 pr_err("ocrdma%d:Async event - qpid %u is not valid\n",
706 if (cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQVALID) {
707 if (cqid < dev->attr.max_cq)
708 cq = dev->cq_tbl[cqid];
710 pr_err("ocrdma%d:Async event - cqid %u is not valid\n",
716 memset(&ib_evt, 0, sizeof(ib_evt));
718 ib_evt.device = &dev->ibdev;
721 case OCRDMA_CQ_ERROR:
722 ib_evt.element.cq = &cq->ibcq;
723 ib_evt.event = IB_EVENT_CQ_ERR;
727 case OCRDMA_CQ_OVERRUN_ERROR:
728 ib_evt.element.cq = &cq->ibcq;
729 ib_evt.event = IB_EVENT_CQ_ERR;
733 case OCRDMA_CQ_QPCAT_ERROR:
734 ib_evt.element.qp = &qp->ibqp;
735 ib_evt.event = IB_EVENT_QP_FATAL;
736 ocrdma_process_qpcat_error(dev, qp);
738 case OCRDMA_QP_ACCESS_ERROR:
739 ib_evt.element.qp = &qp->ibqp;
740 ib_evt.event = IB_EVENT_QP_ACCESS_ERR;
742 case OCRDMA_QP_COMM_EST_EVENT:
743 ib_evt.element.qp = &qp->ibqp;
744 ib_evt.event = IB_EVENT_COMM_EST;
746 case OCRDMA_SQ_DRAINED_EVENT:
747 ib_evt.element.qp = &qp->ibqp;
748 ib_evt.event = IB_EVENT_SQ_DRAINED;
750 case OCRDMA_DEVICE_FATAL_EVENT:
751 ib_evt.element.port_num = 1;
752 ib_evt.event = IB_EVENT_DEVICE_FATAL;
756 case OCRDMA_SRQCAT_ERROR:
757 ib_evt.element.srq = &qp->srq->ibsrq;
758 ib_evt.event = IB_EVENT_SRQ_ERR;
762 case OCRDMA_SRQ_LIMIT_EVENT:
763 ib_evt.element.srq = &qp->srq->ibsrq;
764 ib_evt.event = IB_EVENT_SRQ_LIMIT_REACHED;
768 case OCRDMA_QP_LAST_WQE_EVENT:
769 ib_evt.element.qp = &qp->ibqp;
770 ib_evt.event = IB_EVENT_QP_LAST_WQE_REACHED;
777 pr_err("%s() unknown type=0x%x\n", __func__, type);
781 if (type < OCRDMA_MAX_ASYNC_ERRORS)
782 atomic_inc(&dev->async_err_stats[type]);
785 if (qp->ibqp.event_handler)
786 qp->ibqp.event_handler(&ib_evt, qp->ibqp.qp_context);
787 } else if (cq_event) {
788 if (cq->ibcq.event_handler)
789 cq->ibcq.event_handler(&ib_evt, cq->ibcq.cq_context);
790 } else if (srq_event) {
791 if (qp->srq->ibsrq.event_handler)
792 qp->srq->ibsrq.event_handler(&ib_evt,
795 } else if (dev_event) {
796 pr_err("%s: Fatal event received\n", dev->ibdev.name);
797 ib_dispatch_event(&ib_evt);
802 static void ocrdma_process_grp5_aync(struct ocrdma_dev *dev,
803 struct ocrdma_ae_mcqe *cqe)
805 struct ocrdma_ae_pvid_mcqe *evt;
806 int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
807 OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
810 case OCRDMA_ASYNC_EVENT_PVID_STATE:
811 evt = (struct ocrdma_ae_pvid_mcqe *)cqe;
812 if ((evt->tag_enabled & OCRDMA_AE_PVID_MCQE_ENABLED_MASK) >>
813 OCRDMA_AE_PVID_MCQE_ENABLED_SHIFT)
814 dev->pvid = ((evt->tag_enabled &
815 OCRDMA_AE_PVID_MCQE_TAG_MASK) >>
816 OCRDMA_AE_PVID_MCQE_TAG_SHIFT);
819 case OCRDMA_ASYNC_EVENT_COS_VALUE:
820 atomic_set(&dev->update_sl, 1);
823 /* Not interested evts. */
828 static void ocrdma_process_link_state(struct ocrdma_dev *dev,
829 struct ocrdma_ae_mcqe *cqe)
831 struct ocrdma_ae_lnkst_mcqe *evt;
834 evt = (struct ocrdma_ae_lnkst_mcqe *)cqe;
835 lstate = ocrdma_get_ae_link_state(evt->speed_state_ptn);
837 if (!(lstate & OCRDMA_AE_LSC_LLINK_MASK))
840 if (dev->flags & OCRDMA_FLAGS_LINK_STATUS_INIT)
841 ocrdma_update_link_state(dev, (lstate & OCRDMA_LINK_ST_MASK));
844 static void ocrdma_process_acqe(struct ocrdma_dev *dev, void *ae_cqe)
846 /* async CQE processing */
847 struct ocrdma_ae_mcqe *cqe = ae_cqe;
848 u32 evt_code = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_CODE_MASK) >>
849 OCRDMA_AE_MCQE_EVENT_CODE_SHIFT;
851 case OCRDMA_ASYNC_LINK_EVE_CODE:
852 ocrdma_process_link_state(dev, cqe);
854 case OCRDMA_ASYNC_RDMA_EVE_CODE:
855 ocrdma_dispatch_ibevent(dev, cqe);
857 case OCRDMA_ASYNC_GRP5_EVE_CODE:
858 ocrdma_process_grp5_aync(dev, cqe);
861 pr_err("%s(%d) invalid evt code=0x%x\n", __func__,
866 static void ocrdma_process_mcqe(struct ocrdma_dev *dev, struct ocrdma_mcqe *cqe)
868 if (dev->mqe_ctx.tag == cqe->tag_lo && dev->mqe_ctx.cmd_done == false) {
869 dev->mqe_ctx.cqe_status = (cqe->status &
870 OCRDMA_MCQE_STATUS_MASK) >> OCRDMA_MCQE_STATUS_SHIFT;
871 dev->mqe_ctx.ext_status =
872 (cqe->status & OCRDMA_MCQE_ESTATUS_MASK)
873 >> OCRDMA_MCQE_ESTATUS_SHIFT;
874 dev->mqe_ctx.cmd_done = true;
875 wake_up(&dev->mqe_ctx.cmd_wait);
877 pr_err("%s() cqe for invalid tag0x%x.expected=0x%x\n",
878 __func__, cqe->tag_lo, dev->mqe_ctx.tag);
881 static int ocrdma_mq_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
884 struct ocrdma_mcqe *cqe;
887 cqe = ocrdma_get_mcqe(dev);
890 ocrdma_le32_to_cpu(cqe, sizeof(*cqe));
892 if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_AE_MASK)
893 ocrdma_process_acqe(dev, cqe);
894 else if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_CMPL_MASK)
895 ocrdma_process_mcqe(dev, cqe);
896 memset(cqe, 0, sizeof(struct ocrdma_mcqe));
897 ocrdma_mcq_inc_tail(dev);
899 ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, cqe_popped);
903 static struct ocrdma_cq *_ocrdma_qp_buddy_cq_handler(struct ocrdma_dev *dev,
904 struct ocrdma_cq *cq, bool sq)
906 struct ocrdma_qp *qp;
907 struct list_head *cur;
908 struct ocrdma_cq *bcq = NULL;
909 struct list_head *head = sq?(&cq->sq_head):(&cq->rq_head);
911 list_for_each(cur, head) {
913 qp = list_entry(cur, struct ocrdma_qp, sq_entry);
915 qp = list_entry(cur, struct ocrdma_qp, rq_entry);
919 /* if wq and rq share the same cq, than comp_handler
920 * is already invoked.
922 if (qp->sq_cq == qp->rq_cq)
924 /* if completion came on sq, rq's cq is buddy cq.
925 * if completion came on rq, sq's cq is buddy cq.
936 static void ocrdma_qp_buddy_cq_handler(struct ocrdma_dev *dev,
937 struct ocrdma_cq *cq)
940 struct ocrdma_cq *bcq = NULL;
942 /* Go through list of QPs in error state which are using this CQ
943 * and invoke its callback handler to trigger CQE processing for
944 * error/flushed CQE. It is rare to find more than few entries in
945 * this list as most consumers stops after getting error CQE.
946 * List is traversed only once when a matching buddy cq found for a QP.
948 spin_lock_irqsave(&dev->flush_q_lock, flags);
949 /* Check if buddy CQ is present.
950 * true - Check for SQ CQ
951 * false - Check for RQ CQ
953 bcq = _ocrdma_qp_buddy_cq_handler(dev, cq, true);
955 bcq = _ocrdma_qp_buddy_cq_handler(dev, cq, false);
956 spin_unlock_irqrestore(&dev->flush_q_lock, flags);
958 /* if there is valid buddy cq, look for its completion handler */
959 if (bcq && bcq->ibcq.comp_handler) {
960 spin_lock_irqsave(&bcq->comp_handler_lock, flags);
961 (*bcq->ibcq.comp_handler) (&bcq->ibcq, bcq->ibcq.cq_context);
962 spin_unlock_irqrestore(&bcq->comp_handler_lock, flags);
966 static void ocrdma_qp_cq_handler(struct ocrdma_dev *dev, u16 cq_idx)
969 struct ocrdma_cq *cq;
971 if (cq_idx >= OCRDMA_MAX_CQ)
974 cq = dev->cq_tbl[cq_idx];
978 if (cq->ibcq.comp_handler) {
979 spin_lock_irqsave(&cq->comp_handler_lock, flags);
980 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
981 spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
983 ocrdma_qp_buddy_cq_handler(dev, cq);
986 static void ocrdma_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
988 /* process the MQ-CQE. */
989 if (cq_id == dev->mq.cq.id)
990 ocrdma_mq_cq_handler(dev, cq_id);
992 ocrdma_qp_cq_handler(dev, cq_id);
995 static irqreturn_t ocrdma_irq_handler(int irq, void *handle)
997 struct ocrdma_eq *eq = handle;
998 struct ocrdma_dev *dev = eq->dev;
999 struct ocrdma_eqe eqe;
1000 struct ocrdma_eqe *ptr;
1003 int budget = eq->cq_cnt;
1006 ptr = ocrdma_get_eqe(eq);
1008 ocrdma_le32_to_cpu(&eqe, sizeof(eqe));
1009 mcode = (eqe.id_valid & OCRDMA_EQE_MAJOR_CODE_MASK)
1010 >> OCRDMA_EQE_MAJOR_CODE_SHIFT;
1011 if (mcode == OCRDMA_MAJOR_CODE_SENTINAL)
1012 pr_err("EQ full on eqid = 0x%x, eqe = 0x%x\n",
1013 eq->q.id, eqe.id_valid);
1014 if ((eqe.id_valid & OCRDMA_EQE_VALID_MASK) == 0)
1018 /* ring eq doorbell as soon as its consumed. */
1019 ocrdma_ring_eq_db(dev, eq->q.id, false, true, 1);
1020 /* check whether its CQE or not. */
1021 if ((eqe.id_valid & OCRDMA_EQE_FOR_CQE_MASK) == 0) {
1022 cq_id = eqe.id_valid >> OCRDMA_EQE_RESOURCE_ID_SHIFT;
1023 ocrdma_cq_handler(dev, cq_id);
1025 ocrdma_eq_inc_tail(eq);
1027 /* There can be a stale EQE after the last bound CQ is
1028 * destroyed. EQE valid and budget == 0 implies this.
1035 eq->aic_obj.eq_intr_cnt++;
1036 ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
1040 static void ocrdma_post_mqe(struct ocrdma_dev *dev, struct ocrdma_mqe *cmd)
1042 struct ocrdma_mqe *mqe;
1044 dev->mqe_ctx.tag = dev->mq.sq.head;
1045 dev->mqe_ctx.cmd_done = false;
1046 mqe = ocrdma_get_mqe(dev);
1047 cmd->hdr.tag_lo = dev->mq.sq.head;
1048 ocrdma_copy_cpu_to_le32(mqe, cmd, sizeof(*mqe));
1049 /* make sure descriptor is written before ringing doorbell */
1051 ocrdma_mq_inc_head(dev);
1052 ocrdma_ring_mq_db(dev);
1055 static int ocrdma_wait_mqe_cmpl(struct ocrdma_dev *dev)
1058 /* 30 sec timeout */
1059 status = wait_event_timeout(dev->mqe_ctx.cmd_wait,
1060 (dev->mqe_ctx.cmd_done != false),
1061 msecs_to_jiffies(30000));
1065 dev->mqe_ctx.fw_error_state = true;
1066 pr_err("%s(%d) mailbox timeout: fw not responding\n",
1072 /* issue a mailbox command on the MQ */
1073 static int ocrdma_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe)
1076 u16 cqe_status, ext_status;
1077 struct ocrdma_mqe *rsp_mqe;
1078 struct ocrdma_mbx_rsp *rsp = NULL;
1080 mutex_lock(&dev->mqe_ctx.lock);
1081 if (dev->mqe_ctx.fw_error_state)
1083 ocrdma_post_mqe(dev, mqe);
1084 status = ocrdma_wait_mqe_cmpl(dev);
1087 cqe_status = dev->mqe_ctx.cqe_status;
1088 ext_status = dev->mqe_ctx.ext_status;
1089 rsp_mqe = ocrdma_get_mqe_rsp(dev);
1090 ocrdma_copy_le32_to_cpu(mqe, rsp_mqe, (sizeof(*mqe)));
1091 if ((mqe->hdr.spcl_sge_cnt_emb & OCRDMA_MQE_HDR_EMB_MASK) >>
1092 OCRDMA_MQE_HDR_EMB_SHIFT)
1095 if (cqe_status || ext_status) {
1096 pr_err("%s() cqe_status=0x%x, ext_status=0x%x,",
1097 __func__, cqe_status, ext_status);
1099 /* This is for embedded cmds. */
1100 pr_err("opcode=0x%x, subsystem=0x%x\n",
1101 (rsp->subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >>
1102 OCRDMA_MBX_RSP_OPCODE_SHIFT,
1103 (rsp->subsys_op & OCRDMA_MBX_RSP_SUBSYS_MASK) >>
1104 OCRDMA_MBX_RSP_SUBSYS_SHIFT);
1106 status = ocrdma_get_mbx_cqe_errno(cqe_status);
1109 /* For non embedded, rsp errors are handled in ocrdma_nonemb_mbx_cmd */
1110 if (rsp && (mqe->u.rsp.status & OCRDMA_MBX_RSP_STATUS_MASK))
1111 status = ocrdma_get_mbx_errno(mqe->u.rsp.status);
1113 mutex_unlock(&dev->mqe_ctx.lock);
1117 static int ocrdma_nonemb_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe,
1121 struct ocrdma_mbx_rsp *rsp = payload_va;
1123 if ((mqe->hdr.spcl_sge_cnt_emb & OCRDMA_MQE_HDR_EMB_MASK) >>
1124 OCRDMA_MQE_HDR_EMB_SHIFT)
1127 status = ocrdma_mbx_cmd(dev, mqe);
1129 /* For non embedded, only CQE failures are handled in
1130 * ocrdma_mbx_cmd. We need to check for RSP errors.
1132 if (rsp->status & OCRDMA_MBX_RSP_STATUS_MASK)
1133 status = ocrdma_get_mbx_errno(rsp->status);
1136 pr_err("opcode=0x%x, subsystem=0x%x\n",
1137 (rsp->subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >>
1138 OCRDMA_MBX_RSP_OPCODE_SHIFT,
1139 (rsp->subsys_op & OCRDMA_MBX_RSP_SUBSYS_MASK) >>
1140 OCRDMA_MBX_RSP_SUBSYS_SHIFT);
1144 static void ocrdma_get_attr(struct ocrdma_dev *dev,
1145 struct ocrdma_dev_attr *attr,
1146 struct ocrdma_mbx_query_config *rsp)
1149 (rsp->max_pd_ca_ack_delay & OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK) >>
1150 OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT;
1151 attr->udp_encap = (rsp->max_pd_ca_ack_delay &
1152 OCRDMA_MBX_QUERY_CFG_L3_TYPE_MASK) >>
1153 OCRDMA_MBX_QUERY_CFG_L3_TYPE_SHIFT;
1155 (rsp->max_dpp_pds_credits & OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_MASK) >>
1156 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET;
1158 (rsp->qp_srq_cq_ird_ord & OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK) >>
1159 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT;
1161 (rsp->max_srq_rpir_qps & OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK) >>
1162 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET;
1163 attr->max_send_sge = ((rsp->max_recv_send_sge &
1164 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
1165 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT);
1166 attr->max_recv_sge = (rsp->max_recv_send_sge &
1167 OCRDMA_MBX_QUERY_CFG_MAX_RECV_SGE_MASK) >>
1168 OCRDMA_MBX_QUERY_CFG_MAX_RECV_SGE_SHIFT;
1169 attr->max_srq_sge = (rsp->max_srq_rqe_sge &
1170 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK) >>
1171 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET;
1172 attr->max_rdma_sge = (rsp->max_wr_rd_sge &
1173 OCRDMA_MBX_QUERY_CFG_MAX_RD_SGE_MASK) >>
1174 OCRDMA_MBX_QUERY_CFG_MAX_RD_SGE_SHIFT;
1175 attr->max_ord_per_qp = (rsp->max_ird_ord_per_qp &
1176 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK) >>
1177 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT;
1178 attr->max_ird_per_qp = (rsp->max_ird_ord_per_qp &
1179 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK) >>
1180 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT;
1181 attr->cq_overflow_detect = (rsp->qp_srq_cq_ird_ord &
1182 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK) >>
1183 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT;
1184 attr->srq_supported = (rsp->qp_srq_cq_ird_ord &
1185 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK) >>
1186 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT;
1187 attr->local_ca_ack_delay = (rsp->max_pd_ca_ack_delay &
1188 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK) >>
1189 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT;
1190 attr->max_mw = rsp->max_mw;
1191 attr->max_mr = rsp->max_mr;
1192 attr->max_mr_size = ((u64)rsp->max_mr_size_hi << 32) |
1193 rsp->max_mr_size_lo;
1195 attr->max_pages_per_frmr = rsp->max_pages_per_frmr;
1196 attr->max_num_mr_pbl = rsp->max_num_mr_pbl;
1197 attr->max_cqe = rsp->max_cq_cqes_per_cq &
1198 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK;
1199 attr->max_cq = (rsp->max_cq_cqes_per_cq &
1200 OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK) >>
1201 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET;
1202 attr->wqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1203 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK) >>
1204 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET) *
1206 attr->rqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1207 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK) >>
1208 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET) *
1210 attr->max_inline_data =
1211 attr->wqe_size - (sizeof(struct ocrdma_hdr_wqe) +
1212 sizeof(struct ocrdma_sge));
1213 if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
1215 attr->ird_page_size = OCRDMA_MIN_Q_PAGE_SIZE;
1216 attr->num_ird_pages = MAX_OCRDMA_IRD_PAGES;
1218 dev->attr.max_wqe = rsp->max_wqes_rqes_per_q >>
1219 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET;
1220 dev->attr.max_rqe = rsp->max_wqes_rqes_per_q &
1221 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK;
1224 static int ocrdma_check_fw_config(struct ocrdma_dev *dev,
1225 struct ocrdma_fw_conf_rsp *conf)
1229 fn_mode = conf->fn_mode & OCRDMA_FN_MODE_RDMA;
1230 if (fn_mode != OCRDMA_FN_MODE_RDMA)
1232 dev->base_eqid = conf->base_eqid;
1233 dev->max_eq = conf->max_eq;
1237 /* can be issued only during init time. */
1238 static int ocrdma_mbx_query_fw_ver(struct ocrdma_dev *dev)
1240 int status = -ENOMEM;
1241 struct ocrdma_mqe *cmd;
1242 struct ocrdma_fw_ver_rsp *rsp;
1244 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_VER, sizeof(*cmd));
1247 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1248 OCRDMA_CMD_GET_FW_VER,
1249 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1251 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1254 rsp = (struct ocrdma_fw_ver_rsp *)cmd;
1255 memset(&dev->attr.fw_ver[0], 0, sizeof(dev->attr.fw_ver));
1256 memcpy(&dev->attr.fw_ver[0], &rsp->running_ver[0],
1257 sizeof(rsp->running_ver));
1258 ocrdma_le32_to_cpu(dev->attr.fw_ver, sizeof(rsp->running_ver));
1264 /* can be issued only during init time. */
1265 static int ocrdma_mbx_query_fw_config(struct ocrdma_dev *dev)
1267 int status = -ENOMEM;
1268 struct ocrdma_mqe *cmd;
1269 struct ocrdma_fw_conf_rsp *rsp;
1271 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_CONFIG, sizeof(*cmd));
1274 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1275 OCRDMA_CMD_GET_FW_CONFIG,
1276 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1277 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1280 rsp = (struct ocrdma_fw_conf_rsp *)cmd;
1281 status = ocrdma_check_fw_config(dev, rsp);
1287 int ocrdma_mbx_rdma_stats(struct ocrdma_dev *dev, bool reset)
1289 struct ocrdma_rdma_stats_req *req = dev->stats_mem.va;
1290 struct ocrdma_mqe *mqe = &dev->stats_mem.mqe;
1291 struct ocrdma_rdma_stats_resp *old_stats;
1294 old_stats = kmalloc(sizeof(*old_stats), GFP_KERNEL);
1295 if (old_stats == NULL)
1298 memset(mqe, 0, sizeof(*mqe));
1299 mqe->hdr.pyld_len = dev->stats_mem.size;
1300 mqe->hdr.spcl_sge_cnt_emb |=
1301 (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
1302 OCRDMA_MQE_HDR_SGE_CNT_MASK;
1303 mqe->u.nonemb_req.sge[0].pa_lo = (u32) (dev->stats_mem.pa & 0xffffffff);
1304 mqe->u.nonemb_req.sge[0].pa_hi = (u32) upper_32_bits(dev->stats_mem.pa);
1305 mqe->u.nonemb_req.sge[0].len = dev->stats_mem.size;
1307 /* Cache the old stats */
1308 memcpy(old_stats, req, sizeof(struct ocrdma_rdma_stats_resp));
1309 memset(req, 0, dev->stats_mem.size);
1311 ocrdma_init_mch((struct ocrdma_mbx_hdr *)req,
1312 OCRDMA_CMD_GET_RDMA_STATS,
1314 dev->stats_mem.size);
1316 req->reset_stats = reset;
1318 status = ocrdma_nonemb_mbx_cmd(dev, mqe, dev->stats_mem.va);
1320 /* Copy from cache, if mbox fails */
1321 memcpy(req, old_stats, sizeof(struct ocrdma_rdma_stats_resp));
1323 ocrdma_le32_to_cpu(req, dev->stats_mem.size);
1329 static int ocrdma_mbx_get_ctrl_attribs(struct ocrdma_dev *dev)
1331 int status = -ENOMEM;
1332 struct ocrdma_dma_mem dma;
1333 struct ocrdma_mqe *mqe;
1334 struct ocrdma_get_ctrl_attribs_rsp *ctrl_attr_rsp;
1335 struct mgmt_hba_attribs *hba_attribs;
1337 mqe = kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL);
1341 dma.size = sizeof(struct ocrdma_get_ctrl_attribs_rsp);
1342 dma.va = dma_alloc_coherent(&dev->nic_info.pdev->dev,
1343 dma.size, &dma.pa, GFP_KERNEL);
1347 mqe->hdr.pyld_len = dma.size;
1348 mqe->hdr.spcl_sge_cnt_emb |=
1349 (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
1350 OCRDMA_MQE_HDR_SGE_CNT_MASK;
1351 mqe->u.nonemb_req.sge[0].pa_lo = (u32) (dma.pa & 0xffffffff);
1352 mqe->u.nonemb_req.sge[0].pa_hi = (u32) upper_32_bits(dma.pa);
1353 mqe->u.nonemb_req.sge[0].len = dma.size;
1355 memset(dma.va, 0, dma.size);
1356 ocrdma_init_mch((struct ocrdma_mbx_hdr *)dma.va,
1357 OCRDMA_CMD_GET_CTRL_ATTRIBUTES,
1358 OCRDMA_SUBSYS_COMMON,
1361 status = ocrdma_nonemb_mbx_cmd(dev, mqe, dma.va);
1363 ctrl_attr_rsp = (struct ocrdma_get_ctrl_attribs_rsp *)dma.va;
1364 hba_attribs = &ctrl_attr_rsp->ctrl_attribs.hba_attribs;
1366 dev->hba_port_num = (hba_attribs->ptpnum_maxdoms_hbast_cv &
1367 OCRDMA_HBA_ATTRB_PTNUM_MASK)
1368 >> OCRDMA_HBA_ATTRB_PTNUM_SHIFT;
1369 strncpy(dev->model_number,
1370 hba_attribs->controller_model_number, 31);
1372 dma_free_coherent(&dev->nic_info.pdev->dev, dma.size, dma.va, dma.pa);
1378 static int ocrdma_mbx_query_dev(struct ocrdma_dev *dev)
1380 int status = -ENOMEM;
1381 struct ocrdma_mbx_query_config *rsp;
1382 struct ocrdma_mqe *cmd;
1384 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_CONFIG, sizeof(*cmd));
1387 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1390 rsp = (struct ocrdma_mbx_query_config *)cmd;
1391 ocrdma_get_attr(dev, &dev->attr, rsp);
1397 int ocrdma_mbx_get_link_speed(struct ocrdma_dev *dev, u8 *lnk_speed,
1400 int status = -ENOMEM;
1401 struct ocrdma_get_link_speed_rsp *rsp;
1402 struct ocrdma_mqe *cmd;
1404 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1,
1408 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1409 OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1,
1410 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1412 ((struct ocrdma_mbx_hdr *)cmd->u.cmd)->rsvd_version = 0x1;
1414 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1418 rsp = (struct ocrdma_get_link_speed_rsp *)cmd;
1420 *lnk_speed = (rsp->pflt_pps_ld_pnum & OCRDMA_PHY_PS_MASK)
1421 >> OCRDMA_PHY_PS_SHIFT;
1423 *lnk_state = (rsp->res_lnk_st & OCRDMA_LINK_ST_MASK);
1430 static int ocrdma_mbx_get_phy_info(struct ocrdma_dev *dev)
1432 int status = -ENOMEM;
1433 struct ocrdma_mqe *cmd;
1434 struct ocrdma_get_phy_info_rsp *rsp;
1436 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_PHY_DETAILS, sizeof(*cmd));
1440 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1441 OCRDMA_CMD_PHY_DETAILS, OCRDMA_SUBSYS_COMMON,
1444 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1448 rsp = (struct ocrdma_get_phy_info_rsp *)cmd;
1450 (rsp->ityp_ptyp & OCRDMA_PHY_TYPE_MASK);
1451 dev->phy.interface_type =
1452 (rsp->ityp_ptyp & OCRDMA_IF_TYPE_MASK)
1453 >> OCRDMA_IF_TYPE_SHIFT;
1454 dev->phy.auto_speeds_supported =
1455 (rsp->fspeed_aspeed & OCRDMA_ASPEED_SUPP_MASK);
1456 dev->phy.fixed_speeds_supported =
1457 (rsp->fspeed_aspeed & OCRDMA_FSPEED_SUPP_MASK)
1458 >> OCRDMA_FSPEED_SUPP_SHIFT;
1464 int ocrdma_mbx_alloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1466 int status = -ENOMEM;
1467 struct ocrdma_alloc_pd *cmd;
1468 struct ocrdma_alloc_pd_rsp *rsp;
1470 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD, sizeof(*cmd));
1473 if (pd->dpp_enabled)
1474 cmd->enable_dpp_rsvd |= OCRDMA_ALLOC_PD_ENABLE_DPP;
1475 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1478 rsp = (struct ocrdma_alloc_pd_rsp *)cmd;
1479 pd->id = rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_PDID_MASK;
1480 if (rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_DPP) {
1481 pd->dpp_enabled = true;
1482 pd->dpp_page = rsp->dpp_page_pdid >>
1483 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT;
1485 pd->dpp_enabled = false;
1493 int ocrdma_mbx_dealloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1495 int status = -ENOMEM;
1496 struct ocrdma_dealloc_pd *cmd;
1498 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD, sizeof(*cmd));
1502 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1508 static int ocrdma_mbx_alloc_pd_range(struct ocrdma_dev *dev)
1510 int status = -ENOMEM;
1511 size_t pd_bitmap_size;
1512 struct ocrdma_alloc_pd_range *cmd;
1513 struct ocrdma_alloc_pd_range_rsp *rsp;
1515 /* Pre allocate the DPP PDs */
1516 if (dev->attr.max_dpp_pds) {
1517 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD_RANGE,
1521 cmd->pd_count = dev->attr.max_dpp_pds;
1522 cmd->enable_dpp_rsvd |= OCRDMA_ALLOC_PD_ENABLE_DPP;
1523 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1524 rsp = (struct ocrdma_alloc_pd_range_rsp *)cmd;
1526 if (!status && (rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_DPP) &&
1528 dev->pd_mgr->dpp_page_index = rsp->dpp_page_pdid >>
1529 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT;
1530 dev->pd_mgr->pd_dpp_start = rsp->dpp_page_pdid &
1531 OCRDMA_ALLOC_PD_RNG_RSP_START_PDID_MASK;
1532 dev->pd_mgr->max_dpp_pd = rsp->pd_count;
1534 BITS_TO_LONGS(rsp->pd_count) * sizeof(long);
1535 dev->pd_mgr->pd_dpp_bitmap = kzalloc(pd_bitmap_size,
1541 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD_RANGE, sizeof(*cmd));
1545 cmd->pd_count = dev->attr.max_pd - dev->attr.max_dpp_pds;
1546 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1547 rsp = (struct ocrdma_alloc_pd_range_rsp *)cmd;
1548 if (!status && rsp->pd_count) {
1549 dev->pd_mgr->pd_norm_start = rsp->dpp_page_pdid &
1550 OCRDMA_ALLOC_PD_RNG_RSP_START_PDID_MASK;
1551 dev->pd_mgr->max_normal_pd = rsp->pd_count;
1552 pd_bitmap_size = BITS_TO_LONGS(rsp->pd_count) * sizeof(long);
1553 dev->pd_mgr->pd_norm_bitmap = kzalloc(pd_bitmap_size,
1558 if (dev->pd_mgr->pd_norm_bitmap || dev->pd_mgr->pd_dpp_bitmap) {
1559 /* Enable PD resource manager */
1560 dev->pd_mgr->pd_prealloc_valid = true;
1566 static void ocrdma_mbx_dealloc_pd_range(struct ocrdma_dev *dev)
1568 struct ocrdma_dealloc_pd_range *cmd;
1570 /* return normal PDs to firmware */
1571 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD_RANGE, sizeof(*cmd));
1575 if (dev->pd_mgr->max_normal_pd) {
1576 cmd->start_pd_id = dev->pd_mgr->pd_norm_start;
1577 cmd->pd_count = dev->pd_mgr->max_normal_pd;
1578 ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1581 if (dev->pd_mgr->max_dpp_pd) {
1583 /* return DPP PDs to firmware */
1584 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD_RANGE,
1589 cmd->start_pd_id = dev->pd_mgr->pd_dpp_start;
1590 cmd->pd_count = dev->pd_mgr->max_dpp_pd;
1591 ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1597 void ocrdma_alloc_pd_pool(struct ocrdma_dev *dev)
1601 dev->pd_mgr = kzalloc(sizeof(struct ocrdma_pd_resource_mgr),
1606 status = ocrdma_mbx_alloc_pd_range(dev);
1608 pr_err("%s(%d) Unable to initialize PD pool, using default.\n",
1613 static void ocrdma_free_pd_pool(struct ocrdma_dev *dev)
1615 ocrdma_mbx_dealloc_pd_range(dev);
1616 kfree(dev->pd_mgr->pd_norm_bitmap);
1617 kfree(dev->pd_mgr->pd_dpp_bitmap);
1621 static int ocrdma_build_q_conf(u32 *num_entries, int entry_size,
1622 int *num_pages, int *page_size)
1627 *num_entries = roundup_pow_of_two(*num_entries);
1628 mem_size = *num_entries * entry_size;
1629 /* find the possible lowest possible multiplier */
1630 for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1631 if (mem_size <= (OCRDMA_Q_PAGE_BASE_SIZE << i))
1634 if (i >= OCRDMA_MAX_Q_PAGE_SIZE_CNT)
1636 mem_size = roundup(mem_size,
1637 ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES));
1639 mem_size / ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1640 *page_size = ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1641 *num_entries = mem_size / entry_size;
1645 static int ocrdma_mbx_create_ah_tbl(struct ocrdma_dev *dev)
1648 int status = -ENOMEM;
1650 struct ocrdma_create_ah_tbl *cmd;
1651 struct ocrdma_create_ah_tbl_rsp *rsp;
1652 struct pci_dev *pdev = dev->nic_info.pdev;
1654 struct ocrdma_pbe *pbes;
1656 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_AH_TBL, sizeof(*cmd));
1660 max_ah = OCRDMA_MAX_AH;
1661 dev->av_tbl.size = sizeof(struct ocrdma_av) * max_ah;
1663 /* number of PBEs in PBL */
1664 cmd->ah_conf = (OCRDMA_AH_TBL_PAGES <<
1665 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT) &
1666 OCRDMA_CREATE_AH_NUM_PAGES_MASK;
1669 for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1670 if (PAGE_SIZE == (OCRDMA_MIN_Q_PAGE_SIZE << i))
1673 cmd->ah_conf |= (i << OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT) &
1674 OCRDMA_CREATE_AH_PAGE_SIZE_MASK;
1677 cmd->ah_conf |= (sizeof(struct ocrdma_av) <<
1678 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT) &
1679 OCRDMA_CREATE_AH_ENTRY_SIZE_MASK;
1681 dev->av_tbl.pbl.va = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1682 &dev->av_tbl.pbl.pa,
1684 if (dev->av_tbl.pbl.va == NULL)
1687 dev->av_tbl.va = dma_alloc_coherent(&pdev->dev, dev->av_tbl.size,
1689 if (dev->av_tbl.va == NULL)
1691 dev->av_tbl.pa = pa;
1692 dev->av_tbl.num_ah = max_ah;
1693 memset(dev->av_tbl.va, 0, dev->av_tbl.size);
1695 pbes = (struct ocrdma_pbe *)dev->av_tbl.pbl.va;
1696 for (i = 0; i < dev->av_tbl.size / OCRDMA_MIN_Q_PAGE_SIZE; i++) {
1697 pbes[i].pa_lo = (u32)cpu_to_le32(pa & 0xffffffff);
1698 pbes[i].pa_hi = (u32)cpu_to_le32(upper_32_bits(pa));
1701 cmd->tbl_addr[0].lo = (u32)(dev->av_tbl.pbl.pa & 0xFFFFFFFF);
1702 cmd->tbl_addr[0].hi = (u32)upper_32_bits(dev->av_tbl.pbl.pa);
1703 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1706 rsp = (struct ocrdma_create_ah_tbl_rsp *)cmd;
1707 dev->av_tbl.ahid = rsp->ahid & 0xFFFF;
1712 dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1714 dev->av_tbl.va = NULL;
1716 dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1717 dev->av_tbl.pbl.pa);
1718 dev->av_tbl.pbl.va = NULL;
1719 dev->av_tbl.size = 0;
1725 static void ocrdma_mbx_delete_ah_tbl(struct ocrdma_dev *dev)
1727 struct ocrdma_delete_ah_tbl *cmd;
1728 struct pci_dev *pdev = dev->nic_info.pdev;
1730 if (dev->av_tbl.va == NULL)
1733 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_AH_TBL, sizeof(*cmd));
1736 cmd->ahid = dev->av_tbl.ahid;
1738 ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1739 dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1741 dev->av_tbl.va = NULL;
1742 dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1743 dev->av_tbl.pbl.pa);
1747 /* Multiple CQs uses the EQ. This routine returns least used
1748 * EQ to associate with CQ. This will distributes the interrupt
1749 * processing and CPU load to associated EQ, vector and so to that CPU.
1751 static u16 ocrdma_bind_eq(struct ocrdma_dev *dev)
1753 int i, selected_eq = 0, cq_cnt = 0;
1756 mutex_lock(&dev->dev_lock);
1757 cq_cnt = dev->eq_tbl[0].cq_cnt;
1758 eq_id = dev->eq_tbl[0].q.id;
1759 /* find the EQ which is has the least number of
1760 * CQs associated with it.
1762 for (i = 0; i < dev->eq_cnt; i++) {
1763 if (dev->eq_tbl[i].cq_cnt < cq_cnt) {
1764 cq_cnt = dev->eq_tbl[i].cq_cnt;
1765 eq_id = dev->eq_tbl[i].q.id;
1769 dev->eq_tbl[selected_eq].cq_cnt += 1;
1770 mutex_unlock(&dev->dev_lock);
1774 static void ocrdma_unbind_eq(struct ocrdma_dev *dev, u16 eq_id)
1778 mutex_lock(&dev->dev_lock);
1779 i = ocrdma_get_eq_table_index(dev, eq_id);
1782 dev->eq_tbl[i].cq_cnt -= 1;
1783 mutex_unlock(&dev->dev_lock);
1786 int ocrdma_mbx_create_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq,
1787 int entries, int dpp_cq, u16 pd_id)
1789 int status = -ENOMEM; int max_hw_cqe;
1790 struct pci_dev *pdev = dev->nic_info.pdev;
1791 struct ocrdma_create_cq *cmd;
1792 struct ocrdma_create_cq_rsp *rsp;
1793 u32 hw_pages, cqe_size, page_size, cqe_count;
1795 if (entries > dev->attr.max_cqe) {
1796 pr_err("%s(%d) max_cqe=0x%x, requester_cqe=0x%x\n",
1797 __func__, dev->id, dev->attr.max_cqe, entries);
1800 if (dpp_cq && (ocrdma_get_asic_type(dev) != OCRDMA_ASIC_GEN_SKH_R))
1806 cqe_size = OCRDMA_DPP_CQE_SIZE;
1809 cq->max_hw_cqe = dev->attr.max_cqe;
1810 max_hw_cqe = dev->attr.max_cqe;
1811 cqe_size = sizeof(struct ocrdma_cqe);
1812 hw_pages = OCRDMA_CREATE_CQ_MAX_PAGES;
1815 cq->len = roundup(max_hw_cqe * cqe_size, OCRDMA_MIN_Q_PAGE_SIZE);
1817 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_CQ, sizeof(*cmd));
1820 ocrdma_init_mch(&cmd->cmd.req, OCRDMA_CMD_CREATE_CQ,
1821 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1822 cq->va = dma_alloc_coherent(&pdev->dev, cq->len, &cq->pa, GFP_KERNEL);
1827 memset(cq->va, 0, cq->len);
1828 page_size = cq->len / hw_pages;
1829 cmd->cmd.pgsz_pgcnt = (page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
1830 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
1831 cmd->cmd.pgsz_pgcnt |= hw_pages;
1832 cmd->cmd.ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
1834 cq->eqn = ocrdma_bind_eq(dev);
1835 cmd->cmd.req.rsvd_version = OCRDMA_CREATE_CQ_VER3;
1836 cqe_count = cq->len / cqe_size;
1837 cq->cqe_cnt = cqe_count;
1838 if (cqe_count > 1024) {
1839 /* Set cnt to 3 to indicate more than 1024 cq entries */
1840 cmd->cmd.ev_cnt_flags |= (0x3 << OCRDMA_CREATE_CQ_CNT_SHIFT);
1843 switch (cqe_count) {
1856 cmd->cmd.ev_cnt_flags |= (count << OCRDMA_CREATE_CQ_CNT_SHIFT);
1858 /* shared eq between all the consumer cqs. */
1859 cmd->cmd.eqn = cq->eqn;
1860 if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
1862 cmd->cmd.pgsz_pgcnt |= OCRDMA_CREATE_CQ_DPP <<
1863 OCRDMA_CREATE_CQ_TYPE_SHIFT;
1864 cq->phase_change = false;
1865 cmd->cmd.pdid_cqecnt = (cq->len / cqe_size);
1867 cmd->cmd.pdid_cqecnt = (cq->len / cqe_size) - 1;
1868 cmd->cmd.ev_cnt_flags |= OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID;
1869 cq->phase_change = true;
1872 /* pd_id valid only for v3 */
1873 cmd->cmd.pdid_cqecnt |= (pd_id <<
1874 OCRDMA_CREATE_CQ_CMD_PDID_SHIFT);
1875 ocrdma_build_q_pages(&cmd->cmd.pa[0], hw_pages, cq->pa, page_size);
1876 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1880 rsp = (struct ocrdma_create_cq_rsp *)cmd;
1881 cq->id = (u16) (rsp->rsp.cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
1885 ocrdma_unbind_eq(dev, cq->eqn);
1886 dma_free_coherent(&pdev->dev, cq->len, cq->va, cq->pa);
1892 int ocrdma_mbx_destroy_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq)
1894 int status = -ENOMEM;
1895 struct ocrdma_destroy_cq *cmd;
1897 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_CQ, sizeof(*cmd));
1900 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_DELETE_CQ,
1901 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1903 cmd->bypass_flush_qid |=
1904 (cq->id << OCRDMA_DESTROY_CQ_QID_SHIFT) &
1905 OCRDMA_DESTROY_CQ_QID_MASK;
1907 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1908 ocrdma_unbind_eq(dev, cq->eqn);
1909 dma_free_coherent(&dev->nic_info.pdev->dev, cq->len, cq->va, cq->pa);
1914 int ocrdma_mbx_alloc_lkey(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1915 u32 pdid, int addr_check)
1917 int status = -ENOMEM;
1918 struct ocrdma_alloc_lkey *cmd;
1919 struct ocrdma_alloc_lkey_rsp *rsp;
1921 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_LKEY, sizeof(*cmd));
1925 cmd->pbl_sz_flags |= addr_check;
1926 cmd->pbl_sz_flags |= (hwmr->fr_mr << OCRDMA_ALLOC_LKEY_FMR_SHIFT);
1927 cmd->pbl_sz_flags |=
1928 (hwmr->remote_wr << OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT);
1929 cmd->pbl_sz_flags |=
1930 (hwmr->remote_rd << OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT);
1931 cmd->pbl_sz_flags |=
1932 (hwmr->local_wr << OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT);
1933 cmd->pbl_sz_flags |=
1934 (hwmr->remote_atomic << OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT);
1935 cmd->pbl_sz_flags |=
1936 (hwmr->num_pbls << OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT);
1938 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1941 rsp = (struct ocrdma_alloc_lkey_rsp *)cmd;
1942 hwmr->lkey = rsp->lrkey;
1948 int ocrdma_mbx_dealloc_lkey(struct ocrdma_dev *dev, int fr_mr, u32 lkey)
1950 int status = -ENOMEM;
1951 struct ocrdma_dealloc_lkey *cmd;
1953 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_LKEY, sizeof(*cmd));
1957 cmd->rsvd_frmr = fr_mr ? 1 : 0;
1958 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1966 static int ocrdma_mbx_reg_mr(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1967 u32 pdid, u32 pbl_cnt, u32 pbe_size, u32 last)
1969 int status = -ENOMEM;
1971 struct ocrdma_reg_nsmr *cmd;
1972 struct ocrdma_reg_nsmr_rsp *rsp;
1974 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR, sizeof(*cmd));
1978 pdid | (hwmr->num_pbls << OCRDMA_REG_NSMR_NUM_PBL_SHIFT);
1979 cmd->fr_mr = hwmr->fr_mr;
1981 cmd->flags_hpage_pbe_sz |= (hwmr->remote_wr <<
1982 OCRDMA_REG_NSMR_REMOTE_WR_SHIFT);
1983 cmd->flags_hpage_pbe_sz |= (hwmr->remote_rd <<
1984 OCRDMA_REG_NSMR_REMOTE_RD_SHIFT);
1985 cmd->flags_hpage_pbe_sz |= (hwmr->local_wr <<
1986 OCRDMA_REG_NSMR_LOCAL_WR_SHIFT);
1987 cmd->flags_hpage_pbe_sz |= (hwmr->remote_atomic <<
1988 OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT);
1989 cmd->flags_hpage_pbe_sz |= (hwmr->mw_bind <<
1990 OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT);
1991 cmd->flags_hpage_pbe_sz |= (last << OCRDMA_REG_NSMR_LAST_SHIFT);
1993 cmd->flags_hpage_pbe_sz |= (hwmr->pbe_size / OCRDMA_MIN_HPAGE_SIZE);
1994 cmd->flags_hpage_pbe_sz |= (hwmr->pbl_size / OCRDMA_MIN_HPAGE_SIZE) <<
1995 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT;
1996 cmd->totlen_low = hwmr->len;
1997 cmd->totlen_high = upper_32_bits(hwmr->len);
1998 cmd->fbo_low = (u32) (hwmr->fbo & 0xffffffff);
1999 cmd->fbo_high = (u32) upper_32_bits(hwmr->fbo);
2000 cmd->va_loaddr = (u32) hwmr->va;
2001 cmd->va_hiaddr = (u32) upper_32_bits(hwmr->va);
2003 for (i = 0; i < pbl_cnt; i++) {
2004 cmd->pbl[i].lo = (u32) (hwmr->pbl_table[i].pa & 0xffffffff);
2005 cmd->pbl[i].hi = upper_32_bits(hwmr->pbl_table[i].pa);
2007 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2010 rsp = (struct ocrdma_reg_nsmr_rsp *)cmd;
2011 hwmr->lkey = rsp->lrkey;
2017 static int ocrdma_mbx_reg_mr_cont(struct ocrdma_dev *dev,
2018 struct ocrdma_hw_mr *hwmr, u32 pbl_cnt,
2019 u32 pbl_offset, u32 last)
2021 int status = -ENOMEM;
2023 struct ocrdma_reg_nsmr_cont *cmd;
2025 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR_CONT, sizeof(*cmd));
2028 cmd->lrkey = hwmr->lkey;
2029 cmd->num_pbl_offset = (pbl_cnt << OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT) |
2030 (pbl_offset & OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK);
2031 cmd->last = last << OCRDMA_REG_NSMR_CONT_LAST_SHIFT;
2033 for (i = 0; i < pbl_cnt; i++) {
2035 (u32) (hwmr->pbl_table[i + pbl_offset].pa & 0xffffffff);
2037 upper_32_bits(hwmr->pbl_table[i + pbl_offset].pa);
2039 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2047 int ocrdma_reg_mr(struct ocrdma_dev *dev,
2048 struct ocrdma_hw_mr *hwmr, u32 pdid, int acc)
2052 u32 cur_pbl_cnt, pbl_offset;
2053 u32 pending_pbl_cnt = hwmr->num_pbls;
2056 cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
2057 if (cur_pbl_cnt == pending_pbl_cnt)
2060 status = ocrdma_mbx_reg_mr(dev, hwmr, pdid,
2061 cur_pbl_cnt, hwmr->pbe_size, last);
2063 pr_err("%s() status=%d\n", __func__, status);
2066 /* if there is no more pbls to register then exit. */
2071 pbl_offset += cur_pbl_cnt;
2072 pending_pbl_cnt -= cur_pbl_cnt;
2073 cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
2074 /* if we reach the end of the pbls, then need to set the last
2075 * bit, indicating no more pbls to register for this memory key.
2077 if (cur_pbl_cnt == pending_pbl_cnt)
2080 status = ocrdma_mbx_reg_mr_cont(dev, hwmr, cur_pbl_cnt,
2086 pr_err("%s() err. status=%d\n", __func__, status);
2091 bool ocrdma_is_qp_in_sq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
2093 struct ocrdma_qp *tmp;
2095 list_for_each_entry(tmp, &cq->sq_head, sq_entry) {
2104 bool ocrdma_is_qp_in_rq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
2106 struct ocrdma_qp *tmp;
2108 list_for_each_entry(tmp, &cq->rq_head, rq_entry) {
2117 void ocrdma_flush_qp(struct ocrdma_qp *qp)
2120 unsigned long flags;
2121 struct ocrdma_dev *dev = get_ocrdma_dev(qp->ibqp.device);
2123 spin_lock_irqsave(&dev->flush_q_lock, flags);
2124 found = ocrdma_is_qp_in_sq_flushlist(qp->sq_cq, qp);
2126 list_add_tail(&qp->sq_entry, &qp->sq_cq->sq_head);
2128 found = ocrdma_is_qp_in_rq_flushlist(qp->rq_cq, qp);
2130 list_add_tail(&qp->rq_entry, &qp->rq_cq->rq_head);
2132 spin_unlock_irqrestore(&dev->flush_q_lock, flags);
2135 static void ocrdma_init_hwq_ptr(struct ocrdma_qp *qp)
2143 int ocrdma_qp_state_change(struct ocrdma_qp *qp, enum ib_qp_state new_ib_state,
2144 enum ib_qp_state *old_ib_state)
2146 unsigned long flags;
2147 enum ocrdma_qp_state new_state;
2148 new_state = get_ocrdma_qp_state(new_ib_state);
2150 /* sync with wqe and rqe posting */
2151 spin_lock_irqsave(&qp->q_lock, flags);
2154 *old_ib_state = get_ibqp_state(qp->state);
2155 if (new_state == qp->state) {
2156 spin_unlock_irqrestore(&qp->q_lock, flags);
2161 if (new_state == OCRDMA_QPS_INIT) {
2162 ocrdma_init_hwq_ptr(qp);
2163 ocrdma_del_flush_qp(qp);
2164 } else if (new_state == OCRDMA_QPS_ERR) {
2165 ocrdma_flush_qp(qp);
2168 qp->state = new_state;
2170 spin_unlock_irqrestore(&qp->q_lock, flags);
2174 static u32 ocrdma_set_create_qp_mbx_access_flags(struct ocrdma_qp *qp)
2177 if (qp->cap_flags & OCRDMA_QP_INB_RD)
2178 flags |= OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK;
2179 if (qp->cap_flags & OCRDMA_QP_INB_WR)
2180 flags |= OCRDMA_CREATE_QP_REQ_INB_WREN_MASK;
2181 if (qp->cap_flags & OCRDMA_QP_MW_BIND)
2182 flags |= OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK;
2183 if (qp->cap_flags & OCRDMA_QP_LKEY0)
2184 flags |= OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK;
2185 if (qp->cap_flags & OCRDMA_QP_FAST_REG)
2186 flags |= OCRDMA_CREATE_QP_REQ_FMR_EN_MASK;
2190 static int ocrdma_set_create_qp_sq_cmd(struct ocrdma_create_qp_req *cmd,
2191 struct ib_qp_init_attr *attrs,
2192 struct ocrdma_qp *qp)
2195 u32 len, hw_pages, hw_page_size;
2197 struct ocrdma_pd *pd = qp->pd;
2198 struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
2199 struct pci_dev *pdev = dev->nic_info.pdev;
2200 u32 max_wqe_allocated;
2201 u32 max_sges = attrs->cap.max_send_sge;
2203 /* QP1 may exceed 127 */
2204 max_wqe_allocated = min_t(u32, attrs->cap.max_send_wr + 1,
2207 status = ocrdma_build_q_conf(&max_wqe_allocated,
2208 dev->attr.wqe_size, &hw_pages, &hw_page_size);
2210 pr_err("%s() req. max_send_wr=0x%x\n", __func__,
2214 qp->sq.max_cnt = max_wqe_allocated;
2215 len = (hw_pages * hw_page_size);
2217 qp->sq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2220 memset(qp->sq.va, 0, len);
2223 qp->sq.entry_size = dev->attr.wqe_size;
2224 ocrdma_build_q_pages(&cmd->wq_addr[0], hw_pages, pa, hw_page_size);
2226 cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
2227 << OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT);
2228 cmd->num_wq_rq_pages |= (hw_pages <<
2229 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT) &
2230 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK;
2231 cmd->max_sge_send_write |= (max_sges <<
2232 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT) &
2233 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK;
2234 cmd->max_sge_send_write |= (max_sges <<
2235 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT) &
2236 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK;
2237 cmd->max_wqe_rqe |= (ilog2(qp->sq.max_cnt) <<
2238 OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT) &
2239 OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK;
2240 cmd->wqe_rqe_size |= (dev->attr.wqe_size <<
2241 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT) &
2242 OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK;
2246 static int ocrdma_set_create_qp_rq_cmd(struct ocrdma_create_qp_req *cmd,
2247 struct ib_qp_init_attr *attrs,
2248 struct ocrdma_qp *qp)
2251 u32 len, hw_pages, hw_page_size;
2253 struct ocrdma_pd *pd = qp->pd;
2254 struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
2255 struct pci_dev *pdev = dev->nic_info.pdev;
2256 u32 max_rqe_allocated = attrs->cap.max_recv_wr + 1;
2258 status = ocrdma_build_q_conf(&max_rqe_allocated, dev->attr.rqe_size,
2259 &hw_pages, &hw_page_size);
2261 pr_err("%s() req. max_recv_wr=0x%x\n", __func__,
2262 attrs->cap.max_recv_wr + 1);
2265 qp->rq.max_cnt = max_rqe_allocated;
2266 len = (hw_pages * hw_page_size);
2268 qp->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2271 memset(qp->rq.va, 0, len);
2274 qp->rq.entry_size = dev->attr.rqe_size;
2276 ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
2277 cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
2278 OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT);
2279 cmd->num_wq_rq_pages |=
2280 (hw_pages << OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT) &
2281 OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK;
2282 cmd->max_sge_recv_flags |= (attrs->cap.max_recv_sge <<
2283 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT) &
2284 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK;
2285 cmd->max_wqe_rqe |= (ilog2(qp->rq.max_cnt) <<
2286 OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT) &
2287 OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK;
2288 cmd->wqe_rqe_size |= (dev->attr.rqe_size <<
2289 OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT) &
2290 OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK;
2294 static void ocrdma_set_create_qp_dpp_cmd(struct ocrdma_create_qp_req *cmd,
2295 struct ocrdma_pd *pd,
2296 struct ocrdma_qp *qp,
2297 u8 enable_dpp_cq, u16 dpp_cq_id)
2300 qp->dpp_enabled = true;
2301 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
2304 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
2305 cmd->dpp_credits_cqid = dpp_cq_id;
2306 cmd->dpp_credits_cqid |= OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT <<
2307 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT;
2310 static int ocrdma_set_create_qp_ird_cmd(struct ocrdma_create_qp_req *cmd,
2311 struct ocrdma_qp *qp)
2313 struct ocrdma_pd *pd = qp->pd;
2314 struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
2315 struct pci_dev *pdev = dev->nic_info.pdev;
2317 int ird_page_size = dev->attr.ird_page_size;
2318 int ird_q_len = dev->attr.num_ird_pages * ird_page_size;
2319 struct ocrdma_hdr_wqe *rqe;
2322 if (dev->attr.ird == 0)
2325 qp->ird_q_va = dma_alloc_coherent(&pdev->dev, ird_q_len,
2329 memset(qp->ird_q_va, 0, ird_q_len);
2330 ocrdma_build_q_pages(&cmd->ird_addr[0], dev->attr.num_ird_pages,
2332 for (; i < ird_q_len / dev->attr.rqe_size; i++) {
2333 rqe = (struct ocrdma_hdr_wqe *)(qp->ird_q_va +
2334 (i * dev->attr.rqe_size));
2337 rqe->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
2338 rqe->cw |= (8 << OCRDMA_WQE_SIZE_SHIFT);
2339 rqe->cw |= (8 << OCRDMA_WQE_NXT_WQE_SIZE_SHIFT);
2344 static void ocrdma_get_create_qp_rsp(struct ocrdma_create_qp_rsp *rsp,
2345 struct ocrdma_qp *qp,
2346 struct ib_qp_init_attr *attrs,
2347 u16 *dpp_offset, u16 *dpp_credit_lmt)
2349 u32 max_wqe_allocated, max_rqe_allocated;
2350 qp->id = rsp->qp_id & OCRDMA_CREATE_QP_RSP_QP_ID_MASK;
2351 qp->rq.dbid = rsp->sq_rq_id & OCRDMA_CREATE_QP_RSP_RQ_ID_MASK;
2352 qp->sq.dbid = rsp->sq_rq_id >> OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT;
2353 qp->max_ird = rsp->max_ord_ird & OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK;
2354 qp->max_ord = (rsp->max_ord_ird >> OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT);
2355 qp->dpp_enabled = false;
2356 if (rsp->dpp_response & OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK) {
2357 qp->dpp_enabled = true;
2358 *dpp_credit_lmt = (rsp->dpp_response &
2359 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK) >>
2360 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT;
2361 *dpp_offset = (rsp->dpp_response &
2362 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK) >>
2363 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT;
2366 rsp->max_wqe_rqe >> OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT;
2367 max_wqe_allocated = 1 << max_wqe_allocated;
2368 max_rqe_allocated = 1 << ((u16)rsp->max_wqe_rqe);
2370 qp->sq.max_cnt = max_wqe_allocated;
2371 qp->sq.max_wqe_idx = max_wqe_allocated - 1;
2374 qp->rq.max_cnt = max_rqe_allocated;
2375 qp->rq.max_wqe_idx = max_rqe_allocated - 1;
2379 int ocrdma_mbx_create_qp(struct ocrdma_qp *qp, struct ib_qp_init_attr *attrs,
2380 u8 enable_dpp_cq, u16 dpp_cq_id, u16 *dpp_offset,
2381 u16 *dpp_credit_lmt)
2383 int status = -ENOMEM;
2385 struct ocrdma_pd *pd = qp->pd;
2386 struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
2387 struct pci_dev *pdev = dev->nic_info.pdev;
2388 struct ocrdma_cq *cq;
2389 struct ocrdma_create_qp_req *cmd;
2390 struct ocrdma_create_qp_rsp *rsp;
2393 switch (attrs->qp_type) {
2395 qptype = OCRDMA_QPT_GSI;
2398 qptype = OCRDMA_QPT_RC;
2401 qptype = OCRDMA_QPT_UD;
2407 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_QP, sizeof(*cmd));
2410 cmd->type_pgsz_pdn |= (qptype << OCRDMA_CREATE_QP_REQ_QPT_SHIFT) &
2411 OCRDMA_CREATE_QP_REQ_QPT_MASK;
2412 status = ocrdma_set_create_qp_sq_cmd(cmd, attrs, qp);
2417 struct ocrdma_srq *srq = get_ocrdma_srq(attrs->srq);
2418 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK;
2419 cmd->rq_addr[0].lo = srq->id;
2422 status = ocrdma_set_create_qp_rq_cmd(cmd, attrs, qp);
2427 status = ocrdma_set_create_qp_ird_cmd(cmd, qp);
2431 cmd->type_pgsz_pdn |= (pd->id << OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT) &
2432 OCRDMA_CREATE_QP_REQ_PD_ID_MASK;
2434 flags = ocrdma_set_create_qp_mbx_access_flags(qp);
2436 cmd->max_sge_recv_flags |= flags;
2437 cmd->max_ord_ird |= (dev->attr.max_ord_per_qp <<
2438 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT) &
2439 OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK;
2440 cmd->max_ord_ird |= (dev->attr.max_ird_per_qp <<
2441 OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT) &
2442 OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK;
2443 cq = get_ocrdma_cq(attrs->send_cq);
2444 cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT) &
2445 OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK;
2447 cq = get_ocrdma_cq(attrs->recv_cq);
2448 cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT) &
2449 OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK;
2452 if (pd->dpp_enabled && attrs->cap.max_inline_data && pd->num_dpp_qp &&
2453 (attrs->cap.max_inline_data <= dev->attr.max_inline_data)) {
2454 ocrdma_set_create_qp_dpp_cmd(cmd, pd, qp, enable_dpp_cq,
2458 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2461 rsp = (struct ocrdma_create_qp_rsp *)cmd;
2462 ocrdma_get_create_qp_rsp(rsp, qp, attrs, dpp_offset, dpp_credit_lmt);
2463 qp->state = OCRDMA_QPS_RST;
2468 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2470 pr_err("%s(%d) rq_err\n", __func__, dev->id);
2471 dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2473 pr_err("%s(%d) sq_err\n", __func__, dev->id);
2478 int ocrdma_mbx_query_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2479 struct ocrdma_qp_params *param)
2481 int status = -ENOMEM;
2482 struct ocrdma_query_qp *cmd;
2483 struct ocrdma_query_qp_rsp *rsp;
2485 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_QP, sizeof(*rsp));
2488 cmd->qp_id = qp->id;
2489 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2492 rsp = (struct ocrdma_query_qp_rsp *)cmd;
2493 memcpy(param, &rsp->params, sizeof(struct ocrdma_qp_params));
2499 static int ocrdma_set_av_params(struct ocrdma_qp *qp,
2500 struct ocrdma_modify_qp *cmd,
2501 struct ib_qp_attr *attrs,
2505 struct rdma_ah_attr *ah_attr = &attrs->ah_attr;
2506 union ib_gid sgid, zgid;
2507 struct ib_gid_attr sgid_attr;
2508 u32 vlan_id = 0xFFFF;
2509 u8 mac_addr[6], hdr_type;
2511 struct sockaddr_in _sockaddr_in;
2512 struct sockaddr_in6 _sockaddr_in6;
2513 } sgid_addr, dgid_addr;
2514 struct ocrdma_dev *dev = get_ocrdma_dev(qp->ibqp.device);
2515 const struct ib_global_route *grh;
2517 if ((rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH) == 0)
2519 grh = rdma_ah_read_grh(ah_attr);
2520 if (atomic_cmpxchg(&dev->update_sl, 1, 0))
2521 ocrdma_init_service_level(dev);
2522 cmd->params.tclass_sq_psn |=
2523 (grh->traffic_class << OCRDMA_QP_PARAMS_TCLASS_SHIFT);
2524 cmd->params.rnt_rc_sl_fl |=
2525 (grh->flow_label & OCRDMA_QP_PARAMS_FLOW_LABEL_MASK);
2526 cmd->params.rnt_rc_sl_fl |= (rdma_ah_get_sl(ah_attr) <<
2527 OCRDMA_QP_PARAMS_SL_SHIFT);
2528 cmd->params.hop_lmt_rq_psn |=
2529 (grh->hop_limit << OCRDMA_QP_PARAMS_HOP_LMT_SHIFT);
2530 cmd->flags |= OCRDMA_QP_PARA_FLOW_LBL_VALID;
2533 memcpy(&cmd->params.dgid[0], &grh->dgid.raw[0],
2534 sizeof(cmd->params.dgid));
2536 status = ib_get_cached_gid(&dev->ibdev, 1, grh->sgid_index,
2538 if (!status && sgid_attr.ndev) {
2539 vlan_id = rdma_vlan_dev_vlan_id(sgid_attr.ndev);
2540 memcpy(mac_addr, sgid_attr.ndev->dev_addr, ETH_ALEN);
2541 dev_put(sgid_attr.ndev);
2544 memset(&zgid, 0, sizeof(zgid));
2545 if (!memcmp(&sgid, &zgid, sizeof(zgid)))
2548 qp->sgid_idx = grh->sgid_index;
2549 memcpy(&cmd->params.sgid[0], &sgid.raw[0], sizeof(cmd->params.sgid));
2550 status = ocrdma_resolve_dmac(dev, ah_attr, &mac_addr[0]);
2553 cmd->params.dmac_b0_to_b3 = mac_addr[0] | (mac_addr[1] << 8) |
2554 (mac_addr[2] << 16) | (mac_addr[3] << 24);
2556 hdr_type = ib_gid_to_network_type(sgid_attr.gid_type, &sgid);
2557 if (hdr_type == RDMA_NETWORK_IPV4) {
2558 rdma_gid2ip((struct sockaddr *)&sgid_addr, &sgid);
2559 rdma_gid2ip((struct sockaddr *)&dgid_addr, &grh->dgid);
2560 memcpy(&cmd->params.dgid[0],
2561 &dgid_addr._sockaddr_in.sin_addr.s_addr, 4);
2562 memcpy(&cmd->params.sgid[0],
2563 &sgid_addr._sockaddr_in.sin_addr.s_addr, 4);
2565 /* convert them to LE format. */
2566 ocrdma_cpu_to_le32(&cmd->params.dgid[0], sizeof(cmd->params.dgid));
2567 ocrdma_cpu_to_le32(&cmd->params.sgid[0], sizeof(cmd->params.sgid));
2568 cmd->params.vlan_dmac_b4_to_b5 = mac_addr[4] | (mac_addr[5] << 8);
2570 if (vlan_id == 0xFFFF)
2572 if (vlan_id || dev->pfc_state) {
2574 pr_err("ocrdma%d:Using VLAN with PFC is recommended\n",
2576 pr_err("ocrdma%d:Using VLAN 0 for this connection\n",
2579 cmd->params.vlan_dmac_b4_to_b5 |=
2580 vlan_id << OCRDMA_QP_PARAMS_VLAN_SHIFT;
2581 cmd->flags |= OCRDMA_QP_PARA_VLAN_EN_VALID;
2582 cmd->params.rnt_rc_sl_fl |=
2583 (dev->sl & 0x07) << OCRDMA_QP_PARAMS_SL_SHIFT;
2585 cmd->params.max_sge_recv_flags |= ((hdr_type <<
2586 OCRDMA_QP_PARAMS_FLAGS_L3_TYPE_SHIFT) &
2587 OCRDMA_QP_PARAMS_FLAGS_L3_TYPE_MASK);
2591 static int ocrdma_set_qp_params(struct ocrdma_qp *qp,
2592 struct ocrdma_modify_qp *cmd,
2593 struct ib_qp_attr *attrs, int attr_mask)
2596 struct ocrdma_dev *dev = get_ocrdma_dev(qp->ibqp.device);
2598 if (attr_mask & IB_QP_PKEY_INDEX) {
2599 cmd->params.path_mtu_pkey_indx |= (attrs->pkey_index &
2600 OCRDMA_QP_PARAMS_PKEY_INDEX_MASK);
2601 cmd->flags |= OCRDMA_QP_PARA_PKEY_VALID;
2603 if (attr_mask & IB_QP_QKEY) {
2604 qp->qkey = attrs->qkey;
2605 cmd->params.qkey = attrs->qkey;
2606 cmd->flags |= OCRDMA_QP_PARA_QKEY_VALID;
2608 if (attr_mask & IB_QP_AV) {
2609 status = ocrdma_set_av_params(qp, cmd, attrs, attr_mask);
2612 } else if (qp->qp_type == IB_QPT_GSI || qp->qp_type == IB_QPT_UD) {
2613 /* set the default mac address for UD, GSI QPs */
2614 cmd->params.dmac_b0_to_b3 = dev->nic_info.mac_addr[0] |
2615 (dev->nic_info.mac_addr[1] << 8) |
2616 (dev->nic_info.mac_addr[2] << 16) |
2617 (dev->nic_info.mac_addr[3] << 24);
2618 cmd->params.vlan_dmac_b4_to_b5 = dev->nic_info.mac_addr[4] |
2619 (dev->nic_info.mac_addr[5] << 8);
2621 if ((attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) &&
2622 attrs->en_sqd_async_notify) {
2623 cmd->params.max_sge_recv_flags |=
2624 OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC;
2625 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2627 if (attr_mask & IB_QP_DEST_QPN) {
2628 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->dest_qp_num &
2629 OCRDMA_QP_PARAMS_DEST_QPN_MASK);
2630 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2632 if (attr_mask & IB_QP_PATH_MTU) {
2633 if (attrs->path_mtu < IB_MTU_512 ||
2634 attrs->path_mtu > IB_MTU_4096) {
2635 pr_err("ocrdma%d: IB MTU %d is not supported\n",
2636 dev->id, ib_mtu_enum_to_int(attrs->path_mtu));
2640 cmd->params.path_mtu_pkey_indx |=
2641 (ib_mtu_enum_to_int(attrs->path_mtu) <<
2642 OCRDMA_QP_PARAMS_PATH_MTU_SHIFT) &
2643 OCRDMA_QP_PARAMS_PATH_MTU_MASK;
2644 cmd->flags |= OCRDMA_QP_PARA_PMTU_VALID;
2646 if (attr_mask & IB_QP_TIMEOUT) {
2647 cmd->params.ack_to_rnr_rtc_dest_qpn |= attrs->timeout <<
2648 OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT;
2649 cmd->flags |= OCRDMA_QP_PARA_ACK_TO_VALID;
2651 if (attr_mask & IB_QP_RETRY_CNT) {
2652 cmd->params.rnt_rc_sl_fl |= (attrs->retry_cnt <<
2653 OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT) &
2654 OCRDMA_QP_PARAMS_RETRY_CNT_MASK;
2655 cmd->flags |= OCRDMA_QP_PARA_RETRY_CNT_VALID;
2657 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2658 cmd->params.rnt_rc_sl_fl |= (attrs->min_rnr_timer <<
2659 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT) &
2660 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK;
2661 cmd->flags |= OCRDMA_QP_PARA_RNT_VALID;
2663 if (attr_mask & IB_QP_RNR_RETRY) {
2664 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->rnr_retry <<
2665 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT)
2666 & OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK;
2667 cmd->flags |= OCRDMA_QP_PARA_RRC_VALID;
2669 if (attr_mask & IB_QP_SQ_PSN) {
2670 cmd->params.tclass_sq_psn |= (attrs->sq_psn & 0x00ffffff);
2671 cmd->flags |= OCRDMA_QP_PARA_SQPSN_VALID;
2673 if (attr_mask & IB_QP_RQ_PSN) {
2674 cmd->params.hop_lmt_rq_psn |= (attrs->rq_psn & 0x00ffffff);
2675 cmd->flags |= OCRDMA_QP_PARA_RQPSN_VALID;
2677 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2678 if (attrs->max_rd_atomic > dev->attr.max_ord_per_qp) {
2682 qp->max_ord = attrs->max_rd_atomic;
2683 cmd->flags |= OCRDMA_QP_PARA_MAX_ORD_VALID;
2685 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2686 if (attrs->max_dest_rd_atomic > dev->attr.max_ird_per_qp) {
2690 qp->max_ird = attrs->max_dest_rd_atomic;
2691 cmd->flags |= OCRDMA_QP_PARA_MAX_IRD_VALID;
2693 cmd->params.max_ord_ird = (qp->max_ord <<
2694 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT) |
2695 (qp->max_ird & OCRDMA_QP_PARAMS_MAX_IRD_MASK);
2700 int ocrdma_mbx_modify_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2701 struct ib_qp_attr *attrs, int attr_mask)
2703 int status = -ENOMEM;
2704 struct ocrdma_modify_qp *cmd;
2706 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_QP, sizeof(*cmd));
2710 cmd->params.id = qp->id;
2712 if (attr_mask & IB_QP_STATE) {
2713 cmd->params.max_sge_recv_flags |=
2714 (get_ocrdma_qp_state(attrs->qp_state) <<
2715 OCRDMA_QP_PARAMS_STATE_SHIFT) &
2716 OCRDMA_QP_PARAMS_STATE_MASK;
2717 cmd->flags |= OCRDMA_QP_PARA_QPS_VALID;
2719 cmd->params.max_sge_recv_flags |=
2720 (qp->state << OCRDMA_QP_PARAMS_STATE_SHIFT) &
2721 OCRDMA_QP_PARAMS_STATE_MASK;
2724 status = ocrdma_set_qp_params(qp, cmd, attrs, attr_mask);
2727 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2736 int ocrdma_mbx_destroy_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp)
2738 int status = -ENOMEM;
2739 struct ocrdma_destroy_qp *cmd;
2740 struct pci_dev *pdev = dev->nic_info.pdev;
2742 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_QP, sizeof(*cmd));
2745 cmd->qp_id = qp->id;
2746 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2753 dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2754 if (!qp->srq && qp->rq.va)
2755 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2756 if (qp->dpp_enabled)
2757 qp->pd->num_dpp_qp++;
2761 int ocrdma_mbx_create_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq,
2762 struct ib_srq_init_attr *srq_attr,
2763 struct ocrdma_pd *pd)
2765 int status = -ENOMEM;
2766 int hw_pages, hw_page_size;
2768 struct ocrdma_create_srq_rsp *rsp;
2769 struct ocrdma_create_srq *cmd;
2771 struct pci_dev *pdev = dev->nic_info.pdev;
2772 u32 max_rqe_allocated;
2774 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ, sizeof(*cmd));
2778 cmd->pgsz_pdid = pd->id & OCRDMA_CREATE_SRQ_PD_ID_MASK;
2779 max_rqe_allocated = srq_attr->attr.max_wr + 1;
2780 status = ocrdma_build_q_conf(&max_rqe_allocated,
2782 &hw_pages, &hw_page_size);
2784 pr_err("%s() req. max_wr=0x%x\n", __func__,
2785 srq_attr->attr.max_wr);
2789 len = hw_pages * hw_page_size;
2790 srq->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2795 ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
2797 srq->rq.entry_size = dev->attr.rqe_size;
2800 srq->rq.max_cnt = max_rqe_allocated;
2802 cmd->max_sge_rqe = ilog2(max_rqe_allocated);
2803 cmd->max_sge_rqe |= srq_attr->attr.max_sge <<
2804 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT;
2806 cmd->pgsz_pdid |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
2807 << OCRDMA_CREATE_SRQ_PG_SZ_SHIFT);
2808 cmd->pages_rqe_sz |= (dev->attr.rqe_size
2809 << OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT)
2810 & OCRDMA_CREATE_SRQ_RQE_SIZE_MASK;
2811 cmd->pages_rqe_sz |= hw_pages << OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT;
2813 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2816 rsp = (struct ocrdma_create_srq_rsp *)cmd;
2818 srq->rq.dbid = rsp->id;
2819 max_rqe_allocated = ((rsp->max_sge_rqe_allocated &
2820 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK) >>
2821 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT);
2822 max_rqe_allocated = (1 << max_rqe_allocated);
2823 srq->rq.max_cnt = max_rqe_allocated;
2824 srq->rq.max_wqe_idx = max_rqe_allocated - 1;
2825 srq->rq.max_sges = (rsp->max_sge_rqe_allocated &
2826 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK) >>
2827 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT;
2830 dma_free_coherent(&pdev->dev, srq->rq.len, srq->rq.va, pa);
2836 int ocrdma_mbx_modify_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2838 int status = -ENOMEM;
2839 struct ocrdma_modify_srq *cmd;
2840 struct ocrdma_pd *pd = srq->pd;
2841 struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
2843 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_SRQ, sizeof(*cmd));
2847 cmd->limit_max_rqe |= srq_attr->srq_limit <<
2848 OCRDMA_MODIFY_SRQ_LIMIT_SHIFT;
2849 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2854 int ocrdma_mbx_query_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2856 int status = -ENOMEM;
2857 struct ocrdma_query_srq *cmd;
2858 struct ocrdma_dev *dev = get_ocrdma_dev(srq->ibsrq.device);
2860 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_SRQ, sizeof(*cmd));
2863 cmd->id = srq->rq.dbid;
2864 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2866 struct ocrdma_query_srq_rsp *rsp =
2867 (struct ocrdma_query_srq_rsp *)cmd;
2869 rsp->srq_lmt_max_sge &
2870 OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK;
2872 rsp->max_rqe_pdid >> OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT;
2873 srq_attr->srq_limit = rsp->srq_lmt_max_sge >>
2874 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT;
2880 int ocrdma_mbx_destroy_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq)
2882 int status = -ENOMEM;
2883 struct ocrdma_destroy_srq *cmd;
2884 struct pci_dev *pdev = dev->nic_info.pdev;
2885 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_SRQ, sizeof(*cmd));
2889 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2891 dma_free_coherent(&pdev->dev, srq->rq.len,
2892 srq->rq.va, srq->rq.pa);
2897 static int ocrdma_mbx_get_dcbx_config(struct ocrdma_dev *dev, u32 ptype,
2898 struct ocrdma_dcbx_cfg *dcbxcfg)
2902 struct ocrdma_mqe cmd;
2904 struct ocrdma_get_dcbx_cfg_req *req = NULL;
2905 struct ocrdma_get_dcbx_cfg_rsp *rsp = NULL;
2906 struct pci_dev *pdev = dev->nic_info.pdev;
2907 struct ocrdma_mqe_sge *mqe_sge = cmd.u.nonemb_req.sge;
2909 memset(&cmd, 0, sizeof(struct ocrdma_mqe));
2910 cmd.hdr.pyld_len = max_t (u32, sizeof(struct ocrdma_get_dcbx_cfg_rsp),
2911 sizeof(struct ocrdma_get_dcbx_cfg_req));
2912 req = dma_alloc_coherent(&pdev->dev, cmd.hdr.pyld_len, &pa, GFP_KERNEL);
2918 cmd.hdr.spcl_sge_cnt_emb |= (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
2919 OCRDMA_MQE_HDR_SGE_CNT_MASK;
2920 mqe_sge->pa_lo = (u32) (pa & 0xFFFFFFFFUL);
2921 mqe_sge->pa_hi = (u32) upper_32_bits(pa);
2922 mqe_sge->len = cmd.hdr.pyld_len;
2924 memset(req, 0, sizeof(struct ocrdma_get_dcbx_cfg_req));
2925 ocrdma_init_mch(&req->hdr, OCRDMA_CMD_GET_DCBX_CONFIG,
2926 OCRDMA_SUBSYS_DCBX, cmd.hdr.pyld_len);
2927 req->param_type = ptype;
2929 status = ocrdma_mbx_cmd(dev, &cmd);
2933 rsp = (struct ocrdma_get_dcbx_cfg_rsp *)req;
2934 ocrdma_le32_to_cpu(rsp, sizeof(struct ocrdma_get_dcbx_cfg_rsp));
2935 memcpy(dcbxcfg, &rsp->cfg, sizeof(struct ocrdma_dcbx_cfg));
2938 dma_free_coherent(&pdev->dev, cmd.hdr.pyld_len, req, pa);
2943 #define OCRDMA_MAX_SERVICE_LEVEL_INDEX 0x08
2944 #define OCRDMA_DEFAULT_SERVICE_LEVEL 0x05
2946 static int ocrdma_parse_dcbxcfg_rsp(struct ocrdma_dev *dev, int ptype,
2947 struct ocrdma_dcbx_cfg *dcbxcfg,
2950 int status = -EINVAL, indx, slindx;
2952 struct ocrdma_app_parameter *app_param;
2953 u8 valid, proto_sel;
2954 u8 app_prio, pfc_prio;
2957 if (!(dcbxcfg->tcv_aev_opv_st & OCRDMA_DCBX_STATE_MASK)) {
2958 pr_info("%s ocrdma%d DCBX is disabled\n",
2959 dev_name(&dev->nic_info.pdev->dev), dev->id);
2963 if (!ocrdma_is_enabled_and_synced(dcbxcfg->pfc_state)) {
2964 pr_info("%s ocrdma%d priority flow control(%s) is %s%s\n",
2965 dev_name(&dev->nic_info.pdev->dev), dev->id,
2966 (ptype > 0 ? "operational" : "admin"),
2967 (dcbxcfg->pfc_state & OCRDMA_STATE_FLAG_ENABLED) ?
2968 "enabled" : "disabled",
2969 (dcbxcfg->pfc_state & OCRDMA_STATE_FLAG_SYNC) ?
2970 "" : ", not sync'ed");
2973 pr_info("%s ocrdma%d priority flow control is enabled and sync'ed\n",
2974 dev_name(&dev->nic_info.pdev->dev), dev->id);
2977 ventry_cnt = (dcbxcfg->tcv_aev_opv_st >>
2978 OCRDMA_DCBX_APP_ENTRY_SHIFT)
2979 & OCRDMA_DCBX_STATE_MASK;
2981 for (indx = 0; indx < ventry_cnt; indx++) {
2982 app_param = &dcbxcfg->app_param[indx];
2983 valid = (app_param->valid_proto_app >>
2984 OCRDMA_APP_PARAM_VALID_SHIFT)
2985 & OCRDMA_APP_PARAM_VALID_MASK;
2986 proto_sel = (app_param->valid_proto_app
2987 >> OCRDMA_APP_PARAM_PROTO_SEL_SHIFT)
2988 & OCRDMA_APP_PARAM_PROTO_SEL_MASK;
2989 proto = app_param->valid_proto_app &
2990 OCRDMA_APP_PARAM_APP_PROTO_MASK;
2993 valid && proto == ETH_P_IBOE &&
2994 proto_sel == OCRDMA_PROTO_SELECT_L2) {
2995 for (slindx = 0; slindx <
2996 OCRDMA_MAX_SERVICE_LEVEL_INDEX; slindx++) {
2997 app_prio = ocrdma_get_app_prio(
2998 (u8 *)app_param->app_prio,
3000 pfc_prio = ocrdma_get_pfc_prio(
3001 (u8 *)dcbxcfg->pfc_prio,
3004 if (app_prio && pfc_prio) {
3010 if (slindx == OCRDMA_MAX_SERVICE_LEVEL_INDEX) {
3011 pr_info("%s ocrdma%d application priority not set for 0x%x protocol\n",
3012 dev_name(&dev->nic_info.pdev->dev),
3022 void ocrdma_init_service_level(struct ocrdma_dev *dev)
3024 int status = 0, indx;
3025 struct ocrdma_dcbx_cfg dcbxcfg;
3026 u8 srvc_lvl = OCRDMA_DEFAULT_SERVICE_LEVEL;
3027 int ptype = OCRDMA_PARAMETER_TYPE_OPER;
3029 for (indx = 0; indx < 2; indx++) {
3030 status = ocrdma_mbx_get_dcbx_config(dev, ptype, &dcbxcfg);
3032 pr_err("%s(): status=%d\n", __func__, status);
3033 ptype = OCRDMA_PARAMETER_TYPE_ADMIN;
3037 status = ocrdma_parse_dcbxcfg_rsp(dev, ptype,
3038 &dcbxcfg, &srvc_lvl);
3040 ptype = OCRDMA_PARAMETER_TYPE_ADMIN;
3048 pr_info("%s ocrdma%d service level default\n",
3049 dev_name(&dev->nic_info.pdev->dev), dev->id);
3051 pr_info("%s ocrdma%d service level %d\n",
3052 dev_name(&dev->nic_info.pdev->dev), dev->id,
3055 dev->pfc_state = ocrdma_is_enabled_and_synced(dcbxcfg.pfc_state);
3059 int ocrdma_alloc_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
3062 int status = -EINVAL;
3063 struct ocrdma_av *av;
3064 unsigned long flags;
3066 av = dev->av_tbl.va;
3067 spin_lock_irqsave(&dev->av_tbl.lock, flags);
3068 for (i = 0; i < dev->av_tbl.num_ah; i++) {
3069 if (av->valid == 0) {
3070 av->valid = OCRDMA_AV_VALID;
3078 if (i == dev->av_tbl.num_ah)
3080 spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
3084 int ocrdma_free_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
3086 unsigned long flags;
3087 spin_lock_irqsave(&dev->av_tbl.lock, flags);
3089 spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
3093 static int ocrdma_create_eqs(struct ocrdma_dev *dev)
3095 int num_eq, i, status = 0;
3097 unsigned long flags = 0;
3099 num_eq = dev->nic_info.msix.num_vectors -
3100 dev->nic_info.msix.start_vector;
3101 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX) {
3103 flags = IRQF_SHARED;
3105 num_eq = min_t(u32, num_eq, num_online_cpus());
3111 dev->eq_tbl = kzalloc(sizeof(struct ocrdma_eq) * num_eq, GFP_KERNEL);
3115 for (i = 0; i < num_eq; i++) {
3116 status = ocrdma_create_eq(dev, &dev->eq_tbl[i],
3122 sprintf(dev->eq_tbl[i].irq_name, "ocrdma%d-%d",
3124 irq = ocrdma_get_irq(dev, &dev->eq_tbl[i]);
3125 status = request_irq(irq, ocrdma_irq_handler, flags,
3126 dev->eq_tbl[i].irq_name,
3132 /* one eq is sufficient for data path to work */
3135 ocrdma_destroy_eqs(dev);
3139 static int ocrdma_mbx_modify_eqd(struct ocrdma_dev *dev, struct ocrdma_eq *eq,
3142 int i, status = -ENOMEM;
3143 struct ocrdma_modify_eqd_req *cmd;
3145 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_EQ_DELAY, sizeof(*cmd));
3149 ocrdma_init_mch(&cmd->cmd.req, OCRDMA_CMD_MODIFY_EQ_DELAY,
3150 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
3152 cmd->cmd.num_eq = num;
3153 for (i = 0; i < num; i++) {
3154 cmd->cmd.set_eqd[i].eq_id = eq[i].q.id;
3155 cmd->cmd.set_eqd[i].phase = 0;
3156 cmd->cmd.set_eqd[i].delay_multiplier =
3157 (eq[i].aic_obj.prev_eqd * 65)/100;
3159 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
3167 static int ocrdma_modify_eqd(struct ocrdma_dev *dev, struct ocrdma_eq *eq,
3173 num_eqs = min(num, 8);
3174 ocrdma_mbx_modify_eqd(dev, &eq[i], num_eqs);
3179 ocrdma_mbx_modify_eqd(dev, eq, num);
3184 void ocrdma_eqd_set_task(struct work_struct *work)
3186 struct ocrdma_dev *dev =
3187 container_of(work, struct ocrdma_dev, eqd_work.work);
3188 struct ocrdma_eq *eq = 0;
3189 int i, num = 0, status = -EINVAL;
3192 for (i = 0; i < dev->eq_cnt; i++) {
3193 eq = &dev->eq_tbl[i];
3194 if (eq->aic_obj.eq_intr_cnt > eq->aic_obj.prev_eq_intr_cnt) {
3195 eq_intr = eq->aic_obj.eq_intr_cnt -
3196 eq->aic_obj.prev_eq_intr_cnt;
3197 if ((eq_intr > EQ_INTR_PER_SEC_THRSH_HI) &&
3198 (eq->aic_obj.prev_eqd == EQ_AIC_MIN_EQD)) {
3199 eq->aic_obj.prev_eqd = EQ_AIC_MAX_EQD;
3201 } else if ((eq_intr < EQ_INTR_PER_SEC_THRSH_LOW) &&
3202 (eq->aic_obj.prev_eqd == EQ_AIC_MAX_EQD)) {
3203 eq->aic_obj.prev_eqd = EQ_AIC_MIN_EQD;
3207 eq->aic_obj.prev_eq_intr_cnt = eq->aic_obj.eq_intr_cnt;
3211 status = ocrdma_modify_eqd(dev, &dev->eq_tbl[0], num);
3212 schedule_delayed_work(&dev->eqd_work, msecs_to_jiffies(1000));
3215 int ocrdma_init_hw(struct ocrdma_dev *dev)
3219 /* create the eqs */
3220 status = ocrdma_create_eqs(dev);
3223 status = ocrdma_create_mq(dev);
3226 status = ocrdma_mbx_query_fw_config(dev);
3229 status = ocrdma_mbx_query_dev(dev);
3232 status = ocrdma_mbx_query_fw_ver(dev);
3235 status = ocrdma_mbx_create_ah_tbl(dev);
3238 status = ocrdma_mbx_get_phy_info(dev);
3240 goto info_attrb_err;
3241 status = ocrdma_mbx_get_ctrl_attribs(dev);
3243 goto info_attrb_err;
3248 ocrdma_mbx_delete_ah_tbl(dev);
3250 ocrdma_destroy_mq(dev);
3252 ocrdma_destroy_eqs(dev);
3254 pr_err("%s() status=%d\n", __func__, status);
3258 void ocrdma_cleanup_hw(struct ocrdma_dev *dev)
3260 ocrdma_free_pd_pool(dev);
3261 ocrdma_mbx_delete_ah_tbl(dev);
3263 /* cleanup the control path */
3264 ocrdma_destroy_mq(dev);
3266 /* cleanup the eqs */
3267 ocrdma_destroy_eqs(dev);