drivers/input/touchscreen/hideep.c

   1 /*
   2  * Copyright (C) 2012-2017 Hideep, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License version 2
   6  * as published by the Free Software Foudation.
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/of.h>
  11 #include <linux/firmware.h>
  12 #include <linux/delay.h>
  13 #include <linux/gpio/consumer.h>
  14 #include <linux/i2c.h>
  15 #include <linux/acpi.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/regmap.h>
  18 #include <linux/sysfs.h>
  19 #include <linux/input.h>
  20 #include <linux/input/mt.h>
  21 #include <linux/input/touchscreen.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <asm/unaligned.h>
  24
  25 #define HIDEEP_TS_NAME                  "HiDeep Touchscreen"
  26 #define HIDEEP_I2C_NAME                 "hideep_ts"
  27
  28 #define HIDEEP_MT_MAX                   10
  29 #define HIDEEP_KEY_MAX                  3
  30
  31 /* count(2) + touch data(100) + key data(6) */
  32 #define HIDEEP_MAX_EVENT                108UL
  33
  34 #define HIDEEP_TOUCH_EVENT_INDEX        2
  35 #define HIDEEP_KEY_EVENT_INDEX          102
  36
  37 /* Touch & key event */
  38 #define HIDEEP_EVENT_ADDR               0x240
  39
  40 /* command list */
  41 #define HIDEEP_RESET_CMD                0x9800
  42
  43 /* event bit */
  44 #define HIDEEP_MT_RELEASED              BIT(4)
  45 #define HIDEEP_KEY_PRESSED              BIT(7)
  46 #define HIDEEP_KEY_FIRST_PRESSED        BIT(8)
  47 #define HIDEEP_KEY_PRESSED_MASK         (HIDEEP_KEY_PRESSED | \
  48                                          HIDEEP_KEY_FIRST_PRESSED)
  49
  50 #define HIDEEP_KEY_IDX_MASK             0x0f
  51
  52 /* For NVM */
  53 #define HIDEEP_YRAM_BASE                0x40000000
  54 #define HIDEEP_PERIPHERAL_BASE          0x50000000
  55 #define HIDEEP_ESI_BASE                 (HIDEEP_PERIPHERAL_BASE + 0x00000000)
  56 #define HIDEEP_FLASH_BASE               (HIDEEP_PERIPHERAL_BASE + 0x01000000)
  57 #define HIDEEP_SYSCON_BASE              (HIDEEP_PERIPHERAL_BASE + 0x02000000)
  58
  59 #define HIDEEP_SYSCON_MOD_CON           (HIDEEP_SYSCON_BASE + 0x0000)
  60 #define HIDEEP_SYSCON_SPC_CON           (HIDEEP_SYSCON_BASE + 0x0004)
  61 #define HIDEEP_SYSCON_CLK_CON           (HIDEEP_SYSCON_BASE + 0x0008)
  62 #define HIDEEP_SYSCON_CLK_ENA           (HIDEEP_SYSCON_BASE + 0x000C)
  63 #define HIDEEP_SYSCON_RST_CON           (HIDEEP_SYSCON_BASE + 0x0010)
  64 #define HIDEEP_SYSCON_WDT_CON           (HIDEEP_SYSCON_BASE + 0x0014)
  65 #define HIDEEP_SYSCON_WDT_CNT           (HIDEEP_SYSCON_BASE + 0x0018)
  66 #define HIDEEP_SYSCON_PWR_CON           (HIDEEP_SYSCON_BASE + 0x0020)
  67 #define HIDEEP_SYSCON_PGM_ID            (HIDEEP_SYSCON_BASE + 0x00F4)
  68
  69 #define HIDEEP_FLASH_CON                (HIDEEP_FLASH_BASE + 0x0000)
  70 #define HIDEEP_FLASH_STA                (HIDEEP_FLASH_BASE + 0x0004)
  71 #define HIDEEP_FLASH_CFG                (HIDEEP_FLASH_BASE + 0x0008)
  72 #define HIDEEP_FLASH_TIM                (HIDEEP_FLASH_BASE + 0x000C)
  73 #define HIDEEP_FLASH_CACHE_CFG          (HIDEEP_FLASH_BASE + 0x0010)
  74 #define HIDEEP_FLASH_PIO_SIG            (HIDEEP_FLASH_BASE + 0x400000)
  75
  76 #define HIDEEP_ESI_TX_INVALID           (HIDEEP_ESI_BASE + 0x0008)
  77
  78 #define HIDEEP_PERASE                   0x00040000
  79 #define HIDEEP_WRONLY                   0x00100000
  80
  81 #define HIDEEP_NVM_MASK_OFS             0x0000000C
  82 #define HIDEEP_NVM_DEFAULT_PAGE         0
  83 #define HIDEEP_NVM_SFR_WPAGE            1
  84 #define HIDEEP_NVM_SFR_RPAGE            2
  85
  86 #define HIDEEP_PIO_SIG                  0x00400000
  87 #define HIDEEP_PROT_MODE                0x03400000
  88
  89 #define HIDEEP_NVM_PAGE_SIZE            128
  90
  91 #define HIDEEP_DWZ_INFO                 0x000002C0
  92
  93 struct hideep_event {
  94         __le16 x;
  95         __le16 y;
  96         __le16 z;
  97         u8 w;
  98         u8 flag;
  99         u8 type;
 100         u8 index;
 101 };
 102
 103 struct dwz_info {
 104         __be32 code_start;
 105         u8 code_crc[12];
 106
 107         __be32 c_code_start;
 108         __be16 gen_ver;
 109         __be16 c_code_len;
 110
 111         __be32 vr_start;
 112         __be16 rsv0;
 113         __be16 vr_len;
 114
 115         __be32 ft_start;
 116         __be16 vr_version;
 117         __be16 ft_len;
 118
 119         __be16 core_ver;
 120         __be16 boot_ver;
 121
 122         __be16 release_ver;
 123         __be16 custom_ver;
 124
 125         u8 factory_id;
 126         u8 panel_type;
 127         u8 model_name[6];
 128
 129         __be16 extra_option;
 130         __be16 product_code;
 131
 132         __be16 vendor_id;
 133         __be16 product_id;
 134 };
 135
 136 struct pgm_packet {
 137         struct {
 138                 u8 unused[3];
 139                 u8 len;
 140                 __be32 addr;
 141         } header;
 142         __be32 payload[HIDEEP_NVM_PAGE_SIZE / sizeof(__be32)];
 143 };
 144
 145 #define HIDEEP_XFER_BUF_SIZE    sizeof(struct pgm_packet)
 146
 147 struct hideep_ts {
 148         struct i2c_client *client;
 149         struct input_dev *input_dev;
 150         struct regmap *reg;
 151
 152         struct touchscreen_properties prop;
 153
 154         struct gpio_desc *reset_gpio;
 155
 156         struct regulator *vcc_vdd;
 157         struct regulator *vcc_vid;
 158
 159         struct mutex dev_mutex;
 160
 161         u32 tch_count;
 162         u32 lpm_count;
 163
 164         /*
 165          * Data buffer to read packet from the device (contacts and key
 166          * states). We align it on double-word boundary to keep word-sized
 167          * fields in contact data and double-word-sized fields in program
 168          * packet aligned.
 169          */
 170         u8 xfer_buf[HIDEEP_XFER_BUF_SIZE] __aligned(4);
 171
 172         int key_num;
 173         u32 key_codes[HIDEEP_KEY_MAX];
 174
 175         struct dwz_info dwz_info;
 176
 177         unsigned int fw_size;
 178         u32 nvm_mask;
 179 };
 180
 181 static int hideep_pgm_w_mem(struct hideep_ts *ts, u32 addr,
 182                             const __be32 *data, size_t count)
 183 {
 184         struct pgm_packet *packet = (void *)ts->xfer_buf;
 185         size_t len = count * sizeof(*data);
 186         struct i2c_msg msg = {
 187                 .addr   = ts->client->addr,
 188                 .len    = len + sizeof(packet->header.len) +
 189                                 sizeof(packet->header.addr),
 190                 .buf    = &packet->header.len,
 191         };
 192         int ret;
 193
 194         if (len > HIDEEP_NVM_PAGE_SIZE)
 195                 return -EINVAL;
 196
 197         packet->header.len = 0x80 | (count - 1);
 198         packet->header.addr = cpu_to_be32(addr);
 199         memcpy(packet->payload, data, len);
 200
 201         ret = i2c_transfer(ts->client->adapter, &msg, 1);
 202         if (ret != 1)
 203                 return ret < 0 ? ret : -EIO;
 204
 205         return 0;
 206 }
 207
 208 static int hideep_pgm_r_mem(struct hideep_ts *ts, u32 addr,
 209                             __be32 *data, size_t count)
 210 {
 211         struct pgm_packet *packet = (void *)ts->xfer_buf;
 212         size_t len = count * sizeof(*data);
 213         struct i2c_msg msg[] = {
 214                 {
 215                         .addr   = ts->client->addr,
 216                         .len    = sizeof(packet->header.len) +
 217                                         sizeof(packet->header.addr),
 218                         .buf    = &packet->header.len,
 219                 },
 220                 {
 221                         .addr   = ts->client->addr,
 222                         .flags  = I2C_M_RD,
 223                         .len    = len,
 224                         .buf    = (u8 *)data,
 225                 },
 226         };
 227         int ret;
 228
 229         if (len > HIDEEP_NVM_PAGE_SIZE)
 230                 return -EINVAL;
 231
 232         packet->header.len = count - 1;
 233         packet->header.addr = cpu_to_be32(addr);
 234
 235         ret = i2c_transfer(ts->client->adapter, msg, ARRAY_SIZE(msg));
 236         if (ret != ARRAY_SIZE(msg))
 237                 return ret < 0 ? ret : -EIO;
 238
 239         return 0;
 240 }
 241
 242 static int hideep_pgm_r_reg(struct hideep_ts *ts, u32 addr, u32 *val)
 243 {
 244         __be32 data;
 245         int error;
 246
 247         error = hideep_pgm_r_mem(ts, addr, &data, 1);
 248         if (error) {
 249                 dev_err(&ts->client->dev,
 250                         "read of register %#08x failed: %d\n",
 251                         addr, error);
 252                 return error;
 253         }
 254
 255         *val = be32_to_cpu(data);
 256         return 0;
 257 }
 258
 259 static int hideep_pgm_w_reg(struct hideep_ts *ts, u32 addr, u32 val)
 260 {
 261         __be32 data = cpu_to_be32(val);
 262         int error;
 263
 264         error = hideep_pgm_w_mem(ts, addr, &data, 1);
 265         if (error) {
 266                 dev_err(&ts->client->dev,
 267                         "write to register %#08x (%#08x) failed: %d\n",
 268                         addr, val, error);
 269                 return error;
 270         }
 271
 272         return 0;
 273 }
 274
 275 #define SW_RESET_IN_PGM(clk)                                    \
 276 {                                                               \
 277         hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CNT, (clk));     \
 278         hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CON, 0x03);      \
 279         hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CON, 0x01);      \
 280 }
 281
 282 #define SET_FLASH_PIO(ce)                                       \
 283         hideep_pgm_w_reg(ts, HIDEEP_FLASH_CON,                  \
 284                          0x01 | ((ce) << 1))
 285
 286 #define SET_PIO_SIG(x, y)                                       \
 287         hideep_pgm_w_reg(ts, HIDEEP_FLASH_PIO_SIG + (x), (y))
 288
 289 #define SET_FLASH_HWCONTROL()                                   \
 290         hideep_pgm_w_reg(ts, HIDEEP_FLASH_CON, 0x00)
 291
 292 #define NVM_W_SFR(x, y)                                         \
 293 {                                                               \
 294         SET_FLASH_PIO(1);                                       \
 295         SET_PIO_SIG(x, y);                                      \
 296         SET_FLASH_PIO(0);                                       \
 297 }
 298
 299 static void hideep_pgm_set(struct hideep_ts *ts)
 300 {
 301         hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CON, 0x00);
 302         hideep_pgm_w_reg(ts, HIDEEP_SYSCON_SPC_CON, 0x00);
 303         hideep_pgm_w_reg(ts, HIDEEP_SYSCON_CLK_ENA, 0xFF);
 304         hideep_pgm_w_reg(ts, HIDEEP_SYSCON_CLK_CON, 0x01);
 305         hideep_pgm_w_reg(ts, HIDEEP_SYSCON_PWR_CON, 0x01);
 306         hideep_pgm_w_reg(ts, HIDEEP_FLASH_TIM, 0x03);
 307         hideep_pgm_w_reg(ts, HIDEEP_FLASH_CACHE_CFG, 0x00);
 308 }
 309
 310 static int hideep_pgm_get_pattern(struct hideep_ts *ts, u32 *pattern)
 311 {
 312         u16 p1 = 0xAF39;
 313         u16 p2 = 0xDF9D;
 314         int error;
 315
 316         error = regmap_bulk_write(ts->reg, p1, &p2, 1);
 317         if (error) {
 318                 dev_err(&ts->client->dev,
 319                         "%s: regmap_bulk_write() failed with %d\n",
 320                         __func__, error);
 321                 return error;
 322         }
 323
 324         usleep_range(1000, 1100);
 325
 326         /* flush invalid Tx load register */
 327         error = hideep_pgm_w_reg(ts, HIDEEP_ESI_TX_INVALID, 0x01);
 328         if (error)
 329                 return error;
 330
 331         error = hideep_pgm_r_reg(ts, HIDEEP_SYSCON_PGM_ID, pattern);
 332         if (error)
 333                 return error;
 334
 335         return 0;
 336 }
 337
 338 static int hideep_enter_pgm(struct hideep_ts *ts)
 339 {
 340         int retry_count = 10;
 341         u32 pattern;
 342         int error;
 343
 344         while (retry_count--) {
 345                 error = hideep_pgm_get_pattern(ts, &pattern);
 346                 if (error) {
 347                         dev_err(&ts->client->dev,
 348                                 "hideep_pgm_get_pattern failed: %d\n", error);
 349                 } else if (pattern != 0x39AF9DDF) {
 350                         dev_err(&ts->client->dev, "%s: bad pattern: %#08x\n",
 351                                 __func__, pattern);
 352                 } else {
 353                         dev_dbg(&ts->client->dev, "found magic code");
 354
 355                         hideep_pgm_set(ts);
 356                         usleep_range(1000, 1100);
 357
 358                         return 0;
 359                 }
 360         }
 361
 362         dev_err(&ts->client->dev, "failed to  enter pgm mode\n");
 363         SW_RESET_IN_PGM(1000);
 364         return -EIO;
 365 }
 366
 367 static int hideep_nvm_unlock(struct hideep_ts *ts)
 368 {
 369         u32 unmask_code;
 370         int error;
 371
 372         hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_SFR_RPAGE);
 373         error = hideep_pgm_r_reg(ts, 0x0000000C, &unmask_code);
 374         hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_DEFAULT_PAGE);
 375         if (error)
 376                 return error;
 377
 378         /* make it unprotected code */
 379         unmask_code &= ~HIDEEP_PROT_MODE;
 380
 381         /* compare unmask code */
 382         if (unmask_code != ts->nvm_mask)
 383                 dev_warn(&ts->client->dev,
 384                          "read mask code different %#08x vs %#08x",
 385                          unmask_code, ts->nvm_mask);
 386
 387         hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_SFR_WPAGE);
 388         SET_FLASH_PIO(0);
 389
 390         NVM_W_SFR(HIDEEP_NVM_MASK_OFS, ts->nvm_mask);
 391         SET_FLASH_HWCONTROL();
 392         hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_DEFAULT_PAGE);
 393
 394         return 0;
 395 }
 396
 397 static int hideep_check_status(struct hideep_ts *ts)
 398 {
 399         int time_out = 100;
 400         int status;
 401         int error;
 402
 403         while (time_out--) {
 404                 error = hideep_pgm_r_reg(ts, HIDEEP_FLASH_STA, &status);
 405                 if (!error && status)
 406                         return 0;
 407
 408                 usleep_range(1000, 1100);
 409         }
 410
 411         return -ETIMEDOUT;
 412 }
 413
 414 static int hideep_program_page(struct hideep_ts *ts, u32 addr,
 415                                const __be32 *ucode, size_t xfer_count)
 416 {
 417         u32 val;
 418         int error;
 419
 420         error = hideep_check_status(ts);
 421         if (error)
 422                 return -EBUSY;
 423
 424         addr &= ~(HIDEEP_NVM_PAGE_SIZE - 1);
 425
 426         SET_FLASH_PIO(0);
 427         SET_FLASH_PIO(1);
 428
 429         /* erase page */
 430         SET_PIO_SIG(HIDEEP_PERASE | addr, 0xFFFFFFFF);
 431
 432         SET_FLASH_PIO(0);
 433
 434         error = hideep_check_status(ts);
 435         if (error)
 436                 return -EBUSY;
 437
 438         /* write page */
 439         SET_FLASH_PIO(1);
 440
 441         val = be32_to_cpu(ucode[0]);
 442         SET_PIO_SIG(HIDEEP_WRONLY | addr, val);
 443
 444         hideep_pgm_w_mem(ts, HIDEEP_FLASH_PIO_SIG | HIDEEP_WRONLY,
 445                          ucode, xfer_count);
 446
 447         val = be32_to_cpu(ucode[xfer_count - 1]);
 448         SET_PIO_SIG(124, val);
 449
 450         SET_FLASH_PIO(0);
 451
 452         usleep_range(1000, 1100);
 453
 454         error = hideep_check_status(ts);
 455         if (error)
 456                 return -EBUSY;
 457
 458         SET_FLASH_HWCONTROL();
 459
 460         return 0;
 461 }
 462
 463 static int hideep_program_nvm(struct hideep_ts *ts,
 464                               const __be32 *ucode, size_t ucode_len)
 465 {
 466         struct pgm_packet *packet_r = (void *)ts->xfer_buf;
 467         __be32 *current_ucode = packet_r->payload;
 468         size_t xfer_len;
 469         size_t xfer_count;
 470         u32 addr = 0;
 471         int error;
 472
 473        error = hideep_nvm_unlock(ts);
 474        if (error)
 475                return error;
 476
 477         while (ucode_len > 0) {
 478                 xfer_len = min_t(size_t, ucode_len, HIDEEP_NVM_PAGE_SIZE);
 479                 xfer_count = xfer_len / sizeof(*ucode);
 480
 481                 error = hideep_pgm_r_mem(ts, 0x00000000 + addr,
 482                                          current_ucode, xfer_count);
 483                 if (error) {
 484                         dev_err(&ts->client->dev,
 485                                 "%s: failed to read page at offset %#08x: %d\n",
 486                                 __func__, addr, error);
 487                         return error;
 488                 }
 489
 490                 /* See if the page needs updating */
 491                 if (memcmp(ucode, current_ucode, xfer_len)) {
 492                         error = hideep_program_page(ts, addr,
 493                                                     ucode, xfer_count);
 494                         if (error) {
 495                                 dev_err(&ts->client->dev,
 496                                         "%s: iwrite failure @%#08x: %d\n",
 497                                         __func__, addr, error);
 498                                 return error;
 499                         }
 500
 501                         usleep_range(1000, 1100);
 502                 }
 503
 504                 ucode += xfer_count;
 505                 addr += xfer_len;
 506                 ucode_len -= xfer_len;
 507         }
 508
 509         return 0;
 510 }
 511
 512 static int hideep_verify_nvm(struct hideep_ts *ts,
 513                              const __be32 *ucode, size_t ucode_len)
 514 {
 515         struct pgm_packet *packet_r = (void *)ts->xfer_buf;
 516         __be32 *current_ucode = packet_r->payload;
 517         size_t xfer_len;
 518         size_t xfer_count;
 519         u32 addr = 0;
 520         int i;
 521         int error;
 522
 523         while (ucode_len > 0) {
 524                 xfer_len = min_t(size_t, ucode_len, HIDEEP_NVM_PAGE_SIZE);
 525                 xfer_count = xfer_len / sizeof(*ucode);
 526
 527                 error = hideep_pgm_r_mem(ts, 0x00000000 + addr,
 528                                          current_ucode, xfer_count);
 529                 if (error) {
 530                         dev_err(&ts->client->dev,
 531                                 "%s: failed to read page at offset %#08x: %d\n",
 532                                 __func__, addr, error);
 533                         return error;
 534                 }
 535
 536                 if (memcmp(ucode, current_ucode, xfer_len)) {
 537                         const u8 *ucode_bytes = (const u8 *)ucode;
 538                         const u8 *current_bytes = (const u8 *)current_ucode;
 539
 540                         for (i = 0; i < xfer_len; i++)
 541                                 if (ucode_bytes[i] != current_bytes[i])
 542                                         dev_err(&ts->client->dev,
 543                                                 "%s: mismatch @%#08x: (%#02x vs %#02x)\n",
 544                                                 __func__, addr + i,
 545                                                 ucode_bytes[i],
 546                                                 current_bytes[i]);
 547
 548                         return -EIO;
 549                 }
 550
 551                 ucode += xfer_count;
 552                 addr += xfer_len;
 553                 ucode_len -= xfer_len;
 554         }
 555
 556         return 0;
 557 }
 558
 559 static int hideep_load_dwz(struct hideep_ts *ts)
 560 {
 561         u16 product_code;
 562         int error;
 563
 564         error = hideep_enter_pgm(ts);
 565         if (error)
 566                 return error;
 567
 568         msleep(50);
 569
 570         error = hideep_pgm_r_mem(ts, HIDEEP_DWZ_INFO,
 571                                  (void *)&ts->dwz_info,
 572                                  sizeof(ts->dwz_info) / sizeof(__be32));
 573
 574         SW_RESET_IN_PGM(10);
 575         msleep(50);
 576
 577         if (error) {
 578                 dev_err(&ts->client->dev,
 579                         "failed to fetch DWZ data: %d\n", error);
 580                 return error;
 581         }
 582
 583         product_code = be16_to_cpu(ts->dwz_info.product_code);
 584
 585         switch (product_code & 0xF0) {
 586         case 0x40:
 587                 dev_dbg(&ts->client->dev, "used crimson IC");
 588                 ts->fw_size = 1024 * 48;
 589                 ts->nvm_mask = 0x00310000;
 590                 break;
 591         case 0x60:
 592                 dev_dbg(&ts->client->dev, "used lime IC");
 593                 ts->fw_size = 1024 * 64;
 594                 ts->nvm_mask = 0x0030027B;
 595                 break;
 596         default:
 597                 dev_err(&ts->client->dev, "product code is wrong: %#04x",
 598                         product_code);
 599                 return -EINVAL;
 600         }
 601
 602         dev_dbg(&ts->client->dev, "firmware release version: %#04x",
 603                 be16_to_cpu(ts->dwz_info.release_ver));
 604
 605         return 0;
 606 }
 607
 608 static int hideep_flash_firmware(struct hideep_ts *ts,
 609                                  const __be32 *ucode, size_t ucode_len)
 610 {
 611         int retry_cnt = 3;
 612         int error;
 613
 614         while (retry_cnt--) {
 615                 error = hideep_program_nvm(ts, ucode, ucode_len);
 616                 if (!error) {
 617                         error = hideep_verify_nvm(ts, ucode, ucode_len);
 618                         if (!error)
 619                                 return 0;
 620                 }
 621         }
 622
 623         return error;
 624 }
 625
 626 static int hideep_update_firmware(struct hideep_ts *ts,
 627                                   const __be32 *ucode, size_t ucode_len)
 628 {
 629         int error, error2;
 630
 631         dev_dbg(&ts->client->dev, "starting firmware update");
 632
 633         /* enter program mode */
 634         error = hideep_enter_pgm(ts);
 635         if (error)
 636                 return error;
 637
 638         error = hideep_flash_firmware(ts, ucode, ucode_len);
 639         if (error)
 640                 dev_err(&ts->client->dev,
 641                         "firmware update failed: %d\n", error);
 642         else
 643                 dev_dbg(&ts->client->dev, "firmware updated successfully\n");
 644
 645         SW_RESET_IN_PGM(1000);
 646
 647         error2 = hideep_load_dwz(ts);
 648         if (error2)
 649                 dev_err(&ts->client->dev,
 650                         "failed to load dwz after firmware update: %d\n",
 651                         error2);
 652
 653         return error ?: error2;
 654 }
 655
 656 static int hideep_power_on(struct hideep_ts *ts)
 657 {
 658         int error = 0;
 659
 660         error = regulator_enable(ts->vcc_vdd);
 661         if (error)
 662                 dev_err(&ts->client->dev,
 663                         "failed to enable 'vdd' regulator: %d", error);
 664
 665         usleep_range(999, 1000);
 666
 667         error = regulator_enable(ts->vcc_vid);
 668         if (error)
 669                 dev_err(&ts->client->dev,
 670                         "failed to enable 'vcc_vid' regulator: %d",
 671                         error);
 672
 673         msleep(30);
 674
 675         if (ts->reset_gpio) {
 676                 gpiod_set_value_cansleep(ts->reset_gpio, 0);
 677         } else {
 678                 error = regmap_write(ts->reg, HIDEEP_RESET_CMD, 0x01);
 679                 if (error)
 680                         dev_err(&ts->client->dev,
 681                                 "failed to send 'reset' command: %d\n", error);
 682         }
 683
 684         msleep(50);
 685
 686         return error;
 687 }
 688
 689 static void hideep_power_off(void *data)
 690 {
 691         struct hideep_ts *ts = data;
 692
 693         if (ts->reset_gpio)
 694                 gpiod_set_value(ts->reset_gpio, 1);
 695
 696         regulator_disable(ts->vcc_vid);
 697         regulator_disable(ts->vcc_vdd);
 698 }
 699
 700 #define __GET_MT_TOOL_TYPE(type) ((type) == 0x01 ? MT_TOOL_FINGER : MT_TOOL_PEN)
 701
 702 static void hideep_report_slot(struct input_dev *input,
 703                                const struct hideep_event *event)
 704 {
 705         input_mt_slot(input, event->index & 0x0f);
 706         input_mt_report_slot_state(input,
 707                                    __GET_MT_TOOL_TYPE(event->type),
 708                                    !(event->flag & HIDEEP_MT_RELEASED));
 709         if (!(event->flag & HIDEEP_MT_RELEASED)) {
 710                 input_report_abs(input, ABS_MT_POSITION_X,
 711                                  le16_to_cpup(&event->x));
 712                 input_report_abs(input, ABS_MT_POSITION_Y,
 713                                  le16_to_cpup(&event->y));
 714                 input_report_abs(input, ABS_MT_PRESSURE,
 715                                  le16_to_cpup(&event->z));
 716                 input_report_abs(input, ABS_MT_TOUCH_MAJOR, event->w);
 717         }
 718 }
 719
 720 static void hideep_parse_and_report(struct hideep_ts *ts)
 721 {
 722         const struct hideep_event *events =
 723                         (void *)&ts->xfer_buf[HIDEEP_TOUCH_EVENT_INDEX];
 724         const u8 *keys = &ts->xfer_buf[HIDEEP_KEY_EVENT_INDEX];
 725         int touch_count = ts->xfer_buf[0];
 726         int key_count = ts->xfer_buf[1] & 0x0f;
 727         int lpm_count = ts->xfer_buf[1] & 0xf0;
 728         int i;
 729
 730         /* get touch event count */
 731         dev_dbg(&ts->client->dev, "mt = %d, key = %d, lpm = %02x",
 732                 touch_count, key_count, lpm_count);
 733
 734         touch_count = min(touch_count, HIDEEP_MT_MAX);
 735         for (i = 0; i < touch_count; i++)
 736                 hideep_report_slot(ts->input_dev, events + i);
 737
 738         key_count = min(key_count, HIDEEP_KEY_MAX);
 739         for (i = 0; i < key_count; i++) {
 740                 u8 key_data = keys[i * 2];
 741
 742                 input_report_key(ts->input_dev,
 743                                  ts->key_codes[key_data & HIDEEP_KEY_IDX_MASK],
 744                                  key_data & HIDEEP_KEY_PRESSED_MASK);
 745         }
 746
 747         input_mt_sync_frame(ts->input_dev);
 748         input_sync(ts->input_dev);
 749 }
 750
 751 static irqreturn_t hideep_irq(int irq, void *handle)
 752 {
 753         struct hideep_ts *ts = handle;
 754         int error;
 755
 756         BUILD_BUG_ON(HIDEEP_MAX_EVENT > HIDEEP_XFER_BUF_SIZE);
 757
 758         error = regmap_bulk_read(ts->reg, HIDEEP_EVENT_ADDR,
 759                                  ts->xfer_buf, HIDEEP_MAX_EVENT / 2);
 760         if (error) {
 761                 dev_err(&ts->client->dev, "failed to read events: %d\n", error);
 762                 goto out;
 763         }
 764
 765         hideep_parse_and_report(ts);
 766
 767 out:
 768         return IRQ_HANDLED;
 769 }
 770
 771 static int hideep_get_axis_info(struct hideep_ts *ts)
 772 {
 773         __le16 val[2];
 774         int error;
 775
 776         error = regmap_bulk_read(ts->reg, 0x28, val, ARRAY_SIZE(val));
 777         if (error)
 778                 return error;
 779
 780         ts->prop.max_x = le16_to_cpup(val);
 781         ts->prop.max_y = le16_to_cpup(val + 1);
 782
 783         dev_dbg(&ts->client->dev, "X: %d, Y: %d",
 784                 ts->prop.max_x, ts->prop.max_y);
 785
 786         return 0;
 787 }
 788
 789 static int hideep_init_input(struct hideep_ts *ts)
 790 {
 791         struct device *dev = &ts->client->dev;
 792         int i;
 793         int error;
 794
 795         ts->input_dev = devm_input_allocate_device(dev);
 796         if (!ts->input_dev) {
 797                 dev_err(dev, "failed to allocate input device\n");
 798                 return -ENOMEM;
 799         }
 800
 801         ts->input_dev->name = HIDEEP_TS_NAME;
 802         ts->input_dev->id.bustype = BUS_I2C;
 803         input_set_drvdata(ts->input_dev, ts);
 804
 805         input_set_capability(ts->input_dev, EV_ABS, ABS_MT_POSITION_X);
 806         input_set_capability(ts->input_dev, EV_ABS, ABS_MT_POSITION_Y);
 807         input_set_abs_params(ts->input_dev, ABS_MT_PRESSURE, 0, 65535, 0, 0);
 808         input_set_abs_params(ts->input_dev, ABS_MT_TOUCH_MAJOR, 0, 255, 0, 0);
 809         input_set_abs_params(ts->input_dev, ABS_MT_TOOL_TYPE,
 810                              0, MT_TOOL_MAX, 0, 0);
 811         touchscreen_parse_properties(ts->input_dev, true, &ts->prop);
 812
 813         if (ts->prop.max_x == 0 || ts->prop.max_y == 0) {
 814                 error = hideep_get_axis_info(ts);
 815                 if (error)
 816                         return error;
 817         }
 818
 819         error = input_mt_init_slots(ts->input_dev, HIDEEP_MT_MAX,
 820                                     INPUT_MT_DIRECT);
 821         if (error)
 822                 return error;
 823
 824         ts->key_num = device_property_read_u32_array(dev, "linux,keycodes",
 825                                                      NULL, 0);
 826         if (ts->key_num > HIDEEP_KEY_MAX) {
 827                 dev_err(dev, "too many keys defined: %d\n",
 828                         ts->key_num);
 829                 return -EINVAL;
 830         }
 831
 832         if (ts->key_num <= 0) {
 833                 dev_dbg(dev,
 834                         "missing or malformed 'linux,keycodes' property\n");
 835         } else {
 836                 error = device_property_read_u32_array(dev, "linux,keycodes",
 837                                                        ts->key_codes,
 838                                                        ts->key_num);
 839                 if (error) {
 840                         dev_dbg(dev, "failed to read keymap: %d", error);
 841                         return error;
 842                 }
 843
 844                 if (ts->key_num) {
 845                         ts->input_dev->keycode = ts->key_codes;
 846                         ts->input_dev->keycodesize = sizeof(ts->key_codes[0]);
 847                         ts->input_dev->keycodemax = ts->key_num;
 848
 849                         for (i = 0; i < ts->key_num; i++)
 850                                 input_set_capability(ts->input_dev, EV_KEY,
 851                                         ts->key_codes[i]);
 852                 }
 853         }
 854
 855         error = input_register_device(ts->input_dev);
 856         if (error) {
 857                 dev_err(dev, "failed to register input device: %d", error);
 858                 return error;
 859         }
 860
 861         return 0;
 862 }
 863
 864 static ssize_t hideep_update_fw(struct device *dev,
 865                                 struct device_attribute *attr,
 866                                 const char *buf, size_t count)
 867 {
 868         struct i2c_client *client = to_i2c_client(dev);
 869         struct hideep_ts *ts = i2c_get_clientdata(client);
 870         const struct firmware *fw_entry;
 871         char *fw_name;
 872         int mode;
 873         int error;
 874
 875         error = kstrtoint(buf, 0, &mode);
 876         if (error)
 877                 return error;
 878
 879         fw_name = kasprintf(GFP_KERNEL, "/*(DEBLOBBED)*/",
 880                             be16_to_cpu(ts->dwz_info.product_id));
 881         if (!fw_name)
 882                 return -ENOMEM;
 883
 884         error = reject_firmware(&fw_entry, fw_name, dev);
 885         if (error) {
 886                 dev_err(dev, "failed to request firmware %s: %d",
 887                         fw_name, error);
 888                 goto out_free_fw_name;
 889         }
 890
 891         if (fw_entry->size % sizeof(__be32)) {
 892                 dev_err(dev, "invalid firmware size %zu\n", fw_entry->size);
 893                 error = -EINVAL;
 894                 goto out_release_fw;
 895         }
 896
 897         if (fw_entry->size > ts->fw_size) {
 898                 dev_err(dev, "fw size (%zu) is too big (memory size %d)\n",
 899                         fw_entry->size, ts->fw_size);
 900                 error = -EFBIG;
 901                 goto out_release_fw;
 902         }
 903
 904         mutex_lock(&ts->dev_mutex);
 905         disable_irq(client->irq);
 906
 907         error = hideep_update_firmware(ts, (const __be32 *)fw_entry->data,
 908                                        fw_entry->size);
 909
 910         enable_irq(client->irq);
 911         mutex_unlock(&ts->dev_mutex);
 912
 913 out_release_fw:
 914         release_firmware(fw_entry);
 915 out_free_fw_name:
 916         kfree(fw_name);
 917
 918         return error ?: count;
 919 }
 920
 921 static ssize_t hideep_fw_version_show(struct device *dev,
 922                                       struct device_attribute *attr, char *buf)
 923 {
 924         struct i2c_client *client = to_i2c_client(dev);
 925         struct hideep_ts *ts = i2c_get_clientdata(client);
 926         ssize_t len;
 927
 928         mutex_lock(&ts->dev_mutex);
 929         len = scnprintf(buf, PAGE_SIZE, "%04x\n",
 930                         be16_to_cpu(ts->dwz_info.release_ver));
 931         mutex_unlock(&ts->dev_mutex);
 932
 933         return len;
 934 }
 935
 936 static ssize_t hideep_product_id_show(struct device *dev,
 937                                       struct device_attribute *attr, char *buf)
 938 {
 939         struct i2c_client *client = to_i2c_client(dev);
 940         struct hideep_ts *ts = i2c_get_clientdata(client);
 941         ssize_t len;
 942
 943         mutex_lock(&ts->dev_mutex);
 944         len = scnprintf(buf, PAGE_SIZE, "%04x\n",
 945                         be16_to_cpu(ts->dwz_info.product_id));
 946         mutex_unlock(&ts->dev_mutex);
 947
 948         return len;
 949 }
 950
 951 static DEVICE_ATTR(version, 0664, hideep_fw_version_show, NULL);
 952 static DEVICE_ATTR(product_id, 0664, hideep_product_id_show, NULL);
 953 static DEVICE_ATTR(update_fw, 0664, NULL, hideep_update_fw);
 954
 955 static struct attribute *hideep_ts_sysfs_entries[] = {
 956         &dev_attr_version.attr,
 957         &dev_attr_product_id.attr,
 958         &dev_attr_update_fw.attr,
 959         NULL,
 960 };
 961
 962 static const struct attribute_group hideep_ts_attr_group = {
 963         .attrs = hideep_ts_sysfs_entries,
 964 };
 965
 966 static int __maybe_unused hideep_suspend(struct device *dev)
 967 {
 968         struct i2c_client *client = to_i2c_client(dev);
 969         struct hideep_ts *ts = i2c_get_clientdata(client);
 970
 971         disable_irq(client->irq);
 972         hideep_power_off(ts);
 973
 974         return 0;
 975 }
 976
 977 static int __maybe_unused hideep_resume(struct device *dev)
 978 {
 979         struct i2c_client *client = to_i2c_client(dev);
 980         struct hideep_ts *ts = i2c_get_clientdata(client);
 981         int error;
 982
 983         error = hideep_power_on(ts);
 984         if (error) {
 985                 dev_err(&client->dev, "power on failed");
 986                 return error;
 987         }
 988
 989         enable_irq(client->irq);
 990
 991         return 0;
 992 }
 993
 994 static SIMPLE_DEV_PM_OPS(hideep_pm_ops, hideep_suspend, hideep_resume);
 995
 996 static const struct regmap_config hideep_regmap_config = {
 997         .reg_bits = 16,
 998         .reg_format_endian = REGMAP_ENDIAN_LITTLE,
 999         .val_bits = 16,
1000         .val_format_endian = REGMAP_ENDIAN_LITTLE,
1001         .max_register = 0xffff,
1002 };
1003
1004 static int hideep_probe(struct i2c_client *client,
1005                         const struct i2c_device_id *id)
1006 {
1007         struct hideep_ts *ts;
1008         int error;
1009
1010         /* check i2c bus */
1011         if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1012                 dev_err(&client->dev, "check i2c device error");
1013                 return -ENODEV;
1014         }
1015
1016         if (client->irq <= 0) {
1017                 dev_err(&client->dev, "missing irq: %d\n", client->irq);
1018                 return -EINVAL;
1019         }
1020
1021         ts = devm_kzalloc(&client->dev, sizeof(*ts), GFP_KERNEL);
1022         if (!ts)
1023                 return -ENOMEM;
1024
1025         ts->client = client;
1026         i2c_set_clientdata(client, ts);
1027         mutex_init(&ts->dev_mutex);
1028
1029         ts->reg = devm_regmap_init_i2c(client, &hideep_regmap_config);
1030         if (IS_ERR(ts->reg)) {
1031                 error = PTR_ERR(ts->reg);
1032                 dev_err(&client->dev,
1033                         "failed to initialize regmap: %d\n", error);
1034                 return error;
1035         }
1036
1037         ts->vcc_vdd = devm_regulator_get(&client->dev, "vdd");
1038         if (IS_ERR(ts->vcc_vdd))
1039                 return PTR_ERR(ts->vcc_vdd);
1040
1041         ts->vcc_vid = devm_regulator_get(&client->dev, "vid");
1042         if (IS_ERR(ts->vcc_vid))
1043                 return PTR_ERR(ts->vcc_vid);
1044
1045         ts->reset_gpio = devm_gpiod_get_optional(&client->dev,
1046                                                  "reset", GPIOD_OUT_HIGH);
1047         if (IS_ERR(ts->reset_gpio))
1048                 return PTR_ERR(ts->reset_gpio);
1049
1050         error = hideep_power_on(ts);
1051         if (error) {
1052                 dev_err(&client->dev, "power on failed: %d\n", error);
1053                 return error;
1054         }
1055
1056         error = devm_add_action_or_reset(&client->dev, hideep_power_off, ts);
1057         if (error)
1058                 return error;
1059
1060         error = hideep_load_dwz(ts);
1061         if (error) {
1062                 dev_err(&client->dev, "failed to load dwz: %d", error);
1063                 return error;
1064         }
1065
1066         error = hideep_init_input(ts);
1067         if (error)
1068                 return error;
1069
1070         error = devm_request_threaded_irq(&client->dev, client->irq,
1071                                           NULL, hideep_irq, IRQF_ONESHOT,
1072                                           client->name, ts);
1073         if (error) {
1074                 dev_err(&client->dev, "failed to request irq %d: %d\n",
1075                         client->irq, error);
1076                 return error;
1077         }
1078
1079         error = devm_device_add_group(&client->dev, &hideep_ts_attr_group);
1080         if (error) {
1081                 dev_err(&client->dev,
1082                         "failed to add sysfs attributes: %d\n", error);
1083                 return error;
1084         }
1085
1086         return 0;
1087 }
1088
1089 static const struct i2c_device_id hideep_i2c_id[] = {
1090         { HIDEEP_I2C_NAME, 0 },
1091         { }
1092 };
1093 MODULE_DEVICE_TABLE(i2c, hideep_i2c_id);
1094
1095 #ifdef CONFIG_ACPI
1096 static const struct acpi_device_id hideep_acpi_id[] = {
1097         { "HIDP0001", 0 },
1098         { }
1099 };
1100 MODULE_DEVICE_TABLE(acpi, hideep_acpi_id);
1101 #endif
1102
1103 #ifdef CONFIG_OF
1104 static const struct of_device_id hideep_match_table[] = {
1105         { .compatible = "hideep,hideep-ts" },
1106         { }
1107 };
1108 MODULE_DEVICE_TABLE(of, hideep_match_table);
1109 #endif
1110
1111 static struct i2c_driver hideep_driver = {
1112         .driver = {
1113                 .name                   = HIDEEP_I2C_NAME,
1114                 .of_match_table         = of_match_ptr(hideep_match_table),
1115                 .acpi_match_table       = ACPI_PTR(hideep_acpi_id),
1116                 .pm                     = &hideep_pm_ops,
1117         },
1118         .id_table       = hideep_i2c_id,
1119         .probe          = hideep_probe,
1120 };
1121
1122 module_i2c_driver(hideep_driver);
1123
1124 MODULE_DESCRIPTION("Driver for HiDeep Touchscreen Controller");
1125 MODULE_AUTHOR("anthony.kim@hideep.com");
1126 MODULE_LICENSE("GPL v2");