drivers/iommu/exynos-iommu.c

   1 /*
   2  * Copyright (c) 2011,2016 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9
  10 #ifdef CONFIG_EXYNOS_IOMMU_DEBUG
  11 #define DEBUG
  12 #endif
  13
  14 #include <linux/clk.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/iommu.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/list.h>
  21 #include <linux/of.h>
  22 #include <linux/of_iommu.h>
  23 #include <linux/of_platform.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/slab.h>
  27 #include <linux/dma-iommu.h>
  28
  29 typedef u32 sysmmu_iova_t;
  30 typedef u32 sysmmu_pte_t;
  31
  32 /* We do not consider super section mapping (16MB) */
  33 #define SECT_ORDER 20
  34 #define LPAGE_ORDER 16
  35 #define SPAGE_ORDER 12
  36
  37 #define SECT_SIZE (1 << SECT_ORDER)
  38 #define LPAGE_SIZE (1 << LPAGE_ORDER)
  39 #define SPAGE_SIZE (1 << SPAGE_ORDER)
  40
  41 #define SECT_MASK (~(SECT_SIZE - 1))
  42 #define LPAGE_MASK (~(LPAGE_SIZE - 1))
  43 #define SPAGE_MASK (~(SPAGE_SIZE - 1))
  44
  45 #define lv1ent_fault(sent) ((*(sent) == ZERO_LV2LINK) || \
  46                            ((*(sent) & 3) == 0) || ((*(sent) & 3) == 3))
  47 #define lv1ent_zero(sent) (*(sent) == ZERO_LV2LINK)
  48 #define lv1ent_page_zero(sent) ((*(sent) & 3) == 1)
  49 #define lv1ent_page(sent) ((*(sent) != ZERO_LV2LINK) && \
  50                           ((*(sent) & 3) == 1))
  51 #define lv1ent_section(sent) ((*(sent) & 3) == 2)
  52
  53 #define lv2ent_fault(pent) ((*(pent) & 3) == 0)
  54 #define lv2ent_small(pent) ((*(pent) & 2) == 2)
  55 #define lv2ent_large(pent) ((*(pent) & 3) == 1)
  56
  57 #ifdef CONFIG_BIG_ENDIAN
  58 #warning "revisit driver if we can enable big-endian ptes"
  59 #endif
  60
  61 /*
  62  * v1.x - v3.x SYSMMU supports 32bit physical and 32bit virtual address spaces
  63  * v5.0 introduced support for 36bit physical address space by shifting
  64  * all page entry values by 4 bits.
  65  * All SYSMMU controllers in the system support the address spaces of the same
  66  * size, so PG_ENT_SHIFT can be initialized on first SYSMMU probe to proper
  67  * value (0 or 4).
  68  */
  69 static short PG_ENT_SHIFT = -1;
  70 #define SYSMMU_PG_ENT_SHIFT 0
  71 #define SYSMMU_V5_PG_ENT_SHIFT 4
  72
  73 #define sect_to_phys(ent) (((phys_addr_t) ent) << PG_ENT_SHIFT)
  74 #define section_phys(sent) (sect_to_phys(*(sent)) & SECT_MASK)
  75 #define section_offs(iova) (iova & (SECT_SIZE - 1))
  76 #define lpage_phys(pent) (sect_to_phys(*(pent)) & LPAGE_MASK)
  77 #define lpage_offs(iova) (iova & (LPAGE_SIZE - 1))
  78 #define spage_phys(pent) (sect_to_phys(*(pent)) & SPAGE_MASK)
  79 #define spage_offs(iova) (iova & (SPAGE_SIZE - 1))
  80
  81 #define NUM_LV1ENTRIES 4096
  82 #define NUM_LV2ENTRIES (SECT_SIZE / SPAGE_SIZE)
  83
  84 static u32 lv1ent_offset(sysmmu_iova_t iova)
  85 {
  86         return iova >> SECT_ORDER;
  87 }
  88
  89 static u32 lv2ent_offset(sysmmu_iova_t iova)
  90 {
  91         return (iova >> SPAGE_ORDER) & (NUM_LV2ENTRIES - 1);
  92 }
  93
  94 #define LV1TABLE_SIZE (NUM_LV1ENTRIES * sizeof(sysmmu_pte_t))
  95 #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(sysmmu_pte_t))
  96
  97 #define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE)
  98 #define lv2table_base(sent) (sect_to_phys(*(sent) & 0xFFFFFFC0))
  99
 100 #define mk_lv1ent_sect(pa) ((pa >> PG_ENT_SHIFT) | 2)
 101 #define mk_lv1ent_page(pa) ((pa >> PG_ENT_SHIFT) | 1)
 102 #define mk_lv2ent_lpage(pa) ((pa >> PG_ENT_SHIFT) | 1)
 103 #define mk_lv2ent_spage(pa) ((pa >> PG_ENT_SHIFT) | 2)
 104
 105 #define CTRL_ENABLE     0x5
 106 #define CTRL_BLOCK      0x7
 107 #define CTRL_DISABLE    0x0
 108
 109 #define CFG_LRU         0x1
 110 #define CFG_QOS(n)      ((n & 0xF) << 7)
 111 #define CFG_ACGEN       (1 << 24) /* System MMU 3.3 only */
 112 #define CFG_SYSSEL      (1 << 22) /* System MMU 3.2 only */
 113 #define CFG_FLPDCACHE   (1 << 20) /* System MMU 3.2+ only */
 114
 115 /* common registers */
 116 #define REG_MMU_CTRL            0x000
 117 #define REG_MMU_CFG             0x004
 118 #define REG_MMU_STATUS          0x008
 119 #define REG_MMU_VERSION         0x034
 120
 121 #define MMU_MAJ_VER(val)        ((val) >> 7)
 122 #define MMU_MIN_VER(val)        ((val) & 0x7F)
 123 #define MMU_RAW_VER(reg)        (((reg) >> 21) & ((1 << 11) - 1)) /* 11 bits */
 124
 125 #define MAKE_MMU_VER(maj, min)  ((((maj) & 0xF) << 7) | ((min) & 0x7F))
 126
 127 /* v1.x - v3.x registers */
 128 #define REG_MMU_FLUSH           0x00C
 129 #define REG_MMU_FLUSH_ENTRY     0x010
 130 #define REG_PT_BASE_ADDR        0x014
 131 #define REG_INT_STATUS          0x018
 132 #define REG_INT_CLEAR           0x01C
 133
 134 #define REG_PAGE_FAULT_ADDR     0x024
 135 #define REG_AW_FAULT_ADDR       0x028
 136 #define REG_AR_FAULT_ADDR       0x02C
 137 #define REG_DEFAULT_SLAVE_ADDR  0x030
 138
 139 /* v5.x registers */
 140 #define REG_V5_PT_BASE_PFN      0x00C
 141 #define REG_V5_MMU_FLUSH_ALL    0x010
 142 #define REG_V5_MMU_FLUSH_ENTRY  0x014
 143 #define REG_V5_INT_STATUS       0x060
 144 #define REG_V5_INT_CLEAR        0x064
 145 #define REG_V5_FAULT_AR_VA      0x070
 146 #define REG_V5_FAULT_AW_VA      0x080
 147
 148 #define has_sysmmu(dev)         (dev->archdata.iommu != NULL)
 149
 150 static struct device *dma_dev;
 151 static struct kmem_cache *lv2table_kmem_cache;
 152 static sysmmu_pte_t *zero_lv2_table;
 153 #define ZERO_LV2LINK mk_lv1ent_page(virt_to_phys(zero_lv2_table))
 154
 155 static sysmmu_pte_t *section_entry(sysmmu_pte_t *pgtable, sysmmu_iova_t iova)
 156 {
 157         return pgtable + lv1ent_offset(iova);
 158 }
 159
 160 static sysmmu_pte_t *page_entry(sysmmu_pte_t *sent, sysmmu_iova_t iova)
 161 {
 162         return (sysmmu_pte_t *)phys_to_virt(
 163                                 lv2table_base(sent)) + lv2ent_offset(iova);
 164 }
 165
 166 /*
 167  * IOMMU fault information register
 168  */
 169 struct sysmmu_fault_info {
 170         unsigned int bit;       /* bit number in STATUS register */
 171         unsigned short addr_reg; /* register to read VA fault address */
 172         const char *name;       /* human readable fault name */
 173         unsigned int type;      /* fault type for report_iommu_fault */
 174 };
 175
 176 static const struct sysmmu_fault_info sysmmu_faults[] = {
 177         { 0, REG_PAGE_FAULT_ADDR, "PAGE", IOMMU_FAULT_READ },
 178         { 1, REG_AR_FAULT_ADDR, "AR MULTI-HIT", IOMMU_FAULT_READ },
 179         { 2, REG_AW_FAULT_ADDR, "AW MULTI-HIT", IOMMU_FAULT_WRITE },
 180         { 3, REG_DEFAULT_SLAVE_ADDR, "BUS ERROR", IOMMU_FAULT_READ },
 181         { 4, REG_AR_FAULT_ADDR, "AR SECURITY PROTECTION", IOMMU_FAULT_READ },
 182         { 5, REG_AR_FAULT_ADDR, "AR ACCESS PROTECTION", IOMMU_FAULT_READ },
 183         { 6, REG_AW_FAULT_ADDR, "AW SECURITY PROTECTION", IOMMU_FAULT_WRITE },
 184         { 7, REG_AW_FAULT_ADDR, "AW ACCESS PROTECTION", IOMMU_FAULT_WRITE },
 185 };
 186
 187 static const struct sysmmu_fault_info sysmmu_v5_faults[] = {
 188         { 0, REG_V5_FAULT_AR_VA, "AR PTW", IOMMU_FAULT_READ },
 189         { 1, REG_V5_FAULT_AR_VA, "AR PAGE", IOMMU_FAULT_READ },
 190         { 2, REG_V5_FAULT_AR_VA, "AR MULTI-HIT", IOMMU_FAULT_READ },
 191         { 3, REG_V5_FAULT_AR_VA, "AR ACCESS PROTECTION", IOMMU_FAULT_READ },
 192         { 4, REG_V5_FAULT_AR_VA, "AR SECURITY PROTECTION", IOMMU_FAULT_READ },
 193         { 16, REG_V5_FAULT_AW_VA, "AW PTW", IOMMU_FAULT_WRITE },
 194         { 17, REG_V5_FAULT_AW_VA, "AW PAGE", IOMMU_FAULT_WRITE },
 195         { 18, REG_V5_FAULT_AW_VA, "AW MULTI-HIT", IOMMU_FAULT_WRITE },
 196         { 19, REG_V5_FAULT_AW_VA, "AW ACCESS PROTECTION", IOMMU_FAULT_WRITE },
 197         { 20, REG_V5_FAULT_AW_VA, "AW SECURITY PROTECTION", IOMMU_FAULT_WRITE },
 198 };
 199
 200 /*
 201  * This structure is attached to dev.archdata.iommu of the master device
 202  * on device add, contains a list of SYSMMU controllers defined by device tree,
 203  * which are bound to given master device. It is usually referenced by 'owner'
 204  * pointer.
 205 */
 206 struct exynos_iommu_owner {
 207         struct list_head controllers;   /* list of sysmmu_drvdata.owner_node */
 208         struct iommu_domain *domain;    /* domain this device is attached */
 209 };
 210
 211 /*
 212  * This structure exynos specific generalization of struct iommu_domain.
 213  * It contains list of SYSMMU controllers from all master devices, which has
 214  * been attached to this domain and page tables of IO address space defined by
 215  * it. It is usually referenced by 'domain' pointer.
 216  */
 217 struct exynos_iommu_domain {
 218         struct list_head clients; /* list of sysmmu_drvdata.domain_node */
 219         sysmmu_pte_t *pgtable;  /* lv1 page table, 16KB */
 220         short *lv2entcnt;       /* free lv2 entry counter for each section */
 221         spinlock_t lock;        /* lock for modyfying list of clients */
 222         spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
 223         struct iommu_domain domain; /* generic domain data structure */
 224 };
 225
 226 /*
 227  * This structure hold all data of a single SYSMMU controller, this includes
 228  * hw resources like registers and clocks, pointers and list nodes to connect
 229  * it to all other structures, internal state and parameters read from device
 230  * tree. It is usually referenced by 'data' pointer.
 231  */
 232 struct sysmmu_drvdata {
 233         struct device *sysmmu;          /* SYSMMU controller device */
 234         struct device *master;          /* master device (owner) */
 235         void __iomem *sfrbase;          /* our registers */
 236         struct clk *clk;                /* SYSMMU's clock */
 237         struct clk *aclk;               /* SYSMMU's aclk clock */
 238         struct clk *pclk;               /* SYSMMU's pclk clock */
 239         struct clk *clk_master;         /* master's device clock */
 240         int activations;                /* number of calls to sysmmu_enable */
 241         spinlock_t lock;                /* lock for modyfying state */
 242         struct exynos_iommu_domain *domain; /* domain we belong to */
 243         struct list_head domain_node;   /* node for domain clients list */
 244         struct list_head owner_node;    /* node for owner controllers list */
 245         phys_addr_t pgtable;            /* assigned page table structure */
 246         unsigned int version;           /* our version */
 247 };
 248
 249 static struct exynos_iommu_domain *to_exynos_domain(struct iommu_domain *dom)
 250 {
 251         return container_of(dom, struct exynos_iommu_domain, domain);
 252 }
 253
 254 static bool set_sysmmu_active(struct sysmmu_drvdata *data)
 255 {
 256         /* return true if the System MMU was not active previously
 257            and it needs to be initialized */
 258         return ++data->activations == 1;
 259 }
 260
 261 static bool set_sysmmu_inactive(struct sysmmu_drvdata *data)
 262 {
 263         /* return true if the System MMU is needed to be disabled */
 264         BUG_ON(data->activations < 1);
 265         return --data->activations == 0;
 266 }
 267
 268 static bool is_sysmmu_active(struct sysmmu_drvdata *data)
 269 {
 270         return data->activations > 0;
 271 }
 272
 273 static void sysmmu_unblock(struct sysmmu_drvdata *data)
 274 {
 275         writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL);
 276 }
 277
 278 static bool sysmmu_block(struct sysmmu_drvdata *data)
 279 {
 280         int i = 120;
 281
 282         writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL);
 283         while ((i > 0) && !(readl(data->sfrbase + REG_MMU_STATUS) & 1))
 284                 --i;
 285
 286         if (!(readl(data->sfrbase + REG_MMU_STATUS) & 1)) {
 287                 sysmmu_unblock(data);
 288                 return false;
 289         }
 290
 291         return true;
 292 }
 293
 294 static void __sysmmu_tlb_invalidate(struct sysmmu_drvdata *data)
 295 {
 296         if (MMU_MAJ_VER(data->version) < 5)
 297                 writel(0x1, data->sfrbase + REG_MMU_FLUSH);
 298         else
 299                 writel(0x1, data->sfrbase + REG_V5_MMU_FLUSH_ALL);
 300 }
 301
 302 static void __sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data,
 303                                 sysmmu_iova_t iova, unsigned int num_inv)
 304 {
 305         unsigned int i;
 306
 307         for (i = 0; i < num_inv; i++) {
 308                 if (MMU_MAJ_VER(data->version) < 5)
 309                         writel((iova & SPAGE_MASK) | 1,
 310                                      data->sfrbase + REG_MMU_FLUSH_ENTRY);
 311                 else
 312                         writel((iova & SPAGE_MASK) | 1,
 313                                      data->sfrbase + REG_V5_MMU_FLUSH_ENTRY);
 314                 iova += SPAGE_SIZE;
 315         }
 316 }
 317
 318 static void __sysmmu_set_ptbase(struct sysmmu_drvdata *data, phys_addr_t pgd)
 319 {
 320         if (MMU_MAJ_VER(data->version) < 5)
 321                 writel(pgd, data->sfrbase + REG_PT_BASE_ADDR);
 322         else
 323                 writel(pgd >> PAGE_SHIFT,
 324                              data->sfrbase + REG_V5_PT_BASE_PFN);
 325
 326         __sysmmu_tlb_invalidate(data);
 327 }
 328
 329 static void __sysmmu_enable_clocks(struct sysmmu_drvdata *data)
 330 {
 331         BUG_ON(clk_prepare_enable(data->clk_master));
 332         BUG_ON(clk_prepare_enable(data->clk));
 333         BUG_ON(clk_prepare_enable(data->pclk));
 334         BUG_ON(clk_prepare_enable(data->aclk));
 335 }
 336
 337 static void __sysmmu_disable_clocks(struct sysmmu_drvdata *data)
 338 {
 339         clk_disable_unprepare(data->aclk);
 340         clk_disable_unprepare(data->pclk);
 341         clk_disable_unprepare(data->clk);
 342         clk_disable_unprepare(data->clk_master);
 343 }
 344
 345 static void __sysmmu_get_version(struct sysmmu_drvdata *data)
 346 {
 347         u32 ver;
 348
 349         __sysmmu_enable_clocks(data);
 350
 351         ver = readl(data->sfrbase + REG_MMU_VERSION);
 352
 353         /* controllers on some SoCs don't report proper version */
 354         if (ver == 0x80000001u)
 355                 data->version = MAKE_MMU_VER(1, 0);
 356         else
 357                 data->version = MMU_RAW_VER(ver);
 358
 359         dev_dbg(data->sysmmu, "hardware version: %d.%d\n",
 360                 MMU_MAJ_VER(data->version), MMU_MIN_VER(data->version));
 361
 362         __sysmmu_disable_clocks(data);
 363 }
 364
 365 static void show_fault_information(struct sysmmu_drvdata *data,
 366                                    const struct sysmmu_fault_info *finfo,
 367                                    sysmmu_iova_t fault_addr)
 368 {
 369         sysmmu_pte_t *ent;
 370
 371         dev_err(data->sysmmu, "%s FAULT occurred at %#x (page table base: %pa)\n",
 372                 finfo->name, fault_addr, &data->pgtable);
 373         ent = section_entry(phys_to_virt(data->pgtable), fault_addr);
 374         dev_err(data->sysmmu, "\tLv1 entry: %#x\n", *ent);
 375         if (lv1ent_page(ent)) {
 376                 ent = page_entry(ent, fault_addr);
 377                 dev_err(data->sysmmu, "\t Lv2 entry: %#x\n", *ent);
 378         }
 379 }
 380
 381 static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
 382 {
 383         /* SYSMMU is in blocked state when interrupt occurred. */
 384         struct sysmmu_drvdata *data = dev_id;
 385         const struct sysmmu_fault_info *finfo;
 386         unsigned int i, n, itype;
 387         sysmmu_iova_t fault_addr = -1;
 388         unsigned short reg_status, reg_clear;
 389         int ret = -ENOSYS;
 390
 391         WARN_ON(!is_sysmmu_active(data));
 392
 393         if (MMU_MAJ_VER(data->version) < 5) {
 394                 reg_status = REG_INT_STATUS;
 395                 reg_clear = REG_INT_CLEAR;
 396                 finfo = sysmmu_faults;
 397                 n = ARRAY_SIZE(sysmmu_faults);
 398         } else {
 399                 reg_status = REG_V5_INT_STATUS;
 400                 reg_clear = REG_V5_INT_CLEAR;
 401                 finfo = sysmmu_v5_faults;
 402                 n = ARRAY_SIZE(sysmmu_v5_faults);
 403         }
 404
 405         spin_lock(&data->lock);
 406
 407         clk_enable(data->clk_master);
 408
 409         itype = __ffs(readl(data->sfrbase + reg_status));
 410         for (i = 0; i < n; i++, finfo++)
 411                 if (finfo->bit == itype)
 412                         break;
 413         /* unknown/unsupported fault */
 414         BUG_ON(i == n);
 415
 416         /* print debug message */
 417         fault_addr = readl(data->sfrbase + finfo->addr_reg);
 418         show_fault_information(data, finfo, fault_addr);
 419
 420         if (data->domain)
 421                 ret = report_iommu_fault(&data->domain->domain,
 422                                         data->master, fault_addr, finfo->type);
 423         /* fault is not recovered by fault handler */
 424         BUG_ON(ret != 0);
 425
 426         writel(1 << itype, data->sfrbase + reg_clear);
 427
 428         sysmmu_unblock(data);
 429
 430         clk_disable(data->clk_master);
 431
 432         spin_unlock(&data->lock);
 433
 434         return IRQ_HANDLED;
 435 }
 436
 437 static void __sysmmu_disable_nocount(struct sysmmu_drvdata *data)
 438 {
 439         clk_enable(data->clk_master);
 440
 441         writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL);
 442         writel(0, data->sfrbase + REG_MMU_CFG);
 443
 444         __sysmmu_disable_clocks(data);
 445 }
 446
 447 static bool __sysmmu_disable(struct sysmmu_drvdata *data)
 448 {
 449         bool disabled;
 450         unsigned long flags;
 451
 452         spin_lock_irqsave(&data->lock, flags);
 453
 454         disabled = set_sysmmu_inactive(data);
 455
 456         if (disabled) {
 457                 data->pgtable = 0;
 458                 data->domain = NULL;
 459
 460                 __sysmmu_disable_nocount(data);
 461
 462                 dev_dbg(data->sysmmu, "Disabled\n");
 463         } else  {
 464                 dev_dbg(data->sysmmu, "%d times left to disable\n",
 465                                         data->activations);
 466         }
 467
 468         spin_unlock_irqrestore(&data->lock, flags);
 469
 470         return disabled;
 471 }
 472
 473 static void __sysmmu_init_config(struct sysmmu_drvdata *data)
 474 {
 475         unsigned int cfg;
 476
 477         if (data->version <= MAKE_MMU_VER(3, 1))
 478                 cfg = CFG_LRU | CFG_QOS(15);
 479         else if (data->version <= MAKE_MMU_VER(3, 2))
 480                 cfg = CFG_LRU | CFG_QOS(15) | CFG_FLPDCACHE | CFG_SYSSEL;
 481         else
 482                 cfg = CFG_QOS(15) | CFG_FLPDCACHE | CFG_ACGEN;
 483
 484         writel(cfg, data->sfrbase + REG_MMU_CFG);
 485 }
 486
 487 static void __sysmmu_enable_nocount(struct sysmmu_drvdata *data)
 488 {
 489         __sysmmu_enable_clocks(data);
 490
 491         writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL);
 492
 493         __sysmmu_init_config(data);
 494
 495         __sysmmu_set_ptbase(data, data->pgtable);
 496
 497         writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL);
 498
 499         /*
 500          * SYSMMU driver keeps master's clock enabled only for the short
 501          * time, while accessing the registers. For performing address
 502          * translation during DMA transaction it relies on the client
 503          * driver to enable it.
 504          */
 505         clk_disable(data->clk_master);
 506 }
 507
 508 static int __sysmmu_enable(struct sysmmu_drvdata *data, phys_addr_t pgtable,
 509                            struct exynos_iommu_domain *domain)
 510 {
 511         int ret = 0;
 512         unsigned long flags;
 513
 514         spin_lock_irqsave(&data->lock, flags);
 515         if (set_sysmmu_active(data)) {
 516                 data->pgtable = pgtable;
 517                 data->domain = domain;
 518
 519                 __sysmmu_enable_nocount(data);
 520
 521                 dev_dbg(data->sysmmu, "Enabled\n");
 522         } else {
 523                 ret = (pgtable == data->pgtable) ? 1 : -EBUSY;
 524
 525                 dev_dbg(data->sysmmu, "already enabled\n");
 526         }
 527
 528         if (WARN_ON(ret < 0))
 529                 set_sysmmu_inactive(data); /* decrement count */
 530
 531         spin_unlock_irqrestore(&data->lock, flags);
 532
 533         return ret;
 534 }
 535
 536 static void sysmmu_tlb_invalidate_flpdcache(struct sysmmu_drvdata *data,
 537                                             sysmmu_iova_t iova)
 538 {
 539         unsigned long flags;
 540
 541
 542         spin_lock_irqsave(&data->lock, flags);
 543         if (is_sysmmu_active(data) && data->version >= MAKE_MMU_VER(3, 3)) {
 544                 clk_enable(data->clk_master);
 545                 if (sysmmu_block(data)) {
 546                         if (data->version >= MAKE_MMU_VER(5, 0))
 547                                 __sysmmu_tlb_invalidate(data);
 548                         else
 549                                 __sysmmu_tlb_invalidate_entry(data, iova, 1);
 550                         sysmmu_unblock(data);
 551                 }
 552                 clk_disable(data->clk_master);
 553         }
 554         spin_unlock_irqrestore(&data->lock, flags);
 555
 556 }
 557
 558 static void sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data,
 559                                         sysmmu_iova_t iova, size_t size)
 560 {
 561         unsigned long flags;
 562
 563         spin_lock_irqsave(&data->lock, flags);
 564         if (is_sysmmu_active(data)) {
 565                 unsigned int num_inv = 1;
 566
 567                 clk_enable(data->clk_master);
 568
 569                 /*
 570                  * L2TLB invalidation required
 571                  * 4KB page: 1 invalidation
 572                  * 64KB page: 16 invalidations
 573                  * 1MB page: 64 invalidations
 574                  * because it is set-associative TLB
 575                  * with 8-way and 64 sets.
 576                  * 1MB page can be cached in one of all sets.
 577                  * 64KB page can be one of 16 consecutive sets.
 578                  */
 579                 if (MMU_MAJ_VER(data->version) == 2)
 580                         num_inv = min_t(unsigned int, size / PAGE_SIZE, 64);
 581
 582                 if (sysmmu_block(data)) {
 583                         __sysmmu_tlb_invalidate_entry(data, iova, num_inv);
 584                         sysmmu_unblock(data);
 585                 }
 586                 clk_disable(data->clk_master);
 587         } else {
 588                 dev_dbg(data->master,
 589                         "disabled. Skipping TLB invalidation @ %#x\n", iova);
 590         }
 591         spin_unlock_irqrestore(&data->lock, flags);
 592 }
 593
 594 static struct iommu_ops exynos_iommu_ops;
 595
 596 static int __init exynos_sysmmu_probe(struct platform_device *pdev)
 597 {
 598         int irq, ret;
 599         struct device *dev = &pdev->dev;
 600         struct sysmmu_drvdata *data;
 601         struct resource *res;
 602
 603         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 604         if (!data)
 605                 return -ENOMEM;
 606
 607         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 608         data->sfrbase = devm_ioremap_resource(dev, res);
 609         if (IS_ERR(data->sfrbase))
 610                 return PTR_ERR(data->sfrbase);
 611
 612         irq = platform_get_irq(pdev, 0);
 613         if (irq <= 0) {
 614                 dev_err(dev, "Unable to find IRQ resource\n");
 615                 return irq;
 616         }
 617
 618         ret = devm_request_irq(dev, irq, exynos_sysmmu_irq, 0,
 619                                 dev_name(dev), data);
 620         if (ret) {
 621                 dev_err(dev, "Unabled to register handler of irq %d\n", irq);
 622                 return ret;
 623         }
 624
 625         data->clk = devm_clk_get(dev, "sysmmu");
 626         if (PTR_ERR(data->clk) == -ENOENT)
 627                 data->clk = NULL;
 628         else if (IS_ERR(data->clk))
 629                 return PTR_ERR(data->clk);
 630
 631         data->aclk = devm_clk_get(dev, "aclk");
 632         if (PTR_ERR(data->aclk) == -ENOENT)
 633                 data->aclk = NULL;
 634         else if (IS_ERR(data->aclk))
 635                 return PTR_ERR(data->aclk);
 636
 637         data->pclk = devm_clk_get(dev, "pclk");
 638         if (PTR_ERR(data->pclk) == -ENOENT)
 639                 data->pclk = NULL;
 640         else if (IS_ERR(data->pclk))
 641                 return PTR_ERR(data->pclk);
 642
 643         if (!data->clk && (!data->aclk || !data->pclk)) {
 644                 dev_err(dev, "Failed to get device clock(s)!\n");
 645                 return -ENOSYS;
 646         }
 647
 648         data->clk_master = devm_clk_get(dev, "master");
 649         if (PTR_ERR(data->clk_master) == -ENOENT)
 650                 data->clk_master = NULL;
 651         else if (IS_ERR(data->clk_master))
 652                 return PTR_ERR(data->clk_master);
 653
 654         data->sysmmu = dev;
 655         spin_lock_init(&data->lock);
 656
 657         platform_set_drvdata(pdev, data);
 658
 659         __sysmmu_get_version(data);
 660         if (PG_ENT_SHIFT < 0) {
 661                 if (MMU_MAJ_VER(data->version) < 5)
 662                         PG_ENT_SHIFT = SYSMMU_PG_ENT_SHIFT;
 663                 else
 664                         PG_ENT_SHIFT = SYSMMU_V5_PG_ENT_SHIFT;
 665         }
 666
 667         pm_runtime_enable(dev);
 668
 669         of_iommu_set_ops(dev->of_node, &exynos_iommu_ops);
 670
 671         return 0;
 672 }
 673
 674 #ifdef CONFIG_PM_SLEEP
 675 static int exynos_sysmmu_suspend(struct device *dev)
 676 {
 677         struct sysmmu_drvdata *data = dev_get_drvdata(dev);
 678
 679         dev_dbg(dev, "suspend\n");
 680         if (is_sysmmu_active(data)) {
 681                 __sysmmu_disable_nocount(data);
 682                 pm_runtime_put(dev);
 683         }
 684         return 0;
 685 }
 686
 687 static int exynos_sysmmu_resume(struct device *dev)
 688 {
 689         struct sysmmu_drvdata *data = dev_get_drvdata(dev);
 690
 691         dev_dbg(dev, "resume\n");
 692         if (is_sysmmu_active(data)) {
 693                 pm_runtime_get_sync(dev);
 694                 __sysmmu_enable_nocount(data);
 695         }
 696         return 0;
 697 }
 698 #endif
 699
 700 static const struct dev_pm_ops sysmmu_pm_ops = {
 701         SET_LATE_SYSTEM_SLEEP_PM_OPS(exynos_sysmmu_suspend, exynos_sysmmu_resume)
 702 };
 703
 704 static const struct of_device_id sysmmu_of_match[] __initconst = {
 705         { .compatible   = "samsung,exynos-sysmmu", },
 706         { },
 707 };
 708
 709 static struct platform_driver exynos_sysmmu_driver __refdata = {
 710         .probe  = exynos_sysmmu_probe,
 711         .driver = {
 712                 .name           = "exynos-sysmmu",
 713                 .of_match_table = sysmmu_of_match,
 714                 .pm             = &sysmmu_pm_ops,
 715                 .suppress_bind_attrs = true,
 716         }
 717 };
 718
 719 static inline void update_pte(sysmmu_pte_t *ent, sysmmu_pte_t val)
 720 {
 721         dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent), sizeof(*ent),
 722                                 DMA_TO_DEVICE);
 723         *ent = cpu_to_le32(val);
 724         dma_sync_single_for_device(dma_dev, virt_to_phys(ent), sizeof(*ent),
 725                                    DMA_TO_DEVICE);
 726 }
 727
 728 static struct iommu_domain *exynos_iommu_domain_alloc(unsigned type)
 729 {
 730         struct exynos_iommu_domain *domain;
 731         dma_addr_t handle;
 732         int i;
 733
 734         /* Check if correct PTE offsets are initialized */
 735         BUG_ON(PG_ENT_SHIFT < 0 || !dma_dev);
 736
 737         domain = kzalloc(sizeof(*domain), GFP_KERNEL);
 738         if (!domain)
 739                 return NULL;
 740
 741         if (type == IOMMU_DOMAIN_DMA) {
 742                 if (iommu_get_dma_cookie(&domain->domain) != 0)
 743                         goto err_pgtable;
 744         } else if (type != IOMMU_DOMAIN_UNMANAGED) {
 745                 goto err_pgtable;
 746         }
 747
 748         domain->pgtable = (sysmmu_pte_t *)__get_free_pages(GFP_KERNEL, 2);
 749         if (!domain->pgtable)
 750                 goto err_dma_cookie;
 751
 752         domain->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 1);
 753         if (!domain->lv2entcnt)
 754                 goto err_counter;
 755
 756         /* Workaround for System MMU v3.3 to prevent caching 1MiB mapping */
 757         for (i = 0; i < NUM_LV1ENTRIES; i += 8) {
 758                 domain->pgtable[i + 0] = ZERO_LV2LINK;
 759                 domain->pgtable[i + 1] = ZERO_LV2LINK;
 760                 domain->pgtable[i + 2] = ZERO_LV2LINK;
 761                 domain->pgtable[i + 3] = ZERO_LV2LINK;
 762                 domain->pgtable[i + 4] = ZERO_LV2LINK;
 763                 domain->pgtable[i + 5] = ZERO_LV2LINK;
 764                 domain->pgtable[i + 6] = ZERO_LV2LINK;
 765                 domain->pgtable[i + 7] = ZERO_LV2LINK;
 766         }
 767
 768         handle = dma_map_single(dma_dev, domain->pgtable, LV1TABLE_SIZE,
 769                                 DMA_TO_DEVICE);
 770         /* For mapping page table entries we rely on dma == phys */
 771         BUG_ON(handle != virt_to_phys(domain->pgtable));
 772
 773         spin_lock_init(&domain->lock);
 774         spin_lock_init(&domain->pgtablelock);
 775         INIT_LIST_HEAD(&domain->clients);
 776
 777         domain->domain.geometry.aperture_start = 0;
 778         domain->domain.geometry.aperture_end   = ~0UL;
 779         domain->domain.geometry.force_aperture = true;
 780
 781         return &domain->domain;
 782
 783 err_counter:
 784         free_pages((unsigned long)domain->pgtable, 2);
 785 err_dma_cookie:
 786         if (type == IOMMU_DOMAIN_DMA)
 787                 iommu_put_dma_cookie(&domain->domain);
 788 err_pgtable:
 789         kfree(domain);
 790         return NULL;
 791 }
 792
 793 static void exynos_iommu_domain_free(struct iommu_domain *iommu_domain)
 794 {
 795         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
 796         struct sysmmu_drvdata *data, *next;
 797         unsigned long flags;
 798         int i;
 799
 800         WARN_ON(!list_empty(&domain->clients));
 801
 802         spin_lock_irqsave(&domain->lock, flags);
 803
 804         list_for_each_entry_safe(data, next, &domain->clients, domain_node) {
 805                 if (__sysmmu_disable(data))
 806                         data->master = NULL;
 807                 list_del_init(&data->domain_node);
 808         }
 809
 810         spin_unlock_irqrestore(&domain->lock, flags);
 811
 812         if (iommu_domain->type == IOMMU_DOMAIN_DMA)
 813                 iommu_put_dma_cookie(iommu_domain);
 814
 815         dma_unmap_single(dma_dev, virt_to_phys(domain->pgtable), LV1TABLE_SIZE,
 816                          DMA_TO_DEVICE);
 817
 818         for (i = 0; i < NUM_LV1ENTRIES; i++)
 819                 if (lv1ent_page(domain->pgtable + i)) {
 820                         phys_addr_t base = lv2table_base(domain->pgtable + i);
 821
 822                         dma_unmap_single(dma_dev, base, LV2TABLE_SIZE,
 823                                          DMA_TO_DEVICE);
 824                         kmem_cache_free(lv2table_kmem_cache,
 825                                         phys_to_virt(base));
 826                 }
 827
 828         free_pages((unsigned long)domain->pgtable, 2);
 829         free_pages((unsigned long)domain->lv2entcnt, 1);
 830         kfree(domain);
 831 }
 832
 833 static void exynos_iommu_detach_device(struct iommu_domain *iommu_domain,
 834                                     struct device *dev)
 835 {
 836         struct exynos_iommu_owner *owner = dev->archdata.iommu;
 837         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
 838         phys_addr_t pagetable = virt_to_phys(domain->pgtable);
 839         struct sysmmu_drvdata *data, *next;
 840         unsigned long flags;
 841         bool found = false;
 842
 843         if (!has_sysmmu(dev) || owner->domain != iommu_domain)
 844                 return;
 845
 846         spin_lock_irqsave(&domain->lock, flags);
 847         list_for_each_entry_safe(data, next, &domain->clients, domain_node) {
 848                 if (data->master == dev) {
 849                         if (__sysmmu_disable(data)) {
 850                                 data->master = NULL;
 851                                 list_del_init(&data->domain_node);
 852                         }
 853                         pm_runtime_put(data->sysmmu);
 854                         found = true;
 855                 }
 856         }
 857         spin_unlock_irqrestore(&domain->lock, flags);
 858
 859         owner->domain = NULL;
 860
 861         if (found)
 862                 dev_dbg(dev, "%s: Detached IOMMU with pgtable %pa\n",
 863                                         __func__, &pagetable);
 864         else
 865                 dev_err(dev, "%s: No IOMMU is attached\n", __func__);
 866 }
 867
 868 static int exynos_iommu_attach_device(struct iommu_domain *iommu_domain,
 869                                    struct device *dev)
 870 {
 871         struct exynos_iommu_owner *owner = dev->archdata.iommu;
 872         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
 873         struct sysmmu_drvdata *data;
 874         phys_addr_t pagetable = virt_to_phys(domain->pgtable);
 875         unsigned long flags;
 876         int ret = -ENODEV;
 877
 878         if (!has_sysmmu(dev))
 879                 return -ENODEV;
 880
 881         if (owner->domain)
 882                 exynos_iommu_detach_device(owner->domain, dev);
 883
 884         list_for_each_entry(data, &owner->controllers, owner_node) {
 885                 pm_runtime_get_sync(data->sysmmu);
 886                 ret = __sysmmu_enable(data, pagetable, domain);
 887                 if (ret >= 0) {
 888                         data->master = dev;
 889
 890                         spin_lock_irqsave(&domain->lock, flags);
 891                         list_add_tail(&data->domain_node, &domain->clients);
 892                         spin_unlock_irqrestore(&domain->lock, flags);
 893                 }
 894         }
 895
 896         if (ret < 0) {
 897                 dev_err(dev, "%s: Failed to attach IOMMU with pgtable %pa\n",
 898                                         __func__, &pagetable);
 899                 return ret;
 900         }
 901
 902         owner->domain = iommu_domain;
 903         dev_dbg(dev, "%s: Attached IOMMU with pgtable %pa %s\n",
 904                 __func__, &pagetable, (ret == 0) ? "" : ", again");
 905
 906         return ret;
 907 }
 908
 909 static sysmmu_pte_t *alloc_lv2entry(struct exynos_iommu_domain *domain,
 910                 sysmmu_pte_t *sent, sysmmu_iova_t iova, short *pgcounter)
 911 {
 912         if (lv1ent_section(sent)) {
 913                 WARN(1, "Trying mapping on %#08x mapped with 1MiB page", iova);
 914                 return ERR_PTR(-EADDRINUSE);
 915         }
 916
 917         if (lv1ent_fault(sent)) {
 918                 sysmmu_pte_t *pent;
 919                 bool need_flush_flpd_cache = lv1ent_zero(sent);
 920
 921                 pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC);
 922                 BUG_ON((uintptr_t)pent & (LV2TABLE_SIZE - 1));
 923                 if (!pent)
 924                         return ERR_PTR(-ENOMEM);
 925
 926                 update_pte(sent, mk_lv1ent_page(virt_to_phys(pent)));
 927                 kmemleak_ignore(pent);
 928                 *pgcounter = NUM_LV2ENTRIES;
 929                 dma_map_single(dma_dev, pent, LV2TABLE_SIZE, DMA_TO_DEVICE);
 930
 931                 /*
 932                  * If pre-fetched SLPD is a faulty SLPD in zero_l2_table,
 933                  * FLPD cache may cache the address of zero_l2_table. This
 934                  * function replaces the zero_l2_table with new L2 page table
 935                  * to write valid mappings.
 936                  * Accessing the valid area may cause page fault since FLPD
 937                  * cache may still cache zero_l2_table for the valid area
 938                  * instead of new L2 page table that has the mapping
 939                  * information of the valid area.
 940                  * Thus any replacement of zero_l2_table with other valid L2
 941                  * page table must involve FLPD cache invalidation for System
 942                  * MMU v3.3.
 943                  * FLPD cache invalidation is performed with TLB invalidation
 944                  * by VPN without blocking. It is safe to invalidate TLB without
 945                  * blocking because the target address of TLB invalidation is
 946                  * not currently mapped.
 947                  */
 948                 if (need_flush_flpd_cache) {
 949                         struct sysmmu_drvdata *data;
 950
 951                         spin_lock(&domain->lock);
 952                         list_for_each_entry(data, &domain->clients, domain_node)
 953                                 sysmmu_tlb_invalidate_flpdcache(data, iova);
 954                         spin_unlock(&domain->lock);
 955                 }
 956         }
 957
 958         return page_entry(sent, iova);
 959 }
 960
 961 static int lv1set_section(struct exynos_iommu_domain *domain,
 962                           sysmmu_pte_t *sent, sysmmu_iova_t iova,
 963                           phys_addr_t paddr, short *pgcnt)
 964 {
 965         if (lv1ent_section(sent)) {
 966                 WARN(1, "Trying mapping on 1MiB@%#08x that is mapped",
 967                         iova);
 968                 return -EADDRINUSE;
 969         }
 970
 971         if (lv1ent_page(sent)) {
 972                 if (*pgcnt != NUM_LV2ENTRIES) {
 973                         WARN(1, "Trying mapping on 1MiB@%#08x that is mapped",
 974                                 iova);
 975                         return -EADDRINUSE;
 976                 }
 977
 978                 kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0));
 979                 *pgcnt = 0;
 980         }
 981
 982         update_pte(sent, mk_lv1ent_sect(paddr));
 983
 984         spin_lock(&domain->lock);
 985         if (lv1ent_page_zero(sent)) {
 986                 struct sysmmu_drvdata *data;
 987                 /*
 988                  * Flushing FLPD cache in System MMU v3.3 that may cache a FLPD
 989                  * entry by speculative prefetch of SLPD which has no mapping.
 990                  */
 991                 list_for_each_entry(data, &domain->clients, domain_node)
 992                         sysmmu_tlb_invalidate_flpdcache(data, iova);
 993         }
 994         spin_unlock(&domain->lock);
 995
 996         return 0;
 997 }
 998
 999 static int lv2set_page(sysmmu_pte_t *pent, phys_addr_t paddr, size_t size,
1000                                                                 short *pgcnt)
1001 {
1002         if (size == SPAGE_SIZE) {
1003                 if (WARN_ON(!lv2ent_fault(pent)))
1004                         return -EADDRINUSE;
1005
1006                 update_pte(pent, mk_lv2ent_spage(paddr));
1007                 *pgcnt -= 1;
1008         } else { /* size == LPAGE_SIZE */
1009                 int i;
1010                 dma_addr_t pent_base = virt_to_phys(pent);
1011
1012                 dma_sync_single_for_cpu(dma_dev, pent_base,
1013                                         sizeof(*pent) * SPAGES_PER_LPAGE,
1014                                         DMA_TO_DEVICE);
1015                 for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) {
1016                         if (WARN_ON(!lv2ent_fault(pent))) {
1017                                 if (i > 0)
1018                                         memset(pent - i, 0, sizeof(*pent) * i);
1019                                 return -EADDRINUSE;
1020                         }
1021
1022                         *pent = mk_lv2ent_lpage(paddr);
1023                 }
1024                 dma_sync_single_for_device(dma_dev, pent_base,
1025                                            sizeof(*pent) * SPAGES_PER_LPAGE,
1026                                            DMA_TO_DEVICE);
1027                 *pgcnt -= SPAGES_PER_LPAGE;
1028         }
1029
1030         return 0;
1031 }
1032
1033 /*
1034  * *CAUTION* to the I/O virtual memory managers that support exynos-iommu:
1035  *
1036  * System MMU v3.x has advanced logic to improve address translation
1037  * performance with caching more page table entries by a page table walk.
1038  * However, the logic has a bug that while caching faulty page table entries,
1039  * System MMU reports page fault if the cached fault entry is hit even though
1040  * the fault entry is updated to a valid entry after the entry is cached.
1041  * To prevent caching faulty page table entries which may be updated to valid
1042  * entries later, the virtual memory manager should care about the workaround
1043  * for the problem. The following describes the workaround.
1044  *
1045  * Any two consecutive I/O virtual address regions must have a hole of 128KiB
1046  * at maximum to prevent misbehavior of System MMU 3.x (workaround for h/w bug).
1047  *
1048  * Precisely, any start address of I/O virtual region must be aligned with
1049  * the following sizes for System MMU v3.1 and v3.2.
1050  * System MMU v3.1: 128KiB
1051  * System MMU v3.2: 256KiB
1052  *
1053  * Because System MMU v3.3 caches page table entries more aggressively, it needs
1054  * more workarounds.
1055  * - Any two consecutive I/O virtual regions must have a hole of size larger
1056  *   than or equal to 128KiB.
1057  * - Start address of an I/O virtual region must be aligned by 128KiB.
1058  */
1059 static int exynos_iommu_map(struct iommu_domain *iommu_domain,
1060                             unsigned long l_iova, phys_addr_t paddr, size_t size,
1061                             int prot)
1062 {
1063         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
1064         sysmmu_pte_t *entry;
1065         sysmmu_iova_t iova = (sysmmu_iova_t)l_iova;
1066         unsigned long flags;
1067         int ret = -ENOMEM;
1068
1069         BUG_ON(domain->pgtable == NULL);
1070
1071         spin_lock_irqsave(&domain->pgtablelock, flags);
1072
1073         entry = section_entry(domain->pgtable, iova);
1074
1075         if (size == SECT_SIZE) {
1076                 ret = lv1set_section(domain, entry, iova, paddr,
1077                                      &domain->lv2entcnt[lv1ent_offset(iova)]);
1078         } else {
1079                 sysmmu_pte_t *pent;
1080
1081                 pent = alloc_lv2entry(domain, entry, iova,
1082                                       &domain->lv2entcnt[lv1ent_offset(iova)]);
1083
1084                 if (IS_ERR(pent))
1085                         ret = PTR_ERR(pent);
1086                 else
1087                         ret = lv2set_page(pent, paddr, size,
1088                                        &domain->lv2entcnt[lv1ent_offset(iova)]);
1089         }
1090
1091         if (ret)
1092                 pr_err("%s: Failed(%d) to map %#zx bytes @ %#x\n",
1093                         __func__, ret, size, iova);
1094
1095         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1096
1097         return ret;
1098 }
1099
1100 static void exynos_iommu_tlb_invalidate_entry(struct exynos_iommu_domain *domain,
1101                                               sysmmu_iova_t iova, size_t size)
1102 {
1103         struct sysmmu_drvdata *data;
1104         unsigned long flags;
1105
1106         spin_lock_irqsave(&domain->lock, flags);
1107
1108         list_for_each_entry(data, &domain->clients, domain_node)
1109                 sysmmu_tlb_invalidate_entry(data, iova, size);
1110
1111         spin_unlock_irqrestore(&domain->lock, flags);
1112 }
1113
1114 static size_t exynos_iommu_unmap(struct iommu_domain *iommu_domain,
1115                                  unsigned long l_iova, size_t size)
1116 {
1117         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
1118         sysmmu_iova_t iova = (sysmmu_iova_t)l_iova;
1119         sysmmu_pte_t *ent;
1120         size_t err_pgsize;
1121         unsigned long flags;
1122
1123         BUG_ON(domain->pgtable == NULL);
1124
1125         spin_lock_irqsave(&domain->pgtablelock, flags);
1126
1127         ent = section_entry(domain->pgtable, iova);
1128
1129         if (lv1ent_section(ent)) {
1130                 if (WARN_ON(size < SECT_SIZE)) {
1131                         err_pgsize = SECT_SIZE;
1132                         goto err;
1133                 }
1134
1135                 /* workaround for h/w bug in System MMU v3.3 */
1136                 update_pte(ent, ZERO_LV2LINK);
1137                 size = SECT_SIZE;
1138                 goto done;
1139         }
1140
1141         if (unlikely(lv1ent_fault(ent))) {
1142                 if (size > SECT_SIZE)
1143                         size = SECT_SIZE;
1144                 goto done;
1145         }
1146
1147         /* lv1ent_page(sent) == true here */
1148
1149         ent = page_entry(ent, iova);
1150
1151         if (unlikely(lv2ent_fault(ent))) {
1152                 size = SPAGE_SIZE;
1153                 goto done;
1154         }
1155
1156         if (lv2ent_small(ent)) {
1157                 update_pte(ent, 0);
1158                 size = SPAGE_SIZE;
1159                 domain->lv2entcnt[lv1ent_offset(iova)] += 1;
1160                 goto done;
1161         }
1162
1163         /* lv1ent_large(ent) == true here */
1164         if (WARN_ON(size < LPAGE_SIZE)) {
1165                 err_pgsize = LPAGE_SIZE;
1166                 goto err;
1167         }
1168
1169         dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent),
1170                                 sizeof(*ent) * SPAGES_PER_LPAGE,
1171                                 DMA_TO_DEVICE);
1172         memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE);
1173         dma_sync_single_for_device(dma_dev, virt_to_phys(ent),
1174                                    sizeof(*ent) * SPAGES_PER_LPAGE,
1175                                    DMA_TO_DEVICE);
1176         size = LPAGE_SIZE;
1177         domain->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE;
1178 done:
1179         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1180
1181         exynos_iommu_tlb_invalidate_entry(domain, iova, size);
1182
1183         return size;
1184 err:
1185         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1186
1187         pr_err("%s: Failed: size(%#zx) @ %#x is smaller than page size %#zx\n",
1188                 __func__, size, iova, err_pgsize);
1189
1190         return 0;
1191 }
1192
1193 static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *iommu_domain,
1194                                           dma_addr_t iova)
1195 {
1196         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
1197         sysmmu_pte_t *entry;
1198         unsigned long flags;
1199         phys_addr_t phys = 0;
1200
1201         spin_lock_irqsave(&domain->pgtablelock, flags);
1202
1203         entry = section_entry(domain->pgtable, iova);
1204
1205         if (lv1ent_section(entry)) {
1206                 phys = section_phys(entry) + section_offs(iova);
1207         } else if (lv1ent_page(entry)) {
1208                 entry = page_entry(entry, iova);
1209
1210                 if (lv2ent_large(entry))
1211                         phys = lpage_phys(entry) + lpage_offs(iova);
1212                 else if (lv2ent_small(entry))
1213                         phys = spage_phys(entry) + spage_offs(iova);
1214         }
1215
1216         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1217
1218         return phys;
1219 }
1220
1221 static struct iommu_group *get_device_iommu_group(struct device *dev)
1222 {
1223         struct iommu_group *group;
1224
1225         group = iommu_group_get(dev);
1226         if (!group)
1227                 group = iommu_group_alloc();
1228
1229         return group;
1230 }
1231
1232 static int exynos_iommu_add_device(struct device *dev)
1233 {
1234         struct iommu_group *group;
1235
1236         if (!has_sysmmu(dev))
1237                 return -ENODEV;
1238
1239         group = iommu_group_get_for_dev(dev);
1240
1241         if (IS_ERR(group))
1242                 return PTR_ERR(group);
1243
1244         iommu_group_put(group);
1245
1246         return 0;
1247 }
1248
1249 static void exynos_iommu_remove_device(struct device *dev)
1250 {
1251         if (!has_sysmmu(dev))
1252                 return;
1253
1254         iommu_group_remove_device(dev);
1255 }
1256
1257 static int exynos_iommu_of_xlate(struct device *dev,
1258                                  struct of_phandle_args *spec)
1259 {
1260         struct exynos_iommu_owner *owner = dev->archdata.iommu;
1261         struct platform_device *sysmmu = of_find_device_by_node(spec->np);
1262         struct sysmmu_drvdata *data;
1263
1264         if (!sysmmu)
1265                 return -ENODEV;
1266
1267         data = platform_get_drvdata(sysmmu);
1268         if (!data) {
1269                 put_device(&sysmmu->dev);
1270                 return -ENODEV;
1271         }
1272
1273         if (!owner) {
1274                 owner = kzalloc(sizeof(*owner), GFP_KERNEL);
1275                 if (!owner) {
1276                         put_device(&sysmmu->dev);
1277                         return -ENOMEM;
1278                 }
1279
1280                 INIT_LIST_HEAD(&owner->controllers);
1281                 dev->archdata.iommu = owner;
1282         }
1283
1284         list_add_tail(&data->owner_node, &owner->controllers);
1285         return 0;
1286 }
1287
1288 static struct iommu_ops exynos_iommu_ops = {
1289         .domain_alloc = exynos_iommu_domain_alloc,
1290         .domain_free = exynos_iommu_domain_free,
1291         .attach_dev = exynos_iommu_attach_device,
1292         .detach_dev = exynos_iommu_detach_device,
1293         .map = exynos_iommu_map,
1294         .unmap = exynos_iommu_unmap,
1295         .map_sg = default_iommu_map_sg,
1296         .iova_to_phys = exynos_iommu_iova_to_phys,
1297         .device_group = get_device_iommu_group,
1298         .add_device = exynos_iommu_add_device,
1299         .remove_device = exynos_iommu_remove_device,
1300         .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE,
1301         .of_xlate = exynos_iommu_of_xlate,
1302 };
1303
1304 static bool init_done;
1305
1306 static int __init exynos_iommu_init(void)
1307 {
1308         int ret;
1309
1310         lv2table_kmem_cache = kmem_cache_create("exynos-iommu-lv2table",
1311                                 LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL);
1312         if (!lv2table_kmem_cache) {
1313                 pr_err("%s: Failed to create kmem cache\n", __func__);
1314                 return -ENOMEM;
1315         }
1316
1317         ret = platform_driver_register(&exynos_sysmmu_driver);
1318         if (ret) {
1319                 pr_err("%s: Failed to register driver\n", __func__);
1320                 goto err_reg_driver;
1321         }
1322
1323         zero_lv2_table = kmem_cache_zalloc(lv2table_kmem_cache, GFP_KERNEL);
1324         if (zero_lv2_table == NULL) {
1325                 pr_err("%s: Failed to allocate zero level2 page table\n",
1326                         __func__);
1327                 ret = -ENOMEM;
1328                 goto err_zero_lv2;
1329         }
1330
1331         ret = bus_set_iommu(&platform_bus_type, &exynos_iommu_ops);
1332         if (ret) {
1333                 pr_err("%s: Failed to register exynos-iommu driver.\n",
1334                                                                 __func__);
1335                 goto err_set_iommu;
1336         }
1337
1338         init_done = true;
1339
1340         return 0;
1341 err_set_iommu:
1342         kmem_cache_free(lv2table_kmem_cache, zero_lv2_table);
1343 err_zero_lv2:
1344         platform_driver_unregister(&exynos_sysmmu_driver);
1345 err_reg_driver:
1346         kmem_cache_destroy(lv2table_kmem_cache);
1347         return ret;
1348 }
1349
1350 static int __init exynos_iommu_of_setup(struct device_node *np)
1351 {
1352         struct platform_device *pdev;
1353
1354         if (!init_done)
1355                 exynos_iommu_init();
1356
1357         pdev = of_platform_device_create(np, NULL, platform_bus_type.dev_root);
1358         if (!pdev)
1359                 return -ENODEV;
1360
1361         /*
1362          * use the first registered sysmmu device for performing
1363          * dma mapping operations on iommu page tables (cpu cache flush)
1364          */
1365         if (!dma_dev)
1366                 dma_dev = &pdev->dev;
1367
1368         return 0;
1369 }
1370
1371 IOMMU_OF_DECLARE(exynos_iommu_of, "samsung,exynos-sysmmu",
1372                  exynos_iommu_of_setup);