1 // SPDX-License-Identifier: GPL-2.0
3 #define pr_fmt(fmt) "DMAR-IR: " fmt
5 #include <linux/interrupt.h>
6 #include <linux/dmar.h>
7 #include <linux/spinlock.h>
8 #include <linux/slab.h>
9 #include <linux/jiffies.h>
10 #include <linux/hpet.h>
11 #include <linux/pci.h>
12 #include <linux/irq.h>
13 #include <linux/intel-iommu.h>
14 #include <linux/acpi.h>
15 #include <linux/irqdomain.h>
16 #include <linux/crash_dump.h>
17 #include <asm/io_apic.h>
20 #include <asm/irq_remapping.h>
21 #include <asm/pci-direct.h>
22 #include <asm/msidef.h>
24 #include "irq_remapping.h"
32 struct intel_iommu *iommu;
34 unsigned int bus; /* PCI bus number */
35 unsigned int devfn; /* PCI devfn number */
39 struct intel_iommu *iommu;
46 struct intel_iommu *iommu;
53 struct intel_ir_data {
54 struct irq_2_iommu irq_2_iommu;
55 struct irte irte_entry;
57 struct msi_msg msi_entry;
61 #define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0)
62 #define IRTE_DEST(dest) ((eim_mode) ? dest : dest << 8)
64 static int __read_mostly eim_mode;
65 static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
66 static struct hpet_scope ir_hpet[MAX_HPET_TBS];
73 * ->iommu->register_lock
75 * intel_irq_remap_ops.{supported,prepare,enable,disable,reenable} are called
76 * in single-threaded environment with interrupt disabled, so no need to tabke
77 * the dmar_global_lock.
79 static DEFINE_RAW_SPINLOCK(irq_2_ir_lock);
80 static const struct irq_domain_ops intel_ir_domain_ops;
82 static void iommu_disable_irq_remapping(struct intel_iommu *iommu);
83 static int __init parse_ioapics_under_ir(void);
85 static bool ir_pre_enabled(struct intel_iommu *iommu)
87 return (iommu->flags & VTD_FLAG_IRQ_REMAP_PRE_ENABLED);
90 static void clear_ir_pre_enabled(struct intel_iommu *iommu)
92 iommu->flags &= ~VTD_FLAG_IRQ_REMAP_PRE_ENABLED;
95 static void init_ir_status(struct intel_iommu *iommu)
99 gsts = readl(iommu->reg + DMAR_GSTS_REG);
100 if (gsts & DMA_GSTS_IRES)
101 iommu->flags |= VTD_FLAG_IRQ_REMAP_PRE_ENABLED;
104 static int alloc_irte(struct intel_iommu *iommu, int irq,
105 struct irq_2_iommu *irq_iommu, u16 count)
107 struct ir_table *table = iommu->ir_table;
108 unsigned int mask = 0;
112 if (!count || !irq_iommu)
116 count = __roundup_pow_of_two(count);
120 if (mask > ecap_max_handle_mask(iommu->ecap)) {
121 pr_err("Requested mask %x exceeds the max invalidation handle"
122 " mask value %Lx\n", mask,
123 ecap_max_handle_mask(iommu->ecap));
127 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
128 index = bitmap_find_free_region(table->bitmap,
129 INTR_REMAP_TABLE_ENTRIES, mask);
131 pr_warn("IR%d: can't allocate an IRTE\n", iommu->seq_id);
133 irq_iommu->iommu = iommu;
134 irq_iommu->irte_index = index;
135 irq_iommu->sub_handle = 0;
136 irq_iommu->irte_mask = mask;
137 irq_iommu->mode = IRQ_REMAPPING;
139 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
144 static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
148 desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
152 return qi_submit_sync(&desc, iommu);
155 static int modify_irte(struct irq_2_iommu *irq_iommu,
156 struct irte *irte_modified)
158 struct intel_iommu *iommu;
166 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
168 iommu = irq_iommu->iommu;
170 index = irq_iommu->irte_index + irq_iommu->sub_handle;
171 irte = &iommu->ir_table->base[index];
173 #if defined(CONFIG_HAVE_CMPXCHG_DOUBLE)
174 if ((irte->pst == 1) || (irte_modified->pst == 1)) {
177 ret = cmpxchg_double(&irte->low, &irte->high,
178 irte->low, irte->high,
179 irte_modified->low, irte_modified->high);
181 * We use cmpxchg16 to atomically update the 128-bit IRTE,
182 * and it cannot be updated by the hardware or other processors
183 * behind us, so the return value of cmpxchg16 should be the
184 * same as the old value.
190 set_64bit(&irte->low, irte_modified->low);
191 set_64bit(&irte->high, irte_modified->high);
193 __iommu_flush_cache(iommu, irte, sizeof(*irte));
195 rc = qi_flush_iec(iommu, index, 0);
197 /* Update iommu mode according to the IRTE mode */
198 irq_iommu->mode = irte->pst ? IRQ_POSTING : IRQ_REMAPPING;
199 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
204 static struct intel_iommu *map_hpet_to_ir(u8 hpet_id)
208 for (i = 0; i < MAX_HPET_TBS; i++)
209 if (ir_hpet[i].id == hpet_id && ir_hpet[i].iommu)
210 return ir_hpet[i].iommu;
214 static struct intel_iommu *map_ioapic_to_ir(int apic)
218 for (i = 0; i < MAX_IO_APICS; i++)
219 if (ir_ioapic[i].id == apic && ir_ioapic[i].iommu)
220 return ir_ioapic[i].iommu;
224 static struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
226 struct dmar_drhd_unit *drhd;
228 drhd = dmar_find_matched_drhd_unit(dev);
235 static int clear_entries(struct irq_2_iommu *irq_iommu)
237 struct irte *start, *entry, *end;
238 struct intel_iommu *iommu;
241 if (irq_iommu->sub_handle)
244 iommu = irq_iommu->iommu;
245 index = irq_iommu->irte_index;
247 start = iommu->ir_table->base + index;
248 end = start + (1 << irq_iommu->irte_mask);
250 for (entry = start; entry < end; entry++) {
251 set_64bit(&entry->low, 0);
252 set_64bit(&entry->high, 0);
254 bitmap_release_region(iommu->ir_table->bitmap, index,
255 irq_iommu->irte_mask);
257 return qi_flush_iec(iommu, index, irq_iommu->irte_mask);
261 * source validation type
263 #define SVT_NO_VERIFY 0x0 /* no verification is required */
264 #define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fields */
265 #define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */
268 * source-id qualifier
270 #define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */
271 #define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore
272 * the third least significant bit
274 #define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore
275 * the second and third least significant bits
277 #define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore
278 * the least three significant bits
282 * set SVT, SQ and SID fields of irte to verify
283 * source ids of interrupt requests
285 static void set_irte_sid(struct irte *irte, unsigned int svt,
286 unsigned int sq, unsigned int sid)
288 if (disable_sourceid_checking)
295 static int set_ioapic_sid(struct irte *irte, int apic)
303 down_read(&dmar_global_lock);
304 for (i = 0; i < MAX_IO_APICS; i++) {
305 if (ir_ioapic[i].iommu && ir_ioapic[i].id == apic) {
306 sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn;
310 up_read(&dmar_global_lock);
313 pr_warn("Failed to set source-id of IOAPIC (%d)\n", apic);
317 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, sid);
322 static int set_hpet_sid(struct irte *irte, u8 id)
330 down_read(&dmar_global_lock);
331 for (i = 0; i < MAX_HPET_TBS; i++) {
332 if (ir_hpet[i].iommu && ir_hpet[i].id == id) {
333 sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn;
337 up_read(&dmar_global_lock);
340 pr_warn("Failed to set source-id of HPET block (%d)\n", id);
345 * Should really use SQ_ALL_16. Some platforms are broken.
346 * While we figure out the right quirks for these broken platforms, use
347 * SQ_13_IGNORE_3 for now.
349 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid);
354 struct set_msi_sid_data {
355 struct pci_dev *pdev;
359 static int set_msi_sid_cb(struct pci_dev *pdev, u16 alias, void *opaque)
361 struct set_msi_sid_data *data = opaque;
369 static int set_msi_sid(struct irte *irte, struct pci_dev *dev)
371 struct set_msi_sid_data data;
376 pci_for_each_dma_alias(dev, set_msi_sid_cb, &data);
379 * DMA alias provides us with a PCI device and alias. The only case
380 * where the it will return an alias on a different bus than the
381 * device is the case of a PCIe-to-PCI bridge, where the alias is for
382 * the subordinate bus. In this case we can only verify the bus.
384 * If the alias device is on a different bus than our source device
385 * then we have a topology based alias, use it.
387 * Otherwise, the alias is for a device DMA quirk and we cannot
388 * assume that MSI uses the same requester ID. Therefore use the
391 if (PCI_BUS_NUM(data.alias) != data.pdev->bus->number)
392 set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16,
393 PCI_DEVID(PCI_BUS_NUM(data.alias),
395 else if (data.pdev->bus->number != dev->bus->number)
396 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, data.alias);
398 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16,
399 PCI_DEVID(dev->bus->number, dev->devfn));
404 static int iommu_load_old_irte(struct intel_iommu *iommu)
406 struct irte *old_ir_table;
407 phys_addr_t irt_phys;
412 /* Check whether the old ir-table has the same size as ours */
413 irta = dmar_readq(iommu->reg + DMAR_IRTA_REG);
414 if ((irta & INTR_REMAP_TABLE_REG_SIZE_MASK)
415 != INTR_REMAP_TABLE_REG_SIZE)
418 irt_phys = irta & VTD_PAGE_MASK;
419 size = INTR_REMAP_TABLE_ENTRIES*sizeof(struct irte);
421 /* Map the old IR table */
422 old_ir_table = memremap(irt_phys, size, MEMREMAP_WB);
427 memcpy(iommu->ir_table->base, old_ir_table, size);
429 __iommu_flush_cache(iommu, iommu->ir_table->base, size);
432 * Now check the table for used entries and mark those as
433 * allocated in the bitmap
435 for (i = 0; i < INTR_REMAP_TABLE_ENTRIES; i++) {
436 if (iommu->ir_table->base[i].present)
437 bitmap_set(iommu->ir_table->bitmap, i, 1);
440 memunmap(old_ir_table);
446 static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode)
452 addr = virt_to_phys((void *)iommu->ir_table->base);
454 raw_spin_lock_irqsave(&iommu->register_lock, flags);
456 dmar_writeq(iommu->reg + DMAR_IRTA_REG,
457 (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
459 /* Set interrupt-remapping table pointer */
460 writel(iommu->gcmd | DMA_GCMD_SIRTP, iommu->reg + DMAR_GCMD_REG);
462 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
463 readl, (sts & DMA_GSTS_IRTPS), sts);
464 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
467 * Global invalidation of interrupt entry cache to make sure the
468 * hardware uses the new irq remapping table.
470 qi_global_iec(iommu);
473 static void iommu_enable_irq_remapping(struct intel_iommu *iommu)
478 raw_spin_lock_irqsave(&iommu->register_lock, flags);
480 /* Enable interrupt-remapping */
481 iommu->gcmd |= DMA_GCMD_IRE;
482 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
483 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
484 readl, (sts & DMA_GSTS_IRES), sts);
486 /* Block compatibility-format MSIs */
487 if (sts & DMA_GSTS_CFIS) {
488 iommu->gcmd &= ~DMA_GCMD_CFI;
489 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
490 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
491 readl, !(sts & DMA_GSTS_CFIS), sts);
495 * With CFI clear in the Global Command register, we should be
496 * protected from dangerous (i.e. compatibility) interrupts
497 * regardless of x2apic status. Check just to be sure.
499 if (sts & DMA_GSTS_CFIS)
501 "Compatibility-format IRQs enabled despite intr remapping;\n"
502 "you are vulnerable to IRQ injection.\n");
504 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
507 static int intel_setup_irq_remapping(struct intel_iommu *iommu)
509 struct ir_table *ir_table;
510 struct fwnode_handle *fn;
511 unsigned long *bitmap;
517 ir_table = kzalloc(sizeof(struct ir_table), GFP_KERNEL);
521 pages = alloc_pages_node(iommu->node, GFP_KERNEL | __GFP_ZERO,
522 INTR_REMAP_PAGE_ORDER);
524 pr_err("IR%d: failed to allocate pages of order %d\n",
525 iommu->seq_id, INTR_REMAP_PAGE_ORDER);
529 bitmap = kcalloc(BITS_TO_LONGS(INTR_REMAP_TABLE_ENTRIES),
530 sizeof(long), GFP_ATOMIC);
531 if (bitmap == NULL) {
532 pr_err("IR%d: failed to allocate bitmap\n", iommu->seq_id);
536 fn = irq_domain_alloc_named_id_fwnode("INTEL-IR", iommu->seq_id);
538 goto out_free_bitmap;
541 irq_domain_create_hierarchy(arch_get_ir_parent_domain(),
542 0, INTR_REMAP_TABLE_ENTRIES,
543 fn, &intel_ir_domain_ops,
545 if (!iommu->ir_domain) {
546 pr_err("IR%d: failed to allocate irqdomain\n", iommu->seq_id);
547 goto out_free_fwnode;
549 iommu->ir_msi_domain =
550 arch_create_remap_msi_irq_domain(iommu->ir_domain,
554 ir_table->base = page_address(pages);
555 ir_table->bitmap = bitmap;
556 iommu->ir_table = ir_table;
559 * If the queued invalidation is already initialized,
560 * shouldn't disable it.
564 * Clear previous faults.
566 dmar_fault(-1, iommu);
567 dmar_disable_qi(iommu);
569 if (dmar_enable_qi(iommu)) {
570 pr_err("Failed to enable queued invalidation\n");
571 goto out_free_ir_domain;
575 init_ir_status(iommu);
577 if (ir_pre_enabled(iommu)) {
578 if (!is_kdump_kernel()) {
579 pr_warn("IRQ remapping was enabled on %s but we are not in kdump mode\n",
581 clear_ir_pre_enabled(iommu);
582 iommu_disable_irq_remapping(iommu);
583 } else if (iommu_load_old_irte(iommu))
584 pr_err("Failed to copy IR table for %s from previous kernel\n",
587 pr_info("Copied IR table for %s from previous kernel\n",
591 iommu_set_irq_remapping(iommu, eim_mode);
596 if (iommu->ir_msi_domain)
597 irq_domain_remove(iommu->ir_msi_domain);
598 iommu->ir_msi_domain = NULL;
599 irq_domain_remove(iommu->ir_domain);
600 iommu->ir_domain = NULL;
602 irq_domain_free_fwnode(fn);
606 __free_pages(pages, INTR_REMAP_PAGE_ORDER);
610 iommu->ir_table = NULL;
615 static void intel_teardown_irq_remapping(struct intel_iommu *iommu)
617 struct fwnode_handle *fn;
619 if (iommu && iommu->ir_table) {
620 if (iommu->ir_msi_domain) {
621 fn = iommu->ir_msi_domain->fwnode;
623 irq_domain_remove(iommu->ir_msi_domain);
624 irq_domain_free_fwnode(fn);
625 iommu->ir_msi_domain = NULL;
627 if (iommu->ir_domain) {
628 fn = iommu->ir_domain->fwnode;
630 irq_domain_remove(iommu->ir_domain);
631 irq_domain_free_fwnode(fn);
632 iommu->ir_domain = NULL;
634 free_pages((unsigned long)iommu->ir_table->base,
635 INTR_REMAP_PAGE_ORDER);
636 kfree(iommu->ir_table->bitmap);
637 kfree(iommu->ir_table);
638 iommu->ir_table = NULL;
643 * Disable Interrupt Remapping.
645 static void iommu_disable_irq_remapping(struct intel_iommu *iommu)
650 if (!ecap_ir_support(iommu->ecap))
654 * global invalidation of interrupt entry cache before disabling
655 * interrupt-remapping.
657 qi_global_iec(iommu);
659 raw_spin_lock_irqsave(&iommu->register_lock, flags);
661 sts = readl(iommu->reg + DMAR_GSTS_REG);
662 if (!(sts & DMA_GSTS_IRES))
665 iommu->gcmd &= ~DMA_GCMD_IRE;
666 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
668 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
669 readl, !(sts & DMA_GSTS_IRES), sts);
672 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
675 static int __init dmar_x2apic_optout(void)
677 struct acpi_table_dmar *dmar;
678 dmar = (struct acpi_table_dmar *)dmar_tbl;
679 if (!dmar || no_x2apic_optout)
681 return dmar->flags & DMAR_X2APIC_OPT_OUT;
684 static void __init intel_cleanup_irq_remapping(void)
686 struct dmar_drhd_unit *drhd;
687 struct intel_iommu *iommu;
689 for_each_iommu(iommu, drhd) {
690 if (ecap_ir_support(iommu->ecap)) {
691 iommu_disable_irq_remapping(iommu);
692 intel_teardown_irq_remapping(iommu);
696 if (x2apic_supported())
697 pr_warn("Failed to enable irq remapping. You are vulnerable to irq-injection attacks.\n");
700 static int __init intel_prepare_irq_remapping(void)
702 struct dmar_drhd_unit *drhd;
703 struct intel_iommu *iommu;
706 if (irq_remap_broken) {
707 pr_warn("This system BIOS has enabled interrupt remapping\n"
708 "on a chipset that contains an erratum making that\n"
709 "feature unstable. To maintain system stability\n"
710 "interrupt remapping is being disabled. Please\n"
711 "contact your BIOS vendor for an update\n");
712 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
716 if (dmar_table_init() < 0)
719 if (!dmar_ir_support())
722 if (parse_ioapics_under_ir()) {
723 pr_info("Not enabling interrupt remapping\n");
727 /* First make sure all IOMMUs support IRQ remapping */
728 for_each_iommu(iommu, drhd)
729 if (!ecap_ir_support(iommu->ecap))
732 /* Detect remapping mode: lapic or x2apic */
733 if (x2apic_supported()) {
734 eim = !dmar_x2apic_optout();
736 pr_info("x2apic is disabled because BIOS sets x2apic opt out bit.");
737 pr_info("Use 'intremap=no_x2apic_optout' to override the BIOS setting.\n");
741 for_each_iommu(iommu, drhd) {
742 if (eim && !ecap_eim_support(iommu->ecap)) {
743 pr_info("%s does not support EIM\n", iommu->name);
750 pr_info("Queued invalidation will be enabled to support x2apic and Intr-remapping.\n");
752 /* Do the initializations early */
753 for_each_iommu(iommu, drhd) {
754 if (intel_setup_irq_remapping(iommu)) {
755 pr_err("Failed to setup irq remapping for %s\n",
764 intel_cleanup_irq_remapping();
769 * Set Posted-Interrupts capability.
771 static inline void set_irq_posting_cap(void)
773 struct dmar_drhd_unit *drhd;
774 struct intel_iommu *iommu;
776 if (!disable_irq_post) {
778 * If IRTE is in posted format, the 'pda' field goes across the
779 * 64-bit boundary, we need use cmpxchg16b to atomically update
780 * it. We only expose posted-interrupt when X86_FEATURE_CX16
781 * is supported. Actually, hardware platforms supporting PI
782 * should have X86_FEATURE_CX16 support, this has been confirmed
783 * with Intel hardware guys.
785 if (boot_cpu_has(X86_FEATURE_CX16))
786 intel_irq_remap_ops.capability |= 1 << IRQ_POSTING_CAP;
788 for_each_iommu(iommu, drhd)
789 if (!cap_pi_support(iommu->cap)) {
790 intel_irq_remap_ops.capability &=
791 ~(1 << IRQ_POSTING_CAP);
797 static int __init intel_enable_irq_remapping(void)
799 struct dmar_drhd_unit *drhd;
800 struct intel_iommu *iommu;
804 * Setup Interrupt-remapping for all the DRHD's now.
806 for_each_iommu(iommu, drhd) {
807 if (!ir_pre_enabled(iommu))
808 iommu_enable_irq_remapping(iommu);
815 irq_remapping_enabled = 1;
817 set_irq_posting_cap();
819 pr_info("Enabled IRQ remapping in %s mode\n", eim_mode ? "x2apic" : "xapic");
821 return eim_mode ? IRQ_REMAP_X2APIC_MODE : IRQ_REMAP_XAPIC_MODE;
824 intel_cleanup_irq_remapping();
828 static int ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope,
829 struct intel_iommu *iommu,
830 struct acpi_dmar_hardware_unit *drhd)
832 struct acpi_dmar_pci_path *path;
834 int count, free = -1;
837 path = (struct acpi_dmar_pci_path *)(scope + 1);
838 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
839 / sizeof(struct acpi_dmar_pci_path);
841 while (--count > 0) {
843 * Access PCI directly due to the PCI
844 * subsystem isn't initialized yet.
846 bus = read_pci_config_byte(bus, path->device, path->function,
851 for (count = 0; count < MAX_HPET_TBS; count++) {
852 if (ir_hpet[count].iommu == iommu &&
853 ir_hpet[count].id == scope->enumeration_id)
855 else if (ir_hpet[count].iommu == NULL && free == -1)
859 pr_warn("Exceeded Max HPET blocks\n");
863 ir_hpet[free].iommu = iommu;
864 ir_hpet[free].id = scope->enumeration_id;
865 ir_hpet[free].bus = bus;
866 ir_hpet[free].devfn = PCI_DEVFN(path->device, path->function);
867 pr_info("HPET id %d under DRHD base 0x%Lx\n",
868 scope->enumeration_id, drhd->address);
873 static int ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope,
874 struct intel_iommu *iommu,
875 struct acpi_dmar_hardware_unit *drhd)
877 struct acpi_dmar_pci_path *path;
879 int count, free = -1;
882 path = (struct acpi_dmar_pci_path *)(scope + 1);
883 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
884 / sizeof(struct acpi_dmar_pci_path);
886 while (--count > 0) {
888 * Access PCI directly due to the PCI
889 * subsystem isn't initialized yet.
891 bus = read_pci_config_byte(bus, path->device, path->function,
896 for (count = 0; count < MAX_IO_APICS; count++) {
897 if (ir_ioapic[count].iommu == iommu &&
898 ir_ioapic[count].id == scope->enumeration_id)
900 else if (ir_ioapic[count].iommu == NULL && free == -1)
904 pr_warn("Exceeded Max IO APICS\n");
908 ir_ioapic[free].bus = bus;
909 ir_ioapic[free].devfn = PCI_DEVFN(path->device, path->function);
910 ir_ioapic[free].iommu = iommu;
911 ir_ioapic[free].id = scope->enumeration_id;
912 pr_info("IOAPIC id %d under DRHD base 0x%Lx IOMMU %d\n",
913 scope->enumeration_id, drhd->address, iommu->seq_id);
918 static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header,
919 struct intel_iommu *iommu)
922 struct acpi_dmar_hardware_unit *drhd;
923 struct acpi_dmar_device_scope *scope;
926 drhd = (struct acpi_dmar_hardware_unit *)header;
927 start = (void *)(drhd + 1);
928 end = ((void *)drhd) + header->length;
930 while (start < end && ret == 0) {
932 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC)
933 ret = ir_parse_one_ioapic_scope(scope, iommu, drhd);
934 else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET)
935 ret = ir_parse_one_hpet_scope(scope, iommu, drhd);
936 start += scope->length;
942 static void ir_remove_ioapic_hpet_scope(struct intel_iommu *iommu)
946 for (i = 0; i < MAX_HPET_TBS; i++)
947 if (ir_hpet[i].iommu == iommu)
948 ir_hpet[i].iommu = NULL;
950 for (i = 0; i < MAX_IO_APICS; i++)
951 if (ir_ioapic[i].iommu == iommu)
952 ir_ioapic[i].iommu = NULL;
956 * Finds the assocaition between IOAPIC's and its Interrupt-remapping
959 static int __init parse_ioapics_under_ir(void)
961 struct dmar_drhd_unit *drhd;
962 struct intel_iommu *iommu;
963 bool ir_supported = false;
966 for_each_iommu(iommu, drhd) {
969 if (!ecap_ir_support(iommu->ecap))
972 ret = ir_parse_ioapic_hpet_scope(drhd->hdr, iommu);
982 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
983 int ioapic_id = mpc_ioapic_id(ioapic_idx);
984 if (!map_ioapic_to_ir(ioapic_id)) {
985 pr_err(FW_BUG "ioapic %d has no mapping iommu, "
986 "interrupt remapping will be disabled\n",
995 static int __init ir_dev_scope_init(void)
999 if (!irq_remapping_enabled)
1002 down_write(&dmar_global_lock);
1003 ret = dmar_dev_scope_init();
1004 up_write(&dmar_global_lock);
1008 rootfs_initcall(ir_dev_scope_init);
1010 static void disable_irq_remapping(void)
1012 struct dmar_drhd_unit *drhd;
1013 struct intel_iommu *iommu = NULL;
1016 * Disable Interrupt-remapping for all the DRHD's now.
1018 for_each_iommu(iommu, drhd) {
1019 if (!ecap_ir_support(iommu->ecap))
1022 iommu_disable_irq_remapping(iommu);
1026 * Clear Posted-Interrupts capability.
1028 if (!disable_irq_post)
1029 intel_irq_remap_ops.capability &= ~(1 << IRQ_POSTING_CAP);
1032 static int reenable_irq_remapping(int eim)
1034 struct dmar_drhd_unit *drhd;
1036 struct intel_iommu *iommu = NULL;
1038 for_each_iommu(iommu, drhd)
1040 dmar_reenable_qi(iommu);
1043 * Setup Interrupt-remapping for all the DRHD's now.
1045 for_each_iommu(iommu, drhd) {
1046 if (!ecap_ir_support(iommu->ecap))
1049 /* Set up interrupt remapping for iommu.*/
1050 iommu_set_irq_remapping(iommu, eim);
1051 iommu_enable_irq_remapping(iommu);
1058 set_irq_posting_cap();
1064 * handle error condition gracefully here!
1069 static void prepare_irte(struct irte *irte, int vector, unsigned int dest)
1071 memset(irte, 0, sizeof(*irte));
1074 irte->dst_mode = apic->irq_dest_mode;
1076 * Trigger mode in the IRTE will always be edge, and for IO-APIC, the
1077 * actual level or edge trigger will be setup in the IO-APIC
1078 * RTE. This will help simplify level triggered irq migration.
1079 * For more details, see the comments (in io_apic.c) explainig IO-APIC
1080 * irq migration in the presence of interrupt-remapping.
1082 irte->trigger_mode = 0;
1083 irte->dlvry_mode = apic->irq_delivery_mode;
1084 irte->vector = vector;
1085 irte->dest_id = IRTE_DEST(dest);
1086 irte->redir_hint = 1;
1089 static struct irq_domain *intel_get_ir_irq_domain(struct irq_alloc_info *info)
1091 struct intel_iommu *iommu = NULL;
1096 switch (info->type) {
1097 case X86_IRQ_ALLOC_TYPE_IOAPIC:
1098 iommu = map_ioapic_to_ir(info->ioapic_id);
1100 case X86_IRQ_ALLOC_TYPE_HPET:
1101 iommu = map_hpet_to_ir(info->hpet_id);
1103 case X86_IRQ_ALLOC_TYPE_MSI:
1104 case X86_IRQ_ALLOC_TYPE_MSIX:
1105 iommu = map_dev_to_ir(info->msi_dev);
1112 return iommu ? iommu->ir_domain : NULL;
1115 static struct irq_domain *intel_get_irq_domain(struct irq_alloc_info *info)
1117 struct intel_iommu *iommu;
1122 switch (info->type) {
1123 case X86_IRQ_ALLOC_TYPE_MSI:
1124 case X86_IRQ_ALLOC_TYPE_MSIX:
1125 iommu = map_dev_to_ir(info->msi_dev);
1127 return iommu->ir_msi_domain;
1136 struct irq_remap_ops intel_irq_remap_ops = {
1137 .prepare = intel_prepare_irq_remapping,
1138 .enable = intel_enable_irq_remapping,
1139 .disable = disable_irq_remapping,
1140 .reenable = reenable_irq_remapping,
1141 .enable_faulting = enable_drhd_fault_handling,
1142 .get_ir_irq_domain = intel_get_ir_irq_domain,
1143 .get_irq_domain = intel_get_irq_domain,
1146 static void intel_ir_reconfigure_irte(struct irq_data *irqd, bool force)
1148 struct intel_ir_data *ir_data = irqd->chip_data;
1149 struct irte *irte = &ir_data->irte_entry;
1150 struct irq_cfg *cfg = irqd_cfg(irqd);
1153 * Atomically updates the IRTE with the new destination, vector
1154 * and flushes the interrupt entry cache.
1156 irte->vector = cfg->vector;
1157 irte->dest_id = IRTE_DEST(cfg->dest_apicid);
1159 /* Update the hardware only if the interrupt is in remapped mode. */
1160 if (force || ir_data->irq_2_iommu.mode == IRQ_REMAPPING)
1161 modify_irte(&ir_data->irq_2_iommu, irte);
1165 * Migrate the IO-APIC irq in the presence of intr-remapping.
1167 * For both level and edge triggered, irq migration is a simple atomic
1168 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
1170 * For level triggered, we eliminate the io-apic RTE modification (with the
1171 * updated vector information), by using a virtual vector (io-apic pin number).
1172 * Real vector that is used for interrupting cpu will be coming from
1173 * the interrupt-remapping table entry.
1175 * As the migration is a simple atomic update of IRTE, the same mechanism
1176 * is used to migrate MSI irq's in the presence of interrupt-remapping.
1179 intel_ir_set_affinity(struct irq_data *data, const struct cpumask *mask,
1182 struct irq_data *parent = data->parent_data;
1183 struct irq_cfg *cfg = irqd_cfg(data);
1186 ret = parent->chip->irq_set_affinity(parent, mask, force);
1187 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
1190 intel_ir_reconfigure_irte(data, false);
1192 * After this point, all the interrupts will start arriving
1193 * at the new destination. So, time to cleanup the previous
1194 * vector allocation.
1196 send_cleanup_vector(cfg);
1198 return IRQ_SET_MASK_OK_DONE;
1201 static void intel_ir_compose_msi_msg(struct irq_data *irq_data,
1202 struct msi_msg *msg)
1204 struct intel_ir_data *ir_data = irq_data->chip_data;
1206 *msg = ir_data->msi_entry;
1209 static int intel_ir_set_vcpu_affinity(struct irq_data *data, void *info)
1211 struct intel_ir_data *ir_data = data->chip_data;
1212 struct vcpu_data *vcpu_pi_info = info;
1214 /* stop posting interrupts, back to remapping mode */
1215 if (!vcpu_pi_info) {
1216 modify_irte(&ir_data->irq_2_iommu, &ir_data->irte_entry);
1218 struct irte irte_pi;
1221 * We are not caching the posted interrupt entry. We
1222 * copy the data from the remapped entry and modify
1223 * the fields which are relevant for posted mode. The
1224 * cached remapped entry is used for switching back to
1227 memset(&irte_pi, 0, sizeof(irte_pi));
1228 dmar_copy_shared_irte(&irte_pi, &ir_data->irte_entry);
1230 /* Update the posted mode fields */
1232 irte_pi.p_urgent = 0;
1233 irte_pi.p_vector = vcpu_pi_info->vector;
1234 irte_pi.pda_l = (vcpu_pi_info->pi_desc_addr >>
1235 (32 - PDA_LOW_BIT)) & ~(-1UL << PDA_LOW_BIT);
1236 irte_pi.pda_h = (vcpu_pi_info->pi_desc_addr >> 32) &
1237 ~(-1UL << PDA_HIGH_BIT);
1239 modify_irte(&ir_data->irq_2_iommu, &irte_pi);
1245 static struct irq_chip intel_ir_chip = {
1247 .irq_ack = apic_ack_irq,
1248 .irq_set_affinity = intel_ir_set_affinity,
1249 .irq_compose_msi_msg = intel_ir_compose_msi_msg,
1250 .irq_set_vcpu_affinity = intel_ir_set_vcpu_affinity,
1253 static void intel_irq_remapping_prepare_irte(struct intel_ir_data *data,
1254 struct irq_cfg *irq_cfg,
1255 struct irq_alloc_info *info,
1256 int index, int sub_handle)
1258 struct IR_IO_APIC_route_entry *entry;
1259 struct irte *irte = &data->irte_entry;
1260 struct msi_msg *msg = &data->msi_entry;
1262 prepare_irte(irte, irq_cfg->vector, irq_cfg->dest_apicid);
1263 switch (info->type) {
1264 case X86_IRQ_ALLOC_TYPE_IOAPIC:
1265 /* Set source-id of interrupt request */
1266 set_ioapic_sid(irte, info->ioapic_id);
1267 apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: Set IRTE entry (P:%d FPD:%d Dst_Mode:%d Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X Avail:%X Vector:%02X Dest:%08X SID:%04X SQ:%X SVT:%X)\n",
1268 info->ioapic_id, irte->present, irte->fpd,
1269 irte->dst_mode, irte->redir_hint,
1270 irte->trigger_mode, irte->dlvry_mode,
1271 irte->avail, irte->vector, irte->dest_id,
1272 irte->sid, irte->sq, irte->svt);
1274 entry = (struct IR_IO_APIC_route_entry *)info->ioapic_entry;
1275 info->ioapic_entry = NULL;
1276 memset(entry, 0, sizeof(*entry));
1277 entry->index2 = (index >> 15) & 0x1;
1280 entry->index = (index & 0x7fff);
1282 * IO-APIC RTE will be configured with virtual vector.
1283 * irq handler will do the explicit EOI to the io-apic.
1285 entry->vector = info->ioapic_pin;
1286 entry->mask = 0; /* enable IRQ */
1287 entry->trigger = info->ioapic_trigger;
1288 entry->polarity = info->ioapic_polarity;
1289 if (info->ioapic_trigger)
1290 entry->mask = 1; /* Mask level triggered irqs. */
1293 case X86_IRQ_ALLOC_TYPE_HPET:
1294 case X86_IRQ_ALLOC_TYPE_MSI:
1295 case X86_IRQ_ALLOC_TYPE_MSIX:
1296 if (info->type == X86_IRQ_ALLOC_TYPE_HPET)
1297 set_hpet_sid(irte, info->hpet_id);
1299 set_msi_sid(irte, info->msi_dev);
1301 msg->address_hi = MSI_ADDR_BASE_HI;
1302 msg->data = sub_handle;
1303 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
1305 MSI_ADDR_IR_INDEX1(index) |
1306 MSI_ADDR_IR_INDEX2(index);
1315 static void intel_free_irq_resources(struct irq_domain *domain,
1316 unsigned int virq, unsigned int nr_irqs)
1318 struct irq_data *irq_data;
1319 struct intel_ir_data *data;
1320 struct irq_2_iommu *irq_iommu;
1321 unsigned long flags;
1323 for (i = 0; i < nr_irqs; i++) {
1324 irq_data = irq_domain_get_irq_data(domain, virq + i);
1325 if (irq_data && irq_data->chip_data) {
1326 data = irq_data->chip_data;
1327 irq_iommu = &data->irq_2_iommu;
1328 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
1329 clear_entries(irq_iommu);
1330 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
1331 irq_domain_reset_irq_data(irq_data);
1337 static int intel_irq_remapping_alloc(struct irq_domain *domain,
1338 unsigned int virq, unsigned int nr_irqs,
1341 struct intel_iommu *iommu = domain->host_data;
1342 struct irq_alloc_info *info = arg;
1343 struct intel_ir_data *data, *ird;
1344 struct irq_data *irq_data;
1345 struct irq_cfg *irq_cfg;
1348 if (!info || !iommu)
1350 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
1351 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
1355 * With IRQ remapping enabled, don't need contiguous CPU vectors
1356 * to support multiple MSI interrupts.
1358 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
1359 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
1361 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
1366 data = kzalloc(sizeof(*data), GFP_KERNEL);
1368 goto out_free_parent;
1370 down_read(&dmar_global_lock);
1371 index = alloc_irte(iommu, virq, &data->irq_2_iommu, nr_irqs);
1372 up_read(&dmar_global_lock);
1374 pr_warn("Failed to allocate IRTE\n");
1376 goto out_free_parent;
1379 for (i = 0; i < nr_irqs; i++) {
1380 irq_data = irq_domain_get_irq_data(domain, virq + i);
1381 irq_cfg = irqd_cfg(irq_data);
1382 if (!irq_data || !irq_cfg) {
1390 ird = kzalloc(sizeof(*ird), GFP_KERNEL);
1393 /* Initialize the common data */
1394 ird->irq_2_iommu = data->irq_2_iommu;
1395 ird->irq_2_iommu.sub_handle = i;
1400 irq_data->hwirq = (index << 16) + i;
1401 irq_data->chip_data = ird;
1402 irq_data->chip = &intel_ir_chip;
1403 intel_irq_remapping_prepare_irte(ird, irq_cfg, info, index, i);
1404 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
1409 intel_free_irq_resources(domain, virq, i);
1411 irq_domain_free_irqs_common(domain, virq, nr_irqs);
1415 static void intel_irq_remapping_free(struct irq_domain *domain,
1416 unsigned int virq, unsigned int nr_irqs)
1418 intel_free_irq_resources(domain, virq, nr_irqs);
1419 irq_domain_free_irqs_common(domain, virq, nr_irqs);
1422 static int intel_irq_remapping_activate(struct irq_domain *domain,
1423 struct irq_data *irq_data, bool reserve)
1425 intel_ir_reconfigure_irte(irq_data, true);
1429 static void intel_irq_remapping_deactivate(struct irq_domain *domain,
1430 struct irq_data *irq_data)
1432 struct intel_ir_data *data = irq_data->chip_data;
1435 memset(&entry, 0, sizeof(entry));
1436 modify_irte(&data->irq_2_iommu, &entry);
1439 static const struct irq_domain_ops intel_ir_domain_ops = {
1440 .alloc = intel_irq_remapping_alloc,
1441 .free = intel_irq_remapping_free,
1442 .activate = intel_irq_remapping_activate,
1443 .deactivate = intel_irq_remapping_deactivate,
1447 * Support of Interrupt Remapping Unit Hotplug
1449 static int dmar_ir_add(struct dmar_drhd_unit *dmaru, struct intel_iommu *iommu)
1452 int eim = x2apic_enabled();
1454 if (eim && !ecap_eim_support(iommu->ecap)) {
1455 pr_info("DRHD %Lx: EIM not supported by DRHD, ecap %Lx\n",
1456 iommu->reg_phys, iommu->ecap);
1460 if (ir_parse_ioapic_hpet_scope(dmaru->hdr, iommu)) {
1461 pr_warn("DRHD %Lx: failed to parse managed IOAPIC/HPET\n",
1466 /* TODO: check all IOAPICs are covered by IOMMU */
1468 /* Setup Interrupt-remapping now. */
1469 ret = intel_setup_irq_remapping(iommu);
1471 pr_err("Failed to setup irq remapping for %s\n",
1473 intel_teardown_irq_remapping(iommu);
1474 ir_remove_ioapic_hpet_scope(iommu);
1476 iommu_enable_irq_remapping(iommu);
1482 int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
1485 struct intel_iommu *iommu = dmaru->iommu;
1487 if (!irq_remapping_enabled)
1491 if (!ecap_ir_support(iommu->ecap))
1493 if (irq_remapping_cap(IRQ_POSTING_CAP) &&
1494 !cap_pi_support(iommu->cap))
1498 if (!iommu->ir_table)
1499 ret = dmar_ir_add(dmaru, iommu);
1501 if (iommu->ir_table) {
1502 if (!bitmap_empty(iommu->ir_table->bitmap,
1503 INTR_REMAP_TABLE_ENTRIES)) {
1506 iommu_disable_irq_remapping(iommu);
1507 intel_teardown_irq_remapping(iommu);
1508 ir_remove_ioapic_hpet_scope(iommu);