drivers/iommu/ipmmu-vmsa.c

   1 /*
   2  * IPMMU VMSA
   3  *
   4  * Copyright (C) 2014 Renesas Electronics Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  */
  10
  11 #include <linux/bitmap.h>
  12 #include <linux/delay.h>
  13 #include <linux/dma-iommu.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/err.h>
  16 #include <linux/export.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/iommu.h>
  20 #include <linux/module.h>
  21 #include <linux/of.h>
  22 #include <linux/of_device.h>
  23 #include <linux/of_iommu.h>
  24 #include <linux/of_platform.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/sizes.h>
  27 #include <linux/slab.h>
  28 #include <linux/sys_soc.h>
  29
  30 #if defined(CONFIG_ARM) && !defined(CONFIG_IOMMU_DMA)
  31 #include <asm/dma-iommu.h>
  32 #include <asm/pgalloc.h>
  33 #else
  34 #define arm_iommu_create_mapping(...)   NULL
  35 #define arm_iommu_attach_device(...)    -ENODEV
  36 #define arm_iommu_release_mapping(...)  do {} while (0)
  37 #define arm_iommu_detach_device(...)    do {} while (0)
  38 #endif
  39
  40 #include "io-pgtable.h"
  41
  42 #define IPMMU_CTX_MAX 8
  43
  44 struct ipmmu_features {
  45         bool use_ns_alias_offset;
  46         bool has_cache_leaf_nodes;
  47         unsigned int number_of_contexts;
  48         bool setup_imbuscr;
  49         bool twobit_imttbcr_sl0;
  50         bool reserved_context;
  51 };
  52
  53 struct ipmmu_vmsa_device {
  54         struct device *dev;
  55         void __iomem *base;
  56         struct iommu_device iommu;
  57         struct ipmmu_vmsa_device *root;
  58         const struct ipmmu_features *features;
  59         unsigned int num_utlbs;
  60         unsigned int num_ctx;
  61         spinlock_t lock;                        /* Protects ctx and domains[] */
  62         DECLARE_BITMAP(ctx, IPMMU_CTX_MAX);
  63         struct ipmmu_vmsa_domain *domains[IPMMU_CTX_MAX];
  64
  65         struct iommu_group *group;
  66         struct dma_iommu_mapping *mapping;
  67 };
  68
  69 struct ipmmu_vmsa_domain {
  70         struct ipmmu_vmsa_device *mmu;
  71         struct iommu_domain io_domain;
  72
  73         struct io_pgtable_cfg cfg;
  74         struct io_pgtable_ops *iop;
  75
  76         unsigned int context_id;
  77         struct mutex mutex;                     /* Protects mappings */
  78 };
  79
  80 static struct ipmmu_vmsa_domain *to_vmsa_domain(struct iommu_domain *dom)
  81 {
  82         return container_of(dom, struct ipmmu_vmsa_domain, io_domain);
  83 }
  84
  85 static struct ipmmu_vmsa_device *to_ipmmu(struct device *dev)
  86 {
  87         return dev->iommu_fwspec ? dev->iommu_fwspec->iommu_priv : NULL;
  88 }
  89
  90 #define TLB_LOOP_TIMEOUT                100     /* 100us */
  91
  92 /* -----------------------------------------------------------------------------
  93  * Registers Definition
  94  */
  95
  96 #define IM_NS_ALIAS_OFFSET              0x800
  97
  98 #define IM_CTX_SIZE                     0x40
  99
 100 #define IMCTR                           0x0000
 101 #define IMCTR_TRE                       (1 << 17)
 102 #define IMCTR_AFE                       (1 << 16)
 103 #define IMCTR_RTSEL_MASK                (3 << 4)
 104 #define IMCTR_RTSEL_SHIFT               4
 105 #define IMCTR_TREN                      (1 << 3)
 106 #define IMCTR_INTEN                     (1 << 2)
 107 #define IMCTR_FLUSH                     (1 << 1)
 108 #define IMCTR_MMUEN                     (1 << 0)
 109
 110 #define IMCAAR                          0x0004
 111
 112 #define IMTTBCR                         0x0008
 113 #define IMTTBCR_EAE                     (1 << 31)
 114 #define IMTTBCR_PMB                     (1 << 30)
 115 #define IMTTBCR_SH1_NON_SHAREABLE       (0 << 28)
 116 #define IMTTBCR_SH1_OUTER_SHAREABLE     (2 << 28)
 117 #define IMTTBCR_SH1_INNER_SHAREABLE     (3 << 28)
 118 #define IMTTBCR_SH1_MASK                (3 << 28)
 119 #define IMTTBCR_ORGN1_NC                (0 << 26)
 120 #define IMTTBCR_ORGN1_WB_WA             (1 << 26)
 121 #define IMTTBCR_ORGN1_WT                (2 << 26)
 122 #define IMTTBCR_ORGN1_WB                (3 << 26)
 123 #define IMTTBCR_ORGN1_MASK              (3 << 26)
 124 #define IMTTBCR_IRGN1_NC                (0 << 24)
 125 #define IMTTBCR_IRGN1_WB_WA             (1 << 24)
 126 #define IMTTBCR_IRGN1_WT                (2 << 24)
 127 #define IMTTBCR_IRGN1_WB                (3 << 24)
 128 #define IMTTBCR_IRGN1_MASK              (3 << 24)
 129 #define IMTTBCR_TSZ1_MASK               (7 << 16)
 130 #define IMTTBCR_TSZ1_SHIFT              16
 131 #define IMTTBCR_SH0_NON_SHAREABLE       (0 << 12)
 132 #define IMTTBCR_SH0_OUTER_SHAREABLE     (2 << 12)
 133 #define IMTTBCR_SH0_INNER_SHAREABLE     (3 << 12)
 134 #define IMTTBCR_SH0_MASK                (3 << 12)
 135 #define IMTTBCR_ORGN0_NC                (0 << 10)
 136 #define IMTTBCR_ORGN0_WB_WA             (1 << 10)
 137 #define IMTTBCR_ORGN0_WT                (2 << 10)
 138 #define IMTTBCR_ORGN0_WB                (3 << 10)
 139 #define IMTTBCR_ORGN0_MASK              (3 << 10)
 140 #define IMTTBCR_IRGN0_NC                (0 << 8)
 141 #define IMTTBCR_IRGN0_WB_WA             (1 << 8)
 142 #define IMTTBCR_IRGN0_WT                (2 << 8)
 143 #define IMTTBCR_IRGN0_WB                (3 << 8)
 144 #define IMTTBCR_IRGN0_MASK              (3 << 8)
 145 #define IMTTBCR_SL0_LVL_2               (0 << 4)
 146 #define IMTTBCR_SL0_LVL_1               (1 << 4)
 147 #define IMTTBCR_TSZ0_MASK               (7 << 0)
 148 #define IMTTBCR_TSZ0_SHIFT              O
 149
 150 #define IMTTBCR_SL0_TWOBIT_LVL_3        (0 << 6)
 151 #define IMTTBCR_SL0_TWOBIT_LVL_2        (1 << 6)
 152 #define IMTTBCR_SL0_TWOBIT_LVL_1        (2 << 6)
 153
 154 #define IMBUSCR                         0x000c
 155 #define IMBUSCR_DVM                     (1 << 2)
 156 #define IMBUSCR_BUSSEL_SYS              (0 << 0)
 157 #define IMBUSCR_BUSSEL_CCI              (1 << 0)
 158 #define IMBUSCR_BUSSEL_IMCAAR           (2 << 0)
 159 #define IMBUSCR_BUSSEL_CCI_IMCAAR       (3 << 0)
 160 #define IMBUSCR_BUSSEL_MASK             (3 << 0)
 161
 162 #define IMTTLBR0                        0x0010
 163 #define IMTTUBR0                        0x0014
 164 #define IMTTLBR1                        0x0018
 165 #define IMTTUBR1                        0x001c
 166
 167 #define IMSTR                           0x0020
 168 #define IMSTR_ERRLVL_MASK               (3 << 12)
 169 #define IMSTR_ERRLVL_SHIFT              12
 170 #define IMSTR_ERRCODE_TLB_FORMAT        (1 << 8)
 171 #define IMSTR_ERRCODE_ACCESS_PERM       (4 << 8)
 172 #define IMSTR_ERRCODE_SECURE_ACCESS     (5 << 8)
 173 #define IMSTR_ERRCODE_MASK              (7 << 8)
 174 #define IMSTR_MHIT                      (1 << 4)
 175 #define IMSTR_ABORT                     (1 << 2)
 176 #define IMSTR_PF                        (1 << 1)
 177 #define IMSTR_TF                        (1 << 0)
 178
 179 #define IMMAIR0                         0x0028
 180 #define IMMAIR1                         0x002c
 181 #define IMMAIR_ATTR_MASK                0xff
 182 #define IMMAIR_ATTR_DEVICE              0x04
 183 #define IMMAIR_ATTR_NC                  0x44
 184 #define IMMAIR_ATTR_WBRWA               0xff
 185 #define IMMAIR_ATTR_SHIFT(n)            ((n) << 3)
 186 #define IMMAIR_ATTR_IDX_NC              0
 187 #define IMMAIR_ATTR_IDX_WBRWA           1
 188 #define IMMAIR_ATTR_IDX_DEV             2
 189
 190 #define IMEAR                           0x0030
 191
 192 #define IMPCTR                          0x0200
 193 #define IMPSTR                          0x0208
 194 #define IMPEAR                          0x020c
 195 #define IMPMBA(n)                       (0x0280 + ((n) * 4))
 196 #define IMPMBD(n)                       (0x02c0 + ((n) * 4))
 197
 198 #define IMUCTR(n)                       ((n) < 32 ? IMUCTR0(n) : IMUCTR32(n))
 199 #define IMUCTR0(n)                      (0x0300 + ((n) * 16))
 200 #define IMUCTR32(n)                     (0x0600 + (((n) - 32) * 16))
 201 #define IMUCTR_FIXADDEN                 (1 << 31)
 202 #define IMUCTR_FIXADD_MASK              (0xff << 16)
 203 #define IMUCTR_FIXADD_SHIFT             16
 204 #define IMUCTR_TTSEL_MMU(n)             ((n) << 4)
 205 #define IMUCTR_TTSEL_PMB                (8 << 4)
 206 #define IMUCTR_TTSEL_MASK               (15 << 4)
 207 #define IMUCTR_FLUSH                    (1 << 1)
 208 #define IMUCTR_MMUEN                    (1 << 0)
 209
 210 #define IMUASID(n)                      ((n) < 32 ? IMUASID0(n) : IMUASID32(n))
 211 #define IMUASID0(n)                     (0x0308 + ((n) * 16))
 212 #define IMUASID32(n)                    (0x0608 + (((n) - 32) * 16))
 213 #define IMUASID_ASID8_MASK              (0xff << 8)
 214 #define IMUASID_ASID8_SHIFT             8
 215 #define IMUASID_ASID0_MASK              (0xff << 0)
 216 #define IMUASID_ASID0_SHIFT             0
 217
 218 /* -----------------------------------------------------------------------------
 219  * Root device handling
 220  */
 221
 222 static struct platform_driver ipmmu_driver;
 223
 224 static bool ipmmu_is_root(struct ipmmu_vmsa_device *mmu)
 225 {
 226         return mmu->root == mmu;
 227 }
 228
 229 static int __ipmmu_check_device(struct device *dev, void *data)
 230 {
 231         struct ipmmu_vmsa_device *mmu = dev_get_drvdata(dev);
 232         struct ipmmu_vmsa_device **rootp = data;
 233
 234         if (ipmmu_is_root(mmu))
 235                 *rootp = mmu;
 236
 237         return 0;
 238 }
 239
 240 static struct ipmmu_vmsa_device *ipmmu_find_root(void)
 241 {
 242         struct ipmmu_vmsa_device *root = NULL;
 243
 244         return driver_for_each_device(&ipmmu_driver.driver, NULL, &root,
 245                                       __ipmmu_check_device) == 0 ? root : NULL;
 246 }
 247
 248 /* -----------------------------------------------------------------------------
 249  * Read/Write Access
 250  */
 251
 252 static u32 ipmmu_read(struct ipmmu_vmsa_device *mmu, unsigned int offset)
 253 {
 254         return ioread32(mmu->base + offset);
 255 }
 256
 257 static void ipmmu_write(struct ipmmu_vmsa_device *mmu, unsigned int offset,
 258                         u32 data)
 259 {
 260         iowrite32(data, mmu->base + offset);
 261 }
 262
 263 static u32 ipmmu_ctx_read_root(struct ipmmu_vmsa_domain *domain,
 264                                unsigned int reg)
 265 {
 266         return ipmmu_read(domain->mmu->root,
 267                           domain->context_id * IM_CTX_SIZE + reg);
 268 }
 269
 270 static void ipmmu_ctx_write_root(struct ipmmu_vmsa_domain *domain,
 271                                  unsigned int reg, u32 data)
 272 {
 273         ipmmu_write(domain->mmu->root,
 274                     domain->context_id * IM_CTX_SIZE + reg, data);
 275 }
 276
 277 static void ipmmu_ctx_write_all(struct ipmmu_vmsa_domain *domain,
 278                                 unsigned int reg, u32 data)
 279 {
 280         if (domain->mmu != domain->mmu->root)
 281                 ipmmu_write(domain->mmu,
 282                             domain->context_id * IM_CTX_SIZE + reg, data);
 283
 284         ipmmu_write(domain->mmu->root,
 285                     domain->context_id * IM_CTX_SIZE + reg, data);
 286 }
 287
 288 /* -----------------------------------------------------------------------------
 289  * TLB and microTLB Management
 290  */
 291
 292 /* Wait for any pending TLB invalidations to complete */
 293 static void ipmmu_tlb_sync(struct ipmmu_vmsa_domain *domain)
 294 {
 295         unsigned int count = 0;
 296
 297         while (ipmmu_ctx_read_root(domain, IMCTR) & IMCTR_FLUSH) {
 298                 cpu_relax();
 299                 if (++count == TLB_LOOP_TIMEOUT) {
 300                         dev_err_ratelimited(domain->mmu->dev,
 301                         "TLB sync timed out -- MMU may be deadlocked\n");
 302                         return;
 303                 }
 304                 udelay(1);
 305         }
 306 }
 307
 308 static void ipmmu_tlb_invalidate(struct ipmmu_vmsa_domain *domain)
 309 {
 310         u32 reg;
 311
 312         reg = ipmmu_ctx_read_root(domain, IMCTR);
 313         reg |= IMCTR_FLUSH;
 314         ipmmu_ctx_write_all(domain, IMCTR, reg);
 315
 316         ipmmu_tlb_sync(domain);
 317 }
 318
 319 /*
 320  * Enable MMU translation for the microTLB.
 321  */
 322 static void ipmmu_utlb_enable(struct ipmmu_vmsa_domain *domain,
 323                               unsigned int utlb)
 324 {
 325         struct ipmmu_vmsa_device *mmu = domain->mmu;
 326
 327         /*
 328          * TODO: Reference-count the microTLB as several bus masters can be
 329          * connected to the same microTLB.
 330          */
 331
 332         /* TODO: What should we set the ASID to ? */
 333         ipmmu_write(mmu, IMUASID(utlb), 0);
 334         /* TODO: Do we need to flush the microTLB ? */
 335         ipmmu_write(mmu, IMUCTR(utlb),
 336                     IMUCTR_TTSEL_MMU(domain->context_id) | IMUCTR_FLUSH |
 337                     IMUCTR_MMUEN);
 338 }
 339
 340 /*
 341  * Disable MMU translation for the microTLB.
 342  */
 343 static void ipmmu_utlb_disable(struct ipmmu_vmsa_domain *domain,
 344                                unsigned int utlb)
 345 {
 346         struct ipmmu_vmsa_device *mmu = domain->mmu;
 347
 348         ipmmu_write(mmu, IMUCTR(utlb), 0);
 349 }
 350
 351 static void ipmmu_tlb_flush_all(void *cookie)
 352 {
 353         struct ipmmu_vmsa_domain *domain = cookie;
 354
 355         ipmmu_tlb_invalidate(domain);
 356 }
 357
 358 static void ipmmu_tlb_add_flush(unsigned long iova, size_t size,
 359                                 size_t granule, bool leaf, void *cookie)
 360 {
 361         /* The hardware doesn't support selective TLB flush. */
 362 }
 363
 364 static const struct iommu_gather_ops ipmmu_gather_ops = {
 365         .tlb_flush_all = ipmmu_tlb_flush_all,
 366         .tlb_add_flush = ipmmu_tlb_add_flush,
 367         .tlb_sync = ipmmu_tlb_flush_all,
 368 };
 369
 370 /* -----------------------------------------------------------------------------
 371  * Domain/Context Management
 372  */
 373
 374 static int ipmmu_domain_allocate_context(struct ipmmu_vmsa_device *mmu,
 375                                          struct ipmmu_vmsa_domain *domain)
 376 {
 377         unsigned long flags;
 378         int ret;
 379
 380         spin_lock_irqsave(&mmu->lock, flags);
 381
 382         ret = find_first_zero_bit(mmu->ctx, mmu->num_ctx);
 383         if (ret != mmu->num_ctx) {
 384                 mmu->domains[ret] = domain;
 385                 set_bit(ret, mmu->ctx);
 386         } else
 387                 ret = -EBUSY;
 388
 389         spin_unlock_irqrestore(&mmu->lock, flags);
 390
 391         return ret;
 392 }
 393
 394 static void ipmmu_domain_free_context(struct ipmmu_vmsa_device *mmu,
 395                                       unsigned int context_id)
 396 {
 397         unsigned long flags;
 398
 399         spin_lock_irqsave(&mmu->lock, flags);
 400
 401         clear_bit(context_id, mmu->ctx);
 402         mmu->domains[context_id] = NULL;
 403
 404         spin_unlock_irqrestore(&mmu->lock, flags);
 405 }
 406
 407 static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain)
 408 {
 409         u64 ttbr;
 410         u32 tmp;
 411         int ret;
 412
 413         /*
 414          * Allocate the page table operations.
 415          *
 416          * VMSA states in section B3.6.3 "Control of Secure or Non-secure memory
 417          * access, Long-descriptor format" that the NStable bit being set in a
 418          * table descriptor will result in the NStable and NS bits of all child
 419          * entries being ignored and considered as being set. The IPMMU seems
 420          * not to comply with this, as it generates a secure access page fault
 421          * if any of the NStable and NS bits isn't set when running in
 422          * non-secure mode.
 423          */
 424         domain->cfg.quirks = IO_PGTABLE_QUIRK_ARM_NS;
 425         domain->cfg.pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K;
 426         domain->cfg.ias = 32;
 427         domain->cfg.oas = 40;
 428         domain->cfg.tlb = &ipmmu_gather_ops;
 429         domain->io_domain.geometry.aperture_end = DMA_BIT_MASK(32);
 430         domain->io_domain.geometry.force_aperture = true;
 431         /*
 432          * TODO: Add support for coherent walk through CCI with DVM and remove
 433          * cache handling. For now, delegate it to the io-pgtable code.
 434          */
 435         domain->cfg.iommu_dev = domain->mmu->root->dev;
 436
 437         /*
 438          * Find an unused context.
 439          */
 440         ret = ipmmu_domain_allocate_context(domain->mmu->root, domain);
 441         if (ret < 0)
 442                 return ret;
 443
 444         domain->context_id = ret;
 445
 446         domain->iop = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &domain->cfg,
 447                                            domain);
 448         if (!domain->iop) {
 449                 ipmmu_domain_free_context(domain->mmu->root,
 450                                           domain->context_id);
 451                 return -EINVAL;
 452         }
 453
 454         /* TTBR0 */
 455         ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr[0];
 456         ipmmu_ctx_write_root(domain, IMTTLBR0, ttbr);
 457         ipmmu_ctx_write_root(domain, IMTTUBR0, ttbr >> 32);
 458
 459         /*
 460          * TTBCR
 461          * We use long descriptors with inner-shareable WBWA tables and allocate
 462          * the whole 32-bit VA space to TTBR0.
 463          */
 464         if (domain->mmu->features->twobit_imttbcr_sl0)
 465                 tmp = IMTTBCR_SL0_TWOBIT_LVL_1;
 466         else
 467                 tmp = IMTTBCR_SL0_LVL_1;
 468
 469         ipmmu_ctx_write_root(domain, IMTTBCR, IMTTBCR_EAE |
 470                              IMTTBCR_SH0_INNER_SHAREABLE | IMTTBCR_ORGN0_WB_WA |
 471                              IMTTBCR_IRGN0_WB_WA | tmp);
 472
 473         /* MAIR0 */
 474         ipmmu_ctx_write_root(domain, IMMAIR0,
 475                              domain->cfg.arm_lpae_s1_cfg.mair[0]);
 476
 477         /* IMBUSCR */
 478         if (domain->mmu->features->setup_imbuscr)
 479                 ipmmu_ctx_write_root(domain, IMBUSCR,
 480                                      ipmmu_ctx_read_root(domain, IMBUSCR) &
 481                                      ~(IMBUSCR_DVM | IMBUSCR_BUSSEL_MASK));
 482
 483         /*
 484          * IMSTR
 485          * Clear all interrupt flags.
 486          */
 487         ipmmu_ctx_write_root(domain, IMSTR, ipmmu_ctx_read_root(domain, IMSTR));
 488
 489         /*
 490          * IMCTR
 491          * Enable the MMU and interrupt generation. The long-descriptor
 492          * translation table format doesn't use TEX remapping. Don't enable AF
 493          * software management as we have no use for it. Flush the TLB as
 494          * required when modifying the context registers.
 495          */
 496         ipmmu_ctx_write_all(domain, IMCTR,
 497                             IMCTR_INTEN | IMCTR_FLUSH | IMCTR_MMUEN);
 498
 499         return 0;
 500 }
 501
 502 static void ipmmu_domain_destroy_context(struct ipmmu_vmsa_domain *domain)
 503 {
 504         if (!domain->mmu)
 505                 return;
 506
 507         /*
 508          * Disable the context. Flush the TLB as required when modifying the
 509          * context registers.
 510          *
 511          * TODO: Is TLB flush really needed ?
 512          */
 513         ipmmu_ctx_write_all(domain, IMCTR, IMCTR_FLUSH);
 514         ipmmu_tlb_sync(domain);
 515         ipmmu_domain_free_context(domain->mmu->root, domain->context_id);
 516 }
 517
 518 /* -----------------------------------------------------------------------------
 519  * Fault Handling
 520  */
 521
 522 static irqreturn_t ipmmu_domain_irq(struct ipmmu_vmsa_domain *domain)
 523 {
 524         const u32 err_mask = IMSTR_MHIT | IMSTR_ABORT | IMSTR_PF | IMSTR_TF;
 525         struct ipmmu_vmsa_device *mmu = domain->mmu;
 526         u32 status;
 527         u32 iova;
 528
 529         status = ipmmu_ctx_read_root(domain, IMSTR);
 530         if (!(status & err_mask))
 531                 return IRQ_NONE;
 532
 533         iova = ipmmu_ctx_read_root(domain, IMEAR);
 534
 535         /*
 536          * Clear the error status flags. Unlike traditional interrupt flag
 537          * registers that must be cleared by writing 1, this status register
 538          * seems to require 0. The error address register must be read before,
 539          * otherwise its value will be 0.
 540          */
 541         ipmmu_ctx_write_root(domain, IMSTR, 0);
 542
 543         /* Log fatal errors. */
 544         if (status & IMSTR_MHIT)
 545                 dev_err_ratelimited(mmu->dev, "Multiple TLB hits @0x%08x\n",
 546                                     iova);
 547         if (status & IMSTR_ABORT)
 548                 dev_err_ratelimited(mmu->dev, "Page Table Walk Abort @0x%08x\n",
 549                                     iova);
 550
 551         if (!(status & (IMSTR_PF | IMSTR_TF)))
 552                 return IRQ_NONE;
 553
 554         /*
 555          * Try to handle page faults and translation faults.
 556          *
 557          * TODO: We need to look up the faulty device based on the I/O VA. Use
 558          * the IOMMU device for now.
 559          */
 560         if (!report_iommu_fault(&domain->io_domain, mmu->dev, iova, 0))
 561                 return IRQ_HANDLED;
 562
 563         dev_err_ratelimited(mmu->dev,
 564                             "Unhandled fault: status 0x%08x iova 0x%08x\n",
 565                             status, iova);
 566
 567         return IRQ_HANDLED;
 568 }
 569
 570 static irqreturn_t ipmmu_irq(int irq, void *dev)
 571 {
 572         struct ipmmu_vmsa_device *mmu = dev;
 573         irqreturn_t status = IRQ_NONE;
 574         unsigned int i;
 575         unsigned long flags;
 576
 577         spin_lock_irqsave(&mmu->lock, flags);
 578
 579         /*
 580          * Check interrupts for all active contexts.
 581          */
 582         for (i = 0; i < mmu->num_ctx; i++) {
 583                 if (!mmu->domains[i])
 584                         continue;
 585                 if (ipmmu_domain_irq(mmu->domains[i]) == IRQ_HANDLED)
 586                         status = IRQ_HANDLED;
 587         }
 588
 589         spin_unlock_irqrestore(&mmu->lock, flags);
 590
 591         return status;
 592 }
 593
 594 /* -----------------------------------------------------------------------------
 595  * IOMMU Operations
 596  */
 597
 598 static struct iommu_domain *__ipmmu_domain_alloc(unsigned type)
 599 {
 600         struct ipmmu_vmsa_domain *domain;
 601
 602         domain = kzalloc(sizeof(*domain), GFP_KERNEL);
 603         if (!domain)
 604                 return NULL;
 605
 606         mutex_init(&domain->mutex);
 607
 608         return &domain->io_domain;
 609 }
 610
 611 static struct iommu_domain *ipmmu_domain_alloc(unsigned type)
 612 {
 613         struct iommu_domain *io_domain = NULL;
 614
 615         switch (type) {
 616         case IOMMU_DOMAIN_UNMANAGED:
 617                 io_domain = __ipmmu_domain_alloc(type);
 618                 break;
 619
 620         case IOMMU_DOMAIN_DMA:
 621                 io_domain = __ipmmu_domain_alloc(type);
 622                 if (io_domain && iommu_get_dma_cookie(io_domain)) {
 623                         kfree(io_domain);
 624                         io_domain = NULL;
 625                 }
 626                 break;
 627         }
 628
 629         return io_domain;
 630 }
 631
 632 static void ipmmu_domain_free(struct iommu_domain *io_domain)
 633 {
 634         struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
 635
 636         /*
 637          * Free the domain resources. We assume that all devices have already
 638          * been detached.
 639          */
 640         iommu_put_dma_cookie(io_domain);
 641         ipmmu_domain_destroy_context(domain);
 642         free_io_pgtable_ops(domain->iop);
 643         kfree(domain);
 644 }
 645
 646 static int ipmmu_attach_device(struct iommu_domain *io_domain,
 647                                struct device *dev)
 648 {
 649         struct iommu_fwspec *fwspec = dev->iommu_fwspec;
 650         struct ipmmu_vmsa_device *mmu = to_ipmmu(dev);
 651         struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
 652         unsigned int i;
 653         int ret = 0;
 654
 655         if (!mmu) {
 656                 dev_err(dev, "Cannot attach to IPMMU\n");
 657                 return -ENXIO;
 658         }
 659
 660         mutex_lock(&domain->mutex);
 661
 662         if (!domain->mmu) {
 663                 /* The domain hasn't been used yet, initialize it. */
 664                 domain->mmu = mmu;
 665                 ret = ipmmu_domain_init_context(domain);
 666                 if (ret < 0) {
 667                         dev_err(dev, "Unable to initialize IPMMU context\n");
 668                         domain->mmu = NULL;
 669                 } else {
 670                         dev_info(dev, "Using IPMMU context %u\n",
 671                                  domain->context_id);
 672                 }
 673         } else if (domain->mmu != mmu) {
 674                 /*
 675                  * Something is wrong, we can't attach two devices using
 676                  * different IOMMUs to the same domain.
 677                  */
 678                 dev_err(dev, "Can't attach IPMMU %s to domain on IPMMU %s\n",
 679                         dev_name(mmu->dev), dev_name(domain->mmu->dev));
 680                 ret = -EINVAL;
 681         } else
 682                 dev_info(dev, "Reusing IPMMU context %u\n", domain->context_id);
 683
 684         mutex_unlock(&domain->mutex);
 685
 686         if (ret < 0)
 687                 return ret;
 688
 689         for (i = 0; i < fwspec->num_ids; ++i)
 690                 ipmmu_utlb_enable(domain, fwspec->ids[i]);
 691
 692         return 0;
 693 }
 694
 695 static void ipmmu_detach_device(struct iommu_domain *io_domain,
 696                                 struct device *dev)
 697 {
 698         struct iommu_fwspec *fwspec = dev->iommu_fwspec;
 699         struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
 700         unsigned int i;
 701
 702         for (i = 0; i < fwspec->num_ids; ++i)
 703                 ipmmu_utlb_disable(domain, fwspec->ids[i]);
 704
 705         /*
 706          * TODO: Optimize by disabling the context when no device is attached.
 707          */
 708 }
 709
 710 static int ipmmu_map(struct iommu_domain *io_domain, unsigned long iova,
 711                      phys_addr_t paddr, size_t size, int prot)
 712 {
 713         struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
 714
 715         if (!domain)
 716                 return -ENODEV;
 717
 718         return domain->iop->map(domain->iop, iova, paddr, size, prot);
 719 }
 720
 721 static size_t ipmmu_unmap(struct iommu_domain *io_domain, unsigned long iova,
 722                           size_t size)
 723 {
 724         struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
 725
 726         return domain->iop->unmap(domain->iop, iova, size);
 727 }
 728
 729 static void ipmmu_iotlb_sync(struct iommu_domain *io_domain)
 730 {
 731         struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
 732
 733         if (domain->mmu)
 734                 ipmmu_tlb_flush_all(domain);
 735 }
 736
 737 static phys_addr_t ipmmu_iova_to_phys(struct iommu_domain *io_domain,
 738                                       dma_addr_t iova)
 739 {
 740         struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
 741
 742         /* TODO: Is locking needed ? */
 743
 744         return domain->iop->iova_to_phys(domain->iop, iova);
 745 }
 746
 747 static int ipmmu_init_platform_device(struct device *dev,
 748                                       struct of_phandle_args *args)
 749 {
 750         struct platform_device *ipmmu_pdev;
 751
 752         ipmmu_pdev = of_find_device_by_node(args->np);
 753         if (!ipmmu_pdev)
 754                 return -ENODEV;
 755
 756         dev->iommu_fwspec->iommu_priv = platform_get_drvdata(ipmmu_pdev);
 757         return 0;
 758 }
 759
 760 static bool ipmmu_slave_whitelist(struct device *dev)
 761 {
 762         /* By default, do not allow use of IPMMU */
 763         return false;
 764 }
 765
 766 static const struct soc_device_attribute soc_rcar_gen3[] = {
 767         { .soc_id = "r8a7795", },
 768         { .soc_id = "r8a7796", },
 769         { .soc_id = "r8a77965", },
 770         { .soc_id = "r8a77970", },
 771         { .soc_id = "r8a77995", },
 772         { /* sentinel */ }
 773 };
 774
 775 static int ipmmu_of_xlate(struct device *dev,
 776                           struct of_phandle_args *spec)
 777 {
 778         /* For R-Car Gen3 use a white list to opt-in slave devices */
 779         if (soc_device_match(soc_rcar_gen3) && !ipmmu_slave_whitelist(dev))
 780                 return -ENODEV;
 781
 782         iommu_fwspec_add_ids(dev, spec->args, 1);
 783
 784         /* Initialize once - xlate() will call multiple times */
 785         if (to_ipmmu(dev))
 786                 return 0;
 787
 788         return ipmmu_init_platform_device(dev, spec);
 789 }
 790
 791 static int ipmmu_init_arm_mapping(struct device *dev)
 792 {
 793         struct ipmmu_vmsa_device *mmu = to_ipmmu(dev);
 794         struct iommu_group *group;
 795         int ret;
 796
 797         /* Create a device group and add the device to it. */
 798         group = iommu_group_alloc();
 799         if (IS_ERR(group)) {
 800                 dev_err(dev, "Failed to allocate IOMMU group\n");
 801                 return PTR_ERR(group);
 802         }
 803
 804         ret = iommu_group_add_device(group, dev);
 805         iommu_group_put(group);
 806
 807         if (ret < 0) {
 808                 dev_err(dev, "Failed to add device to IPMMU group\n");
 809                 return ret;
 810         }
 811
 812         /*
 813          * Create the ARM mapping, used by the ARM DMA mapping core to allocate
 814          * VAs. This will allocate a corresponding IOMMU domain.
 815          *
 816          * TODO:
 817          * - Create one mapping per context (TLB).
 818          * - Make the mapping size configurable ? We currently use a 2GB mapping
 819          *   at a 1GB offset to ensure that NULL VAs will fault.
 820          */
 821         if (!mmu->mapping) {
 822                 struct dma_iommu_mapping *mapping;
 823
 824                 mapping = arm_iommu_create_mapping(&platform_bus_type,
 825                                                    SZ_1G, SZ_2G);
 826                 if (IS_ERR(mapping)) {
 827                         dev_err(mmu->dev, "failed to create ARM IOMMU mapping\n");
 828                         ret = PTR_ERR(mapping);
 829                         goto error;
 830                 }
 831
 832                 mmu->mapping = mapping;
 833         }
 834
 835         /* Attach the ARM VA mapping to the device. */
 836         ret = arm_iommu_attach_device(dev, mmu->mapping);
 837         if (ret < 0) {
 838                 dev_err(dev, "Failed to attach device to VA mapping\n");
 839                 goto error;
 840         }
 841
 842         return 0;
 843
 844 error:
 845         iommu_group_remove_device(dev);
 846         if (mmu->mapping)
 847                 arm_iommu_release_mapping(mmu->mapping);
 848
 849         return ret;
 850 }
 851
 852 static int ipmmu_add_device(struct device *dev)
 853 {
 854         struct iommu_group *group;
 855
 856         /*
 857          * Only let through devices that have been verified in xlate()
 858          */
 859         if (!to_ipmmu(dev))
 860                 return -ENODEV;
 861
 862         if (IS_ENABLED(CONFIG_ARM) && !IS_ENABLED(CONFIG_IOMMU_DMA))
 863                 return ipmmu_init_arm_mapping(dev);
 864
 865         group = iommu_group_get_for_dev(dev);
 866         if (IS_ERR(group))
 867                 return PTR_ERR(group);
 868
 869         iommu_group_put(group);
 870         return 0;
 871 }
 872
 873 static void ipmmu_remove_device(struct device *dev)
 874 {
 875         arm_iommu_detach_device(dev);
 876         iommu_group_remove_device(dev);
 877 }
 878
 879 static struct iommu_group *ipmmu_find_group(struct device *dev)
 880 {
 881         struct ipmmu_vmsa_device *mmu = to_ipmmu(dev);
 882         struct iommu_group *group;
 883
 884         if (mmu->group)
 885                 return iommu_group_ref_get(mmu->group);
 886
 887         group = iommu_group_alloc();
 888         if (!IS_ERR(group))
 889                 mmu->group = group;
 890
 891         return group;
 892 }
 893
 894 static const struct iommu_ops ipmmu_ops = {
 895         .domain_alloc = ipmmu_domain_alloc,
 896         .domain_free = ipmmu_domain_free,
 897         .attach_dev = ipmmu_attach_device,
 898         .detach_dev = ipmmu_detach_device,
 899         .map = ipmmu_map,
 900         .unmap = ipmmu_unmap,
 901         .flush_iotlb_all = ipmmu_iotlb_sync,
 902         .iotlb_sync = ipmmu_iotlb_sync,
 903         .iova_to_phys = ipmmu_iova_to_phys,
 904         .add_device = ipmmu_add_device,
 905         .remove_device = ipmmu_remove_device,
 906         .device_group = ipmmu_find_group,
 907         .pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K,
 908         .of_xlate = ipmmu_of_xlate,
 909 };
 910
 911 /* -----------------------------------------------------------------------------
 912  * Probe/remove and init
 913  */
 914
 915 static void ipmmu_device_reset(struct ipmmu_vmsa_device *mmu)
 916 {
 917         unsigned int i;
 918
 919         /* Disable all contexts. */
 920         for (i = 0; i < mmu->num_ctx; ++i)
 921                 ipmmu_write(mmu, i * IM_CTX_SIZE + IMCTR, 0);
 922 }
 923
 924 static const struct ipmmu_features ipmmu_features_default = {
 925         .use_ns_alias_offset = true,
 926         .has_cache_leaf_nodes = false,
 927         .number_of_contexts = 1, /* software only tested with one context */
 928         .setup_imbuscr = true,
 929         .twobit_imttbcr_sl0 = false,
 930         .reserved_context = false,
 931 };
 932
 933 static const struct ipmmu_features ipmmu_features_rcar_gen3 = {
 934         .use_ns_alias_offset = false,
 935         .has_cache_leaf_nodes = true,
 936         .number_of_contexts = 8,
 937         .setup_imbuscr = false,
 938         .twobit_imttbcr_sl0 = true,
 939         .reserved_context = true,
 940 };
 941
 942 static const struct of_device_id ipmmu_of_ids[] = {
 943         {
 944                 .compatible = "renesas,ipmmu-vmsa",
 945                 .data = &ipmmu_features_default,
 946         }, {
 947                 .compatible = "renesas,ipmmu-r8a7795",
 948                 .data = &ipmmu_features_rcar_gen3,
 949         }, {
 950                 .compatible = "renesas,ipmmu-r8a7796",
 951                 .data = &ipmmu_features_rcar_gen3,
 952         }, {
 953                 .compatible = "renesas,ipmmu-r8a77965",
 954                 .data = &ipmmu_features_rcar_gen3,
 955         }, {
 956                 .compatible = "renesas,ipmmu-r8a77970",
 957                 .data = &ipmmu_features_rcar_gen3,
 958         }, {
 959                 .compatible = "renesas,ipmmu-r8a77995",
 960                 .data = &ipmmu_features_rcar_gen3,
 961         }, {
 962                 /* Terminator */
 963         },
 964 };
 965
 966 MODULE_DEVICE_TABLE(of, ipmmu_of_ids);
 967
 968 static int ipmmu_probe(struct platform_device *pdev)
 969 {
 970         struct ipmmu_vmsa_device *mmu;
 971         struct resource *res;
 972         int irq;
 973         int ret;
 974
 975         mmu = devm_kzalloc(&pdev->dev, sizeof(*mmu), GFP_KERNEL);
 976         if (!mmu) {
 977                 dev_err(&pdev->dev, "cannot allocate device data\n");
 978                 return -ENOMEM;
 979         }
 980
 981         mmu->dev = &pdev->dev;
 982         mmu->num_utlbs = 48;
 983         spin_lock_init(&mmu->lock);
 984         bitmap_zero(mmu->ctx, IPMMU_CTX_MAX);
 985         mmu->features = of_device_get_match_data(&pdev->dev);
 986         dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40));
 987
 988         /* Map I/O memory and request IRQ. */
 989         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 990         mmu->base = devm_ioremap_resource(&pdev->dev, res);
 991         if (IS_ERR(mmu->base))
 992                 return PTR_ERR(mmu->base);
 993
 994         /*
 995          * The IPMMU has two register banks, for secure and non-secure modes.
 996          * The bank mapped at the beginning of the IPMMU address space
 997          * corresponds to the running mode of the CPU. When running in secure
 998          * mode the non-secure register bank is also available at an offset.
 999          *
1000          * Secure mode operation isn't clearly documented and is thus currently
1001          * not implemented in the driver. Furthermore, preliminary tests of
1002          * non-secure operation with the main register bank were not successful.
1003          * Offset the registers base unconditionally to point to the non-secure
1004          * alias space for now.
1005          */
1006         if (mmu->features->use_ns_alias_offset)
1007                 mmu->base += IM_NS_ALIAS_OFFSET;
1008
1009         mmu->num_ctx = min_t(unsigned int, IPMMU_CTX_MAX,
1010                              mmu->features->number_of_contexts);
1011
1012         irq = platform_get_irq(pdev, 0);
1013
1014         /*
1015          * Determine if this IPMMU instance is a root device by checking for
1016          * the lack of has_cache_leaf_nodes flag or renesas,ipmmu-main property.
1017          */
1018         if (!mmu->features->has_cache_leaf_nodes ||
1019             !of_find_property(pdev->dev.of_node, "renesas,ipmmu-main", NULL))
1020                 mmu->root = mmu;
1021         else
1022                 mmu->root = ipmmu_find_root();
1023
1024         /*
1025          * Wait until the root device has been registered for sure.
1026          */
1027         if (!mmu->root)
1028                 return -EPROBE_DEFER;
1029
1030         /* Root devices have mandatory IRQs */
1031         if (ipmmu_is_root(mmu)) {
1032                 if (irq < 0) {
1033                         dev_err(&pdev->dev, "no IRQ found\n");
1034                         return irq;
1035                 }
1036
1037                 ret = devm_request_irq(&pdev->dev, irq, ipmmu_irq, 0,
1038                                        dev_name(&pdev->dev), mmu);
1039                 if (ret < 0) {
1040                         dev_err(&pdev->dev, "failed to request IRQ %d\n", irq);
1041                         return ret;
1042                 }
1043
1044                 ipmmu_device_reset(mmu);
1045
1046                 if (mmu->features->reserved_context) {
1047                         dev_info(&pdev->dev, "IPMMU context 0 is reserved\n");
1048                         set_bit(0, mmu->ctx);
1049                 }
1050         }
1051
1052         /*
1053          * Register the IPMMU to the IOMMU subsystem in the following cases:
1054          * - R-Car Gen2 IPMMU (all devices registered)
1055          * - R-Car Gen3 IPMMU (leaf devices only - skip root IPMMU-MM device)
1056          */
1057         if (!mmu->features->has_cache_leaf_nodes || !ipmmu_is_root(mmu)) {
1058                 ret = iommu_device_sysfs_add(&mmu->iommu, &pdev->dev, NULL,
1059                                              dev_name(&pdev->dev));
1060                 if (ret)
1061                         return ret;
1062
1063                 iommu_device_set_ops(&mmu->iommu, &ipmmu_ops);
1064                 iommu_device_set_fwnode(&mmu->iommu,
1065                                         &pdev->dev.of_node->fwnode);
1066
1067                 ret = iommu_device_register(&mmu->iommu);
1068                 if (ret)
1069                         return ret;
1070
1071 #if defined(CONFIG_IOMMU_DMA)
1072                 if (!iommu_present(&platform_bus_type))
1073                         bus_set_iommu(&platform_bus_type, &ipmmu_ops);
1074 #endif
1075         }
1076
1077         /*
1078          * We can't create the ARM mapping here as it requires the bus to have
1079          * an IOMMU, which only happens when bus_set_iommu() is called in
1080          * ipmmu_init() after the probe function returns.
1081          */
1082
1083         platform_set_drvdata(pdev, mmu);
1084
1085         return 0;
1086 }
1087
1088 static int ipmmu_remove(struct platform_device *pdev)
1089 {
1090         struct ipmmu_vmsa_device *mmu = platform_get_drvdata(pdev);
1091
1092         iommu_device_sysfs_remove(&mmu->iommu);
1093         iommu_device_unregister(&mmu->iommu);
1094
1095         arm_iommu_release_mapping(mmu->mapping);
1096
1097         ipmmu_device_reset(mmu);
1098
1099         return 0;
1100 }
1101
1102 static struct platform_driver ipmmu_driver = {
1103         .driver = {
1104                 .name = "ipmmu-vmsa",
1105                 .of_match_table = of_match_ptr(ipmmu_of_ids),
1106         },
1107         .probe = ipmmu_probe,
1108         .remove = ipmmu_remove,
1109 };
1110
1111 static int __init ipmmu_init(void)
1112 {
1113         struct device_node *np;
1114         static bool setup_done;
1115         int ret;
1116
1117         if (setup_done)
1118                 return 0;
1119
1120         np = of_find_matching_node(NULL, ipmmu_of_ids);
1121         if (!np)
1122                 return 0;
1123
1124         of_node_put(np);
1125
1126         ret = platform_driver_register(&ipmmu_driver);
1127         if (ret < 0)
1128                 return ret;
1129
1130 #if defined(CONFIG_ARM) && !defined(CONFIG_IOMMU_DMA)
1131         if (!iommu_present(&platform_bus_type))
1132                 bus_set_iommu(&platform_bus_type, &ipmmu_ops);
1133 #endif
1134
1135         setup_done = true;
1136         return 0;
1137 }
1138
1139 static void __exit ipmmu_exit(void)
1140 {
1141         return platform_driver_unregister(&ipmmu_driver);
1142 }
1143
1144 subsys_initcall(ipmmu_init);
1145 module_exit(ipmmu_exit);
1146
1147 MODULE_DESCRIPTION("IOMMU API for Renesas VMSA-compatible IPMMU");
1148 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
1149 MODULE_LICENSE("GPL v2");