drivers/media/dvb-frontends/dib8000.c

   1 /*
   2  * Linux-DVB Driver for DiBcom's DiB8000 chip (ISDB-T).
   3  *
   4  * Copyright (C) 2009 DiBcom (http://www.dibcom.fr/)
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  *  modify it under the terms of the GNU General Public License as
   8  *  published by the Free Software Foundation, version 2.
   9  */
  10
  11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  12
  13 #include <linux/kernel.h>
  14 #include <linux/slab.h>
  15 #include <linux/i2c.h>
  16 #include <linux/mutex.h>
  17 #include <asm/div64.h>
  18
  19 #include <media/dvb_math.h>
  20
  21 #include <media/dvb_frontend.h>
  22
  23 #include "dib8000.h"
  24
  25 #define LAYER_ALL -1
  26 #define LAYER_A   1
  27 #define LAYER_B   2
  28 #define LAYER_C   3
  29
  30 #define MAX_NUMBER_OF_FRONTENDS 6
  31 /* #define DIB8000_AGC_FREEZE */
  32
  33 static int debug;
  34 module_param(debug, int, 0644);
  35 MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
  36
  37 #define dprintk(fmt, arg...) do {                                       \
  38         if (debug)                                                      \
  39                 printk(KERN_DEBUG pr_fmt("%s: " fmt),                   \
  40                        __func__, ##arg);                                \
  41 } while (0)
  42
  43 struct i2c_device {
  44         struct i2c_adapter *adap;
  45         u8 addr;
  46         u8 *i2c_write_buffer;
  47         u8 *i2c_read_buffer;
  48         struct mutex *i2c_buffer_lock;
  49 };
  50
  51 enum param_loop_step {
  52         LOOP_TUNE_1,
  53         LOOP_TUNE_2
  54 };
  55
  56 enum dib8000_autosearch_step {
  57         AS_START = 0,
  58         AS_SEARCHING_FFT,
  59         AS_SEARCHING_GUARD,
  60         AS_DONE = 100,
  61 };
  62
  63 enum timeout_mode {
  64         SYMBOL_DEPENDENT_OFF = 0,
  65         SYMBOL_DEPENDENT_ON,
  66 };
  67
  68 struct dib8000_state {
  69         struct dib8000_config cfg;
  70
  71         struct i2c_device i2c;
  72
  73         struct dibx000_i2c_master i2c_master;
  74
  75         u16 wbd_ref;
  76
  77         u8 current_band;
  78         u32 current_bandwidth;
  79         struct dibx000_agc_config *current_agc;
  80         u32 timf;
  81         u32 timf_default;
  82
  83         u8 div_force_off:1;
  84         u8 div_state:1;
  85         u16 div_sync_wait;
  86
  87         u8 agc_state;
  88         u8 differential_constellation;
  89         u8 diversity_onoff;
  90
  91         s16 ber_monitored_layer;
  92         u16 gpio_dir;
  93         u16 gpio_val;
  94
  95         u16 revision;
  96         u8 isdbt_cfg_loaded;
  97         enum frontend_tune_state tune_state;
  98         s32 status;
  99
 100         struct dvb_frontend *fe[MAX_NUMBER_OF_FRONTENDS];
 101
 102         /* for the I2C transfer */
 103         struct i2c_msg msg[2];
 104         u8 i2c_write_buffer[4];
 105         u8 i2c_read_buffer[2];
 106         struct mutex i2c_buffer_lock;
 107         u8 input_mode_mpeg;
 108
 109         u16 tuner_enable;
 110         struct i2c_adapter dib8096p_tuner_adap;
 111         u16 current_demod_bw;
 112
 113         u16 seg_mask;
 114         u16 seg_diff_mask;
 115         u16 mode;
 116         u8 layer_b_nb_seg;
 117         u8 layer_c_nb_seg;
 118
 119         u8 channel_parameters_set;
 120         u16 autosearch_state;
 121         u16 found_nfft;
 122         u16 found_guard;
 123         u8 subchannel;
 124         u8 symbol_duration;
 125         unsigned long timeout;
 126         u8 longest_intlv_layer;
 127         u16 output_mode;
 128
 129         /* for DVBv5 stats */
 130         s64 init_ucb;
 131         unsigned long per_jiffies_stats;
 132         unsigned long ber_jiffies_stats;
 133         unsigned long ber_jiffies_stats_layer[3];
 134
 135 #ifdef DIB8000_AGC_FREEZE
 136         u16 agc1_max;
 137         u16 agc1_min;
 138         u16 agc2_max;
 139         u16 agc2_min;
 140 #endif
 141 };
 142
 143 enum dib8000_power_mode {
 144         DIB8000_POWER_ALL = 0,
 145         DIB8000_POWER_INTERFACE_ONLY,
 146 };
 147
 148 static u16 dib8000_i2c_read16(struct i2c_device *i2c, u16 reg)
 149 {
 150         u16 ret;
 151         struct i2c_msg msg[2] = {
 152                 {.addr = i2c->addr >> 1, .flags = 0, .len = 2},
 153                 {.addr = i2c->addr >> 1, .flags = I2C_M_RD, .len = 2},
 154         };
 155
 156         if (mutex_lock_interruptible(i2c->i2c_buffer_lock) < 0) {
 157                 dprintk("could not acquire lock\n");
 158                 return 0;
 159         }
 160
 161         msg[0].buf    = i2c->i2c_write_buffer;
 162         msg[0].buf[0] = reg >> 8;
 163         msg[0].buf[1] = reg & 0xff;
 164         msg[1].buf    = i2c->i2c_read_buffer;
 165
 166         if (i2c_transfer(i2c->adap, msg, 2) != 2)
 167                 dprintk("i2c read error on %d\n", reg);
 168
 169         ret = (msg[1].buf[0] << 8) | msg[1].buf[1];
 170         mutex_unlock(i2c->i2c_buffer_lock);
 171         return ret;
 172 }
 173
 174 static u16 __dib8000_read_word(struct dib8000_state *state, u16 reg)
 175 {
 176         u16 ret;
 177
 178         state->i2c_write_buffer[0] = reg >> 8;
 179         state->i2c_write_buffer[1] = reg & 0xff;
 180
 181         memset(state->msg, 0, 2 * sizeof(struct i2c_msg));
 182         state->msg[0].addr = state->i2c.addr >> 1;
 183         state->msg[0].flags = 0;
 184         state->msg[0].buf = state->i2c_write_buffer;
 185         state->msg[0].len = 2;
 186         state->msg[1].addr = state->i2c.addr >> 1;
 187         state->msg[1].flags = I2C_M_RD;
 188         state->msg[1].buf = state->i2c_read_buffer;
 189         state->msg[1].len = 2;
 190
 191         if (i2c_transfer(state->i2c.adap, state->msg, 2) != 2)
 192                 dprintk("i2c read error on %d\n", reg);
 193
 194         ret = (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1];
 195
 196         return ret;
 197 }
 198
 199 static u16 dib8000_read_word(struct dib8000_state *state, u16 reg)
 200 {
 201         u16 ret;
 202
 203         if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
 204                 dprintk("could not acquire lock\n");
 205                 return 0;
 206         }
 207
 208         ret = __dib8000_read_word(state, reg);
 209
 210         mutex_unlock(&state->i2c_buffer_lock);
 211
 212         return ret;
 213 }
 214
 215 static u32 dib8000_read32(struct dib8000_state *state, u16 reg)
 216 {
 217         u16 rw[2];
 218
 219         if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
 220                 dprintk("could not acquire lock\n");
 221                 return 0;
 222         }
 223
 224         rw[0] = __dib8000_read_word(state, reg + 0);
 225         rw[1] = __dib8000_read_word(state, reg + 1);
 226
 227         mutex_unlock(&state->i2c_buffer_lock);
 228
 229         return ((rw[0] << 16) | (rw[1]));
 230 }
 231
 232 static int dib8000_i2c_write16(struct i2c_device *i2c, u16 reg, u16 val)
 233 {
 234         struct i2c_msg msg = {.addr = i2c->addr >> 1, .flags = 0, .len = 4};
 235         int ret = 0;
 236
 237         if (mutex_lock_interruptible(i2c->i2c_buffer_lock) < 0) {
 238                 dprintk("could not acquire lock\n");
 239                 return -EINVAL;
 240         }
 241
 242         msg.buf    = i2c->i2c_write_buffer;
 243         msg.buf[0] = (reg >> 8) & 0xff;
 244         msg.buf[1] = reg & 0xff;
 245         msg.buf[2] = (val >> 8) & 0xff;
 246         msg.buf[3] = val & 0xff;
 247
 248         ret = i2c_transfer(i2c->adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
 249         mutex_unlock(i2c->i2c_buffer_lock);
 250
 251         return ret;
 252 }
 253
 254 static int dib8000_write_word(struct dib8000_state *state, u16 reg, u16 val)
 255 {
 256         int ret;
 257
 258         if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
 259                 dprintk("could not acquire lock\n");
 260                 return -EINVAL;
 261         }
 262
 263         state->i2c_write_buffer[0] = (reg >> 8) & 0xff;
 264         state->i2c_write_buffer[1] = reg & 0xff;
 265         state->i2c_write_buffer[2] = (val >> 8) & 0xff;
 266         state->i2c_write_buffer[3] = val & 0xff;
 267
 268         memset(&state->msg[0], 0, sizeof(struct i2c_msg));
 269         state->msg[0].addr = state->i2c.addr >> 1;
 270         state->msg[0].flags = 0;
 271         state->msg[0].buf = state->i2c_write_buffer;
 272         state->msg[0].len = 4;
 273
 274         ret = (i2c_transfer(state->i2c.adap, state->msg, 1) != 1 ?
 275                         -EREMOTEIO : 0);
 276         mutex_unlock(&state->i2c_buffer_lock);
 277
 278         return ret;
 279 }
 280
 281 static const s16 coeff_2k_sb_1seg_dqpsk[8] = {
 282         (769 << 5) | 0x0a, (745 << 5) | 0x03, (595 << 5) | 0x0d, (769 << 5) | 0x0a, (920 << 5) | 0x09, (784 << 5) | 0x02, (519 << 5) | 0x0c,
 283                 (920 << 5) | 0x09
 284 };
 285
 286 static const s16 coeff_2k_sb_1seg[8] = {
 287         (692 << 5) | 0x0b, (683 << 5) | 0x01, (519 << 5) | 0x09, (692 << 5) | 0x0b, 0 | 0x1f, 0 | 0x1f, 0 | 0x1f, 0 | 0x1f
 288 };
 289
 290 static const s16 coeff_2k_sb_3seg_0dqpsk_1dqpsk[8] = {
 291         (832 << 5) | 0x10, (912 << 5) | 0x05, (900 << 5) | 0x12, (832 << 5) | 0x10, (-931 << 5) | 0x0f, (912 << 5) | 0x04, (807 << 5) | 0x11,
 292                 (-931 << 5) | 0x0f
 293 };
 294
 295 static const s16 coeff_2k_sb_3seg_0dqpsk[8] = {
 296         (622 << 5) | 0x0c, (941 << 5) | 0x04, (796 << 5) | 0x10, (622 << 5) | 0x0c, (982 << 5) | 0x0c, (519 << 5) | 0x02, (572 << 5) | 0x0e,
 297                 (982 << 5) | 0x0c
 298 };
 299
 300 static const s16 coeff_2k_sb_3seg_1dqpsk[8] = {
 301         (699 << 5) | 0x14, (607 << 5) | 0x04, (944 << 5) | 0x13, (699 << 5) | 0x14, (-720 << 5) | 0x0d, (640 << 5) | 0x03, (866 << 5) | 0x12,
 302                 (-720 << 5) | 0x0d
 303 };
 304
 305 static const s16 coeff_2k_sb_3seg[8] = {
 306         (664 << 5) | 0x0c, (925 << 5) | 0x03, (937 << 5) | 0x10, (664 << 5) | 0x0c, (-610 << 5) | 0x0a, (697 << 5) | 0x01, (836 << 5) | 0x0e,
 307                 (-610 << 5) | 0x0a
 308 };
 309
 310 static const s16 coeff_4k_sb_1seg_dqpsk[8] = {
 311         (-955 << 5) | 0x0e, (687 << 5) | 0x04, (818 << 5) | 0x10, (-955 << 5) | 0x0e, (-922 << 5) | 0x0d, (750 << 5) | 0x03, (665 << 5) | 0x0f,
 312                 (-922 << 5) | 0x0d
 313 };
 314
 315 static const s16 coeff_4k_sb_1seg[8] = {
 316         (638 << 5) | 0x0d, (683 << 5) | 0x02, (638 << 5) | 0x0d, (638 << 5) | 0x0d, (-655 << 5) | 0x0a, (517 << 5) | 0x00, (698 << 5) | 0x0d,
 317                 (-655 << 5) | 0x0a
 318 };
 319
 320 static const s16 coeff_4k_sb_3seg_0dqpsk_1dqpsk[8] = {
 321         (-707 << 5) | 0x14, (910 << 5) | 0x06, (889 << 5) | 0x16, (-707 << 5) | 0x14, (-958 << 5) | 0x13, (993 << 5) | 0x05, (523 << 5) | 0x14,
 322                 (-958 << 5) | 0x13
 323 };
 324
 325 static const s16 coeff_4k_sb_3seg_0dqpsk[8] = {
 326         (-723 << 5) | 0x13, (910 << 5) | 0x05, (777 << 5) | 0x14, (-723 << 5) | 0x13, (-568 << 5) | 0x0f, (547 << 5) | 0x03, (696 << 5) | 0x12,
 327                 (-568 << 5) | 0x0f
 328 };
 329
 330 static const s16 coeff_4k_sb_3seg_1dqpsk[8] = {
 331         (-940 << 5) | 0x15, (607 << 5) | 0x05, (915 << 5) | 0x16, (-940 << 5) | 0x15, (-848 << 5) | 0x13, (683 << 5) | 0x04, (543 << 5) | 0x14,
 332                 (-848 << 5) | 0x13
 333 };
 334
 335 static const s16 coeff_4k_sb_3seg[8] = {
 336         (612 << 5) | 0x12, (910 << 5) | 0x04, (864 << 5) | 0x14, (612 << 5) | 0x12, (-869 << 5) | 0x13, (683 << 5) | 0x02, (869 << 5) | 0x12,
 337                 (-869 << 5) | 0x13
 338 };
 339
 340 static const s16 coeff_8k_sb_1seg_dqpsk[8] = {
 341         (-835 << 5) | 0x12, (684 << 5) | 0x05, (735 << 5) | 0x14, (-835 << 5) | 0x12, (-598 << 5) | 0x10, (781 << 5) | 0x04, (739 << 5) | 0x13,
 342                 (-598 << 5) | 0x10
 343 };
 344
 345 static const s16 coeff_8k_sb_1seg[8] = {
 346         (673 << 5) | 0x0f, (683 << 5) | 0x03, (808 << 5) | 0x12, (673 << 5) | 0x0f, (585 << 5) | 0x0f, (512 << 5) | 0x01, (780 << 5) | 0x0f,
 347                 (585 << 5) | 0x0f
 348 };
 349
 350 static const s16 coeff_8k_sb_3seg_0dqpsk_1dqpsk[8] = {
 351         (863 << 5) | 0x17, (930 << 5) | 0x07, (878 << 5) | 0x19, (863 << 5) | 0x17, (0 << 5) | 0x14, (521 << 5) | 0x05, (980 << 5) | 0x18,
 352                 (0 << 5) | 0x14
 353 };
 354
 355 static const s16 coeff_8k_sb_3seg_0dqpsk[8] = {
 356         (-924 << 5) | 0x17, (910 << 5) | 0x06, (774 << 5) | 0x17, (-924 << 5) | 0x17, (-877 << 5) | 0x15, (565 << 5) | 0x04, (553 << 5) | 0x15,
 357                 (-877 << 5) | 0x15
 358 };
 359
 360 static const s16 coeff_8k_sb_3seg_1dqpsk[8] = {
 361         (-921 << 5) | 0x19, (607 << 5) | 0x06, (881 << 5) | 0x19, (-921 << 5) | 0x19, (-921 << 5) | 0x14, (713 << 5) | 0x05, (1018 << 5) | 0x18,
 362                 (-921 << 5) | 0x14
 363 };
 364
 365 static const s16 coeff_8k_sb_3seg[8] = {
 366         (514 << 5) | 0x14, (910 << 5) | 0x05, (861 << 5) | 0x17, (514 << 5) | 0x14, (690 << 5) | 0x14, (683 << 5) | 0x03, (662 << 5) | 0x15,
 367                 (690 << 5) | 0x14
 368 };
 369
 370 static const s16 ana_fe_coeff_3seg[24] = {
 371         81, 80, 78, 74, 68, 61, 54, 45, 37, 28, 19, 11, 4, 1022, 1017, 1013, 1010, 1008, 1008, 1008, 1008, 1010, 1014, 1017
 372 };
 373
 374 static const s16 ana_fe_coeff_1seg[24] = {
 375         249, 226, 164, 82, 5, 981, 970, 988, 1018, 20, 31, 26, 8, 1012, 1000, 1018, 1012, 8, 15, 14, 9, 3, 1017, 1003
 376 };
 377
 378 static const s16 ana_fe_coeff_13seg[24] = {
 379         396, 305, 105, -51, -77, -12, 41, 31, -11, -30, -11, 14, 15, -2, -13, -7, 5, 8, 1, -6, -7, -3, 0, 1
 380 };
 381
 382 static u16 fft_to_mode(struct dib8000_state *state)
 383 {
 384         u16 mode;
 385         switch (state->fe[0]->dtv_property_cache.transmission_mode) {
 386         case TRANSMISSION_MODE_2K:
 387                 mode = 1;
 388                 break;
 389         case TRANSMISSION_MODE_4K:
 390                 mode = 2;
 391                 break;
 392         default:
 393         case TRANSMISSION_MODE_AUTO:
 394         case TRANSMISSION_MODE_8K:
 395                 mode = 3;
 396                 break;
 397         }
 398         return mode;
 399 }
 400
 401 static void dib8000_set_acquisition_mode(struct dib8000_state *state)
 402 {
 403         u16 nud = dib8000_read_word(state, 298);
 404         nud |= (1 << 3) | (1 << 0);
 405         dprintk("acquisition mode activated\n");
 406         dib8000_write_word(state, 298, nud);
 407 }
 408 static int dib8000_set_output_mode(struct dvb_frontend *fe, int mode)
 409 {
 410         struct dib8000_state *state = fe->demodulator_priv;
 411         u16 outreg, fifo_threshold, smo_mode, sram = 0x0205;    /* by default SDRAM deintlv is enabled */
 412
 413         state->output_mode = mode;
 414         outreg = 0;
 415         fifo_threshold = 1792;
 416         smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1);
 417
 418         dprintk("-I-    Setting output mode for demod %p to %d\n",
 419                         &state->fe[0], mode);
 420
 421         switch (mode) {
 422         case OUTMODE_MPEG2_PAR_GATED_CLK:       // STBs with parallel gated clock
 423                 outreg = (1 << 10);     /* 0x0400 */
 424                 break;
 425         case OUTMODE_MPEG2_PAR_CONT_CLK:        // STBs with parallel continues clock
 426                 outreg = (1 << 10) | (1 << 6);  /* 0x0440 */
 427                 break;
 428         case OUTMODE_MPEG2_SERIAL:      // STBs with serial input
 429                 outreg = (1 << 10) | (2 << 6) | (0 << 1);       /* 0x0482 */
 430                 break;
 431         case OUTMODE_DIVERSITY:
 432                 if (state->cfg.hostbus_diversity) {
 433                         outreg = (1 << 10) | (4 << 6);  /* 0x0500 */
 434                         sram &= 0xfdff;
 435                 } else
 436                         sram |= 0x0c00;
 437                 break;
 438         case OUTMODE_MPEG2_FIFO:        // e.g. USB feeding
 439                 smo_mode |= (3 << 1);
 440                 fifo_threshold = 512;
 441                 outreg = (1 << 10) | (5 << 6);
 442                 break;
 443         case OUTMODE_HIGH_Z:    // disable
 444                 outreg = 0;
 445                 break;
 446
 447         case OUTMODE_ANALOG_ADC:
 448                 outreg = (1 << 10) | (3 << 6);
 449                 dib8000_set_acquisition_mode(state);
 450                 break;
 451
 452         default:
 453                 dprintk("Unhandled output_mode passed to be set for demod %p\n",
 454                                 &state->fe[0]);
 455                 return -EINVAL;
 456         }
 457
 458         if (state->cfg.output_mpeg2_in_188_bytes)
 459                 smo_mode |= (1 << 5);
 460
 461         dib8000_write_word(state, 299, smo_mode);
 462         dib8000_write_word(state, 300, fifo_threshold); /* synchronous fread */
 463         dib8000_write_word(state, 1286, outreg);
 464         dib8000_write_word(state, 1291, sram);
 465
 466         return 0;
 467 }
 468
 469 static int dib8000_set_diversity_in(struct dvb_frontend *fe, int onoff)
 470 {
 471         struct dib8000_state *state = fe->demodulator_priv;
 472         u16 tmp, sync_wait = dib8000_read_word(state, 273) & 0xfff0;
 473
 474         dprintk("set diversity input to %i\n", onoff);
 475         if (!state->differential_constellation) {
 476                 dib8000_write_word(state, 272, 1 << 9); //dvsy_off_lmod4 = 1
 477                 dib8000_write_word(state, 273, sync_wait | (1 << 2) | 2);       // sync_enable = 1; comb_mode = 2
 478         } else {
 479                 dib8000_write_word(state, 272, 0);      //dvsy_off_lmod4 = 0
 480                 dib8000_write_word(state, 273, sync_wait);      // sync_enable = 0; comb_mode = 0
 481         }
 482         state->diversity_onoff = onoff;
 483
 484         switch (onoff) {
 485         case 0:         /* only use the internal way - not the diversity input */
 486                 dib8000_write_word(state, 270, 1);
 487                 dib8000_write_word(state, 271, 0);
 488                 break;
 489         case 1:         /* both ways */
 490                 dib8000_write_word(state, 270, 6);
 491                 dib8000_write_word(state, 271, 6);
 492                 break;
 493         case 2:         /* only the diversity input */
 494                 dib8000_write_word(state, 270, 0);
 495                 dib8000_write_word(state, 271, 1);
 496                 break;
 497         }
 498
 499         if (state->revision == 0x8002) {
 500                 tmp = dib8000_read_word(state, 903);
 501                 dib8000_write_word(state, 903, tmp & ~(1 << 3));
 502                 msleep(30);
 503                 dib8000_write_word(state, 903, tmp | (1 << 3));
 504         }
 505         return 0;
 506 }
 507
 508 static void dib8000_set_power_mode(struct dib8000_state *state, enum dib8000_power_mode mode)
 509 {
 510         /* by default everything is going to be powered off */
 511         u16 reg_774 = 0x3fff, reg_775 = 0xffff, reg_776 = 0xffff,
 512                 reg_900 = (dib8000_read_word(state, 900) & 0xfffc) | 0x3,
 513                 reg_1280;
 514
 515         if (state->revision != 0x8090)
 516                 reg_1280 = (dib8000_read_word(state, 1280) & 0x00ff) | 0xff00;
 517         else
 518                 reg_1280 = (dib8000_read_word(state, 1280) & 0x707f) | 0x8f80;
 519
 520         /* now, depending on the requested mode, we power on */
 521         switch (mode) {
 522                 /* power up everything in the demod */
 523         case DIB8000_POWER_ALL:
 524                 reg_774 = 0x0000;
 525                 reg_775 = 0x0000;
 526                 reg_776 = 0x0000;
 527                 reg_900 &= 0xfffc;
 528                 if (state->revision != 0x8090)
 529                         reg_1280 &= 0x00ff;
 530                 else
 531                         reg_1280 &= 0x707f;
 532                 break;
 533         case DIB8000_POWER_INTERFACE_ONLY:
 534                 if (state->revision != 0x8090)
 535                         reg_1280 &= 0x00ff;
 536                 else
 537                         reg_1280 &= 0xfa7b;
 538                 break;
 539         }
 540
 541         dprintk("powermode : 774 : %x ; 775 : %x; 776 : %x ; 900 : %x; 1280 : %x\n", reg_774, reg_775, reg_776, reg_900, reg_1280);
 542         dib8000_write_word(state, 774, reg_774);
 543         dib8000_write_word(state, 775, reg_775);
 544         dib8000_write_word(state, 776, reg_776);
 545         dib8000_write_word(state, 900, reg_900);
 546         dib8000_write_word(state, 1280, reg_1280);
 547 }
 548
 549 static int dib8000_set_adc_state(struct dib8000_state *state, enum dibx000_adc_states no)
 550 {
 551         int ret = 0;
 552         u16 reg, reg_907 = dib8000_read_word(state, 907);
 553         u16 reg_908 = dib8000_read_word(state, 908);
 554
 555         switch (no) {
 556         case DIBX000_SLOW_ADC_ON:
 557                 if (state->revision != 0x8090) {
 558                         reg_908 |= (1 << 1) | (1 << 0);
 559                         ret |= dib8000_write_word(state, 908, reg_908);
 560                         reg_908 &= ~(1 << 1);
 561                 } else {
 562                         reg = dib8000_read_word(state, 1925);
 563                         /* en_slowAdc = 1 & reset_sladc = 1 */
 564                         dib8000_write_word(state, 1925, reg |
 565                                         (1<<4) | (1<<2));
 566
 567                         /* read acces to make it works... strange ... */
 568                         reg = dib8000_read_word(state, 1925);
 569                         msleep(20);
 570                         /* en_slowAdc = 1 & reset_sladc = 0 */
 571                         dib8000_write_word(state, 1925, reg & ~(1<<4));
 572
 573                         reg = dib8000_read_word(state, 921) & ~((0x3 << 14)
 574                                         | (0x3 << 12));
 575                         /* ref = Vin1 => Vbg ; sel = Vin0 or Vin3 ;
 576                            (Vin2 = Vcm) */
 577                         dib8000_write_word(state, 921, reg | (1 << 14)
 578                                         | (3 << 12));
 579                 }
 580                 break;
 581
 582         case DIBX000_SLOW_ADC_OFF:
 583                 if (state->revision == 0x8090) {
 584                         reg = dib8000_read_word(state, 1925);
 585                         /* reset_sladc = 1 en_slowAdc = 0 */
 586                         dib8000_write_word(state, 1925,
 587                                         (reg & ~(1<<2)) | (1<<4));
 588                 }
 589                 reg_908 |= (1 << 1) | (1 << 0);
 590                 break;
 591
 592         case DIBX000_ADC_ON:
 593                 reg_907 &= 0x0fff;
 594                 reg_908 &= 0x0003;
 595                 break;
 596
 597         case DIBX000_ADC_OFF:   // leave the VBG voltage on
 598                 reg_907 = (1 << 13) | (1 << 12);
 599                 reg_908 = (1 << 6) | (1 << 5) | (1 << 4) | (1 << 3) | (1 << 1);
 600                 break;
 601
 602         case DIBX000_VBG_ENABLE:
 603                 reg_907 &= ~(1 << 15);
 604                 break;
 605
 606         case DIBX000_VBG_DISABLE:
 607                 reg_907 |= (1 << 15);
 608                 break;
 609
 610         default:
 611                 break;
 612         }
 613
 614         ret |= dib8000_write_word(state, 907, reg_907);
 615         ret |= dib8000_write_word(state, 908, reg_908);
 616
 617         return ret;
 618 }
 619
 620 static int dib8000_set_bandwidth(struct dvb_frontend *fe, u32 bw)
 621 {
 622         struct dib8000_state *state = fe->demodulator_priv;
 623         u32 timf;
 624
 625         if (bw == 0)
 626                 bw = 6000;
 627
 628         if (state->timf == 0) {
 629                 dprintk("using default timf\n");
 630                 timf = state->timf_default;
 631         } else {
 632                 dprintk("using updated timf\n");
 633                 timf = state->timf;
 634         }
 635
 636         dib8000_write_word(state, 29, (u16) ((timf >> 16) & 0xffff));
 637         dib8000_write_word(state, 30, (u16) ((timf) & 0xffff));
 638
 639         return 0;
 640 }
 641
 642 static int dib8000_sad_calib(struct dib8000_state *state)
 643 {
 644         u8 sad_sel = 3;
 645
 646         if (state->revision == 0x8090) {
 647                 dib8000_write_word(state, 922, (sad_sel << 2));
 648                 dib8000_write_word(state, 923, 2048);
 649
 650                 dib8000_write_word(state, 922, (sad_sel << 2) | 0x1);
 651                 dib8000_write_word(state, 922, (sad_sel << 2));
 652         } else {
 653                 /* internal */
 654                 dib8000_write_word(state, 923, (0 << 1) | (0 << 0));
 655                 dib8000_write_word(state, 924, 776);
 656
 657                 /* do the calibration */
 658                 dib8000_write_word(state, 923, (1 << 0));
 659                 dib8000_write_word(state, 923, (0 << 0));
 660         }
 661
 662         msleep(1);
 663         return 0;
 664 }
 665
 666 static int dib8000_set_wbd_ref(struct dvb_frontend *fe, u16 value)
 667 {
 668         struct dib8000_state *state = fe->demodulator_priv;
 669         if (value > 4095)
 670                 value = 4095;
 671         state->wbd_ref = value;
 672         return dib8000_write_word(state, 106, value);
 673 }
 674
 675 static void dib8000_reset_pll_common(struct dib8000_state *state, const struct dibx000_bandwidth_config *bw)
 676 {
 677         dprintk("ifreq: %d %x, inversion: %d\n", bw->ifreq, bw->ifreq, bw->ifreq >> 25);
 678         if (state->revision != 0x8090) {
 679                 dib8000_write_word(state, 23,
 680                                 (u16) (((bw->internal * 1000) >> 16) & 0xffff));
 681                 dib8000_write_word(state, 24,
 682                                 (u16) ((bw->internal * 1000) & 0xffff));
 683         } else {
 684                 dib8000_write_word(state, 23, (u16) (((bw->internal / 2 * 1000) >> 16) & 0xffff));
 685                 dib8000_write_word(state, 24,
 686                                 (u16) ((bw->internal  / 2 * 1000) & 0xffff));
 687         }
 688         dib8000_write_word(state, 27, (u16) ((bw->ifreq >> 16) & 0x01ff));
 689         dib8000_write_word(state, 28, (u16) (bw->ifreq & 0xffff));
 690         dib8000_write_word(state, 26, (u16) ((bw->ifreq >> 25) & 0x0003));
 691
 692         if (state->revision != 0x8090)
 693                 dib8000_write_word(state, 922, bw->sad_cfg);
 694 }
 695
 696 static void dib8000_reset_pll(struct dib8000_state *state)
 697 {
 698         const struct dibx000_bandwidth_config *pll = state->cfg.pll;
 699         u16 clk_cfg1, reg;
 700
 701         if (state->revision != 0x8090) {
 702                 dib8000_write_word(state, 901,
 703                                 (pll->pll_prediv << 8) | (pll->pll_ratio << 0));
 704
 705                 clk_cfg1 = (1 << 10) | (0 << 9) | (pll->IO_CLK_en_core << 8) |
 706                         (pll->bypclk_div << 5) | (pll->enable_refdiv << 4) |
 707                         (1 << 3) | (pll->pll_range << 1) |
 708                         (pll->pll_reset << 0);
 709
 710                 dib8000_write_word(state, 902, clk_cfg1);
 711                 clk_cfg1 = (clk_cfg1 & 0xfff7) | (pll->pll_bypass << 3);
 712                 dib8000_write_word(state, 902, clk_cfg1);
 713
 714                 dprintk("clk_cfg1: 0x%04x\n", clk_cfg1);
 715
 716                 /* smpl_cfg: P_refclksel=2, P_ensmplsel=1 nodivsmpl=1 */
 717                 if (state->cfg.pll->ADClkSrc == 0)
 718                         dib8000_write_word(state, 904,
 719                                         (0 << 15) | (0 << 12) | (0 << 10) |
 720                                         (pll->modulo << 8) |
 721                                         (pll->ADClkSrc << 7) | (0 << 1));
 722                 else if (state->cfg.refclksel != 0)
 723                         dib8000_write_word(state, 904, (0 << 15) | (1 << 12) |
 724                                         ((state->cfg.refclksel & 0x3) << 10) |
 725                                         (pll->modulo << 8) |
 726                                         (pll->ADClkSrc << 7) | (0 << 1));
 727                 else
 728                         dib8000_write_word(state, 904, (0 << 15) | (1 << 12) |
 729                                         (3 << 10) | (pll->modulo << 8) |
 730                                         (pll->ADClkSrc << 7) | (0 << 1));
 731         } else {
 732                 dib8000_write_word(state, 1856, (!pll->pll_reset<<13) |
 733                                 (pll->pll_range<<12) | (pll->pll_ratio<<6) |
 734                                 (pll->pll_prediv));
 735
 736                 reg = dib8000_read_word(state, 1857);
 737                 dib8000_write_word(state, 1857, reg|(!pll->pll_bypass<<15));
 738
 739                 reg = dib8000_read_word(state, 1858); /* Force clk out pll /2 */
 740                 dib8000_write_word(state, 1858, reg | 1);
 741
 742                 dib8000_write_word(state, 904, (pll->modulo << 8));
 743         }
 744
 745         dib8000_reset_pll_common(state, pll);
 746 }
 747
 748 static int dib8000_update_pll(struct dvb_frontend *fe,
 749                 struct dibx000_bandwidth_config *pll, u32 bw, u8 ratio)
 750 {
 751         struct dib8000_state *state = fe->demodulator_priv;
 752         u16 reg_1857, reg_1856 = dib8000_read_word(state, 1856);
 753         u8 loopdiv, prediv, oldprediv = state->cfg.pll->pll_prediv ;
 754         u32 internal, xtal;
 755
 756         /* get back old values */
 757         prediv = reg_1856 & 0x3f;
 758         loopdiv = (reg_1856 >> 6) & 0x3f;
 759
 760         if ((pll == NULL) || (pll->pll_prediv == prediv &&
 761                                 pll->pll_ratio == loopdiv))
 762                 return -EINVAL;
 763
 764         dprintk("Updating pll (prediv: old =  %d new = %d ; loopdiv : old = %d new = %d)\n", prediv, pll->pll_prediv, loopdiv, pll->pll_ratio);
 765         if (state->revision == 0x8090) {
 766                 reg_1856 &= 0xf000;
 767                 reg_1857 = dib8000_read_word(state, 1857);
 768                 /* disable PLL */
 769                 dib8000_write_word(state, 1857, reg_1857 & ~(1 << 15));
 770
 771                 dib8000_write_word(state, 1856, reg_1856 |
 772                                 ((pll->pll_ratio & 0x3f) << 6) |
 773                                 (pll->pll_prediv & 0x3f));
 774
 775                 /* write new system clk into P_sec_len */
 776                 internal = dib8000_read32(state, 23) / 1000;
 777                 dprintk("Old Internal = %d\n", internal);
 778                 xtal = 2 * (internal / loopdiv) * prediv;
 779                 internal = 1000 * (xtal/pll->pll_prediv) * pll->pll_ratio;
 780                 dprintk("Xtal = %d , New Fmem = %d New Fdemod = %d, New Fsampling = %d\n", xtal, internal/1000, internal/2000, internal/8000);
 781                 dprintk("New Internal = %d\n", internal);
 782
 783                 dib8000_write_word(state, 23,
 784                                 (u16) (((internal / 2) >> 16) & 0xffff));
 785                 dib8000_write_word(state, 24, (u16) ((internal / 2) & 0xffff));
 786                 /* enable PLL */
 787                 dib8000_write_word(state, 1857, reg_1857 | (1 << 15));
 788
 789                 while (((dib8000_read_word(state, 1856)>>15)&0x1) != 1)
 790                         dprintk("Waiting for PLL to lock\n");
 791
 792                 /* verify */
 793                 reg_1856 = dib8000_read_word(state, 1856);
 794                 dprintk("PLL Updated with prediv = %d and loopdiv = %d\n",
 795                                 reg_1856&0x3f, (reg_1856>>6)&0x3f);
 796         } else {
 797                 if (bw != state->current_demod_bw) {
 798                         /** Bandwidth change => force PLL update **/
 799                         dprintk("PLL: Bandwidth Change %d MHz -> %d MHz (prediv: %d->%d)\n", state->current_demod_bw / 1000, bw / 1000, oldprediv, state->cfg.pll->pll_prediv);
 800
 801                         if (state->cfg.pll->pll_prediv != oldprediv) {
 802                                 /** Full PLL change only if prediv is changed **/
 803
 804                                 /** full update => bypass and reconfigure **/
 805                                 dprintk("PLL: New Setting for %d MHz Bandwidth (prediv: %d, ratio: %d)\n", bw/1000, state->cfg.pll->pll_prediv, state->cfg.pll->pll_ratio);
 806                                 dib8000_write_word(state, 902, dib8000_read_word(state, 902) | (1<<3)); /* bypass PLL */
 807                                 dib8000_reset_pll(state);
 808                                 dib8000_write_word(state, 898, 0x0004); /* sad */
 809                         } else
 810                                 ratio = state->cfg.pll->pll_ratio;
 811
 812                         state->current_demod_bw = bw;
 813                 }
 814
 815                 if (ratio != 0) {
 816                         /** ratio update => only change ratio **/
 817                         dprintk("PLL: Update ratio (prediv: %d, ratio: %d)\n", state->cfg.pll->pll_prediv, ratio);
 818                         dib8000_write_word(state, 901, (state->cfg.pll->pll_prediv << 8) | (ratio << 0)); /* only the PLL ratio is updated. */
 819                 }
 820         }
 821
 822         return 0;
 823 }
 824
 825 static int dib8000_reset_gpio(struct dib8000_state *st)
 826 {
 827         /* reset the GPIOs */
 828         dib8000_write_word(st, 1029, st->cfg.gpio_dir);
 829         dib8000_write_word(st, 1030, st->cfg.gpio_val);
 830
 831         /* TODO 782 is P_gpio_od */
 832
 833         dib8000_write_word(st, 1032, st->cfg.gpio_pwm_pos);
 834
 835         dib8000_write_word(st, 1037, st->cfg.pwm_freq_div);
 836         return 0;
 837 }
 838
 839 static int dib8000_cfg_gpio(struct dib8000_state *st, u8 num, u8 dir, u8 val)
 840 {
 841         st->cfg.gpio_dir = dib8000_read_word(st, 1029);
 842         st->cfg.gpio_dir &= ~(1 << num);        /* reset the direction bit */
 843         st->cfg.gpio_dir |= (dir & 0x1) << num; /* set the new direction */
 844         dib8000_write_word(st, 1029, st->cfg.gpio_dir);
 845
 846         st->cfg.gpio_val = dib8000_read_word(st, 1030);
 847         st->cfg.gpio_val &= ~(1 << num);        /* reset the direction bit */
 848         st->cfg.gpio_val |= (val & 0x01) << num;        /* set the new value */
 849         dib8000_write_word(st, 1030, st->cfg.gpio_val);
 850
 851         dprintk("gpio dir: %x: gpio val: %x\n", st->cfg.gpio_dir, st->cfg.gpio_val);
 852
 853         return 0;
 854 }
 855
 856 static int dib8000_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val)
 857 {
 858         struct dib8000_state *state = fe->demodulator_priv;
 859         return dib8000_cfg_gpio(state, num, dir, val);
 860 }
 861
 862 static const u16 dib8000_defaults[] = {
 863         /* auto search configuration - lock0 by default waiting
 864          * for cpil_lock; lock1 cpil_lock; lock2 tmcc_sync_lock */
 865         3, 7,
 866         0x0004,
 867         0x0400,
 868         0x0814,
 869
 870         12, 11,
 871         0x001b,
 872         0x7740,
 873         0x005b,
 874         0x8d80,
 875         0x01c9,
 876         0xc380,
 877         0x0000,
 878         0x0080,
 879         0x0000,
 880         0x0090,
 881         0x0001,
 882         0xd4c0,
 883
 884         /*1, 32,
 885                 0x6680 // P_corm_thres Lock algorithms configuration */
 886
 887         11, 80,                 /* set ADC level to -16 */
 888         (1 << 13) - 825 - 117,
 889         (1 << 13) - 837 - 117,
 890         (1 << 13) - 811 - 117,
 891         (1 << 13) - 766 - 117,
 892         (1 << 13) - 737 - 117,
 893         (1 << 13) - 693 - 117,
 894         (1 << 13) - 648 - 117,
 895         (1 << 13) - 619 - 117,
 896         (1 << 13) - 575 - 117,
 897         (1 << 13) - 531 - 117,
 898         (1 << 13) - 501 - 117,
 899
 900         4, 108,
 901         0,
 902         0,
 903         0,
 904         0,
 905
 906         1, 175,
 907         0x0410,
 908         1, 179,
 909         8192,                   // P_fft_nb_to_cut
 910
 911         6, 181,
 912         0x2800,                 // P_coff_corthres_ ( 2k 4k 8k ) 0x2800
 913         0x2800,
 914         0x2800,
 915         0x2800,                 // P_coff_cpilthres_ ( 2k 4k 8k ) 0x2800
 916         0x2800,
 917         0x2800,
 918
 919         2, 193,
 920         0x0666,                 // P_pha3_thres
 921         0x0000,                 // P_cti_use_cpe, P_cti_use_prog
 922
 923         2, 205,
 924         0x200f,                 // P_cspu_regul, P_cspu_win_cut
 925         0x000f,                 // P_des_shift_work
 926
 927         5, 215,
 928         0x023d,                 // P_adp_regul_cnt
 929         0x00a4,                 // P_adp_noise_cnt
 930         0x00a4,                 // P_adp_regul_ext
 931         0x7ff0,                 // P_adp_noise_ext
 932         0x3ccc,                 // P_adp_fil
 933
 934         1, 230,
 935         0x0000,                 // P_2d_byp_ti_num
 936
 937         1, 263,
 938         0x800,                  //P_equal_thres_wgn
 939
 940         1, 268,
 941         (2 << 9) | 39,          // P_equal_ctrl_synchro, P_equal_speedmode
 942
 943         1, 270,
 944         0x0001,                 // P_div_lock0_wait
 945         1, 285,
 946         0x0020,                 //p_fec_
 947         1, 299,
 948         0x0062,                 /* P_smo_mode, P_smo_rs_discard, P_smo_fifo_flush, P_smo_pid_parse, P_smo_error_discard */
 949
 950         1, 338,
 951         (1 << 12) |             // P_ctrl_corm_thres4pre_freq_inh=1
 952                 (1 << 10) |
 953                 (0 << 9) |              /* P_ctrl_pre_freq_inh=0 */
 954                 (3 << 5) |              /* P_ctrl_pre_freq_step=3 */
 955                 (1 << 0),               /* P_pre_freq_win_len=1 */
 956
 957         0,
 958 };
 959
 960 static u16 dib8000_identify(struct i2c_device *client)
 961 {
 962         u16 value;
 963
 964         //because of glitches sometimes
 965         value = dib8000_i2c_read16(client, 896);
 966
 967         if ((value = dib8000_i2c_read16(client, 896)) != 0x01b3) {
 968                 dprintk("wrong Vendor ID (read=0x%x)\n", value);
 969                 return 0;
 970         }
 971
 972         value = dib8000_i2c_read16(client, 897);
 973         if (value != 0x8000 && value != 0x8001 &&
 974                         value != 0x8002 && value != 0x8090) {
 975                 dprintk("wrong Device ID (%x)\n", value);
 976                 return 0;
 977         }
 978
 979         switch (value) {
 980         case 0x8000:
 981                 dprintk("found DiB8000A\n");
 982                 break;
 983         case 0x8001:
 984                 dprintk("found DiB8000B\n");
 985                 break;
 986         case 0x8002:
 987                 dprintk("found DiB8000C\n");
 988                 break;
 989         case 0x8090:
 990                 dprintk("found DiB8096P\n");
 991                 break;
 992         }
 993         return value;
 994 }
 995
 996 static int dib8000_read_unc_blocks(struct dvb_frontend *fe, u32 *unc);
 997
 998 static void dib8000_reset_stats(struct dvb_frontend *fe)
 999 {
1000         struct dib8000_state *state = fe->demodulator_priv;
1001         struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
1002         u32 ucb;
1003
1004         memset(&c->strength, 0, sizeof(c->strength));
1005         memset(&c->cnr, 0, sizeof(c->cnr));
1006         memset(&c->post_bit_error, 0, sizeof(c->post_bit_error));
1007         memset(&c->post_bit_count, 0, sizeof(c->post_bit_count));
1008         memset(&c->block_error, 0, sizeof(c->block_error));
1009
1010         c->strength.len = 1;
1011         c->cnr.len = 1;
1012         c->block_error.len = 1;
1013         c->block_count.len = 1;
1014         c->post_bit_error.len = 1;
1015         c->post_bit_count.len = 1;
1016
1017         c->strength.stat[0].scale = FE_SCALE_DECIBEL;
1018         c->strength.stat[0].uvalue = 0;
1019
1020         c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1021         c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1022         c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1023         c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1024         c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1025
1026         dib8000_read_unc_blocks(fe, &ucb);
1027
1028         state->init_ucb = -ucb;
1029         state->ber_jiffies_stats = 0;
1030         state->per_jiffies_stats = 0;
1031         memset(&state->ber_jiffies_stats_layer, 0,
1032                sizeof(state->ber_jiffies_stats_layer));
1033 }
1034
1035 static int dib8000_reset(struct dvb_frontend *fe)
1036 {
1037         struct dib8000_state *state = fe->demodulator_priv;
1038
1039         if ((state->revision = dib8000_identify(&state->i2c)) == 0)
1040                 return -EINVAL;
1041
1042         /* sram lead in, rdy */
1043         if (state->revision != 0x8090)
1044                 dib8000_write_word(state, 1287, 0x0003);
1045
1046         if (state->revision == 0x8000)
1047                 dprintk("error : dib8000 MA not supported\n");
1048
1049         dibx000_reset_i2c_master(&state->i2c_master);
1050
1051         dib8000_set_power_mode(state, DIB8000_POWER_ALL);
1052
1053         /* always leave the VBG voltage on - it consumes almost nothing but takes a long time to start */
1054         dib8000_set_adc_state(state, DIBX000_ADC_OFF);
1055
1056         /* restart all parts */
1057         dib8000_write_word(state, 770, 0xffff);
1058         dib8000_write_word(state, 771, 0xffff);
1059         dib8000_write_word(state, 772, 0xfffc);
1060         dib8000_write_word(state, 898, 0x000c); /* restart sad */
1061         if (state->revision == 0x8090)
1062                 dib8000_write_word(state, 1280, 0x0045);
1063         else
1064                 dib8000_write_word(state, 1280, 0x004d);
1065         dib8000_write_word(state, 1281, 0x000c);
1066
1067         dib8000_write_word(state, 770, 0x0000);
1068         dib8000_write_word(state, 771, 0x0000);
1069         dib8000_write_word(state, 772, 0x0000);
1070         dib8000_write_word(state, 898, 0x0004); // sad
1071         dib8000_write_word(state, 1280, 0x0000);
1072         dib8000_write_word(state, 1281, 0x0000);
1073
1074         /* drives */
1075         if (state->revision != 0x8090) {
1076                 if (state->cfg.drives)
1077                         dib8000_write_word(state, 906, state->cfg.drives);
1078                 else {
1079                         dprintk("using standard PAD-drive-settings, please adjust settings in config-struct to be optimal.\n");
1080                         /* min drive SDRAM - not optimal - adjust */
1081                         dib8000_write_word(state, 906, 0x2d98);
1082                 }
1083         }
1084
1085         dib8000_reset_pll(state);
1086         if (state->revision != 0x8090)
1087                 dib8000_write_word(state, 898, 0x0004);
1088
1089         if (dib8000_reset_gpio(state) != 0)
1090                 dprintk("GPIO reset was not successful.\n");
1091
1092         if ((state->revision != 0x8090) &&
1093                         (dib8000_set_output_mode(fe, OUTMODE_HIGH_Z) != 0))
1094                 dprintk("OUTPUT_MODE could not be resetted.\n");
1095
1096         state->current_agc = NULL;
1097
1098         // P_iqc_alpha_pha, P_iqc_alpha_amp, P_iqc_dcc_alpha, ...
1099         /* P_iqc_ca2 = 0; P_iqc_impnc_on = 0; P_iqc_mode = 0; */
1100         if (state->cfg.pll->ifreq == 0)
1101                 dib8000_write_word(state, 40, 0x0755);  /* P_iqc_corr_inh = 0 enable IQcorr block */
1102         else
1103                 dib8000_write_word(state, 40, 0x1f55);  /* P_iqc_corr_inh = 1 disable IQcorr block */
1104
1105         {
1106                 u16 l = 0, r;
1107                 const u16 *n;
1108                 n = dib8000_defaults;
1109                 l = *n++;
1110                 while (l) {
1111                         r = *n++;
1112                         do {
1113                                 dib8000_write_word(state, r, *n++);
1114                                 r++;
1115                         } while (--l);
1116                         l = *n++;
1117                 }
1118         }
1119
1120         state->isdbt_cfg_loaded = 0;
1121
1122         //div_cfg override for special configs
1123         if ((state->revision != 8090) && (state->cfg.div_cfg != 0))
1124                 dib8000_write_word(state, 903, state->cfg.div_cfg);
1125
1126         /* unforce divstr regardless whether i2c enumeration was done or not */
1127         dib8000_write_word(state, 1285, dib8000_read_word(state, 1285) & ~(1 << 1));
1128
1129         dib8000_set_bandwidth(fe, 6000);
1130
1131         dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON);
1132         dib8000_sad_calib(state);
1133         if (state->revision != 0x8090)
1134                 dib8000_set_adc_state(state, DIBX000_SLOW_ADC_OFF);
1135
1136         /* ber_rs_len = 3 */
1137         dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & ~0x60) | (3 << 5));
1138
1139         dib8000_set_power_mode(state, DIB8000_POWER_INTERFACE_ONLY);
1140
1141         dib8000_reset_stats(fe);
1142
1143         return 0;
1144 }
1145
1146 static void dib8000_restart_agc(struct dib8000_state *state)
1147 {
1148         // P_restart_iqc & P_restart_agc
1149         dib8000_write_word(state, 770, 0x0a00);
1150         dib8000_write_word(state, 770, 0x0000);
1151 }
1152
1153 static int dib8000_update_lna(struct dib8000_state *state)
1154 {
1155         u16 dyn_gain;
1156
1157         if (state->cfg.update_lna) {
1158                 // read dyn_gain here (because it is demod-dependent and not tuner)
1159                 dyn_gain = dib8000_read_word(state, 390);
1160
1161                 if (state->cfg.update_lna(state->fe[0], dyn_gain)) {
1162                         dib8000_restart_agc(state);
1163                         return 1;
1164                 }
1165         }
1166         return 0;
1167 }
1168
1169 static int dib8000_set_agc_config(struct dib8000_state *state, u8 band)
1170 {
1171         struct dibx000_agc_config *agc = NULL;
1172         int i;
1173         u16 reg;
1174
1175         if (state->current_band == band && state->current_agc != NULL)
1176                 return 0;
1177         state->current_band = band;
1178
1179         for (i = 0; i < state->cfg.agc_config_count; i++)
1180                 if (state->cfg.agc[i].band_caps & band) {
1181                         agc = &state->cfg.agc[i];
1182                         break;
1183                 }
1184
1185         if (agc == NULL) {
1186                 dprintk("no valid AGC configuration found for band 0x%02x\n", band);
1187                 return -EINVAL;
1188         }
1189
1190         state->current_agc = agc;
1191
1192         /* AGC */
1193         dib8000_write_word(state, 76, agc->setup);
1194         dib8000_write_word(state, 77, agc->inv_gain);
1195         dib8000_write_word(state, 78, agc->time_stabiliz);
1196         dib8000_write_word(state, 101, (agc->alpha_level << 12) | agc->thlock);
1197
1198         // Demod AGC loop configuration
1199         dib8000_write_word(state, 102, (agc->alpha_mant << 5) | agc->alpha_exp);
1200         dib8000_write_word(state, 103, (agc->beta_mant << 6) | agc->beta_exp);
1201
1202         dprintk("WBD: ref: %d, sel: %d, active: %d, alpha: %d\n",
1203                 state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, agc->wbd_sel);
1204
1205         /* AGC continued */
1206         if (state->wbd_ref != 0)
1207                 dib8000_write_word(state, 106, state->wbd_ref);
1208         else                    // use default
1209                 dib8000_write_word(state, 106, agc->wbd_ref);
1210
1211         if (state->revision == 0x8090) {
1212                 reg = dib8000_read_word(state, 922) & (0x3 << 2);
1213                 dib8000_write_word(state, 922, reg | (agc->wbd_sel << 2));
1214         }
1215
1216         dib8000_write_word(state, 107, (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8));
1217         dib8000_write_word(state, 108, agc->agc1_max);
1218         dib8000_write_word(state, 109, agc->agc1_min);
1219         dib8000_write_word(state, 110, agc->agc2_max);
1220         dib8000_write_word(state, 111, agc->agc2_min);
1221         dib8000_write_word(state, 112, (agc->agc1_pt1 << 8) | agc->agc1_pt2);
1222         dib8000_write_word(state, 113, (agc->agc1_slope1 << 8) | agc->agc1_slope2);
1223         dib8000_write_word(state, 114, (agc->agc2_pt1 << 8) | agc->agc2_pt2);
1224         dib8000_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2);
1225
1226         dib8000_write_word(state, 75, agc->agc1_pt3);
1227         if (state->revision != 0x8090)
1228                 dib8000_write_word(state, 923,
1229                                 (dib8000_read_word(state, 923) & 0xffe3) |
1230                                 (agc->wbd_inv << 4) | (agc->wbd_sel << 2));
1231
1232         return 0;
1233 }
1234
1235 static void dib8000_pwm_agc_reset(struct dvb_frontend *fe)
1236 {
1237         struct dib8000_state *state = fe->demodulator_priv;
1238         dib8000_set_adc_state(state, DIBX000_ADC_ON);
1239         dib8000_set_agc_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000)));
1240 }
1241
1242 static int dib8000_agc_soft_split(struct dib8000_state *state)
1243 {
1244         u16 agc, split_offset;
1245
1246         if (!state->current_agc || !state->current_agc->perform_agc_softsplit || state->current_agc->split.max == 0)
1247                 return 0;
1248
1249         // n_agc_global
1250         agc = dib8000_read_word(state, 390);
1251
1252         if (agc > state->current_agc->split.min_thres)
1253                 split_offset = state->current_agc->split.min;
1254         else if (agc < state->current_agc->split.max_thres)
1255                 split_offset = state->current_agc->split.max;
1256         else
1257                 split_offset = state->current_agc->split.max *
1258                         (agc - state->current_agc->split.min_thres) /
1259                         (state->current_agc->split.max_thres - state->current_agc->split.min_thres);
1260
1261         dprintk("AGC split_offset: %d\n", split_offset);
1262
1263         // P_agc_force_split and P_agc_split_offset
1264         dib8000_write_word(state, 107, (dib8000_read_word(state, 107) & 0xff00) | split_offset);
1265         return 5000;
1266 }
1267
1268 static int dib8000_agc_startup(struct dvb_frontend *fe)
1269 {
1270         struct dib8000_state *state = fe->demodulator_priv;
1271         enum frontend_tune_state *tune_state = &state->tune_state;
1272         int ret = 0;
1273         u16 reg;
1274         u32 upd_demod_gain_period = 0x8000;
1275
1276         switch (*tune_state) {
1277         case CT_AGC_START:
1278                 // set power-up level: interf+analog+AGC
1279
1280                 if (state->revision != 0x8090)
1281                         dib8000_set_adc_state(state, DIBX000_ADC_ON);
1282                 else {
1283                         dib8000_set_power_mode(state, DIB8000_POWER_ALL);
1284
1285                         reg = dib8000_read_word(state, 1947)&0xff00;
1286                         dib8000_write_word(state, 1946,
1287                                         upd_demod_gain_period & 0xFFFF);
1288                         /* bit 14 = enDemodGain */
1289                         dib8000_write_word(state, 1947, reg | (1<<14) |
1290                                         ((upd_demod_gain_period >> 16) & 0xFF));
1291
1292                         /* enable adc i & q */
1293                         reg = dib8000_read_word(state, 1920);
1294                         dib8000_write_word(state, 1920, (reg | 0x3) &
1295                                         (~(1 << 7)));
1296                 }
1297
1298                 if (dib8000_set_agc_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000))) != 0) {
1299                         *tune_state = CT_AGC_STOP;
1300                         state->status = FE_STATUS_TUNE_FAILED;
1301                         break;
1302                 }
1303
1304                 ret = 70;
1305                 *tune_state = CT_AGC_STEP_0;
1306                 break;
1307
1308         case CT_AGC_STEP_0:
1309                 //AGC initialization
1310                 if (state->cfg.agc_control)
1311                         state->cfg.agc_control(fe, 1);
1312
1313                 dib8000_restart_agc(state);
1314
1315                 // wait AGC rough lock time
1316                 ret = 50;
1317                 *tune_state = CT_AGC_STEP_1;
1318                 break;
1319
1320         case CT_AGC_STEP_1:
1321                 // wait AGC accurate lock time
1322                 ret = 70;
1323
1324                 if (dib8000_update_lna(state))
1325                         // wait only AGC rough lock time
1326                         ret = 50;
1327                 else
1328                         *tune_state = CT_AGC_STEP_2;
1329                 break;
1330
1331         case CT_AGC_STEP_2:
1332                 dib8000_agc_soft_split(state);
1333
1334                 if (state->cfg.agc_control)
1335                         state->cfg.agc_control(fe, 0);
1336
1337                 *tune_state = CT_AGC_STOP;
1338                 break;
1339         default:
1340                 ret = dib8000_agc_soft_split(state);
1341                 break;
1342         }
1343         return ret;
1344
1345 }
1346
1347 static void dib8096p_host_bus_drive(struct dib8000_state *state, u8 drive)
1348 {
1349         u16 reg;
1350
1351         drive &= 0x7;
1352
1353         /* drive host bus 2, 3, 4 */
1354         reg = dib8000_read_word(state, 1798) &
1355                 ~(0x7 | (0x7 << 6) | (0x7 << 12));
1356         reg |= (drive<<12) | (drive<<6) | drive;
1357         dib8000_write_word(state, 1798, reg);
1358
1359         /* drive host bus 5,6 */
1360         reg = dib8000_read_word(state, 1799) & ~((0x7 << 2) | (0x7 << 8));
1361         reg |= (drive<<8) | (drive<<2);
1362         dib8000_write_word(state, 1799, reg);
1363
1364         /* drive host bus 7, 8, 9 */
1365         reg = dib8000_read_word(state, 1800) &
1366                 ~(0x7 | (0x7 << 6) | (0x7 << 12));
1367         reg |= (drive<<12) | (drive<<6) | drive;
1368         dib8000_write_word(state, 1800, reg);
1369
1370         /* drive host bus 10, 11 */
1371         reg = dib8000_read_word(state, 1801) & ~((0x7 << 2) | (0x7 << 8));
1372         reg |= (drive<<8) | (drive<<2);
1373         dib8000_write_word(state, 1801, reg);
1374
1375         /* drive host bus 12, 13, 14 */
1376         reg = dib8000_read_word(state, 1802) &
1377                 ~(0x7 | (0x7 << 6) | (0x7 << 12));
1378         reg |= (drive<<12) | (drive<<6) | drive;
1379         dib8000_write_word(state, 1802, reg);
1380 }
1381
1382 static u32 dib8096p_calcSyncFreq(u32 P_Kin, u32 P_Kout,
1383                 u32 insertExtSynchro, u32 syncSize)
1384 {
1385         u32 quantif = 3;
1386         u32 nom = (insertExtSynchro * P_Kin+syncSize);
1387         u32 denom = P_Kout;
1388         u32 syncFreq = ((nom << quantif) / denom);
1389
1390         if ((syncFreq & ((1 << quantif) - 1)) != 0)
1391                 syncFreq = (syncFreq >> quantif) + 1;
1392         else
1393                 syncFreq = (syncFreq >> quantif);
1394
1395         if (syncFreq != 0)
1396                 syncFreq = syncFreq - 1;
1397
1398         return syncFreq;
1399 }
1400
1401 static void dib8096p_cfg_DibTx(struct dib8000_state *state, u32 P_Kin,
1402                 u32 P_Kout, u32 insertExtSynchro, u32 synchroMode,
1403                 u32 syncWord, u32 syncSize)
1404 {
1405         dprintk("Configure DibStream Tx\n");
1406
1407         dib8000_write_word(state, 1615, 1);
1408         dib8000_write_word(state, 1603, P_Kin);
1409         dib8000_write_word(state, 1605, P_Kout);
1410         dib8000_write_word(state, 1606, insertExtSynchro);
1411         dib8000_write_word(state, 1608, synchroMode);
1412         dib8000_write_word(state, 1609, (syncWord >> 16) & 0xffff);
1413         dib8000_write_word(state, 1610, syncWord & 0xffff);
1414         dib8000_write_word(state, 1612, syncSize);
1415         dib8000_write_word(state, 1615, 0);
1416 }
1417
1418 static void dib8096p_cfg_DibRx(struct dib8000_state *state, u32 P_Kin,
1419                 u32 P_Kout, u32 synchroMode, u32 insertExtSynchro,
1420                 u32 syncWord, u32 syncSize, u32 dataOutRate)
1421 {
1422         u32 syncFreq;
1423
1424         dprintk("Configure DibStream Rx synchroMode = %d\n", synchroMode);
1425
1426         if ((P_Kin != 0) && (P_Kout != 0)) {
1427                 syncFreq = dib8096p_calcSyncFreq(P_Kin, P_Kout,
1428                                 insertExtSynchro, syncSize);
1429                 dib8000_write_word(state, 1542, syncFreq);
1430         }
1431
1432         dib8000_write_word(state, 1554, 1);
1433         dib8000_write_word(state, 1536, P_Kin);
1434         dib8000_write_word(state, 1537, P_Kout);
1435         dib8000_write_word(state, 1539, synchroMode);
1436         dib8000_write_word(state, 1540, (syncWord >> 16) & 0xffff);
1437         dib8000_write_word(state, 1541, syncWord & 0xffff);
1438         dib8000_write_word(state, 1543, syncSize);
1439         dib8000_write_word(state, 1544, dataOutRate);
1440         dib8000_write_word(state, 1554, 0);
1441 }
1442
1443 static void dib8096p_enMpegMux(struct dib8000_state *state, int onoff)
1444 {
1445         u16 reg_1287;
1446
1447         reg_1287 = dib8000_read_word(state, 1287);
1448
1449         switch (onoff) {
1450         case 1:
1451                         reg_1287 &= ~(1 << 8);
1452                         break;
1453         case 0:
1454                         reg_1287 |= (1 << 8);
1455                         break;
1456         }
1457
1458         dib8000_write_word(state, 1287, reg_1287);
1459 }
1460
1461 static void dib8096p_configMpegMux(struct dib8000_state *state,
1462                 u16 pulseWidth, u16 enSerialMode, u16 enSerialClkDiv2)
1463 {
1464         u16 reg_1287;
1465
1466         dprintk("Enable Mpeg mux\n");
1467
1468         dib8096p_enMpegMux(state, 0);
1469
1470         /* If the input mode is MPEG do not divide the serial clock */
1471         if ((enSerialMode == 1) && (state->input_mode_mpeg == 1))
1472                 enSerialClkDiv2 = 0;
1473
1474         reg_1287 = ((pulseWidth & 0x1f) << 3) |
1475                 ((enSerialMode & 0x1) << 2) | (enSerialClkDiv2 & 0x1);
1476         dib8000_write_word(state, 1287, reg_1287);
1477
1478         dib8096p_enMpegMux(state, 1);
1479 }
1480
1481 static void dib8096p_setDibTxMux(struct dib8000_state *state, int mode)
1482 {
1483         u16 reg_1288 = dib8000_read_word(state, 1288) & ~(0x7 << 7);
1484
1485         switch (mode) {
1486         case MPEG_ON_DIBTX:
1487                         dprintk("SET MPEG ON DIBSTREAM TX\n");
1488                         dib8096p_cfg_DibTx(state, 8, 5, 0, 0, 0, 0);
1489                         reg_1288 |= (1 << 9); break;
1490         case DIV_ON_DIBTX:
1491                         dprintk("SET DIV_OUT ON DIBSTREAM TX\n");
1492                         dib8096p_cfg_DibTx(state, 5, 5, 0, 0, 0, 0);
1493                         reg_1288 |= (1 << 8); break;
1494         case ADC_ON_DIBTX:
1495                         dprintk("SET ADC_OUT ON DIBSTREAM TX\n");
1496                         dib8096p_cfg_DibTx(state, 20, 5, 10, 0, 0, 0);
1497                         reg_1288 |= (1 << 7); break;
1498         default:
1499                         break;
1500         }
1501         dib8000_write_word(state, 1288, reg_1288);
1502 }
1503
1504 static void dib8096p_setHostBusMux(struct dib8000_state *state, int mode)
1505 {
1506         u16 reg_1288 = dib8000_read_word(state, 1288) & ~(0x7 << 4);
1507
1508         switch (mode) {
1509         case DEMOUT_ON_HOSTBUS:
1510                         dprintk("SET DEM OUT OLD INTERF ON HOST BUS\n");
1511                         dib8096p_enMpegMux(state, 0);
1512                         reg_1288 |= (1 << 6);
1513                         break;
1514         case DIBTX_ON_HOSTBUS:
1515                         dprintk("SET DIBSTREAM TX ON HOST BUS\n");
1516                         dib8096p_enMpegMux(state, 0);
1517                         reg_1288 |= (1 << 5);
1518                         break;
1519         case MPEG_ON_HOSTBUS:
1520                         dprintk("SET MPEG MUX ON HOST BUS\n");
1521                         reg_1288 |= (1 << 4);
1522                         break;
1523         default:
1524                         break;
1525         }
1526         dib8000_write_word(state, 1288, reg_1288);
1527 }
1528
1529 static int dib8096p_set_diversity_in(struct dvb_frontend *fe, int onoff)
1530 {
1531         struct dib8000_state *state = fe->demodulator_priv;
1532         u16 reg_1287;
1533
1534         switch (onoff) {
1535         case 0: /* only use the internal way - not the diversity input */
1536                         dprintk("%s mode OFF : by default Enable Mpeg INPUT\n",
1537                                         __func__);
1538                         /* outputRate = 8 */
1539                         dib8096p_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0);
1540
1541                         /* Do not divide the serial clock of MPEG MUX in
1542                            SERIAL MODE in case input mode MPEG is used */
1543                         reg_1287 = dib8000_read_word(state, 1287);
1544                         /* enSerialClkDiv2 == 1 ? */
1545                         if ((reg_1287 & 0x1) == 1) {
1546                                 /* force enSerialClkDiv2 = 0 */
1547                                 reg_1287 &= ~0x1;
1548                                 dib8000_write_word(state, 1287, reg_1287);
1549                         }
1550                         state->input_mode_mpeg = 1;
1551                         break;
1552         case 1: /* both ways */
1553         case 2: /* only the diversity input */
1554                         dprintk("%s ON : Enable diversity INPUT\n", __func__);
1555                         dib8096p_cfg_DibRx(state, 5, 5, 0, 0, 0, 0, 0);
1556                         state->input_mode_mpeg = 0;
1557                         break;
1558         }
1559
1560         dib8000_set_diversity_in(state->fe[0], onoff);
1561         return 0;
1562 }
1563
1564 static int dib8096p_set_output_mode(struct dvb_frontend *fe, int mode)
1565 {
1566         struct dib8000_state *state = fe->demodulator_priv;
1567         u16 outreg, smo_mode, fifo_threshold;
1568         u8 prefer_mpeg_mux_use = 1;
1569         int ret = 0;
1570
1571         state->output_mode = mode;
1572         dib8096p_host_bus_drive(state, 1);
1573
1574         fifo_threshold = 1792;
1575         smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1);
1576         outreg   = dib8000_read_word(state, 1286) &
1577                 ~((1 << 10) | (0x7 << 6) | (1 << 1));
1578
1579         switch (mode) {
1580         case OUTMODE_HIGH_Z:
1581                         outreg = 0;
1582                         break;
1583
1584         case OUTMODE_MPEG2_SERIAL:
1585                         if (prefer_mpeg_mux_use) {
1586                                 dprintk("dib8096P setting output mode TS_SERIAL using Mpeg Mux\n");
1587                                 dib8096p_configMpegMux(state, 3, 1, 1);
1588                                 dib8096p_setHostBusMux(state, MPEG_ON_HOSTBUS);
1589                         } else {/* Use Smooth block */
1590                                 dprintk("dib8096P setting output mode TS_SERIAL using Smooth bloc\n");
1591                                 dib8096p_setHostBusMux(state,
1592                                                 DEMOUT_ON_HOSTBUS);
1593                                 outreg |= (2 << 6) | (0 << 1);
1594                         }
1595                         break;
1596
1597         case OUTMODE_MPEG2_PAR_GATED_CLK:
1598                         if (prefer_mpeg_mux_use) {
1599                                 dprintk("dib8096P setting output mode TS_PARALLEL_GATED using Mpeg Mux\n");
1600                                 dib8096p_configMpegMux(state, 2, 0, 0);
1601                                 dib8096p_setHostBusMux(state, MPEG_ON_HOSTBUS);
1602                         } else { /* Use Smooth block */
1603                                 dprintk("dib8096P setting output mode TS_PARALLEL_GATED using Smooth block\n");
1604                                 dib8096p_setHostBusMux(state,
1605                                                 DEMOUT_ON_HOSTBUS);
1606                                 outreg |= (0 << 6);
1607                         }
1608                         break;
1609
1610         case OUTMODE_MPEG2_PAR_CONT_CLK: /* Using Smooth block only */
1611                         dprintk("dib8096P setting output mode TS_PARALLEL_CONT using Smooth block\n");
1612                         dib8096p_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
1613                         outreg |= (1 << 6);
1614                         break;
1615
1616         case OUTMODE_MPEG2_FIFO:
1617                         /* Using Smooth block because not supported
1618                            by new Mpeg Mux bloc */
1619                         dprintk("dib8096P setting output mode TS_FIFO using Smooth block\n");
1620                         dib8096p_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
1621                         outreg |= (5 << 6);
1622                         smo_mode |= (3 << 1);
1623                         fifo_threshold = 512;
1624                         break;
1625
1626         case OUTMODE_DIVERSITY:
1627                         dprintk("dib8096P setting output mode MODE_DIVERSITY\n");
1628                         dib8096p_setDibTxMux(state, DIV_ON_DIBTX);
1629                         dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS);
1630                         break;
1631
1632         case OUTMODE_ANALOG_ADC:
1633                         dprintk("dib8096P setting output mode MODE_ANALOG_ADC\n");
1634                         dib8096p_setDibTxMux(state, ADC_ON_DIBTX);
1635                         dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS);
1636                         break;
1637         }
1638
1639         if (mode != OUTMODE_HIGH_Z)
1640                 outreg |= (1<<10);
1641
1642         dprintk("output_mpeg2_in_188_bytes = %d\n",
1643                         state->cfg.output_mpeg2_in_188_bytes);
1644         if (state->cfg.output_mpeg2_in_188_bytes)
1645                 smo_mode |= (1 << 5);
1646
1647         ret |= dib8000_write_word(state, 299, smo_mode);
1648         /* synchronous fread */
1649         ret |= dib8000_write_word(state, 299 + 1, fifo_threshold);
1650         ret |= dib8000_write_word(state, 1286, outreg);
1651
1652         return ret;
1653 }
1654
1655 static int map_addr_to_serpar_number(struct i2c_msg *msg)
1656 {
1657         if (msg->buf[0] <= 15)
1658                 msg->buf[0] -= 1;
1659         else if (msg->buf[0] == 17)
1660                 msg->buf[0] = 15;
1661         else if (msg->buf[0] == 16)
1662                 msg->buf[0] = 17;
1663         else if (msg->buf[0] == 19)
1664                 msg->buf[0] = 16;
1665         else if (msg->buf[0] >= 21 && msg->buf[0] <= 25)
1666                 msg->buf[0] -= 3;
1667         else if (msg->buf[0] == 28)
1668                 msg->buf[0] = 23;
1669         else if (msg->buf[0] == 99)
1670                 msg->buf[0] = 99;
1671         else
1672                 return -EINVAL;
1673         return 0;
1674 }
1675
1676 static int dib8096p_tuner_write_serpar(struct i2c_adapter *i2c_adap,
1677                 struct i2c_msg msg[], int num)
1678 {
1679         struct dib8000_state *state = i2c_get_adapdata(i2c_adap);
1680         u8 n_overflow = 1;
1681         u16 i = 1000;
1682         u16 serpar_num = msg[0].buf[0];
1683
1684         while (n_overflow == 1 && i) {
1685                 n_overflow = (dib8000_read_word(state, 1984) >> 1) & 0x1;
1686                 i--;
1687                 if (i == 0)
1688                         dprintk("Tuner ITF: write busy (overflow)\n");
1689         }
1690         dib8000_write_word(state, 1985, (1 << 6) | (serpar_num & 0x3f));
1691         dib8000_write_word(state, 1986, (msg[0].buf[1] << 8) | msg[0].buf[2]);
1692
1693         return num;
1694 }
1695
1696 static int dib8096p_tuner_read_serpar(struct i2c_adapter *i2c_adap,
1697                 struct i2c_msg msg[], int num)
1698 {
1699         struct dib8000_state *state = i2c_get_adapdata(i2c_adap);
1700         u8 n_overflow = 1, n_empty = 1;
1701         u16 i = 1000;
1702         u16 serpar_num = msg[0].buf[0];
1703         u16 read_word;
1704
1705         while (n_overflow == 1 && i) {
1706                 n_overflow = (dib8000_read_word(state, 1984) >> 1) & 0x1;
1707                 i--;
1708                 if (i == 0)
1709                         dprintk("TunerITF: read busy (overflow)\n");
1710         }
1711         dib8000_write_word(state, 1985, (0<<6) | (serpar_num&0x3f));
1712
1713         i = 1000;
1714         while (n_empty == 1 && i) {
1715                 n_empty = dib8000_read_word(state, 1984)&0x1;
1716                 i--;
1717                 if (i == 0)
1718                         dprintk("TunerITF: read busy (empty)\n");
1719         }
1720
1721         read_word = dib8000_read_word(state, 1987);
1722         msg[1].buf[0] = (read_word >> 8) & 0xff;
1723         msg[1].buf[1] = (read_word) & 0xff;
1724
1725         return num;
1726 }
1727
1728 static int dib8096p_tuner_rw_serpar(struct i2c_adapter *i2c_adap,
1729                 struct i2c_msg msg[], int num)
1730 {
1731         if (map_addr_to_serpar_number(&msg[0]) == 0) {
1732                 if (num == 1) /* write */
1733                         return dib8096p_tuner_write_serpar(i2c_adap, msg, 1);
1734                 else /* read */
1735                         return dib8096p_tuner_read_serpar(i2c_adap, msg, 2);
1736         }
1737         return num;
1738 }
1739
1740 static int dib8096p_rw_on_apb(struct i2c_adapter *i2c_adap,
1741                 struct i2c_msg msg[], int num, u16 apb_address)
1742 {
1743         struct dib8000_state *state = i2c_get_adapdata(i2c_adap);
1744         u16 word;
1745
1746         if (num == 1) {         /* write */
1747                 dib8000_write_word(state, apb_address,
1748                                 ((msg[0].buf[1] << 8) | (msg[0].buf[2])));
1749         } else {
1750                 word = dib8000_read_word(state, apb_address);
1751                 msg[1].buf[0] = (word >> 8) & 0xff;
1752                 msg[1].buf[1] = (word) & 0xff;
1753         }
1754         return num;
1755 }
1756
1757 static int dib8096p_tuner_xfer(struct i2c_adapter *i2c_adap,
1758                 struct i2c_msg msg[], int num)
1759 {
1760         struct dib8000_state *state = i2c_get_adapdata(i2c_adap);
1761         u16 apb_address = 0, word;
1762         int i = 0;
1763
1764         switch (msg[0].buf[0]) {
1765         case 0x12:
1766                         apb_address = 1920;
1767                         break;
1768         case 0x14:
1769                         apb_address = 1921;
1770                         break;
1771         case 0x24:
1772                         apb_address = 1922;
1773                         break;
1774         case 0x1a:
1775                         apb_address = 1923;
1776                         break;
1777         case 0x22:
1778                         apb_address = 1924;
1779                         break;
1780         case 0x33:
1781                         apb_address = 1926;
1782                         break;
1783         case 0x34:
1784                         apb_address = 1927;
1785                         break;
1786         case 0x35:
1787                         apb_address = 1928;
1788                         break;
1789         case 0x36:
1790                         apb_address = 1929;
1791                         break;
1792         case 0x37:
1793                         apb_address = 1930;
1794                         break;
1795         case 0x38:
1796                         apb_address = 1931;
1797                         break;
1798         case 0x39:
1799                         apb_address = 1932;
1800                         break;
1801         case 0x2a:
1802                         apb_address = 1935;
1803                         break;
1804         case 0x2b:
1805                         apb_address = 1936;
1806                         break;
1807         case 0x2c:
1808                         apb_address = 1937;
1809                         break;
1810         case 0x2d:
1811                         apb_address = 1938;
1812                         break;
1813         case 0x2e:
1814                         apb_address = 1939;
1815                         break;
1816         case 0x2f:
1817                         apb_address = 1940;
1818                         break;
1819         case 0x30:
1820                         apb_address = 1941;
1821                         break;
1822         case 0x31:
1823                         apb_address = 1942;
1824                         break;
1825         case 0x32:
1826                         apb_address = 1943;
1827                         break;
1828         case 0x3e:
1829                         apb_address = 1944;
1830                         break;
1831         case 0x3f:
1832                         apb_address = 1945;
1833                         break;
1834         case 0x40:
1835                         apb_address = 1948;
1836                         break;
1837         case 0x25:
1838                         apb_address = 936;
1839                         break;
1840         case 0x26:
1841                         apb_address = 937;
1842                         break;
1843         case 0x27:
1844                         apb_address = 938;
1845                         break;
1846         case 0x28:
1847                         apb_address = 939;
1848                         break;
1849         case 0x1d:
1850                         /* get sad sel request */
1851                         i = ((dib8000_read_word(state, 921) >> 12)&0x3);
1852                         word = dib8000_read_word(state, 924+i);
1853                         msg[1].buf[0] = (word >> 8) & 0xff;
1854                         msg[1].buf[1] = (word) & 0xff;
1855                         return num;
1856         case 0x1f:
1857                         if (num == 1) { /* write */
1858                                 word = (u16) ((msg[0].buf[1] << 8) |
1859                                                 msg[0].buf[2]);
1860                                 /* in the VGAMODE Sel are located on bit 0/1 */
1861                                 word &= 0x3;
1862                                 word = (dib8000_read_word(state, 921) &
1863                                                 ~(3<<12)) | (word<<12);
1864                                 /* Set the proper input */
1865                                 dib8000_write_word(state, 921, word);
1866                                 return num;
1867                         }
1868         }
1869
1870         if (apb_address != 0) /* R/W acces via APB */
1871                 return dib8096p_rw_on_apb(i2c_adap, msg, num, apb_address);
1872         else  /* R/W access via SERPAR  */
1873                 return dib8096p_tuner_rw_serpar(i2c_adap, msg, num);
1874
1875         return 0;
1876 }
1877
1878 static u32 dib8096p_i2c_func(struct i2c_adapter *adapter)
1879 {
1880         return I2C_FUNC_I2C;
1881 }
1882
1883 static const struct i2c_algorithm dib8096p_tuner_xfer_algo = {
1884         .master_xfer = dib8096p_tuner_xfer,
1885         .functionality = dib8096p_i2c_func,
1886 };
1887
1888 static struct i2c_adapter *dib8096p_get_i2c_tuner(struct dvb_frontend *fe)
1889 {
1890         struct dib8000_state *st = fe->demodulator_priv;
1891         return &st->dib8096p_tuner_adap;
1892 }
1893
1894 static int dib8096p_tuner_sleep(struct dvb_frontend *fe, int onoff)
1895 {
1896         struct dib8000_state *state = fe->demodulator_priv;
1897         u16 en_cur_state;
1898
1899         dprintk("sleep dib8096p: %d\n", onoff);
1900
1901         en_cur_state = dib8000_read_word(state, 1922);
1902
1903         /* LNAs and MIX are ON and therefore it is a valid configuration */
1904         if (en_cur_state > 0xff)
1905                 state->tuner_enable = en_cur_state ;
1906
1907         if (onoff)
1908                 en_cur_state &= 0x00ff;
1909         else {
1910                 if (state->tuner_enable != 0)
1911                         en_cur_state = state->tuner_enable;
1912         }
1913
1914         dib8000_write_word(state, 1922, en_cur_state);
1915
1916         return 0;
1917 }
1918
1919 static const s32 lut_1000ln_mant[] =
1920 {
1921         908, 7003, 7090, 7170, 7244, 7313, 7377, 7438, 7495, 7549, 7600
1922 };
1923
1924 static s32 dib8000_get_adc_power(struct dvb_frontend *fe, u8 mode)
1925 {
1926         struct dib8000_state *state = fe->demodulator_priv;
1927         u32 ix = 0, tmp_val = 0, exp = 0, mant = 0;
1928         s32 val;
1929
1930         val = dib8000_read32(state, 384);
1931         if (mode) {
1932                 tmp_val = val;
1933                 while (tmp_val >>= 1)
1934                         exp++;
1935                 mant = (val * 1000 / (1<<exp));
1936                 ix = (u8)((mant-1000)/100); /* index of the LUT */
1937                 val = (lut_1000ln_mant[ix] + 693*(exp-20) - 6908);
1938                 val = (val*256)/1000;
1939         }
1940         return val;
1941 }
1942
1943 static int dib8090p_get_dc_power(struct dvb_frontend *fe, u8 IQ)
1944 {
1945         struct dib8000_state *state = fe->demodulator_priv;
1946         int val = 0;
1947
1948         switch (IQ) {
1949         case 1:
1950                         val = dib8000_read_word(state, 403);
1951                         break;
1952         case 0:
1953                         val = dib8000_read_word(state, 404);
1954                         break;
1955         }
1956         if (val  & 0x200)
1957                 val -= 1024;
1958
1959         return val;
1960 }
1961
1962 static void dib8000_update_timf(struct dib8000_state *state)
1963 {
1964         u32 timf = state->timf = dib8000_read32(state, 435);
1965
1966         dib8000_write_word(state, 29, (u16) (timf >> 16));
1967         dib8000_write_word(state, 30, (u16) (timf & 0xffff));
1968         dprintk("Updated timing frequency: %d (default: %d)\n", state->timf, state->timf_default);
1969 }
1970
1971 static u32 dib8000_ctrl_timf(struct dvb_frontend *fe, uint8_t op, uint32_t timf)
1972 {
1973         struct dib8000_state *state = fe->demodulator_priv;
1974
1975         switch (op) {
1976         case DEMOD_TIMF_SET:
1977                         state->timf = timf;
1978                         break;
1979         case DEMOD_TIMF_UPDATE:
1980                         dib8000_update_timf(state);
1981                         break;
1982         case DEMOD_TIMF_GET:
1983                         break;
1984         }
1985         dib8000_set_bandwidth(state->fe[0], 6000);
1986
1987         return state->timf;
1988 }
1989
1990 static const u16 adc_target_16dB[11] = {
1991         7250, 7238, 7264, 7309, 7338, 7382, 7427, 7456, 7500, 7544, 7574
1992 };
1993
1994 static const u8 permu_seg[] = { 6, 5, 7, 4, 8, 3, 9, 2, 10, 1, 11, 0, 12 };
1995
1996 static u16 dib8000_set_layer(struct dib8000_state *state, u8 layer_index, u16 max_constellation)
1997 {
1998         u8  cr, constellation, time_intlv;
1999         struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2000
2001         switch (c->layer[layer_index].modulation) {
2002         case DQPSK:
2003                         constellation = 0;
2004                         break;
2005         case  QPSK:
2006                         constellation = 1;
2007                         break;
2008         case QAM_16:
2009                         constellation = 2;
2010                         break;
2011         case QAM_64:
2012         default:
2013                         constellation = 3;
2014                         break;
2015         }
2016
2017         switch (c->layer[layer_index].fec) {
2018         case FEC_1_2:
2019                         cr = 1;
2020                         break;
2021         case FEC_2_3:
2022                         cr = 2;
2023                         break;
2024         case FEC_3_4:
2025                         cr = 3;
2026                         break;
2027         case FEC_5_6:
2028                         cr = 5;
2029                         break;
2030         case FEC_7_8:
2031         default:
2032                         cr = 7;
2033                         break;
2034         }
2035
2036         time_intlv = fls(c->layer[layer_index].interleaving);
2037         if (time_intlv > 3 && !(time_intlv == 4 && c->isdbt_sb_mode == 1))
2038                 time_intlv = 0;
2039
2040         dib8000_write_word(state, 2 + layer_index, (constellation << 10) | ((c->layer[layer_index].segment_count & 0xf) << 6) | (cr << 3) | time_intlv);
2041         if (c->layer[layer_index].segment_count > 0) {
2042                 switch (max_constellation) {
2043                 case DQPSK:
2044                 case QPSK:
2045                                 if (c->layer[layer_index].modulation == QAM_16 || c->layer[layer_index].modulation == QAM_64)
2046                                         max_constellation = c->layer[layer_index].modulation;
2047                                 break;
2048                 case QAM_16:
2049                                 if (c->layer[layer_index].modulation == QAM_64)
2050                                         max_constellation = c->layer[layer_index].modulation;
2051                                 break;
2052                 }
2053         }
2054
2055         return  max_constellation;
2056 }
2057
2058 static const u16 adp_Q64[4] = {0x0148, 0xfff0, 0x00a4, 0xfff8}; /* P_adp_regul_cnt 0.04, P_adp_noise_cnt -0.002, P_adp_regul_ext 0.02, P_adp_noise_ext -0.001 */
2059 static const u16 adp_Q16[4] = {0x023d, 0xffdf, 0x00a4, 0xfff0}; /* P_adp_regul_cnt 0.07, P_adp_noise_cnt -0.004, P_adp_regul_ext 0.02, P_adp_noise_ext -0.002 */
2060 static const u16 adp_Qdefault[4] = {0x099a, 0xffae, 0x0333, 0xfff8}; /* P_adp_regul_cnt 0.3,  P_adp_noise_cnt -0.01,  P_adp_regul_ext 0.1,  P_adp_noise_ext -0.002 */
2061 static u16 dib8000_adp_fine_tune(struct dib8000_state *state, u16 max_constellation)
2062 {
2063         u16 i, ana_gain = 0;
2064         const u16 *adp;
2065
2066         /* channel estimation fine configuration */
2067         switch (max_constellation) {
2068         case QAM_64:
2069                         ana_gain = 0x7;
2070                         adp = &adp_Q64[0];
2071                         break;
2072         case QAM_16:
2073                         ana_gain = 0x7;
2074                         adp = &adp_Q16[0];
2075                         break;
2076         default:
2077                         ana_gain = 0;
2078                         adp = &adp_Qdefault[0];
2079                         break;
2080         }
2081
2082         for (i = 0; i < 4; i++)
2083                 dib8000_write_word(state, 215 + i, adp[i]);
2084
2085         return ana_gain;
2086 }
2087
2088 static void dib8000_update_ana_gain(struct dib8000_state *state, u16 ana_gain)
2089 {
2090         u16 i;
2091
2092         dib8000_write_word(state, 116, ana_gain);
2093
2094         /* update ADC target depending on ana_gain */
2095         if (ana_gain) { /* set -16dB ADC target for ana_gain=-1 */
2096                 for (i = 0; i < 10; i++)
2097                         dib8000_write_word(state, 80 + i, adc_target_16dB[i]);
2098         } else { /* set -22dB ADC target for ana_gain=0 */
2099                 for (i = 0; i < 10; i++)
2100                         dib8000_write_word(state, 80 + i, adc_target_16dB[i] - 355);
2101         }
2102 }
2103
2104 static void dib8000_load_ana_fe_coefs(struct dib8000_state *state, const s16 *ana_fe)
2105 {
2106         u16 mode = 0;
2107
2108         if (state->isdbt_cfg_loaded == 0)
2109                 for (mode = 0; mode < 24; mode++)
2110                         dib8000_write_word(state, 117 + mode, ana_fe[mode]);
2111 }
2112
2113 static const u16 lut_prbs_2k[13] = {
2114         0x423, 0x009, 0x5C7,
2115         0x7A6, 0x3D8, 0x527,
2116         0x7FF, 0x79B, 0x3D6,
2117         0x3A2, 0x53B, 0x2F4,
2118         0x213
2119 };
2120
2121 static const u16 lut_prbs_4k[13] = {
2122         0x208, 0x0C3, 0x7B9,
2123         0x423, 0x5C7, 0x3D8,
2124         0x7FF, 0x3D6, 0x53B,
2125         0x213, 0x029, 0x0D0,
2126         0x48E
2127 };
2128
2129 static const u16 lut_prbs_8k[13] = {
2130         0x740, 0x069, 0x7DD,
2131         0x208, 0x7B9, 0x5C7,
2132         0x7FF, 0x53B, 0x029,
2133         0x48E, 0x4C4, 0x367,
2134         0x684
2135 };
2136
2137 static u16 dib8000_get_init_prbs(struct dib8000_state *state, u16 subchannel)
2138 {
2139         int sub_channel_prbs_group = 0;
2140         int prbs_group;
2141
2142         sub_channel_prbs_group = subchannel / 3;
2143         if (sub_channel_prbs_group >= ARRAY_SIZE(lut_prbs_2k))
2144                 return 0;
2145
2146         switch (state->fe[0]->dtv_property_cache.transmission_mode) {
2147         case TRANSMISSION_MODE_2K:
2148                 prbs_group = lut_prbs_2k[sub_channel_prbs_group];
2149                 break;
2150         case TRANSMISSION_MODE_4K:
2151                 prbs_group =  lut_prbs_4k[sub_channel_prbs_group];
2152                 break;
2153         default:
2154         case TRANSMISSION_MODE_8K:
2155                 prbs_group = lut_prbs_8k[sub_channel_prbs_group];
2156         }
2157
2158         dprintk("sub_channel_prbs_group = %d , subchannel =%d prbs = 0x%04x\n",
2159                 sub_channel_prbs_group, subchannel, prbs_group);
2160
2161         return prbs_group;
2162 }
2163
2164 static void dib8000_set_13seg_channel(struct dib8000_state *state)
2165 {
2166         u16 i;
2167         u16 coff_pow = 0x2800;
2168
2169         state->seg_mask = 0x1fff; /* All 13 segments enabled */
2170
2171         /* ---- COFF ---- Carloff, the most robust --- */
2172         if (state->isdbt_cfg_loaded == 0) {  /* if not Sound Broadcasting mode : put default values for 13 segments */
2173                 dib8000_write_word(state, 180, (16 << 6) | 9);
2174                 dib8000_write_word(state, 187, (4 << 12) | (8 << 5) | 0x2);
2175                 coff_pow = 0x2800;
2176                 for (i = 0; i < 6; i++)
2177                         dib8000_write_word(state, 181+i, coff_pow);
2178
2179                 /* P_ctrl_corm_thres4pre_freq_inh=1, P_ctrl_pre_freq_mode_sat=1 */
2180                 /* P_ctrl_pre_freq_mode_sat=1, P_ctrl_pre_freq_inh=0, P_ctrl_pre_freq_step = 3, P_pre_freq_win_len=1 */
2181                 dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (3 << 5) | 1);
2182
2183                 /* P_ctrl_pre_freq_win_len=8, P_ctrl_pre_freq_thres_lockin=6 */
2184                 dib8000_write_word(state, 340, (8 << 6) | (6 << 0));
2185                 /* P_ctrl_pre_freq_thres_lockout=4, P_small_use_tmcc/ac/cp=1 */
2186                 dib8000_write_word(state, 341, (4 << 3) | (1 << 2) | (1 << 1) | (1 << 0));
2187
2188                 dib8000_write_word(state, 228, 0);  /* default value */
2189                 dib8000_write_word(state, 265, 31); /* default value */
2190                 dib8000_write_word(state, 205, 0x200f); /* init value */
2191         }
2192
2193         /*
2194          * make the cpil_coff_lock more robust but slower p_coff_winlen
2195          * 6bits; p_coff_thres_lock 6bits (for coff lock if needed)
2196          */
2197
2198         if (state->cfg.pll->ifreq == 0)
2199                 dib8000_write_word(state, 266, ~state->seg_mask | state->seg_diff_mask | 0x40); /* P_equal_noise_seg_inh */
2200
2201         dib8000_load_ana_fe_coefs(state, ana_fe_coeff_13seg);
2202 }
2203
2204 static void dib8000_set_subchannel_prbs(struct dib8000_state *state, u16 init_prbs)
2205 {
2206         u16 reg_1;
2207
2208         reg_1 = dib8000_read_word(state, 1);
2209         dib8000_write_word(state, 1, (init_prbs << 2) | (reg_1 & 0x3)); /* ADDR 1 */
2210 }
2211
2212 static void dib8000_small_fine_tune(struct dib8000_state *state)
2213 {
2214         u16 i;
2215         const s16 *ncoeff;
2216         struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2217
2218         dib8000_write_word(state, 352, state->seg_diff_mask);
2219         dib8000_write_word(state, 353, state->seg_mask);
2220
2221         /* P_small_coef_ext_enable=ISDB-Tsb, P_small_narrow_band=ISDB-Tsb, P_small_last_seg=13, P_small_offset_num_car=5 */
2222         dib8000_write_word(state, 351, (c->isdbt_sb_mode << 9) | (c->isdbt_sb_mode << 8) | (13 << 4) | 5);
2223
2224         if (c->isdbt_sb_mode) {
2225                 /* ---- SMALL ---- */
2226                 switch (c->transmission_mode) {
2227                 case TRANSMISSION_MODE_2K:
2228                                 if (c->isdbt_partial_reception == 0) { /* 1-seg */
2229                                         if (c->layer[0].modulation == DQPSK) /* DQPSK */
2230                                                 ncoeff = coeff_2k_sb_1seg_dqpsk;
2231                                         else /* QPSK or QAM */
2232                                                 ncoeff = coeff_2k_sb_1seg;
2233                                 } else { /* 3-segments */
2234                                         if (c->layer[0].modulation == DQPSK) { /* DQPSK on central segment */
2235                                                 if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */
2236                                                         ncoeff = coeff_2k_sb_3seg_0dqpsk_1dqpsk;
2237                                                 else /* QPSK or QAM on external segments */
2238                                                         ncoeff = coeff_2k_sb_3seg_0dqpsk;
2239                                         } else { /* QPSK or QAM on central segment */
2240                                                 if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */
2241                                                         ncoeff = coeff_2k_sb_3seg_1dqpsk;
2242                                                 else /* QPSK or QAM on external segments */
2243                                                         ncoeff = coeff_2k_sb_3seg;
2244                                         }
2245                                 }
2246                                 break;
2247                 case TRANSMISSION_MODE_4K:
2248                                 if (c->isdbt_partial_reception == 0) { /* 1-seg */
2249                                         if (c->layer[0].modulation == DQPSK) /* DQPSK */
2250                                                 ncoeff = coeff_4k_sb_1seg_dqpsk;
2251                                         else /* QPSK or QAM */
2252                                                 ncoeff = coeff_4k_sb_1seg;
2253                                 } else { /* 3-segments */
2254                                         if (c->layer[0].modulation == DQPSK) { /* DQPSK on central segment */
2255                                                 if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */
2256                                                         ncoeff = coeff_4k_sb_3seg_0dqpsk_1dqpsk;
2257                                                 else /* QPSK or QAM on external segments */
2258                                                         ncoeff = coeff_4k_sb_3seg_0dqpsk;
2259                                         } else { /* QPSK or QAM on central segment */
2260                                                 if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */
2261                                                         ncoeff = coeff_4k_sb_3seg_1dqpsk;
2262                                                 else /* QPSK or QAM on external segments */
2263                                                         ncoeff = coeff_4k_sb_3seg;
2264                                         }
2265                                 }
2266                                 break;
2267                 case TRANSMISSION_MODE_AUTO:
2268                 case TRANSMISSION_MODE_8K:
2269                 default:
2270                                 if (c->isdbt_partial_reception == 0) { /* 1-seg */
2271                                         if (c->layer[0].modulation == DQPSK) /* DQPSK */
2272                                                 ncoeff = coeff_8k_sb_1seg_dqpsk;
2273                                         else /* QPSK or QAM */
2274                                                 ncoeff = coeff_8k_sb_1seg;
2275                                 } else { /* 3-segments */
2276                                         if (c->layer[0].modulation == DQPSK) { /* DQPSK on central segment */
2277                                                 if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */
2278                                                         ncoeff = coeff_8k_sb_3seg_0dqpsk_1dqpsk;
2279                                                 else /* QPSK or QAM on external segments */
2280                                                         ncoeff = coeff_8k_sb_3seg_0dqpsk;
2281                                         } else { /* QPSK or QAM on central segment */
2282                                                 if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */
2283                                                         ncoeff = coeff_8k_sb_3seg_1dqpsk;
2284                                                 else /* QPSK or QAM on external segments */
2285                                                         ncoeff = coeff_8k_sb_3seg;
2286                                         }
2287                                 }
2288                                 break;
2289                 }
2290
2291                 for (i = 0; i < 8; i++)
2292                         dib8000_write_word(state, 343 + i, ncoeff[i]);
2293         }
2294 }
2295
2296 static const u16 coff_thres_1seg[3] = {300, 150, 80};
2297 static const u16 coff_thres_3seg[3] = {350, 300, 250};
2298 static void dib8000_set_sb_channel(struct dib8000_state *state)
2299 {
2300         struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2301         const u16 *coff;
2302         u16 i;
2303
2304         if (c->transmission_mode == TRANSMISSION_MODE_2K || c->transmission_mode == TRANSMISSION_MODE_4K) {
2305                 dib8000_write_word(state, 219, dib8000_read_word(state, 219) | 0x1); /* adp_pass =1 */
2306                 dib8000_write_word(state, 190, dib8000_read_word(state, 190) | (0x1 << 14)); /* pha3_force_pha_shift = 1 */
2307         } else {
2308                 dib8000_write_word(state, 219, dib8000_read_word(state, 219) & 0xfffe); /* adp_pass =0 */
2309                 dib8000_write_word(state, 190, dib8000_read_word(state, 190) & 0xbfff); /* pha3_force_pha_shift = 0 */
2310         }
2311
2312         if (c->isdbt_partial_reception == 1) /* 3-segments */
2313                 state->seg_mask = 0x00E0;
2314         else /* 1-segment */
2315                 state->seg_mask = 0x0040;
2316
2317         dib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200);
2318
2319         /* ---- COFF ---- Carloff, the most robust --- */
2320         /* P_coff_cpil_alpha=4, P_coff_inh=0, P_coff_cpil_winlen=64, P_coff_narrow_band=1, P_coff_square_val=1, P_coff_one_seg=~partial_rcpt, P_coff_use_tmcc=1, P_coff_use_ac=1 */
2321         dib8000_write_word(state, 187, (4 << 12) | (0 << 11) | (63 << 5) | (0x3 << 3) | ((~c->isdbt_partial_reception & 1) << 2) | 0x3);
2322
2323         dib8000_write_word(state, 340, (16 << 6) | (8 << 0)); /* P_ctrl_pre_freq_win_len=16, P_ctrl_pre_freq_thres_lockin=8 */
2324         dib8000_write_word(state, 341, (6 << 3) | (1 << 2) | (1 << 1) | (1 << 0));/* P_ctrl_pre_freq_thres_lockout=6, P_small_use_tmcc/ac/cp=1 */
2325
2326         /* Sound Broadcasting mode 1 seg */
2327         if (c->isdbt_partial_reception == 0) {
2328                 /* P_coff_winlen=63, P_coff_thres_lock=15, P_coff_one_seg_width = (P_mode == 3) , P_coff_one_seg_sym = (P_mode-1) */
2329                 if (state->mode == 3)
2330                         dib8000_write_word(state, 180, 0x1fcf | ((state->mode - 1) << 14));
2331                 else
2332                         dib8000_write_word(state, 180, 0x0fcf | ((state->mode - 1) << 14));
2333
2334                 /* P_ctrl_corm_thres4pre_freq_inh=1,P_ctrl_pre_freq_mode_sat=1, P_ctrl_pre_freq_inh=0, P_ctrl_pre_freq_step = 5, P_pre_freq_win_len=4 */
2335                 dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (5 << 5) | 4);
2336                 coff = &coff_thres_1seg[0];
2337         } else {   /* Sound Broadcasting mode 3 seg */
2338                 dib8000_write_word(state, 180, 0x1fcf | (1 << 14));
2339                 /* P_ctrl_corm_thres4pre_freq_inh = 1, P_ctrl_pre_freq_mode_sat=1, P_ctrl_pre_freq_inh=0, P_ctrl_pre_freq_step = 4, P_pre_freq_win_len=4 */
2340                 dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (4 << 5) | 4);
2341                 coff = &coff_thres_3seg[0];
2342         }
2343
2344         dib8000_write_word(state, 228, 1); /* P_2d_mode_byp=1 */
2345         dib8000_write_word(state, 205, dib8000_read_word(state, 205) & 0xfff0); /* P_cspu_win_cut = 0 */
2346
2347         if (c->isdbt_partial_reception == 0 && c->transmission_mode == TRANSMISSION_MODE_2K)
2348                 dib8000_write_word(state, 265, 15); /* P_equal_noise_sel = 15 */
2349
2350         /* Write COFF thres */
2351         for (i = 0 ; i < 3; i++) {
2352                 dib8000_write_word(state, 181+i, coff[i]);
2353                 dib8000_write_word(state, 184+i, coff[i]);
2354         }
2355
2356         /*
2357          * make the cpil_coff_lock more robust but slower p_coff_winlen
2358          * 6bits; p_coff_thres_lock 6bits (for coff lock if needed)
2359          */
2360
2361         dib8000_write_word(state, 266, ~state->seg_mask | state->seg_diff_mask); /* P_equal_noise_seg_inh */
2362
2363         if (c->isdbt_partial_reception == 0)
2364                 dib8000_write_word(state, 178, 64); /* P_fft_powrange = 64 */
2365         else
2366                 dib8000_write_word(state, 178, 32); /* P_fft_powrange = 32 */
2367 }
2368
2369 static void dib8000_set_isdbt_common_channel(struct dib8000_state *state, u8 seq, u8 autosearching)
2370 {
2371         u16 p_cfr_left_edge  = 0, p_cfr_right_edge = 0;
2372         u16 tmcc_pow = 0, ana_gain = 0, tmp = 0, i = 0, nbseg_diff = 0 ;
2373         u16 max_constellation = DQPSK;
2374         int init_prbs;
2375         struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2376
2377         if (autosearching)
2378                 c->isdbt_partial_reception = 1;
2379
2380         /* P_mode */
2381         dib8000_write_word(state, 10, (seq << 4));
2382
2383         /* init mode */
2384         state->mode = fft_to_mode(state);
2385
2386         /* set guard */
2387         tmp = dib8000_read_word(state, 1);
2388         dib8000_write_word(state, 1, (tmp&0xfffc) | (c->guard_interval & 0x3));
2389
2390         dib8000_write_word(state, 274, (dib8000_read_word(state, 274) & 0xffcf) | ((c->isdbt_partial_reception & 1) << 5) | ((c->isdbt_sb_mode & 1) << 4));
2391
2392         /* signal optimization parameter */
2393         if (c->isdbt_partial_reception) {
2394                 state->seg_diff_mask = (c->layer[0].modulation == DQPSK) << permu_seg[0];
2395                 for (i = 1; i < 3; i++)
2396                         nbseg_diff += (c->layer[i].modulation == DQPSK) * c->layer[i].segment_count;
2397                 for (i = 0; i < nbseg_diff; i++)
2398                         state->seg_diff_mask |= 1 << permu_seg[i+1];
2399         } else {
2400                 for (i = 0; i < 3; i++)
2401                         nbseg_diff += (c->layer[i].modulation == DQPSK) * c->layer[i].segment_count;
2402                 for (i = 0; i < nbseg_diff; i++)
2403                         state->seg_diff_mask |= 1 << permu_seg[i];
2404         }
2405
2406         if (state->seg_diff_mask)
2407                 dib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200);
2408         else
2409                 dib8000_write_word(state, 268, (2 << 9) | 39); /*init value */
2410
2411         for (i = 0; i < 3; i++)
2412                 max_constellation = dib8000_set_layer(state, i, max_constellation);
2413         if (autosearching == 0) {
2414                 state->layer_b_nb_seg = c->layer[1].segment_count;
2415                 state->layer_c_nb_seg = c->layer[2].segment_count;
2416         }
2417
2418         /* WRITE: Mode & Diff mask */
2419         dib8000_write_word(state, 0, (state->mode << 13) | state->seg_diff_mask);
2420
2421         state->differential_constellation = (state->seg_diff_mask != 0);
2422
2423         /* channel estimation fine configuration */
2424         ana_gain = dib8000_adp_fine_tune(state, max_constellation);
2425
2426         /* update ana_gain depending on max constellation */
2427         dib8000_update_ana_gain(state, ana_gain);
2428
2429         /* ---- ANA_FE ---- */
2430         if (c->isdbt_partial_reception) /* 3-segments */
2431                 dib8000_load_ana_fe_coefs(state, ana_fe_coeff_3seg);
2432         else
2433                 dib8000_load_ana_fe_coefs(state, ana_fe_coeff_1seg); /* 1-segment */
2434
2435         /* TSB or ISDBT ? apply it now */
2436         if (c->isdbt_sb_mode) {
2437                 dib8000_set_sb_channel(state);
2438                 init_prbs = dib8000_get_init_prbs(state,
2439                                                   c->isdbt_sb_subchannel);
2440         } else {
2441                 dib8000_set_13seg_channel(state);
2442                 init_prbs = 0xfff;
2443         }
2444
2445         /* SMALL */
2446         dib8000_small_fine_tune(state);
2447
2448         dib8000_set_subchannel_prbs(state, init_prbs);
2449
2450         /* ---- CHAN_BLK ---- */
2451         for (i = 0; i < 13; i++) {
2452                 if ((((~state->seg_diff_mask) >> i) & 1) == 1) {
2453                         p_cfr_left_edge  += (1 << i) * ((i == 0) || ((((state->seg_mask & (~state->seg_diff_mask)) >> (i - 1)) & 1) == 0));
2454                         p_cfr_right_edge += (1 << i) * ((i == 12) || ((((state->seg_mask & (~state->seg_diff_mask)) >> (i + 1)) & 1) == 0));
2455                 }
2456         }
2457         dib8000_write_word(state, 222, p_cfr_left_edge); /* p_cfr_left_edge */
2458         dib8000_write_word(state, 223, p_cfr_right_edge); /* p_cfr_right_edge */
2459         /* "P_cspu_left_edge" & "P_cspu_right_edge" not used => do not care */
2460
2461         dib8000_write_word(state, 189, ~state->seg_mask | state->seg_diff_mask); /* P_lmod4_seg_inh */
2462         dib8000_write_word(state, 192, ~state->seg_mask | state->seg_diff_mask); /* P_pha3_seg_inh */
2463         dib8000_write_word(state, 225, ~state->seg_mask | state->seg_diff_mask); /* P_tac_seg_inh */
2464
2465         if (!autosearching)
2466                 dib8000_write_word(state, 288, (~state->seg_mask | state->seg_diff_mask) & 0x1fff); /* P_tmcc_seg_eq_inh */
2467         else
2468                 dib8000_write_word(state, 288, 0x1fff); /*disable equalisation of the tmcc when autosearch to be able to find the DQPSK channels. */
2469
2470         dib8000_write_word(state, 211, state->seg_mask & (~state->seg_diff_mask)); /* P_des_seg_enabled */
2471         dib8000_write_word(state, 287, ~state->seg_mask | 0x1000); /* P_tmcc_seg_inh */
2472
2473         dib8000_write_word(state, 178, 32); /* P_fft_powrange = 32 */
2474
2475         /* ---- TMCC ---- */
2476         for (i = 0; i < 3; i++)
2477                 tmcc_pow += (((c->layer[i].modulation == DQPSK) * 4 + 1) * c->layer[i].segment_count) ;
2478
2479         /* Quantif of "P_tmcc_dec_thres_?k" is (0, 5+mode, 9); */
2480         /* Threshold is set at 1/4 of max power. */
2481         tmcc_pow *= (1 << (9-2));
2482         dib8000_write_word(state, 290, tmcc_pow); /* P_tmcc_dec_thres_2k */
2483         dib8000_write_word(state, 291, tmcc_pow); /* P_tmcc_dec_thres_4k */
2484         dib8000_write_word(state, 292, tmcc_pow); /* P_tmcc_dec_thres_8k */
2485         /*dib8000_write_word(state, 287, (1 << 13) | 0x1000 ); */
2486
2487         /* ---- PHA3 ---- */
2488         if (state->isdbt_cfg_loaded == 0)
2489                 dib8000_write_word(state, 250, 3285); /* p_2d_hspeed_thr0 */
2490
2491         state->isdbt_cfg_loaded = 0;
2492 }
2493
2494 static u32 dib8000_wait_lock(struct dib8000_state *state, u32 internal,
2495                              u32 wait0_ms, u32 wait1_ms, u32 wait2_ms)
2496 {
2497         u32 value = 0;  /* P_search_end0 wait time */
2498         u16 reg = 11;   /* P_search_end0 start addr */
2499
2500         for (reg = 11; reg < 16; reg += 2) {
2501                 if (reg == 11) {
2502                         if (state->revision == 0x8090)
2503                                 value = internal * wait1_ms;
2504                         else
2505                                 value = internal * wait0_ms;
2506                 } else if (reg == 13)
2507                         value = internal * wait1_ms;
2508                 else if (reg == 15)
2509                         value = internal * wait2_ms;
2510                 dib8000_write_word(state, reg, (u16)((value >> 16) & 0xffff));
2511                 dib8000_write_word(state, (reg + 1), (u16)(value & 0xffff));
2512         }
2513         return value;
2514 }
2515
2516 static int dib8000_autosearch_start(struct dvb_frontend *fe)
2517 {
2518         struct dib8000_state *state = fe->demodulator_priv;
2519         struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2520         u8 slist = 0;
2521         u32 value, internal = state->cfg.pll->internal;
2522
2523         if (state->revision == 0x8090)
2524                 internal = dib8000_read32(state, 23) / 1000;
2525
2526         if ((state->revision >= 0x8002) &&
2527             (state->autosearch_state == AS_SEARCHING_FFT)) {
2528                 dib8000_write_word(state,  37, 0x0065); /* P_ctrl_pha_off_max default values */
2529                 dib8000_write_word(state, 116, 0x0000); /* P_ana_gain to 0 */
2530
2531                 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x1fff) | (0 << 13) | (1 << 15)); /* P_mode = 0, P_restart_search=1 */
2532                 dib8000_write_word(state, 1, (dib8000_read_word(state, 1) & 0xfffc) | 0); /* P_guard = 0 */
2533                 dib8000_write_word(state, 6, 0); /* P_lock0_mask = 0 */
2534                 dib8000_write_word(state, 7, 0); /* P_lock1_mask = 0 */
2535                 dib8000_write_word(state, 8, 0); /* P_lock2_mask = 0 */
2536                 dib8000_write_word(state, 10, (dib8000_read_word(state, 10) & 0x200) | (16 << 4) | (0 << 0)); /* P_search_list=16, P_search_maxtrial=0 */
2537
2538                 if (state->revision == 0x8090)
2539                         value = dib8000_wait_lock(state, internal, 10, 10, 10); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */
2540                 else
2541                         value = dib8000_wait_lock(state, internal, 20, 20, 20); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */
2542
2543                 dib8000_write_word(state, 17, 0);
2544                 dib8000_write_word(state, 18, 200); /* P_search_rstst = 200 */
2545                 dib8000_write_word(state, 19, 0);
2546                 dib8000_write_word(state, 20, 400); /* P_search_rstend = 400 */
2547                 dib8000_write_word(state, 21, (value >> 16) & 0xffff); /* P_search_checkst */
2548                 dib8000_write_word(state, 22, value & 0xffff);
2549
2550                 if (state->revision == 0x8090)
2551                         dib8000_write_word(state, 32, (dib8000_read_word(state, 32) & 0xf0ff) | (0 << 8)); /* P_corm_alpha = 0 */
2552                 else
2553                         dib8000_write_word(state, 32, (dib8000_read_word(state, 32) & 0xf0ff) | (9 << 8)); /* P_corm_alpha = 3 */
2554                 dib8000_write_word(state, 355, 2); /* P_search_param_max = 2 */
2555
2556                 /* P_search_param_select = (1 | 1<<4 | 1 << 8) */
2557                 dib8000_write_word(state, 356, 0);
2558                 dib8000_write_word(state, 357, 0x111);
2559
2560                 dib8000_write_word(state, 770, (dib8000_read_word(state, 770) & 0xdfff) | (1 << 13)); /* P_restart_ccg = 1 */
2561                 dib8000_write_word(state, 770, (dib8000_read_word(state, 770) & 0xdfff) | (0 << 13)); /* P_restart_ccg = 0 */
2562                 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x7ff) | (0 << 15) | (1 << 13)); /* P_restart_search = 0; */
2563         } else if ((state->revision >= 0x8002) &&
2564                    (state->autosearch_state == AS_SEARCHING_GUARD)) {
2565                 c->transmission_mode = TRANSMISSION_MODE_8K;
2566                 c->guard_interval = GUARD_INTERVAL_1_8;
2567                 c->inversion = 0;
2568                 c->layer[0].modulation = QAM_64;
2569                 c->layer[0].fec = FEC_2_3;
2570                 c->layer[0].interleaving = 0;
2571                 c->layer[0].segment_count = 13;
2572
2573                 slist = 16;
2574                 c->transmission_mode = state->found_nfft;
2575
2576                 dib8000_set_isdbt_common_channel(state, slist, 1);
2577
2578                 /* set lock_mask values */
2579                 dib8000_write_word(state, 6, 0x4);
2580                 if (state->revision == 0x8090)
2581                         dib8000_write_word(state, 7, ((1 << 12) | (1 << 11) | (1 << 10)));/* tmcc_dec_lock, tmcc_sync_lock, tmcc_data_lock, tmcc_bch_uncor */
2582                 else
2583                         dib8000_write_word(state, 7, 0x8);
2584                 dib8000_write_word(state, 8, 0x1000);
2585
2586                 /* set lock_mask wait time values */
2587                 if (state->revision == 0x8090)
2588                         dib8000_wait_lock(state, internal, 50, 100, 1000); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */
2589                 else
2590                         dib8000_wait_lock(state, internal, 50, 200, 1000); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */
2591
2592                 dib8000_write_word(state, 355, 3); /* P_search_param_max = 3 */
2593
2594                 /* P_search_param_select = 0xf; look for the 4 different guard intervals */
2595                 dib8000_write_word(state, 356, 0);
2596                 dib8000_write_word(state, 357, 0xf);
2597
2598                 value = dib8000_read_word(state, 0);
2599                 dib8000_write_word(state, 0, (u16)((1 << 15) | value));
2600                 dib8000_read_word(state, 1284);  /* reset the INT. n_irq_pending */
2601                 dib8000_write_word(state, 0, (u16)value);
2602         } else {
2603                 c->inversion = 0;
2604                 c->layer[0].modulation = QAM_64;
2605                 c->layer[0].fec = FEC_2_3;
2606                 c->layer[0].interleaving = 0;
2607                 c->layer[0].segment_count = 13;
2608                 if (!c->isdbt_sb_mode)
2609                         c->layer[0].segment_count = 13;
2610
2611                 /* choose the right list, in sb, always do everything */
2612                 if (c->isdbt_sb_mode) {
2613                         slist = 7;
2614                         dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13));
2615                 } else {
2616                         if (c->guard_interval == GUARD_INTERVAL_AUTO) {
2617                                 if (c->transmission_mode == TRANSMISSION_MODE_AUTO) {
2618                                         c->transmission_mode = TRANSMISSION_MODE_8K;
2619                                         c->guard_interval = GUARD_INTERVAL_1_8;
2620                                         slist = 7;
2621                                         dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13));  /* P_mode = 1 to have autosearch start ok with mode2 */
2622                                 } else {
2623                                         c->guard_interval = GUARD_INTERVAL_1_8;
2624                                         slist = 3;
2625                                 }
2626                         } else {
2627                                 if (c->transmission_mode == TRANSMISSION_MODE_AUTO) {
2628                                         c->transmission_mode = TRANSMISSION_MODE_8K;
2629                                         slist = 2;
2630                                         dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13));  /* P_mode = 1 */
2631                                 } else
2632                                         slist = 0;
2633                         }
2634                 }
2635                 dprintk("Using list for autosearch : %d\n", slist);
2636
2637                 dib8000_set_isdbt_common_channel(state, slist, 1);
2638
2639                 /* set lock_mask values */
2640                 dib8000_write_word(state, 6, 0x4);
2641                 if (state->revision == 0x8090)
2642                         dib8000_write_word(state, 7, (1 << 12) | (1 << 11) | (1 << 10));
2643                 else
2644                         dib8000_write_word(state, 7, 0x8);
2645                 dib8000_write_word(state, 8, 0x1000);
2646
2647                 /* set lock_mask wait time values */
2648                 if (state->revision == 0x8090)
2649                         dib8000_wait_lock(state, internal, 50, 200, 1000); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */
2650                 else
2651                         dib8000_wait_lock(state, internal, 50, 100, 1000); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */
2652
2653                 value = dib8000_read_word(state, 0);
2654                 dib8000_write_word(state, 0, (u16)((1 << 15) | value));
2655                 dib8000_read_word(state, 1284);  /* reset the INT. n_irq_pending */
2656                 dib8000_write_word(state, 0, (u16)value);
2657         }
2658         return 0;
2659 }
2660
2661 static int dib8000_autosearch_irq(struct dvb_frontend *fe)
2662 {
2663         struct dib8000_state *state = fe->demodulator_priv;
2664         u16 irq_pending = dib8000_read_word(state, 1284);
2665
2666         if ((state->revision >= 0x8002) &&
2667             (state->autosearch_state == AS_SEARCHING_FFT)) {
2668                 if (irq_pending & 0x1) {
2669                         dprintk("dib8000_autosearch_irq: max correlation result available\n");
2670                         return 3;
2671                 }
2672         } else {
2673                 if (irq_pending & 0x1) {        /* failed */
2674                         dprintk("dib8000_autosearch_irq failed\n");
2675                         return 1;
2676                 }
2677
2678                 if (irq_pending & 0x2) {        /* succeeded */
2679                         dprintk("dib8000_autosearch_irq succeeded\n");
2680                         return 2;
2681                 }
2682         }
2683
2684         return 0;               // still pending
2685 }
2686
2687 static void dib8000_viterbi_state(struct dib8000_state *state, u8 onoff)
2688 {
2689         u16 tmp;
2690
2691         tmp = dib8000_read_word(state, 771);
2692         if (onoff) /* start P_restart_chd : channel_decoder */
2693                 dib8000_write_word(state, 771, tmp & 0xfffd);
2694         else /* stop P_restart_chd : channel_decoder */
2695                 dib8000_write_word(state, 771, tmp | (1<<1));
2696 }
2697
2698 static void dib8000_set_dds(struct dib8000_state *state, s32 offset_khz)
2699 {
2700         s16 unit_khz_dds_val;
2701         u32 abs_offset_khz = abs(offset_khz);
2702         u32 dds = state->cfg.pll->ifreq & 0x1ffffff;
2703         u8 invert = !!(state->cfg.pll->ifreq & (1 << 25));
2704         u8 ratio;
2705
2706         if (state->revision == 0x8090) {
2707                 ratio = 4;
2708                 unit_khz_dds_val = (1<<26) / (dib8000_read32(state, 23) / 1000);
2709                 if (offset_khz < 0)
2710                         dds = (1 << 26) - (abs_offset_khz * unit_khz_dds_val);
2711                 else
2712                         dds = (abs_offset_khz * unit_khz_dds_val);
2713
2714                 if (invert)
2715                         dds = (1<<26) - dds;
2716         } else {
2717                 ratio = 2;
2718                 unit_khz_dds_val = (u16) (67108864 / state->cfg.pll->internal);
2719
2720                 if (offset_khz < 0)
2721                         unit_khz_dds_val *= -1;
2722
2723                 /* IF tuner */
2724                 if (invert)
2725                         dds -= abs_offset_khz * unit_khz_dds_val;
2726                 else
2727                         dds += abs_offset_khz * unit_khz_dds_val;
2728         }
2729
2730         dprintk("setting a DDS frequency offset of %c%dkHz\n", invert ? '-' : ' ', dds / unit_khz_dds_val);
2731
2732         if (abs_offset_khz <= (state->cfg.pll->internal / ratio)) {
2733                 /* Max dds offset is the half of the demod freq */
2734                 dib8000_write_word(state, 26, invert);
2735                 dib8000_write_word(state, 27, (u16)(dds >> 16) & 0x1ff);
2736                 dib8000_write_word(state, 28, (u16)(dds & 0xffff));
2737         }
2738 }
2739
2740 static void dib8000_set_frequency_offset(struct dib8000_state *state)
2741 {
2742         struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2743         int i;
2744         u32 current_rf;
2745         int total_dds_offset_khz;
2746
2747         if (state->fe[0]->ops.tuner_ops.get_frequency)
2748                 state->fe[0]->ops.tuner_ops.get_frequency(state->fe[0], &current_rf);
2749         else
2750                 current_rf = c->frequency;
2751         current_rf /= 1000;
2752         total_dds_offset_khz = (int)current_rf - (int)c->frequency / 1000;
2753
2754         if (c->isdbt_sb_mode) {
2755                 state->subchannel = c->isdbt_sb_subchannel;
2756
2757                 i = dib8000_read_word(state, 26) & 1; /* P_dds_invspec */
2758                 dib8000_write_word(state, 26, c->inversion ^ i);
2759
2760                 if (state->cfg.pll->ifreq == 0) { /* low if tuner */
2761                         if ((c->inversion ^ i) == 0)
2762                                 dib8000_write_word(state, 26, dib8000_read_word(state, 26) | 1);
2763                 } else {
2764                         if ((c->inversion ^ i) == 0)
2765                                 total_dds_offset_khz *= -1;
2766                 }
2767         }
2768
2769         dprintk("%dkhz tuner offset (frequency = %dHz & current_rf = %dHz) total_dds_offset_hz = %d\n", c->frequency - current_rf, c->frequency, current_rf, total_dds_offset_khz);
2770
2771         /* apply dds offset now */
2772         dib8000_set_dds(state, total_dds_offset_khz);
2773 }
2774
2775 static u16 LUT_isdbt_symbol_duration[4] = { 26, 101, 63 };
2776
2777 static u32 dib8000_get_symbol_duration(struct dib8000_state *state)
2778 {
2779         struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2780         u16 i;
2781
2782         switch (c->transmission_mode) {
2783         case TRANSMISSION_MODE_2K:
2784                         i = 0;
2785                         break;
2786         case TRANSMISSION_MODE_4K:
2787                         i = 2;
2788                         break;
2789         default:
2790         case TRANSMISSION_MODE_AUTO:
2791         case TRANSMISSION_MODE_8K:
2792                         i = 1;
2793                         break;
2794         }
2795
2796         return (LUT_isdbt_symbol_duration[i] / (c->bandwidth_hz / 1000)) + 1;
2797 }
2798
2799 static void dib8000_set_isdbt_loop_params(struct dib8000_state *state, enum param_loop_step loop_step)
2800 {
2801         struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2802         u16 reg_32 = 0, reg_37 = 0;
2803
2804         switch (loop_step) {
2805         case LOOP_TUNE_1:
2806                         if (c->isdbt_sb_mode)  {
2807                                 if (c->isdbt_partial_reception == 0) {
2808                                         reg_32 = ((11 - state->mode) << 12) | (6 << 8) | 0x40; /* P_timf_alpha = (11-P_mode), P_corm_alpha=6, P_corm_thres=0x40 */
2809                                         reg_37 = (3 << 5) | (0 << 4) | (10 - state->mode); /* P_ctrl_pha_off_max=3   P_ctrl_sfreq_inh =0  P_ctrl_sfreq_step = (10-P_mode)  */
2810                                 } else { /* Sound Broadcasting mode 3 seg */
2811                                         reg_32 = ((10 - state->mode) << 12) | (6 << 8) | 0x60; /* P_timf_alpha = (10-P_mode), P_corm_alpha=6, P_corm_thres=0x60 */
2812                                         reg_37 = (3 << 5) | (0 << 4) | (9 - state->mode); /* P_ctrl_pha_off_max=3   P_ctrl_sfreq_inh =0  P_ctrl_sfreq_step = (9-P_mode)  */
2813                                 }
2814                         } else { /* 13-seg start conf offset loop parameters */
2815                                 reg_32 = ((9 - state->mode) << 12) | (6 << 8) | 0x80; /* P_timf_alpha = (9-P_mode, P_corm_alpha=6, P_corm_thres=0x80 */
2816                                 reg_37 = (3 << 5) | (0 << 4) | (8 - state->mode); /* P_ctrl_pha_off_max=3   P_ctrl_sfreq_inh =0  P_ctrl_sfreq_step = 9  */
2817                         }
2818                         break;
2819         case LOOP_TUNE_2:
2820                         if (c->isdbt_sb_mode)  {
2821                                 if (c->isdbt_partial_reception == 0) {  /* Sound Broadcasting mode 1 seg */
2822                                         reg_32 = ((13-state->mode) << 12) | (6 << 8) | 0x40; /* P_timf_alpha = (13-P_mode) , P_corm_alpha=6, P_corm_thres=0x40*/
2823                                         reg_37 = (12-state->mode) | ((5 + state->mode) << 5);
2824                                 } else {  /* Sound Broadcasting mode 3 seg */
2825                                         reg_32 = ((12-state->mode) << 12) | (6 << 8) | 0x60; /* P_timf_alpha = (12-P_mode) , P_corm_alpha=6, P_corm_thres=0x60 */
2826                                         reg_37 = (11-state->mode) | ((5 + state->mode) << 5);
2827                                 }
2828                         } else {  /* 13 seg */
2829                                 reg_32 = ((11-state->mode) << 12) | (6 << 8) | 0x80; /* P_timf_alpha = 8 , P_corm_alpha=6, P_corm_thres=0x80 */
2830                                 reg_37 = ((5+state->mode) << 5) | (10 - state->mode);
2831                         }
2832                         break;
2833         }
2834         dib8000_write_word(state, 32, reg_32);
2835         dib8000_write_word(state, 37, reg_37);
2836 }
2837
2838 static void dib8000_demod_restart(struct dib8000_state *state)
2839 {
2840         dib8000_write_word(state, 770, 0x4000);
2841         dib8000_write_word(state, 770, 0x0000);
2842         return;
2843 }
2844
2845 static void dib8000_set_sync_wait(struct dib8000_state *state)
2846 {
2847         struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2848         u16 sync_wait = 64;
2849
2850         /* P_dvsy_sync_wait - reuse mode */
2851         switch (c->transmission_mode) {
2852         case TRANSMISSION_MODE_8K:
2853                         sync_wait = 256;
2854                         break;
2855         case TRANSMISSION_MODE_4K:
2856                         sync_wait = 128;
2857                         break;
2858         default:
2859         case TRANSMISSION_MODE_2K:
2860                         sync_wait =  64;
2861                         break;
2862         }
2863
2864         if (state->cfg.diversity_delay == 0)
2865                 sync_wait = (sync_wait * (1 << (c->guard_interval)) * 3) / 2 + 48; /* add 50% SFN margin + compensate for one DVSY-fifo */
2866         else
2867                 sync_wait = (sync_wait * (1 << (c->guard_interval)) * 3) / 2 + state->cfg.diversity_delay; /* add 50% SFN margin + compensate for DVSY-fifo */
2868
2869         dib8000_write_word(state, 273, (dib8000_read_word(state, 273) & 0x000f) | (sync_wait << 4));
2870 }
2871
2872 static unsigned long dib8000_get_timeout(struct dib8000_state *state, u32 delay, enum timeout_mode mode)
2873 {
2874         if (mode == SYMBOL_DEPENDENT_ON)
2875                 delay *= state->symbol_duration;
2876
2877         return jiffies + usecs_to_jiffies(delay * 100);
2878 }
2879
2880 static s32 dib8000_get_status(struct dvb_frontend *fe)
2881 {
2882         struct dib8000_state *state = fe->demodulator_priv;
2883         return state->status;
2884 }
2885
2886 static enum frontend_tune_state dib8000_get_tune_state(struct dvb_frontend *fe)
2887 {
2888         struct dib8000_state *state = fe->demodulator_priv;
2889         return state->tune_state;
2890 }
2891
2892 static int dib8000_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state)
2893 {
2894         struct dib8000_state *state = fe->demodulator_priv;
2895
2896         state->tune_state = tune_state;
2897         return 0;
2898 }
2899
2900 static int dib8000_tune_restart_from_demod(struct dvb_frontend *fe)
2901 {
2902         struct dib8000_state *state = fe->demodulator_priv;
2903
2904         state->status = FE_STATUS_TUNE_PENDING;
2905         state->tune_state = CT_DEMOD_START;
2906         return 0;
2907 }
2908
2909 static u16 dib8000_read_lock(struct dvb_frontend *fe)
2910 {
2911         struct dib8000_state *state = fe->demodulator_priv;
2912
2913         if (state->revision == 0x8090)
2914                 return dib8000_read_word(state, 570);
2915         return dib8000_read_word(state, 568);
2916 }
2917
2918 static int dib8090p_init_sdram(struct dib8000_state *state)
2919 {
2920         u16 reg = 0;
2921         dprintk("init sdram\n");
2922
2923         reg = dib8000_read_word(state, 274) & 0xfff0;
2924         dib8000_write_word(state, 274, reg | 0x7); /* P_dintlv_delay_ram = 7 because of MobileSdram */
2925
2926         dib8000_write_word(state, 1803, (7 << 2));
2927
2928         reg = dib8000_read_word(state, 1280);
2929         dib8000_write_word(state, 1280,  reg | (1 << 2)); /* force restart P_restart_sdram */
2930         dib8000_write_word(state, 1280,  reg); /* release restart P_restart_sdram */
2931
2932         return 0;
2933 }
2934
2935 /**
2936  * is_manual_mode - Check if TMCC should be used for parameters settings
2937  * @c:  struct dvb_frontend_properties
2938  *
2939  * By default, TMCC table should be used for parameter settings on most
2940  * usercases. However, sometimes it is desirable to lock the demod to
2941  * use the manual parameters.
2942  *
2943  * On manual mode, the current dib8000_tune state machine is very restrict:
2944  * It requires that both per-layer and per-transponder parameters to be
2945  * properly specified, otherwise the device won't lock.
2946  *
2947  * Check if all those conditions are properly satisfied before allowing
2948  * the device to use the manual frequency lock mode.
2949  */
2950 static int is_manual_mode(struct dtv_frontend_properties *c)
2951 {
2952         int i, n_segs = 0;
2953
2954         /* Use auto mode on DVB-T compat mode */
2955         if (c->delivery_system != SYS_ISDBT)
2956                 return 0;
2957
2958         /*
2959          * Transmission mode is only detected on auto mode, currently
2960          */
2961         if (c->transmission_mode == TRANSMISSION_MODE_AUTO) {
2962                 dprintk("transmission mode auto\n");
2963                 return 0;
2964         }
2965
2966         /*
2967          * Guard interval is only detected on auto mode, currently
2968          */
2969         if (c->guard_interval == GUARD_INTERVAL_AUTO) {
2970                 dprintk("guard interval auto\n");
2971                 return 0;
2972         }
2973
2974         /*
2975          * If no layer is enabled, assume auto mode, as at least one
2976          * layer should be enabled
2977          */
2978         if (!c->isdbt_layer_enabled) {
2979                 dprintk("no layer modulation specified\n");
2980                 return 0;
2981         }
2982
2983         /*
2984          * Check if the per-layer parameters aren't auto and
2985          * disable a layer if segment count is 0 or invalid.
2986          */
2987         for (i = 0; i < 3; i++) {
2988                 if (!(c->isdbt_layer_enabled & 1 << i))
2989                         continue;
2990
2991                 if ((c->layer[i].segment_count > 13) ||
2992                     (c->layer[i].segment_count == 0)) {
2993                         c->isdbt_layer_enabled &= ~(1 << i);
2994                         continue;
2995                 }
2996
2997                 n_segs += c->layer[i].segment_count;
2998
2999                 if ((c->layer[i].modulation == QAM_AUTO) ||
3000                     (c->layer[i].fec == FEC_AUTO)) {
3001                         dprintk("layer %c has either modulation or FEC auto\n",
3002                                 'A' + i);
3003                         return 0;
3004                 }
3005         }
3006
3007         /*
3008          * Userspace specified a wrong number of segments.
3009          *      fallback to auto mode.
3010          */
3011         if (n_segs == 0 || n_segs > 13) {
3012                 dprintk("number of segments is invalid\n");
3013                 return 0;
3014         }
3015
3016         /* Everything looks ok for manual mode */
3017         return 1;
3018 }
3019
3020 static int dib8000_tune(struct dvb_frontend *fe)
3021 {
3022         struct dib8000_state *state = fe->demodulator_priv;
3023         struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
3024         enum frontend_tune_state *tune_state = &state->tune_state;
3025
3026         u16 locks, deeper_interleaver = 0, i;
3027         int ret = 1; /* 1 symbol duration (in 100us unit) delay most of the time */
3028
3029         unsigned long *timeout = &state->timeout;
3030         unsigned long now = jiffies;
3031         u16 init_prbs;
3032 #ifdef DIB8000_AGC_FREEZE
3033         u16 agc1, agc2;
3034 #endif
3035
3036         u32 corm[4] = {0, 0, 0, 0};
3037         u8 find_index, max_value;
3038
3039 #if 0
3040         if (*tune_state < CT_DEMOD_STOP)
3041                 dprintk("IN: context status = %d, TUNE_STATE %d autosearch step = %u jiffies = %lu\n",
3042                         state->channel_parameters_set, *tune_state, state->autosearch_state, now);
3043 #endif
3044
3045         switch (*tune_state) {
3046         case CT_DEMOD_START: /* 30 */
3047                 dib8000_reset_stats(fe);
3048
3049                 if (state->revision == 0x8090)
3050                         dib8090p_init_sdram(state);
3051                 state->status = FE_STATUS_TUNE_PENDING;
3052                 state->channel_parameters_set = is_manual_mode(c);
3053
3054                 dprintk("Tuning channel on %s search mode\n",
3055                         state->channel_parameters_set ? "manual" : "auto");
3056
3057                 dib8000_viterbi_state(state, 0); /* force chan dec in restart */
3058
3059                 /* Layer monitor */
3060                 dib8000_write_word(state, 285, dib8000_read_word(state, 285) & 0x60);
3061
3062                 dib8000_set_frequency_offset(state);
3063                 dib8000_set_bandwidth(fe, c->bandwidth_hz / 1000);
3064
3065                 if (state->channel_parameters_set == 0) { /* The channel struct is unknown, search it ! */
3066 #ifdef DIB8000_AGC_FREEZE
3067                         if (state->revision != 0x8090) {
3068                                 state->agc1_max = dib8000_read_word(state, 108);
3069                                 state->agc1_min = dib8000_read_word(state, 109);
3070                                 state->agc2_max = dib8000_read_word(state, 110);
3071                                 state->agc2_min = dib8000_read_word(state, 111);
3072                                 agc1 = dib8000_read_word(state, 388);
3073                                 agc2 = dib8000_read_word(state, 389);
3074                                 dib8000_write_word(state, 108, agc1);
3075                                 dib8000_write_word(state, 109, agc1);
3076                                 dib8000_write_word(state, 110, agc2);
3077                                 dib8000_write_word(state, 111, agc2);
3078                         }
3079 #endif
3080                         state->autosearch_state = AS_SEARCHING_FFT;
3081                         state->found_nfft = TRANSMISSION_MODE_AUTO;
3082                         state->found_guard = GUARD_INTERVAL_AUTO;
3083                         *tune_state = CT_DEMOD_SEARCH_NEXT;
3084                 } else { /* we already know the channel struct so TUNE only ! */
3085                         state->autosearch_state = AS_DONE;
3086                         *tune_state = CT_DEMOD_STEP_3;
3087                 }
3088                 state->symbol_duration = dib8000_get_symbol_duration(state);
3089                 break;
3090
3091         case CT_DEMOD_SEARCH_NEXT: /* 51 */
3092                 dib8000_autosearch_start(fe);
3093                 if (state->revision == 0x8090)
3094                         ret = 50;
3095                 else
3096                         ret = 15;
3097                 *tune_state = CT_DEMOD_STEP_1;
3098                 break;
3099
3100         case CT_DEMOD_STEP_1: /* 31 */
3101                 switch (dib8000_autosearch_irq(fe)) {
3102                 case 1: /* fail */
3103                         state->status = FE_STATUS_TUNE_FAILED;
3104                         state->autosearch_state = AS_DONE;
3105                         *tune_state = CT_DEMOD_STOP; /* else we are done here */
3106                         break;
3107                 case 2: /* Succes */
3108                         state->status = FE_STATUS_FFT_SUCCESS; /* signal to the upper layer, that there was a channel found and the parameters can be read */
3109                         *tune_state = CT_DEMOD_STEP_3;
3110                         if (state->autosearch_state == AS_SEARCHING_GUARD)
3111                                 *tune_state = CT_DEMOD_STEP_2;
3112                         else
3113                                 state->autosearch_state = AS_DONE;
3114                         break;
3115                 case 3: /* Autosearch FFT max correlation endded */
3116                         *tune_state = CT_DEMOD_STEP_2;
3117                         break;
3118                 }
3119                 break;
3120
3121         case CT_DEMOD_STEP_2:
3122                 switch (state->autosearch_state) {
3123                 case AS_SEARCHING_FFT:
3124                         /* searching for the correct FFT */
3125                         if (state->revision == 0x8090) {
3126                                 corm[2] = (dib8000_read_word(state, 596) << 16) | (dib8000_read_word(state, 597));
3127                                 corm[1] = (dib8000_read_word(state, 598) << 16) | (dib8000_read_word(state, 599));
3128                                 corm[0] = (dib8000_read_word(state, 600) << 16) | (dib8000_read_word(state, 601));
3129                         } else {
3130                                 corm[2] = (dib8000_read_word(state, 594) << 16) | (dib8000_read_word(state, 595));
3131                                 corm[1] = (dib8000_read_word(state, 596) << 16) | (dib8000_read_word(state, 597));
3132                                 corm[0] = (dib8000_read_word(state, 598) << 16) | (dib8000_read_word(state, 599));
3133                         }
3134                         /* dprintk("corm fft: %u %u %u\n", corm[0], corm[1], corm[2]); */
3135
3136                         max_value = 0;
3137                         for (find_index = 1 ; find_index < 3 ; find_index++) {
3138                                 if (corm[max_value] < corm[find_index])
3139                                         max_value = find_index ;
3140                         }
3141
3142                         switch (max_value) {
3143                         case 0:
3144                                 state->found_nfft = TRANSMISSION_MODE_2K;
3145                                 break;
3146                         case 1:
3147                                 state->found_nfft = TRANSMISSION_MODE_4K;
3148                                 break;
3149                         case 2:
3150                         default:
3151                                 state->found_nfft = TRANSMISSION_MODE_8K;
3152                                 break;
3153                         }
3154                         /* dprintk("Autosearch FFT has found Mode %d\n", max_value + 1); */
3155
3156                         *tune_state = CT_DEMOD_SEARCH_NEXT;
3157                         state->autosearch_state = AS_SEARCHING_GUARD;
3158                         if (state->revision == 0x8090)
3159                                 ret = 50;
3160                         else
3161                                 ret = 10;
3162                         break;
3163                 case AS_SEARCHING_GUARD:
3164                         /* searching for the correct guard interval */
3165                         if (state->revision == 0x8090)
3166                                 state->found_guard = dib8000_read_word(state, 572) & 0x3;
3167                         else
3168                                 state->found_guard = dib8000_read_word(state, 570) & 0x3;
3169                         /* dprintk("guard interval found=%i\n", state->found_guard); */
3170
3171                         *tune_state = CT_DEMOD_STEP_3;
3172                         break;
3173                 default:
3174                         /* the demod should never be in this state */
3175                         state->status = FE_STATUS_TUNE_FAILED;
3176                         state->autosearch_state = AS_DONE;
3177                         *tune_state = CT_DEMOD_STOP; /* else we are done here */
3178                         break;
3179                 }
3180                 break;
3181
3182         case CT_DEMOD_STEP_3: /* 33 */
3183                 dib8000_set_isdbt_loop_params(state, LOOP_TUNE_1);
3184                 dib8000_set_isdbt_common_channel(state, 0, 0);/* setting the known channel parameters here */
3185                 *tune_state = CT_DEMOD_STEP_4;
3186                 break;
3187
3188         case CT_DEMOD_STEP_4: /* (34) */
3189                 dib8000_demod_restart(state);
3190
3191                 dib8000_set_sync_wait(state);
3192                 dib8000_set_diversity_in(state->fe[0], state->diversity_onoff);
3193
3194                 locks = (dib8000_read_word(state, 180) >> 6) & 0x3f; /* P_coff_winlen ? */
3195                 /* coff should lock over P_coff_winlen ofdm symbols : give 3 times this length to lock */
3196                 *timeout = dib8000_get_timeout(state, 2 * locks, SYMBOL_DEPENDENT_ON);
3197                 *tune_state = CT_DEMOD_STEP_5;
3198                 break;
3199
3200         case CT_DEMOD_STEP_5: /* (35) */
3201                 locks = dib8000_read_lock(fe);
3202                 if (locks & (0x3 << 11)) { /* coff-lock and off_cpil_lock achieved */
3203                         dib8000_update_timf(state); /* we achieved a coff_cpil_lock - it's time to update the timf */
3204                         if (!state->differential_constellation) {
3205                                 /* 2 times lmod4_win_len + 10 symbols (pipe delay after coff + nb to compute a 1st correlation) */
3206                                 *timeout = dib8000_get_timeout(state, (20 * ((dib8000_read_word(state, 188)>>5)&0x1f)), SYMBOL_DEPENDENT_ON);
3207                                 *tune_state = CT_DEMOD_STEP_7;
3208                         } else {
3209                                 *tune_state = CT_DEMOD_STEP_8;
3210                         }
3211                 } else if (time_after(now, *timeout)) {
3212                         *tune_state = CT_DEMOD_STEP_6; /* goto check for diversity input connection */
3213                 }
3214                 break;
3215
3216         case CT_DEMOD_STEP_6: /* (36)  if there is an input (diversity) */
3217                 if ((state->fe[1] != NULL) && (state->output_mode != OUTMODE_DIVERSITY)) {
3218                         /* if there is a diversity fe in input and this fe is has not already failled : wait here until this this fe has succedeed or failled */
3219                         if (dib8000_get_status(state->fe[1]) <= FE_STATUS_STD_SUCCESS) /* Something is locked on the input fe */
3220                                 *tune_state = CT_DEMOD_STEP_8; /* go for mpeg */
3221                         else if (dib8000_get_status(state->fe[1]) >= FE_STATUS_TUNE_TIME_TOO_SHORT) { /* fe in input failled also, break the current one */
3222                                 *tune_state = CT_DEMOD_STOP; /* else we are done here ; step 8 will close the loops and exit */
3223                                 dib8000_viterbi_state(state, 1); /* start viterbi chandec */
3224                                 dib8000_set_isdbt_loop_params(state, LOOP_TUNE_2);
3225                                 state->status = FE_STATUS_TUNE_FAILED;
3226                         }
3227                 } else {
3228                         dib8000_viterbi_state(state, 1); /* start viterbi chandec */
3229                         dib8000_set_isdbt_loop_params(state, LOOP_TUNE_2);
3230                         *tune_state = CT_DEMOD_STOP; /* else we are done here ; step 8 will close the loops and exit */
3231                         state->status = FE_STATUS_TUNE_FAILED;
3232                 }
3233                 break;
3234
3235         case CT_DEMOD_STEP_7: /* 37 */
3236                 locks = dib8000_read_lock(fe);
3237                 if (locks & (1<<10)) { /* lmod4_lock */
3238                         ret = 14; /* wait for 14 symbols */
3239                         *tune_state = CT_DEMOD_STEP_8;
3240                 } else if (time_after(now, *timeout))
3241                         *tune_state = CT_DEMOD_STEP_6; /* goto check for diversity input connection */
3242                 break;
3243
3244         case CT_DEMOD_STEP_8: /* 38 */
3245                 dib8000_viterbi_state(state, 1); /* start viterbi chandec */
3246                 dib8000_set_isdbt_loop_params(state, LOOP_TUNE_2);
3247
3248                 /* mpeg will never lock on this condition because init_prbs is not set : search for it !*/
3249                 if (c->isdbt_sb_mode
3250                     && c->isdbt_sb_subchannel < 14
3251                     && !state->differential_constellation) {
3252                         state->subchannel = 0;
3253                         *tune_state = CT_DEMOD_STEP_11;
3254                 } else {
3255                         *tune_state = CT_DEMOD_STEP_9;
3256                         state->status = FE_STATUS_LOCKED;
3257                 }
3258                 break;
3259
3260         case CT_DEMOD_STEP_9: /* 39 */
3261                 if ((state->revision == 0x8090) || ((dib8000_read_word(state, 1291) >> 9) & 0x1)) { /* fe capable of deinterleaving : esram */
3262                         /* defines timeout for mpeg lock depending on interleaver length of longest layer */
3263                         for (i = 0; i < 3; i++) {
3264                                 if (c->layer[i].interleaving >= deeper_interleaver) {
3265                                         dprintk("layer%i: time interleaver = %d\n", i, c->layer[i].interleaving);
3266                                         if (c->layer[i].segment_count > 0) { /* valid layer */
3267                                                 deeper_interleaver = c->layer[0].interleaving;
3268                                                 state->longest_intlv_layer = i;
3269                                         }
3270                                 }
3271                         }
3272
3273                         if (deeper_interleaver == 0)
3274                                 locks = 2; /* locks is the tmp local variable name */
3275                         else if (deeper_interleaver == 3)
3276                                 locks = 8;
3277                         else
3278                                 locks = 2 * deeper_interleaver;
3279
3280                         if (state->diversity_onoff != 0) /* because of diversity sync */
3281                                 locks *= 2;
3282
3283                         *timeout = now + msecs_to_jiffies(200 * locks); /* give the mpeg lock 800ms if sram is present */
3284                         dprintk("Deeper interleaver mode = %d on layer %d : timeout mult factor = %d => will use timeout = %ld\n",
3285                                 deeper_interleaver, state->longest_intlv_layer, locks, *timeout);
3286
3287                         *tune_state = CT_DEMOD_STEP_10;
3288                 } else
3289                         *tune_state = CT_DEMOD_STOP;
3290                 break;
3291
3292         case CT_DEMOD_STEP_10: /* 40 */
3293                 locks = dib8000_read_lock(fe);
3294                 if (locks&(1<<(7-state->longest_intlv_layer))) { /* mpeg lock : check the longest one */
3295                         dprintk("ISDB-T layer locks: Layer A %s, Layer B %s, Layer C %s\n",
3296                                 c->layer[0].segment_count ? (locks >> 7) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled",
3297                                 c->layer[1].segment_count ? (locks >> 6) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled",
3298                                 c->layer[2].segment_count ? (locks >> 5) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled");
3299                         if (c->isdbt_sb_mode
3300                             && c->isdbt_sb_subchannel < 14
3301                             && !state->differential_constellation)
3302                                 /* signal to the upper layer, that there was a channel found and the parameters can be read */
3303                                 state->status = FE_STATUS_DEMOD_SUCCESS;
3304                         else
3305                                 state->status = FE_STATUS_DATA_LOCKED;
3306                         *tune_state = CT_DEMOD_STOP;
3307                 } else if (time_after(now, *timeout)) {
3308                         if (c->isdbt_sb_mode
3309                             && c->isdbt_sb_subchannel < 14
3310                             && !state->differential_constellation) { /* continue to try init prbs autosearch */
3311                                 state->subchannel += 3;
3312                                 *tune_state = CT_DEMOD_STEP_11;
3313                         } else { /* we are done mpeg of the longest interleaver xas not locking but let's try if an other layer has locked in the same time */
3314                                 if (locks & (0x7 << 5)) {
3315                                         dprintk("Not all ISDB-T layers locked in %d ms: Layer A %s, Layer B %s, Layer C %s\n",
3316                                                 jiffies_to_msecs(now - *timeout),
3317                                                 c->layer[0].segment_count ? (locks >> 7) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled",
3318                                                 c->layer[1].segment_count ? (locks >> 6) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled",
3319                                                 c->layer[2].segment_count ? (locks >> 5) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled");
3320
3321                                         state->status = FE_STATUS_DATA_LOCKED;
3322                                 } else
3323                                         state->status = FE_STATUS_TUNE_FAILED;
3324                                 *tune_state = CT_DEMOD_STOP;
3325                         }
3326                 }
3327                 break;
3328
3329         case CT_DEMOD_STEP_11:  /* 41 : init prbs autosearch */
3330                 init_prbs = dib8000_get_init_prbs(state, state->subchannel);
3331
3332                 if (init_prbs) {
3333                         dib8000_set_subchannel_prbs(state, init_prbs);
3334                         *tune_state = CT_DEMOD_STEP_9;
3335                 } else {
3336                         *tune_state = CT_DEMOD_STOP;
3337                         state->status = FE_STATUS_TUNE_FAILED;
3338                 }
3339                 break;
3340
3341         default:
3342                 break;
3343         }
3344
3345         /* tuning is finished - cleanup the demod */
3346         switch (*tune_state) {
3347         case CT_DEMOD_STOP: /* (42) */
3348 #ifdef DIB8000_AGC_FREEZE
3349                 if ((state->revision != 0x8090) && (state->agc1_max != 0)) {
3350                         dib8000_write_word(state, 108, state->agc1_max);
3351                         dib8000_write_word(state, 109, state->agc1_min);
3352                         dib8000_write_word(state, 110, state->agc2_max);
3353                         dib8000_write_word(state, 111, state->agc2_min);
3354                         state->agc1_max = 0;
3355                         state->agc1_min = 0;
3356                         state->agc2_max = 0;
3357                         state->agc2_min = 0;
3358                 }
3359 #endif
3360                 ret = 0;
3361                 break;
3362         default:
3363                 break;
3364         }
3365
3366         if ((ret > 0) && (*tune_state > CT_DEMOD_STEP_3))
3367                 return ret * state->symbol_duration;
3368         if ((ret > 0) && (ret < state->symbol_duration))
3369                 return state->symbol_duration; /* at least one symbol */
3370         return ret;
3371 }
3372
3373 static int dib8000_wakeup(struct dvb_frontend *fe)
3374 {
3375         struct dib8000_state *state = fe->demodulator_priv;
3376         u8 index_frontend;
3377         int ret;
3378
3379         dib8000_set_power_mode(state, DIB8000_POWER_ALL);
3380         dib8000_set_adc_state(state, DIBX000_ADC_ON);
3381         if (dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON) != 0)
3382                 dprintk("could not start Slow ADC\n");
3383
3384         if (state->revision == 0x8090)
3385                 dib8000_sad_calib(state);
3386
3387         for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3388                 ret = state->fe[index_frontend]->ops.init(state->fe[index_frontend]);
3389                 if (ret < 0)
3390                         return ret;
3391         }
3392
3393         return 0;
3394 }
3395
3396 static int dib8000_sleep(struct dvb_frontend *fe)
3397 {
3398         struct dib8000_state *state = fe->demodulator_priv;
3399         u8 index_frontend;
3400         int ret;
3401
3402         for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3403                 ret = state->fe[index_frontend]->ops.sleep(state->fe[index_frontend]);
3404                 if (ret < 0)
3405                         return ret;
3406         }
3407
3408         if (state->revision != 0x8090)
3409                 dib8000_set_output_mode(fe, OUTMODE_HIGH_Z);
3410         dib8000_set_power_mode(state, DIB8000_POWER_INTERFACE_ONLY);
3411         return dib8000_set_adc_state(state, DIBX000_SLOW_ADC_OFF) | dib8000_set_adc_state(state, DIBX000_ADC_OFF);
3412 }
3413
3414 static int dib8000_read_status(struct dvb_frontend *fe, enum fe_status *stat);
3415
3416 static int dib8000_get_frontend(struct dvb_frontend *fe,
3417                                 struct dtv_frontend_properties *c)
3418 {
3419         struct dib8000_state *state = fe->demodulator_priv;
3420         u16 i, val = 0;
3421         enum fe_status stat = 0;
3422         u8 index_frontend, sub_index_frontend;
3423
3424         c->bandwidth_hz = 6000000;
3425
3426         /*
3427          * If called to early, get_frontend makes dib8000_tune to either
3428          * not lock or not sync. This causes dvbv5-scan/dvbv5-zap to fail.
3429          * So, let's just return if frontend 0 has not locked.
3430          */
3431         dib8000_read_status(fe, &stat);
3432         if (!(stat & FE_HAS_SYNC))
3433                 return 0;
3434
3435         dprintk("dib8000_get_frontend: TMCC lock\n");
3436         for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3437                 state->fe[index_frontend]->ops.read_status(state->fe[index_frontend], &stat);
3438                 if (stat&FE_HAS_SYNC) {
3439                         dprintk("TMCC lock on the slave%i\n", index_frontend);
3440                         /* synchronize the cache with the other frontends */
3441                         state->fe[index_frontend]->ops.get_frontend(state->fe[index_frontend], c);
3442                         for (sub_index_frontend = 0; (sub_index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[sub_index_frontend] != NULL); sub_index_frontend++) {
3443                                 if (sub_index_frontend != index_frontend) {
3444                                         state->fe[sub_index_frontend]->dtv_property_cache.isdbt_sb_mode = state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode;
3445                                         state->fe[sub_index_frontend]->dtv_property_cache.inversion = state->fe[index_frontend]->dtv_property_cache.inversion;
3446                                         state->fe[sub_index_frontend]->dtv_property_cache.transmission_mode = state->fe[index_frontend]->dtv_property_cache.transmission_mode;
3447                                         state->fe[sub_index_frontend]->dtv_property_cache.guard_interval = state->fe[index_frontend]->dtv_property_cache.guard_interval;
3448                                         state->fe[sub_index_frontend]->dtv_property_cache.isdbt_partial_reception = state->fe[index_frontend]->dtv_property_cache.isdbt_partial_reception;
3449                                         for (i = 0; i < 3; i++) {
3450                                                 state->fe[sub_index_frontend]->dtv_property_cache.layer[i].segment_count = state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count;
3451                                                 state->fe[sub_index_frontend]->dtv_property_cache.layer[i].interleaving = state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving;
3452                                                 state->fe[sub_index_frontend]->dtv_property_cache.layer[i].fec = state->fe[index_frontend]->dtv_property_cache.layer[i].fec;
3453                                                 state->fe[sub_index_frontend]->dtv_property_cache.layer[i].modulation = state->fe[index_frontend]->dtv_property_cache.layer[i].modulation;
3454                                         }
3455                                 }
3456                         }
3457                         return 0;
3458                 }
3459         }
3460
3461         c->isdbt_sb_mode = dib8000_read_word(state, 508) & 0x1;
3462
3463         if (state->revision == 0x8090)
3464                 val = dib8000_read_word(state, 572);
3465         else
3466                 val = dib8000_read_word(state, 570);
3467         c->inversion = (val & 0x40) >> 6;
3468         switch ((val & 0x30) >> 4) {
3469         case 1:
3470                 c->transmission_mode = TRANSMISSION_MODE_2K;
3471                 dprintk("dib8000_get_frontend: transmission mode 2K\n");
3472                 break;
3473         case 2:
3474                 c->transmission_mode = TRANSMISSION_MODE_4K;
3475                 dprintk("dib8000_get_frontend: transmission mode 4K\n");
3476                 break;
3477         case 3:
3478         default:
3479                 c->transmission_mode = TRANSMISSION_MODE_8K;
3480                 dprintk("dib8000_get_frontend: transmission mode 8K\n");
3481                 break;
3482         }
3483
3484         switch (val & 0x3) {
3485         case 0:
3486                 c->guard_interval = GUARD_INTERVAL_1_32;
3487                 dprintk("dib8000_get_frontend: Guard Interval = 1/32\n");
3488                 break;
3489         case 1:
3490                 c->guard_interval = GUARD_INTERVAL_1_16;
3491                 dprintk("dib8000_get_frontend: Guard Interval = 1/16\n");
3492                 break;
3493         case 2:
3494                 dprintk("dib8000_get_frontend: Guard Interval = 1/8\n");
3495                 c->guard_interval = GUARD_INTERVAL_1_8;
3496                 break;
3497         case 3:
3498                 dprintk("dib8000_get_frontend: Guard Interval = 1/4\n");
3499                 c->guard_interval = GUARD_INTERVAL_1_4;
3500                 break;
3501         }
3502
3503         val = dib8000_read_word(state, 505);
3504         c->isdbt_partial_reception = val & 1;
3505         dprintk("dib8000_get_frontend: partial_reception = %d\n", c->isdbt_partial_reception);
3506
3507         for (i = 0; i < 3; i++) {
3508                 int show;
3509
3510                 val = dib8000_read_word(state, 493 + i) & 0x0f;
3511                 c->layer[i].segment_count = val;
3512
3513                 if (val == 0 || val > 13)
3514                         show = 0;
3515                 else
3516                         show = 1;
3517
3518                 if (show)
3519                         dprintk("dib8000_get_frontend: Layer %d segments = %d\n",
3520                                 i, c->layer[i].segment_count);
3521
3522                 val = dib8000_read_word(state, 499 + i) & 0x3;
3523                 /* Interleaving can be 0, 1, 2 or 4 */
3524                 if (val == 3)
3525                         val = 4;
3526                 c->layer[i].interleaving = val;
3527                 if (show)
3528                         dprintk("dib8000_get_frontend: Layer %d time_intlv = %d\n",
3529                                 i, c->layer[i].interleaving);
3530
3531                 val = dib8000_read_word(state, 481 + i);
3532                 switch (val & 0x7) {
3533                 case 1:
3534                         c->layer[i].fec = FEC_1_2;
3535                         if (show)
3536                                 dprintk("dib8000_get_frontend: Layer %d Code Rate = 1/2\n", i);
3537                         break;
3538                 case 2:
3539                         c->layer[i].fec = FEC_2_3;
3540                         if (show)
3541                                 dprintk("dib8000_get_frontend: Layer %d Code Rate = 2/3\n", i);
3542                         break;
3543                 case 3:
3544                         c->layer[i].fec = FEC_3_4;
3545                         if (show)
3546                                 dprintk("dib8000_get_frontend: Layer %d Code Rate = 3/4\n", i);
3547                         break;
3548                 case 5:
3549                         c->layer[i].fec = FEC_5_6;
3550                         if (show)
3551                                 dprintk("dib8000_get_frontend: Layer %d Code Rate = 5/6\n", i);
3552                         break;
3553                 default:
3554                         c->layer[i].fec = FEC_7_8;
3555                         if (show)
3556                                 dprintk("dib8000_get_frontend: Layer %d Code Rate = 7/8\n", i);
3557                         break;
3558                 }
3559
3560                 val = dib8000_read_word(state, 487 + i);
3561                 switch (val & 0x3) {
3562                 case 0:
3563                         c->layer[i].modulation = DQPSK;
3564                         if (show)
3565                                 dprintk("dib8000_get_frontend: Layer %d DQPSK\n", i);
3566                         break;
3567                 case 1:
3568                         c->layer[i].modulation = QPSK;
3569                         if (show)
3570                                 dprintk("dib8000_get_frontend: Layer %d QPSK\n", i);
3571                         break;
3572                 case 2:
3573                         c->layer[i].modulation = QAM_16;
3574                         if (show)
3575                                 dprintk("dib8000_get_frontend: Layer %d QAM16\n", i);
3576                         break;
3577                 case 3:
3578                 default:
3579                         c->layer[i].modulation = QAM_64;
3580                         if (show)
3581                                 dprintk("dib8000_get_frontend: Layer %d QAM64\n", i);
3582                         break;
3583                 }
3584         }
3585
3586         /* synchronize the cache with the other frontends */
3587         for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3588                 state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode = c->isdbt_sb_mode;
3589                 state->fe[index_frontend]->dtv_property_cache.inversion = c->inversion;
3590                 state->fe[index_frontend]->dtv_property_cache.transmission_mode = c->transmission_mode;
3591                 state->fe[index_frontend]->dtv_property_cache.guard_interval = c->guard_interval;
3592                 state->fe[index_frontend]->dtv_property_cache.isdbt_partial_reception = c->isdbt_partial_reception;
3593                 for (i = 0; i < 3; i++) {
3594                         state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count = c->layer[i].segment_count;
3595                         state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving = c->layer[i].interleaving;
3596                         state->fe[index_frontend]->dtv_property_cache.layer[i].fec = c->layer[i].fec;
3597                         state->fe[index_frontend]->dtv_property_cache.layer[i].modulation = c->layer[i].modulation;
3598                 }
3599         }
3600         return 0;
3601 }
3602
3603 static int dib8000_set_frontend(struct dvb_frontend *fe)
3604 {
3605         struct dib8000_state *state = fe->demodulator_priv;
3606         struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
3607         int l, i, active, time, time_slave = 0;
3608         u8 exit_condition, index_frontend;
3609         unsigned long delay, callback_time;
3610
3611         if (c->frequency == 0) {
3612                 dprintk("dib8000: must at least specify frequency\n");
3613                 return 0;
3614         }
3615
3616         if (c->bandwidth_hz == 0) {
3617                 dprintk("dib8000: no bandwidth specified, set to default\n");
3618                 c->bandwidth_hz = 6000000;
3619         }
3620
3621         for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3622                 /* synchronization of the cache */
3623                 state->fe[index_frontend]->dtv_property_cache.delivery_system = SYS_ISDBT;
3624                 memcpy(&state->fe[index_frontend]->dtv_property_cache, &fe->dtv_property_cache, sizeof(struct dtv_frontend_properties));
3625
3626                 /* set output mode and diversity input */
3627                 if (state->revision != 0x8090) {
3628                         dib8000_set_diversity_in(state->fe[index_frontend], 1);
3629                         if (index_frontend != 0)
3630                                 dib8000_set_output_mode(state->fe[index_frontend],
3631                                                 OUTMODE_DIVERSITY);
3632                         else
3633                                 dib8000_set_output_mode(state->fe[0], OUTMODE_HIGH_Z);
3634                 } else {
3635                         dib8096p_set_diversity_in(state->fe[index_frontend], 1);
3636                         if (index_frontend != 0)
3637                                 dib8096p_set_output_mode(state->fe[index_frontend],
3638                                                 OUTMODE_DIVERSITY);
3639                         else
3640                                 dib8096p_set_output_mode(state->fe[0], OUTMODE_HIGH_Z);
3641                 }
3642
3643                 /* tune the tuner */
3644                 if (state->fe[index_frontend]->ops.tuner_ops.set_params)
3645                         state->fe[index_frontend]->ops.tuner_ops.set_params(state->fe[index_frontend]);
3646
3647                 dib8000_set_tune_state(state->fe[index_frontend], CT_AGC_START);
3648         }
3649
3650         /* turn off the diversity of the last chip */
3651         if (state->revision != 0x8090)
3652                 dib8000_set_diversity_in(state->fe[index_frontend - 1], 0);
3653         else
3654                 dib8096p_set_diversity_in(state->fe[index_frontend - 1], 0);
3655
3656         /* start up the AGC */
3657         do {
3658                 time = dib8000_agc_startup(state->fe[0]);
3659                 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3660                         time_slave = dib8000_agc_startup(state->fe[index_frontend]);
3661                         if (time == 0)
3662                                 time = time_slave;
3663                         else if ((time_slave != 0) && (time_slave > time))
3664                                 time = time_slave;
3665                 }
3666                 if (time == 0)
3667                         break;
3668
3669                 /*
3670                  * Despite dib8000_agc_startup returns time at a 0.1 ms range,
3671                  * the actual sleep time depends on CONFIG_HZ. The worse case
3672                  * is when CONFIG_HZ=100. In such case, the minimum granularity
3673                  * is 10ms. On some real field tests, the tuner sometimes don't
3674                  * lock when this timer is lower than 10ms. So, enforce a 10ms
3675                  * granularity.
3676                  */
3677                 time = 10 * (time + 99)/100;
3678                 usleep_range(time * 1000, (time + 1) * 1000);
3679                 exit_condition = 1;
3680                 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3681                         if (dib8000_get_tune_state(state->fe[index_frontend]) != CT_AGC_STOP) {
3682                                 exit_condition = 0;
3683                                 break;
3684                         }
3685                 }
3686         } while (exit_condition == 0);
3687
3688         for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
3689                 dib8000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START);
3690
3691         active = 1;
3692         do {
3693                 callback_time = 0;
3694                 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3695                         delay = dib8000_tune(state->fe[index_frontend]);
3696                         if (delay != 0) {
3697                                 delay = jiffies + usecs_to_jiffies(100 * delay);
3698                                 if (!callback_time || delay < callback_time)
3699                                         callback_time = delay;
3700                         }
3701
3702                         /* we are in autosearch */
3703                         if (state->channel_parameters_set == 0) { /* searching */
3704                                 if ((dib8000_get_status(state->fe[index_frontend]) == FE_STATUS_DEMOD_SUCCESS) || (dib8000_get_status(state->fe[index_frontend]) == FE_STATUS_FFT_SUCCESS)) {
3705                                         dprintk("autosearch succeeded on fe%i\n", index_frontend);
3706                                         dib8000_get_frontend(state->fe[index_frontend], c); /* we read the channel parameters from the frontend which was successful */
3707                                         state->channel_parameters_set = 1;
3708
3709                                         for (l = 0; (l < MAX_NUMBER_OF_FRONTENDS) && (state->fe[l] != NULL); l++) {
3710                                                 if (l != index_frontend) { /* and for all frontend except the successful one */
3711                                                         dprintk("Restarting frontend %d\n", l);
3712                                                         dib8000_tune_restart_from_demod(state->fe[l]);
3713
3714                                                         state->fe[l]->dtv_property_cache.isdbt_sb_mode = state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode;
3715                                                         state->fe[l]->dtv_property_cache.inversion = state->fe[index_frontend]->dtv_property_cache.inversion;
3716                                                         state->fe[l]->dtv_property_cache.transmission_mode = state->fe[index_frontend]->dtv_property_cache.transmission_mode;
3717                                                         state->fe[l]->dtv_property_cache.guard_interval = state->fe[index_frontend]->dtv_property_cache.guard_interval;
3718                                                         state->fe[l]->dtv_property_cache.isdbt_partial_reception = state->fe[index_frontend]->dtv_property_cache.isdbt_partial_reception;
3719                                                         for (i = 0; i < 3; i++) {
3720                                                                 state->fe[l]->dtv_property_cache.layer[i].segment_count = state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count;
3721                                                                 state->fe[l]->dtv_property_cache.layer[i].interleaving = state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving;
3722                                                                 state->fe[l]->dtv_property_cache.layer[i].fec = state->fe[index_frontend]->dtv_property_cache.layer[i].fec;
3723                                                                 state->fe[l]->dtv_property_cache.layer[i].modulation = state->fe[index_frontend]->dtv_property_cache.layer[i].modulation;
3724                                                         }
3725
3726                                                 }
3727                                         }
3728                                 }
3729                         }
3730                 }
3731                 /* tuning is done when the master frontend is done (failed or success) */
3732                 if (dib8000_get_status(state->fe[0]) == FE_STATUS_TUNE_FAILED ||
3733                                 dib8000_get_status(state->fe[0]) == FE_STATUS_LOCKED ||
3734                                 dib8000_get_status(state->fe[0]) == FE_STATUS_DATA_LOCKED) {
3735                         active = 0;
3736                         /* we need to wait for all frontends to be finished */
3737                         for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3738                                 if (dib8000_get_tune_state(state->fe[index_frontend]) != CT_DEMOD_STOP)
3739                                         active = 1;
3740                         }
3741                         if (active == 0)
3742                                 dprintk("tuning done with status %d\n", dib8000_get_status(state->fe[0]));
3743                 }
3744
3745                 if ((active == 1) && (callback_time == 0)) {
3746                         dprintk("strange callback time something went wrong\n");
3747                         active = 0;
3748                 }
3749
3750                 while ((active == 1) && (time_before(jiffies, callback_time)))
3751                         msleep(100);
3752         } while (active);
3753
3754         /* set output mode */
3755         if (state->revision != 0x8090)
3756                 dib8000_set_output_mode(state->fe[0], state->cfg.output_mode);
3757         else {
3758                 dib8096p_set_output_mode(state->fe[0], state->cfg.output_mode);
3759                 if (state->cfg.enMpegOutput == 0) {
3760                         dib8096p_setDibTxMux(state, MPEG_ON_DIBTX);
3761                         dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS);
3762                 }
3763         }
3764
3765         return 0;
3766 }
3767
3768 static int dib8000_get_stats(struct dvb_frontend *fe, enum fe_status stat);
3769
3770 static int dib8000_read_status(struct dvb_frontend *fe, enum fe_status *stat)
3771 {
3772         struct dib8000_state *state = fe->demodulator_priv;
3773         u16 lock_slave = 0, lock;
3774         u8 index_frontend;
3775
3776         lock = dib8000_read_lock(fe);
3777         for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
3778                 lock_slave |= dib8000_read_lock(state->fe[index_frontend]);
3779
3780         *stat = 0;
3781
3782         if (((lock >> 13) & 1) || ((lock_slave >> 13) & 1))
3783                 *stat |= FE_HAS_SIGNAL;
3784
3785         if (((lock >> 8) & 1) || ((lock_slave >> 8) & 1)) /* Equal */
3786                 *stat |= FE_HAS_CARRIER;
3787
3788         if ((((lock >> 1) & 0xf) == 0xf) || (((lock_slave >> 1) & 0xf) == 0xf)) /* TMCC_SYNC */
3789                 *stat |= FE_HAS_SYNC;
3790
3791         if ((((lock >> 12) & 1) || ((lock_slave >> 12) & 1)) && ((lock >> 5) & 7)) /* FEC MPEG */
3792                 *stat |= FE_HAS_LOCK;
3793
3794         if (((lock >> 12) & 1) || ((lock_slave >> 12) & 1)) {
3795                 lock = dib8000_read_word(state, 554); /* Viterbi Layer A */
3796                 if (lock & 0x01)
3797                         *stat |= FE_HAS_VITERBI;
3798
3799                 lock = dib8000_read_word(state, 555); /* Viterbi Layer B */
3800                 if (lock & 0x01)
3801                         *stat |= FE_HAS_VITERBI;
3802
3803                 lock = dib8000_read_word(state, 556); /* Viterbi Layer C */
3804                 if (lock & 0x01)
3805                         *stat |= FE_HAS_VITERBI;
3806         }
3807         dib8000_get_stats(fe, *stat);
3808
3809         return 0;
3810 }
3811
3812 static int dib8000_read_ber(struct dvb_frontend *fe, u32 * ber)
3813 {
3814         struct dib8000_state *state = fe->demodulator_priv;
3815
3816         /* 13 segments */
3817         if (state->revision == 0x8090)
3818                 *ber = (dib8000_read_word(state, 562) << 16) |
3819                         dib8000_read_word(state, 563);
3820         else
3821                 *ber = (dib8000_read_word(state, 560) << 16) |
3822                         dib8000_read_word(state, 561);
3823         return 0;
3824 }
3825
3826 static int dib8000_read_unc_blocks(struct dvb_frontend *fe, u32 * unc)
3827 {
3828         struct dib8000_state *state = fe->demodulator_priv;
3829
3830         /* packet error on 13 seg */
3831         if (state->revision == 0x8090)
3832                 *unc = dib8000_read_word(state, 567);
3833         else
3834                 *unc = dib8000_read_word(state, 565);
3835         return 0;
3836 }
3837
3838 static int dib8000_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
3839 {
3840         struct dib8000_state *state = fe->demodulator_priv;
3841         u8 index_frontend;
3842         u16 val;
3843
3844         *strength = 0;
3845         for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3846                 state->fe[index_frontend]->ops.read_signal_strength(state->fe[index_frontend], &val);
3847                 if (val > 65535 - *strength)
3848                         *strength = 65535;
3849                 else
3850                         *strength += val;
3851         }
3852
3853         val = 65535 - dib8000_read_word(state, 390);
3854         if (val > 65535 - *strength)
3855                 *strength = 65535;
3856         else
3857                 *strength += val;
3858         return 0;
3859 }
3860
3861 static u32 dib8000_get_snr(struct dvb_frontend *fe)
3862 {
3863         struct dib8000_state *state = fe->demodulator_priv;
3864         u32 n, s, exp;
3865         u16 val;
3866
3867         if (state->revision != 0x8090)
3868                 val = dib8000_read_word(state, 542);
3869         else
3870                 val = dib8000_read_word(state, 544);
3871         n = (val >> 6) & 0xff;
3872         exp = (val & 0x3f);
3873         if ((exp & 0x20) != 0)
3874                 exp -= 0x40;
3875         n <<= exp+16;
3876
3877         if (state->revision != 0x8090)
3878                 val = dib8000_read_word(state, 543);
3879         else
3880                 val = dib8000_read_word(state, 545);
3881         s = (val >> 6) & 0xff;
3882         exp = (val & 0x3f);
3883         if ((exp & 0x20) != 0)
3884                 exp -= 0x40;
3885         s <<= exp+16;
3886
3887         if (n > 0) {
3888                 u32 t = (s/n) << 16;
3889                 return t + ((s << 16) - n*t) / n;
3890         }
3891         return 0xffffffff;
3892 }
3893
3894 static int dib8000_read_snr(struct dvb_frontend *fe, u16 * snr)
3895 {
3896         struct dib8000_state *state = fe->demodulator_priv;
3897         u8 index_frontend;
3898         u32 snr_master;
3899
3900         snr_master = dib8000_get_snr(fe);
3901         for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
3902                 snr_master += dib8000_get_snr(state->fe[index_frontend]);
3903
3904         if ((snr_master >> 16) != 0) {
3905                 snr_master = 10*intlog10(snr_master>>16);
3906                 *snr = snr_master / ((1 << 24) / 10);
3907         }
3908         else
3909                 *snr = 0;
3910
3911         return 0;
3912 }
3913
3914 struct per_layer_regs {
3915         u16 lock, ber, per;
3916 };
3917
3918 static const struct per_layer_regs per_layer_regs[] = {
3919         { 554, 560, 562 },
3920         { 555, 576, 578 },
3921         { 556, 581, 583 },
3922 };
3923
3924 struct linear_segments {
3925         unsigned x;
3926         signed y;
3927 };
3928
3929 /*
3930  * Table to estimate signal strength in dBm.
3931  * This table was empirically determinated by measuring the signal
3932  * strength generated by a DTA-2111 RF generator directly connected into
3933  * a dib8076 device (a PixelView PV-D231U stick), using a good quality
3934  * 3 meters RC6 cable and good RC6 connectors.
3935  * The real value can actually be different on other devices, depending
3936  * on several factors, like if LNA is enabled or not, if diversity is
3937  * enabled, type of connectors, etc.
3938  * Yet, it is better to use this measure in dB than a random non-linear
3939  * percentage value, especially for antenna adjustments.
3940  * On my tests, the precision of the measure using this table is about
3941  * 0.5 dB, with sounds reasonable enough.
3942  */
3943 static struct linear_segments strength_to_db_table[] = {
3944         { 55953, 108500 },      /* -22.5 dBm */
3945         { 55394, 108000 },
3946         { 53834, 107000 },
3947         { 52863, 106000 },
3948         { 52239, 105000 },
3949         { 52012, 104000 },
3950         { 51803, 103000 },
3951         { 51566, 102000 },
3952         { 51356, 101000 },
3953         { 51112, 100000 },
3954         { 50869,  99000 },
3955         { 50600,  98000 },
3956         { 50363,  97000 },
3957         { 50117,  96000 },      /* -35 dBm */
3958         { 49889,  95000 },
3959         { 49680,  94000 },
3960         { 49493,  93000 },
3961         { 49302,  92000 },
3962         { 48929,  91000 },
3963         { 48416,  90000 },
3964         { 48035,  89000 },
3965         { 47593,  88000 },
3966         { 47282,  87000 },
3967         { 46953,  86000 },
3968         { 46698,  85000 },
3969         { 45617,  84000 },
3970         { 44773,  83000 },
3971         { 43845,  82000 },
3972         { 43020,  81000 },
3973         { 42010,  80000 },      /* -51 dBm */
3974         {     0,      0 },
3975 };
3976
3977 static u32 interpolate_value(u32 value, struct linear_segments *segments,
3978                              unsigned len)
3979 {
3980         u64 tmp64;
3981         u32 dx;
3982         s32 dy;
3983         int i, ret;
3984
3985         if (value >= segments[0].x)
3986                 return segments[0].y;
3987         if (value < segments[len-1].x)
3988                 return segments[len-1].y;
3989
3990         for (i = 1; i < len - 1; i++) {
3991                 /* If value is identical, no need to interpolate */
3992                 if (value == segments[i].x)
3993                         return segments[i].y;
3994                 if (value > segments[i].x)
3995                         break;
3996         }
3997
3998         /* Linear interpolation between the two (x,y) points */
3999         dy = segments[i - 1].y - segments[i].y;
4000         dx = segments[i - 1].x - segments[i].x;
4001
4002         tmp64 = value - segments[i].x;
4003         tmp64 *= dy;
4004         do_div(tmp64, dx);
4005         ret = segments[i].y + tmp64;
4006
4007         return ret;
4008 }
4009
4010 static u32 dib8000_get_time_us(struct dvb_frontend *fe, int layer)
4011 {
4012         struct dib8000_state *state = fe->demodulator_priv;
4013         struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
4014         int ini_layer, end_layer, i;
4015         u64 time_us, tmp64;
4016         u32 tmp, denom;
4017         int guard, rate_num, rate_denum = 1, bits_per_symbol, nsegs;
4018         int interleaving = 0, fft_div;
4019
4020         if (layer >= 0) {
4021                 ini_layer = layer;
4022                 end_layer = layer + 1;
4023         } else {
4024                 ini_layer = 0;
4025                 end_layer = 3;
4026         }
4027
4028         switch (c->guard_interval) {
4029         case GUARD_INTERVAL_1_4:
4030                 guard = 4;
4031                 break;
4032         case GUARD_INTERVAL_1_8:
4033                 guard = 8;
4034                 break;
4035         case GUARD_INTERVAL_1_16:
4036                 guard = 16;
4037                 break;
4038         default:
4039         case GUARD_INTERVAL_1_32:
4040                 guard = 32;
4041                 break;
4042         }
4043
4044         switch (c->transmission_mode) {
4045         case TRANSMISSION_MODE_2K:
4046                 fft_div = 4;
4047                 break;
4048         case TRANSMISSION_MODE_4K:
4049                 fft_div = 2;
4050                 break;
4051         default:
4052         case TRANSMISSION_MODE_8K:
4053                 fft_div = 1;
4054                 break;
4055         }
4056
4057         denom = 0;
4058         for (i = ini_layer; i < end_layer; i++) {
4059                 nsegs = c->layer[i].segment_count;
4060                 if (nsegs == 0 || nsegs > 13)
4061                         continue;
4062
4063                 switch (c->layer[i].modulation) {
4064                 case DQPSK:
4065                 case QPSK:
4066                         bits_per_symbol = 2;
4067                         break;
4068                 case QAM_16:
4069                         bits_per_symbol = 4;
4070                         break;
4071                 default:
4072                 case QAM_64:
4073                         bits_per_symbol = 6;
4074                         break;
4075                 }
4076
4077                 switch (c->layer[i].fec) {
4078                 case FEC_1_2:
4079                         rate_num = 1;
4080                         rate_denum = 2;
4081                         break;
4082                 case FEC_2_3:
4083                         rate_num = 2;
4084                         rate_denum = 3;
4085                         break;
4086                 case FEC_3_4:
4087                         rate_num = 3;
4088                         rate_denum = 4;
4089                         break;
4090                 case FEC_5_6:
4091                         rate_num = 5;
4092                         rate_denum = 6;
4093                         break;
4094                 default:
4095                 case FEC_7_8:
4096                         rate_num = 7;
4097                         rate_denum = 8;
4098                         break;
4099                 }
4100
4101                 interleaving = c->layer[i].interleaving;
4102
4103                 denom += bits_per_symbol * rate_num * fft_div * nsegs * 384;
4104         }
4105
4106         /* If all goes wrong, wait for 1s for the next stats */
4107         if (!denom)
4108                 return 0;
4109
4110         /* Estimate the period for the total bit rate */
4111         time_us = rate_denum * (1008 * 1562500L);
4112         tmp64 = time_us;
4113         do_div(tmp64, guard);
4114         time_us = time_us + tmp64;
4115         time_us += denom / 2;
4116         do_div(time_us, denom);
4117
4118         tmp = 1008 * 96 * interleaving;
4119         time_us += tmp + tmp / guard;
4120
4121         return time_us;
4122 }
4123
4124 static int dib8000_get_stats(struct dvb_frontend *fe, enum fe_status stat)
4125 {
4126         struct dib8000_state *state = fe->demodulator_priv;
4127         struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
4128         int i;
4129         int show_per_stats = 0;
4130         u32 time_us = 0, snr, val;
4131         u64 blocks;
4132         s32 db;
4133         u16 strength;
4134
4135         /* Get Signal strength */
4136         dib8000_read_signal_strength(fe, &strength);
4137         val = strength;
4138         db = interpolate_value(val,
4139                                strength_to_db_table,
4140                                ARRAY_SIZE(strength_to_db_table)) - 131000;
4141         c->strength.stat[0].svalue = db;
4142
4143         /* UCB/BER/CNR measures require lock */
4144         if (!(stat & FE_HAS_LOCK)) {
4145                 c->cnr.len = 1;
4146                 c->block_count.len = 1;
4147                 c->block_error.len = 1;
4148                 c->post_bit_error.len = 1;
4149                 c->post_bit_count.len = 1;
4150                 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
4151                 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
4152                 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
4153                 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
4154                 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
4155                 return 0;
4156         }
4157
4158         /* Check if time for stats was elapsed */
4159         if (time_after(jiffies, state->per_jiffies_stats)) {
4160                 state->per_jiffies_stats = jiffies + msecs_to_jiffies(1000);
4161
4162                 /* Get SNR */
4163                 snr = dib8000_get_snr(fe);
4164                 for (i = 1; i < MAX_NUMBER_OF_FRONTENDS; i++) {
4165                         if (state->fe[i])
4166                                 snr += dib8000_get_snr(state->fe[i]);
4167                 }
4168                 snr = snr >> 16;
4169
4170                 if (snr) {
4171                         snr = 10 * intlog10(snr);
4172                         snr = (1000L * snr) >> 24;
4173                 } else {
4174                         snr = 0;
4175                 }
4176                 c->cnr.stat[0].svalue = snr;
4177                 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
4178
4179                 /* Get UCB measures */
4180                 dib8000_read_unc_blocks(fe, &val);
4181                 if (val < state->init_ucb)
4182                         state->init_ucb += 0x100000000LL;
4183
4184                 c->block_error.stat[0].scale = FE_SCALE_COUNTER;
4185                 c->block_error.stat[0].uvalue = val + state->init_ucb;
4186
4187                 /* Estimate the number of packets based on bitrate */
4188                 if (!time_us)
4189                         time_us = dib8000_get_time_us(fe, -1);
4190
4191                 if (time_us) {
4192                         blocks = 1250000ULL * 1000000ULL;
4193                         do_div(blocks, time_us * 8 * 204);
4194                         c->block_count.stat[0].scale = FE_SCALE_COUNTER;
4195                         c->block_count.stat[0].uvalue += blocks;
4196                 }
4197
4198                 show_per_stats = 1;
4199         }
4200
4201         /* Get post-BER measures */
4202         if (time_after(jiffies, state->ber_jiffies_stats)) {
4203                 time_us = dib8000_get_time_us(fe, -1);
4204                 state->ber_jiffies_stats = jiffies + msecs_to_jiffies((time_us + 500) / 1000);
4205
4206                 dprintk("Next all layers stats available in %u us.\n", time_us);
4207
4208                 dib8000_read_ber(fe, &val);
4209                 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
4210                 c->post_bit_error.stat[0].uvalue += val;
4211
4212                 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
4213                 c->post_bit_count.stat[0].uvalue += 100000000;
4214         }
4215
4216         if (state->revision < 0x8002)
4217                 return 0;
4218
4219         c->block_error.len = 4;
4220         c->post_bit_error.len = 4;
4221         c->post_bit_count.len = 4;
4222
4223         for (i = 0; i < 3; i++) {
4224                 unsigned nsegs = c->layer[i].segment_count;
4225
4226                 if (nsegs == 0 || nsegs > 13)
4227                         continue;
4228
4229                 time_us = 0;
4230
4231                 if (time_after(jiffies, state->ber_jiffies_stats_layer[i])) {
4232                         time_us = dib8000_get_time_us(fe, i);
4233
4234                         state->ber_jiffies_stats_layer[i] = jiffies + msecs_to_jiffies((time_us + 500) / 1000);
4235                         dprintk("Next layer %c  stats will be available in %u us\n",
4236                                 'A' + i, time_us);
4237
4238                         val = dib8000_read_word(state, per_layer_regs[i].ber);
4239                         c->post_bit_error.stat[1 + i].scale = FE_SCALE_COUNTER;
4240                         c->post_bit_error.stat[1 + i].uvalue += val;
4241
4242                         c->post_bit_count.stat[1 + i].scale = FE_SCALE_COUNTER;
4243                         c->post_bit_count.stat[1 + i].uvalue += 100000000;
4244                 }
4245
4246                 if (show_per_stats) {
4247                         val = dib8000_read_word(state, per_layer_regs[i].per);
4248
4249                         c->block_error.stat[1 + i].scale = FE_SCALE_COUNTER;
4250                         c->block_error.stat[1 + i].uvalue += val;
4251
4252                         if (!time_us)
4253                                 time_us = dib8000_get_time_us(fe, i);
4254                         if (time_us) {
4255                                 blocks = 1250000ULL * 1000000ULL;
4256                                 do_div(blocks, time_us * 8 * 204);
4257                                 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
4258                                 c->block_count.stat[0].uvalue += blocks;
4259                         }
4260                 }
4261         }
4262         return 0;
4263 }
4264
4265 static int dib8000_set_slave_frontend(struct dvb_frontend *fe, struct dvb_frontend *fe_slave)
4266 {
4267         struct dib8000_state *state = fe->demodulator_priv;
4268         u8 index_frontend = 1;
4269
4270         while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL))
4271                 index_frontend++;
4272         if (index_frontend < MAX_NUMBER_OF_FRONTENDS) {
4273                 dprintk("set slave fe %p to index %i\n", fe_slave, index_frontend);
4274                 state->fe[index_frontend] = fe_slave;
4275                 return 0;
4276         }
4277
4278         dprintk("too many slave frontend\n");
4279         return -ENOMEM;
4280 }
4281
4282 static struct dvb_frontend *dib8000_get_slave_frontend(struct dvb_frontend *fe, int slave_index)
4283 {
4284         struct dib8000_state *state = fe->demodulator_priv;
4285
4286         if (slave_index >= MAX_NUMBER_OF_FRONTENDS)
4287                 return NULL;
4288         return state->fe[slave_index];
4289 }
4290
4291 static int dib8000_i2c_enumeration(struct i2c_adapter *host, int no_of_demods,
4292                 u8 default_addr, u8 first_addr, u8 is_dib8096p)
4293 {
4294         int k = 0, ret = 0;
4295         u8 new_addr = 0;
4296         struct i2c_device client = {.adap = host };
4297
4298         client.i2c_write_buffer = kzalloc(4, GFP_KERNEL);
4299         if (!client.i2c_write_buffer) {
4300                 dprintk("%s: not enough memory\n", __func__);
4301                 return -ENOMEM;
4302         }
4303         client.i2c_read_buffer = kzalloc(4, GFP_KERNEL);
4304         if (!client.i2c_read_buffer) {
4305                 dprintk("%s: not enough memory\n", __func__);
4306                 ret = -ENOMEM;
4307                 goto error_memory_read;
4308         }
4309         client.i2c_buffer_lock = kzalloc(sizeof(struct mutex), GFP_KERNEL);
4310         if (!client.i2c_buffer_lock) {
4311                 dprintk("%s: not enough memory\n", __func__);
4312                 ret = -ENOMEM;
4313                 goto error_memory_lock;
4314         }
4315         mutex_init(client.i2c_buffer_lock);
4316
4317         for (k = no_of_demods - 1; k >= 0; k--) {
4318                 /* designated i2c address */
4319                 new_addr = first_addr + (k << 1);
4320
4321                 client.addr = new_addr;
4322                 if (!is_dib8096p)
4323                         dib8000_i2c_write16(&client, 1287, 0x0003);     /* sram lead in, rdy */
4324                 if (dib8000_identify(&client) == 0) {
4325                         /* sram lead in, rdy */
4326                         if (!is_dib8096p)
4327                                 dib8000_i2c_write16(&client, 1287, 0x0003);
4328                         client.addr = default_addr;
4329                         if (dib8000_identify(&client) == 0) {
4330                                 dprintk("#%d: not identified\n", k);
4331                                 ret  = -EINVAL;
4332                                 goto error;
4333                         }
4334                 }
4335
4336                 /* start diversity to pull_down div_str - just for i2c-enumeration */
4337                 dib8000_i2c_write16(&client, 1286, (1 << 10) | (4 << 6));
4338
4339                 /* set new i2c address and force divstart */
4340                 dib8000_i2c_write16(&client, 1285, (new_addr << 2) | 0x2);
4341                 client.addr = new_addr;
4342                 dib8000_identify(&client);
4343
4344                 dprintk("IC %d initialized (to i2c_address 0x%x)\n", k, new_addr);
4345         }
4346
4347         for (k = 0; k < no_of_demods; k++) {
4348                 new_addr = first_addr | (k << 1);
4349                 client.addr = new_addr;
4350
4351                 // unforce divstr
4352                 dib8000_i2c_write16(&client, 1285, new_addr << 2);
4353
4354                 /* deactivate div - it was just for i2c-enumeration */
4355                 dib8000_i2c_write16(&client, 1286, 0);
4356         }
4357
4358 error:
4359         kfree(client.i2c_buffer_lock);
4360 error_memory_lock:
4361         kfree(client.i2c_read_buffer);
4362 error_memory_read:
4363         kfree(client.i2c_write_buffer);
4364
4365         return ret;
4366 }
4367
4368 static int dib8000_fe_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings *tune)
4369 {
4370         tune->min_delay_ms = 1000;
4371         tune->step_size = 0;
4372         tune->max_drift = 0;
4373         return 0;
4374 }
4375
4376 static void dib8000_release(struct dvb_frontend *fe)
4377 {
4378         struct dib8000_state *st = fe->demodulator_priv;
4379         u8 index_frontend;
4380
4381         for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (st->fe[index_frontend] != NULL); index_frontend++)
4382                 dvb_frontend_detach(st->fe[index_frontend]);
4383
4384         dibx000_exit_i2c_master(&st->i2c_master);
4385         i2c_del_adapter(&st->dib8096p_tuner_adap);
4386         kfree(st->fe[0]);
4387         kfree(st);
4388 }
4389
4390 static struct i2c_adapter *dib8000_get_i2c_master(struct dvb_frontend *fe, enum dibx000_i2c_interface intf, int gating)
4391 {
4392         struct dib8000_state *st = fe->demodulator_priv;
4393         return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating);
4394 }
4395
4396 static int dib8000_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
4397 {
4398         struct dib8000_state *st = fe->demodulator_priv;
4399         u16 val = dib8000_read_word(st, 299) & 0xffef;
4400         val |= (onoff & 0x1) << 4;
4401
4402         dprintk("pid filter enabled %d\n", onoff);
4403         return dib8000_write_word(st, 299, val);
4404 }
4405
4406 static int dib8000_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
4407 {
4408         struct dib8000_state *st = fe->demodulator_priv;
4409         dprintk("Index %x, PID %d, OnOff %d\n", id, pid, onoff);
4410         return dib8000_write_word(st, 305 + id, onoff ? (1 << 13) | pid : 0);
4411 }
4412
4413 static const struct dvb_frontend_ops dib8000_ops = {
4414         .delsys = { SYS_ISDBT },
4415         .info = {
4416                  .name = "DiBcom 8000 ISDB-T",
4417                  .frequency_min_hz =  44250 * kHz,
4418                  .frequency_max_hz = 867250 * kHz,
4419                  .frequency_stepsize_hz = 62500,
4420                  .caps = FE_CAN_INVERSION_AUTO |
4421                  FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
4422                  FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
4423                  FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
4424                  FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER | FE_CAN_HIERARCHY_AUTO,
4425                  },
4426
4427         .release = dib8000_release,
4428
4429         .init = dib8000_wakeup,
4430         .sleep = dib8000_sleep,
4431
4432         .set_frontend = dib8000_set_frontend,
4433         .get_tune_settings = dib8000_fe_get_tune_settings,
4434         .get_frontend = dib8000_get_frontend,
4435
4436         .read_status = dib8000_read_status,
4437         .read_ber = dib8000_read_ber,
4438         .read_signal_strength = dib8000_read_signal_strength,
4439         .read_snr = dib8000_read_snr,
4440         .read_ucblocks = dib8000_read_unc_blocks,
4441 };
4442
4443 static struct dvb_frontend *dib8000_init(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib8000_config *cfg)
4444 {
4445         struct dvb_frontend *fe;
4446         struct dib8000_state *state;
4447
4448         dprintk("dib8000_init\n");
4449
4450         state = kzalloc(sizeof(struct dib8000_state), GFP_KERNEL);
4451         if (state == NULL)
4452                 return NULL;
4453         fe = kzalloc(sizeof(struct dvb_frontend), GFP_KERNEL);
4454         if (fe == NULL)
4455                 goto error;
4456
4457         memcpy(&state->cfg, cfg, sizeof(struct dib8000_config));
4458         state->i2c.adap = i2c_adap;
4459         state->i2c.addr = i2c_addr;
4460         state->i2c.i2c_write_buffer = state->i2c_write_buffer;
4461         state->i2c.i2c_read_buffer = state->i2c_read_buffer;
4462         mutex_init(&state->i2c_buffer_lock);
4463         state->i2c.i2c_buffer_lock = &state->i2c_buffer_lock;
4464         state->gpio_val = cfg->gpio_val;
4465         state->gpio_dir = cfg->gpio_dir;
4466
4467         /* Ensure the output mode remains at the previous default if it's
4468          * not specifically set by the caller.
4469          */
4470         if ((state->cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (state->cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK))
4471                 state->cfg.output_mode = OUTMODE_MPEG2_FIFO;
4472
4473         state->fe[0] = fe;
4474         fe->demodulator_priv = state;
4475         memcpy(&state->fe[0]->ops, &dib8000_ops, sizeof(struct dvb_frontend_ops));
4476
4477         state->timf_default = cfg->pll->timf;
4478
4479         if (dib8000_identify(&state->i2c) == 0) {
4480                 kfree(fe);
4481                 goto error;
4482         }
4483
4484         dibx000_init_i2c_master(&state->i2c_master, DIB8000, state->i2c.adap, state->i2c.addr);
4485
4486         /* init 8096p tuner adapter */
4487         strncpy(state->dib8096p_tuner_adap.name, "DiB8096P tuner interface",
4488                         sizeof(state->dib8096p_tuner_adap.name));
4489         state->dib8096p_tuner_adap.algo = &dib8096p_tuner_xfer_algo;
4490         state->dib8096p_tuner_adap.algo_data = NULL;
4491         state->dib8096p_tuner_adap.dev.parent = state->i2c.adap->dev.parent;
4492         i2c_set_adapdata(&state->dib8096p_tuner_adap, state);
4493         i2c_add_adapter(&state->dib8096p_tuner_adap);
4494
4495         dib8000_reset(fe);
4496
4497         dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & ~0x60) | (3 << 5));     /* ber_rs_len = 3 */
4498         state->current_demod_bw = 6000;
4499
4500         return fe;
4501
4502 error:
4503         kfree(state);
4504         return NULL;
4505 }
4506
4507 void *dib8000_attach(struct dib8000_ops *ops)
4508 {
4509         if (!ops)
4510                 return NULL;
4511
4512         ops->pwm_agc_reset = dib8000_pwm_agc_reset;
4513         ops->get_dc_power = dib8090p_get_dc_power;
4514         ops->set_gpio = dib8000_set_gpio;
4515         ops->get_slave_frontend = dib8000_get_slave_frontend;
4516         ops->set_tune_state = dib8000_set_tune_state;
4517         ops->pid_filter_ctrl = dib8000_pid_filter_ctrl;
4518         ops->get_adc_power = dib8000_get_adc_power;
4519         ops->update_pll = dib8000_update_pll;
4520         ops->tuner_sleep = dib8096p_tuner_sleep;
4521         ops->get_tune_state = dib8000_get_tune_state;
4522         ops->get_i2c_tuner = dib8096p_get_i2c_tuner;
4523         ops->set_slave_frontend = dib8000_set_slave_frontend;
4524         ops->pid_filter = dib8000_pid_filter;
4525         ops->ctrl_timf = dib8000_ctrl_timf;
4526         ops->init = dib8000_init;
4527         ops->get_i2c_master = dib8000_get_i2c_master;
4528         ops->i2c_enumeration = dib8000_i2c_enumeration;
4529         ops->set_wbd_ref = dib8000_set_wbd_ref;
4530
4531         return ops;
4532 }
4533 EXPORT_SYMBOL(dib8000_attach);
4534
4535 MODULE_AUTHOR("Olivier Grenie <Olivier.Grenie@parrot.com, Patrick Boettcher <patrick.boettcher@posteo.de>");
4536 MODULE_DESCRIPTION("Driver for the DiBcom 8000 ISDB-T demodulator");
4537 MODULE_LICENSE("GPL");