drivers/media/dvb-frontends/si2165.c

   1 /*
   2  *  Driver for Silicon Labs Si2161 DVB-T and Si2165 DVB-C/-T Demodulator
   3  *
   4  *  Copyright (C) 2013-2017 Matthias Schwarzott <zzam@gentoo.org>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  References:
  17  *  http://www.silabs.com/Support%20Documents/TechnicalDocs/Si2165-short.pdf
  18  */
  19
  20 #include <linux/delay.h>
  21 #include <linux/errno.h>
  22 #include <linux/init.h>
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25 #include <linux/string.h>
  26 #include <linux/slab.h>
  27 #include <linux/firmware.h>
  28 #include <linux/regmap.h>
  29
  30 #include <media/dvb_frontend.h>
  31 #include <media/dvb_math.h>
  32 #include "si2165_priv.h"
  33 #include "si2165.h"
  34
  35 /*
  36  * Hauppauge WinTV-HVR-930C-HD B130 / PCTV QuatroStick 521e 1113xx
  37  * uses 16 MHz xtal
  38  *
  39  * Hauppauge WinTV-HVR-930C-HD B131 / PCTV QuatroStick 522e 1114xx
  40  * uses 24 MHz clock provided by tuner
  41  */
  42
  43 struct si2165_state {
  44         struct i2c_client *client;
  45
  46         struct regmap *regmap;
  47
  48         struct dvb_frontend fe;
  49
  50         struct si2165_config config;
  51
  52         u8 chip_revcode;
  53         u8 chip_type;
  54
  55         /* calculated by xtal and div settings */
  56         u32 fvco_hz;
  57         u32 sys_clk;
  58         u32 adc_clk;
  59
  60         /* DVBv3 stats */
  61         u64 ber_prev;
  62
  63         bool has_dvbc;
  64         bool has_dvbt;
  65         bool firmware_loaded;
  66 };
  67
  68 static int si2165_write(struct si2165_state *state, const u16 reg,
  69                         const u8 *src, const int count)
  70 {
  71         int ret;
  72
  73         dev_dbg(&state->client->dev, "i2c write: reg: 0x%04x, data: %*ph\n",
  74                 reg, count, src);
  75
  76         ret = regmap_bulk_write(state->regmap, reg, src, count);
  77
  78         if (ret)
  79                 dev_err(&state->client->dev, "%s: ret == %d\n", __func__, ret);
  80
  81         return ret;
  82 }
  83
  84 static int si2165_read(struct si2165_state *state,
  85                        const u16 reg, u8 *val, const int count)
  86 {
  87         int ret = regmap_bulk_read(state->regmap, reg, val, count);
  88
  89         if (ret) {
  90                 dev_err(&state->client->dev, "%s: error (addr %02x reg %04x error (ret == %i)\n",
  91                         __func__, state->config.i2c_addr, reg, ret);
  92                 return ret;
  93         }
  94
  95         dev_dbg(&state->client->dev, "i2c read: reg: 0x%04x, data: %*ph\n",
  96                 reg, count, val);
  97
  98         return 0;
  99 }
 100
 101 static int si2165_readreg8(struct si2165_state *state,
 102                            const u16 reg, u8 *val)
 103 {
 104         unsigned int val_tmp;
 105         int ret = regmap_read(state->regmap, reg, &val_tmp);
 106         *val = (u8)val_tmp;
 107         dev_dbg(&state->client->dev, "reg read: R(0x%04x)=0x%02x\n", reg, *val);
 108         return ret;
 109 }
 110
 111 static int si2165_readreg16(struct si2165_state *state,
 112                             const u16 reg, u16 *val)
 113 {
 114         u8 buf[2];
 115
 116         int ret = si2165_read(state, reg, buf, 2);
 117         *val = buf[0] | buf[1] << 8;
 118         dev_dbg(&state->client->dev, "reg read: R(0x%04x)=0x%04x\n", reg, *val);
 119         return ret;
 120 }
 121
 122 static int si2165_readreg24(struct si2165_state *state,
 123                             const u16 reg, u32 *val)
 124 {
 125         u8 buf[3];
 126
 127         int ret = si2165_read(state, reg, buf, 3);
 128         *val = buf[0] | buf[1] << 8 | buf[2] << 16;
 129         dev_dbg(&state->client->dev, "reg read: R(0x%04x)=0x%06x\n", reg, *val);
 130         return ret;
 131 }
 132
 133 static int si2165_writereg8(struct si2165_state *state, const u16 reg, u8 val)
 134 {
 135         return regmap_write(state->regmap, reg, val);
 136 }
 137
 138 static int si2165_writereg16(struct si2165_state *state, const u16 reg, u16 val)
 139 {
 140         u8 buf[2] = { val & 0xff, (val >> 8) & 0xff };
 141
 142         return si2165_write(state, reg, buf, 2);
 143 }
 144
 145 static int si2165_writereg24(struct si2165_state *state, const u16 reg, u32 val)
 146 {
 147         u8 buf[3] = { val & 0xff, (val >> 8) & 0xff, (val >> 16) & 0xff };
 148
 149         return si2165_write(state, reg, buf, 3);
 150 }
 151
 152 static int si2165_writereg32(struct si2165_state *state, const u16 reg, u32 val)
 153 {
 154         u8 buf[4] = {
 155                 val & 0xff,
 156                 (val >> 8) & 0xff,
 157                 (val >> 16) & 0xff,
 158                 (val >> 24) & 0xff
 159         };
 160         return si2165_write(state, reg, buf, 4);
 161 }
 162
 163 static int si2165_writereg_mask8(struct si2165_state *state, const u16 reg,
 164                                  u8 val, u8 mask)
 165 {
 166         if (mask != 0xff) {
 167                 u8 tmp;
 168                 int ret = si2165_readreg8(state, reg, &tmp);
 169
 170                 if (ret < 0)
 171                         return ret;
 172
 173                 val &= mask;
 174                 tmp &= ~mask;
 175                 val |= tmp;
 176         }
 177         return si2165_writereg8(state, reg, val);
 178 }
 179
 180 #define REG16(reg, val) \
 181         { (reg), (val) & 0xff }, \
 182         { (reg) + 1, (val) >> 8 & 0xff }
 183 struct si2165_reg_value_pair {
 184         u16 reg;
 185         u8 val;
 186 };
 187
 188 static int si2165_write_reg_list(struct si2165_state *state,
 189                                  const struct si2165_reg_value_pair *regs,
 190                                  int count)
 191 {
 192         int i;
 193         int ret;
 194
 195         for (i = 0; i < count; i++) {
 196                 ret = si2165_writereg8(state, regs[i].reg, regs[i].val);
 197                 if (ret < 0)
 198                         return ret;
 199         }
 200         return 0;
 201 }
 202
 203 static int si2165_get_tune_settings(struct dvb_frontend *fe,
 204                                     struct dvb_frontend_tune_settings *s)
 205 {
 206         s->min_delay_ms = 1000;
 207         return 0;
 208 }
 209
 210 static int si2165_init_pll(struct si2165_state *state)
 211 {
 212         u32 ref_freq_hz = state->config.ref_freq_hz;
 213         u8 divr = 1; /* 1..7 */
 214         u8 divp = 1; /* only 1 or 4 */
 215         u8 divn = 56; /* 1..63 */
 216         u8 divm = 8;
 217         u8 divl = 12;
 218         u8 buf[4];
 219
 220         /*
 221          * hardcoded values can be deleted if calculation is verified
 222          * or it yields the same values as the windows driver
 223          */
 224         switch (ref_freq_hz) {
 225         case 16000000u:
 226                 divn = 56;
 227                 break;
 228         case 24000000u:
 229                 divr = 2;
 230                 divp = 4;
 231                 divn = 19;
 232                 break;
 233         default:
 234                 /* ref_freq / divr must be between 4 and 16 MHz */
 235                 if (ref_freq_hz > 16000000u)
 236                         divr = 2;
 237
 238                 /*
 239                  * now select divn and divp such that
 240                  * fvco is in 1624..1824 MHz
 241                  */
 242                 if (1624000000u * divr > ref_freq_hz * 2u * 63u)
 243                         divp = 4;
 244
 245                 /* is this already correct regarding rounding? */
 246                 divn = 1624000000u * divr / (ref_freq_hz * 2u * divp);
 247                 break;
 248         }
 249
 250         /* adc_clk and sys_clk depend on xtal and pll settings */
 251         state->fvco_hz = ref_freq_hz / divr
 252                         * 2u * divn * divp;
 253         state->adc_clk = state->fvco_hz / (divm * 4u);
 254         state->sys_clk = state->fvco_hz / (divl * 2u);
 255
 256         /* write all 4 pll registers 0x00a0..0x00a3 at once */
 257         buf[0] = divl;
 258         buf[1] = divm;
 259         buf[2] = (divn & 0x3f) | ((divp == 1) ? 0x40 : 0x00) | 0x80;
 260         buf[3] = divr;
 261         return si2165_write(state, REG_PLL_DIVL, buf, 4);
 262 }
 263
 264 static int si2165_adjust_pll_divl(struct si2165_state *state, u8 divl)
 265 {
 266         state->sys_clk = state->fvco_hz / (divl * 2u);
 267         return si2165_writereg8(state, REG_PLL_DIVL, divl);
 268 }
 269
 270 static u32 si2165_get_fe_clk(struct si2165_state *state)
 271 {
 272         /* assume Oversampling mode Ovr4 is used */
 273         return state->adc_clk;
 274 }
 275
 276 static int si2165_wait_init_done(struct si2165_state *state)
 277 {
 278         int ret;
 279         u8 val = 0;
 280         int i;
 281
 282         for (i = 0; i < 3; ++i) {
 283                 ret = si2165_readreg8(state, REG_INIT_DONE, &val);
 284                 if (ret < 0)
 285                         return ret;
 286                 if (val == 0x01)
 287                         return 0;
 288                 usleep_range(1000, 50000);
 289         }
 290         dev_err(&state->client->dev, "init_done was not set\n");
 291         return -EINVAL;
 292 }
 293
 294 static int si2165_upload_firmware_block(struct si2165_state *state,
 295                                         const u8 *data, u32 len, u32 *poffset,
 296                                         u32 block_count)
 297 {
 298         int ret;
 299         u8 buf_ctrl[4] = { 0x00, 0x00, 0x00, 0xc0 };
 300         u8 wordcount;
 301         u32 cur_block = 0;
 302         u32 offset = poffset ? *poffset : 0;
 303
 304         if (len < 4)
 305                 return -EINVAL;
 306         if (len % 4 != 0)
 307                 return -EINVAL;
 308
 309         dev_dbg(&state->client->dev,
 310                 "fw load: %s: called with len=0x%x offset=0x%x blockcount=0x%x\n",
 311                 __func__, len, offset, block_count);
 312         while (offset + 12 <= len && cur_block < block_count) {
 313                 dev_dbg(&state->client->dev,
 314                         "fw load: %s: in while len=0x%x offset=0x%x cur_block=0x%x blockcount=0x%x\n",
 315                         __func__, len, offset, cur_block, block_count);
 316                 wordcount = data[offset];
 317                 if (wordcount < 1 || data[offset + 1] ||
 318                     data[offset + 2] || data[offset + 3]) {
 319                         dev_warn(&state->client->dev,
 320                                  "bad fw data[0..3] = %*ph\n",
 321                                  4, data);
 322                         return -EINVAL;
 323                 }
 324
 325                 if (offset + 8 + wordcount * 4 > len) {
 326                         dev_warn(&state->client->dev,
 327                                  "len is too small for block len=%d, wordcount=%d\n",
 328                                 len, wordcount);
 329                         return -EINVAL;
 330                 }
 331
 332                 buf_ctrl[0] = wordcount - 1;
 333
 334                 ret = si2165_write(state, REG_DCOM_CONTROL_BYTE, buf_ctrl, 4);
 335                 if (ret < 0)
 336                         goto error;
 337                 ret = si2165_write(state, REG_DCOM_ADDR, data + offset + 4, 4);
 338                 if (ret < 0)
 339                         goto error;
 340
 341                 offset += 8;
 342
 343                 while (wordcount > 0) {
 344                         ret = si2165_write(state, REG_DCOM_DATA,
 345                                            data + offset, 4);
 346                         if (ret < 0)
 347                                 goto error;
 348                         wordcount--;
 349                         offset += 4;
 350                 }
 351                 cur_block++;
 352         }
 353
 354         dev_dbg(&state->client->dev,
 355                 "fw load: %s: after while len=0x%x offset=0x%x cur_block=0x%x blockcount=0x%x\n",
 356                 __func__, len, offset, cur_block, block_count);
 357
 358         if (poffset)
 359                 *poffset = offset;
 360
 361         dev_dbg(&state->client->dev,
 362                 "fw load: %s: returned offset=0x%x\n",
 363                 __func__, offset);
 364
 365         return 0;
 366 error:
 367         return ret;
 368 }
 369
 370 static int si2165_upload_firmware(struct si2165_state *state)
 371 {
 372         /* int ret; */
 373         u8 val[3];
 374         u16 val16;
 375         int ret;
 376
 377         const struct firmware *fw = NULL;
 378         u8 *fw_file;
 379         const u8 *data;
 380         u32 len;
 381         u32 offset;
 382         u8 patch_version;
 383         u8 block_count;
 384         u16 crc_expected;
 385
 386         switch (state->chip_revcode) {
 387         case 0x03: /* revision D */
 388                 fw_file = SI2165_FIRMWARE_REV_D;
 389                 break;
 390         default:
 391                 dev_info(&state->client->dev, "no firmware file for revision=%d\n",
 392                          state->chip_revcode);
 393                 return 0;
 394         }
 395
 396         /* request the firmware, this will block and timeout */
 397         ret = reject_firmware(&fw, fw_file, &state->client->dev);
 398         if (ret) {
 399                 dev_warn(&state->client->dev, "firmware file '%s' not found\n",
 400                          fw_file);
 401                 goto error;
 402         }
 403
 404         data = fw->data;
 405         len = fw->size;
 406
 407         dev_info(&state->client->dev, "downloading firmware from file '%s' size=%d\n",
 408                  fw_file, len);
 409
 410         if (len % 4 != 0) {
 411                 dev_warn(&state->client->dev, "firmware size is not multiple of 4\n");
 412                 ret = -EINVAL;
 413                 goto error;
 414         }
 415
 416         /* check header (8 bytes) */
 417         if (len < 8) {
 418                 dev_warn(&state->client->dev, "firmware header is missing\n");
 419                 ret = -EINVAL;
 420                 goto error;
 421         }
 422
 423         if (data[0] != 1 || data[1] != 0) {
 424                 dev_warn(&state->client->dev, "firmware file version is wrong\n");
 425                 ret = -EINVAL;
 426                 goto error;
 427         }
 428
 429         patch_version = data[2];
 430         block_count = data[4];
 431         crc_expected = data[7] << 8 | data[6];
 432
 433         /* start uploading fw */
 434         /* boot/wdog status */
 435         ret = si2165_writereg8(state, REG_WDOG_AND_BOOT, 0x00);
 436         if (ret < 0)
 437                 goto error;
 438         /* reset */
 439         ret = si2165_writereg8(state, REG_RST_ALL, 0x00);
 440         if (ret < 0)
 441                 goto error;
 442         /* boot/wdog status */
 443         ret = si2165_readreg8(state, REG_WDOG_AND_BOOT, val);
 444         if (ret < 0)
 445                 goto error;
 446
 447         /* enable reset on error */
 448         ret = si2165_readreg8(state, REG_EN_RST_ERROR, val);
 449         if (ret < 0)
 450                 goto error;
 451         ret = si2165_readreg8(state, REG_EN_RST_ERROR, val);
 452         if (ret < 0)
 453                 goto error;
 454         ret = si2165_writereg8(state, REG_EN_RST_ERROR, 0x02);
 455         if (ret < 0)
 456                 goto error;
 457
 458         /* start right after the header */
 459         offset = 8;
 460
 461         dev_info(&state->client->dev, "%s: extracted patch_version=0x%02x, block_count=0x%02x, crc_expected=0x%04x\n",
 462                  __func__, patch_version, block_count, crc_expected);
 463
 464         ret = si2165_upload_firmware_block(state, data, len, &offset, 1);
 465         if (ret < 0)
 466                 goto error;
 467
 468         ret = si2165_writereg8(state, REG_PATCH_VERSION, patch_version);
 469         if (ret < 0)
 470                 goto error;
 471
 472         /* reset crc */
 473         ret = si2165_writereg8(state, REG_RST_CRC, 0x01);
 474         if (ret)
 475                 goto error;
 476
 477         ret = si2165_upload_firmware_block(state, data, len,
 478                                            &offset, block_count);
 479         if (ret < 0) {
 480                 dev_err(&state->client->dev,
 481                         "firmware could not be uploaded\n");
 482                 goto error;
 483         }
 484
 485         /* read crc */
 486         ret = si2165_readreg16(state, REG_CRC, &val16);
 487         if (ret)
 488                 goto error;
 489
 490         if (val16 != crc_expected) {
 491                 dev_err(&state->client->dev,
 492                         "firmware crc mismatch %04x != %04x\n",
 493                         val16, crc_expected);
 494                 ret = -EINVAL;
 495                 goto error;
 496         }
 497
 498         ret = si2165_upload_firmware_block(state, data, len, &offset, 5);
 499         if (ret)
 500                 goto error;
 501
 502         if (len != offset) {
 503                 dev_err(&state->client->dev,
 504                         "firmware len mismatch %04x != %04x\n",
 505                         len, offset);
 506                 ret = -EINVAL;
 507                 goto error;
 508         }
 509
 510         /* reset watchdog error register */
 511         ret = si2165_writereg_mask8(state, REG_WDOG_AND_BOOT, 0x02, 0x02);
 512         if (ret < 0)
 513                 goto error;
 514
 515         /* enable reset on error */
 516         ret = si2165_writereg_mask8(state, REG_EN_RST_ERROR, 0x01, 0x01);
 517         if (ret < 0)
 518                 goto error;
 519
 520         dev_info(&state->client->dev, "fw load finished\n");
 521
 522         ret = 0;
 523         state->firmware_loaded = true;
 524 error:
 525         if (fw) {
 526                 release_firmware(fw);
 527                 fw = NULL;
 528         }
 529
 530         return ret;
 531 }
 532
 533 static int si2165_init(struct dvb_frontend *fe)
 534 {
 535         int ret = 0;
 536         struct si2165_state *state = fe->demodulator_priv;
 537         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 538         u8 val;
 539         u8 patch_version = 0x00;
 540
 541         dev_dbg(&state->client->dev, "%s: called\n", __func__);
 542
 543         /* powerup */
 544         ret = si2165_writereg8(state, REG_CHIP_MODE, state->config.chip_mode);
 545         if (ret < 0)
 546                 goto error;
 547         /* dsp_clock_enable */
 548         ret = si2165_writereg8(state, REG_DSP_CLOCK, 0x01);
 549         if (ret < 0)
 550                 goto error;
 551         /* verify chip_mode */
 552         ret = si2165_readreg8(state, REG_CHIP_MODE, &val);
 553         if (ret < 0)
 554                 goto error;
 555         if (val != state->config.chip_mode) {
 556                 dev_err(&state->client->dev, "could not set chip_mode\n");
 557                 return -EINVAL;
 558         }
 559
 560         /* agc */
 561         ret = si2165_writereg8(state, REG_AGC_IF_TRI, 0x00);
 562         if (ret < 0)
 563                 goto error;
 564         ret = si2165_writereg8(state, REG_AGC_IF_SLR, 0x01);
 565         if (ret < 0)
 566                 goto error;
 567         ret = si2165_writereg8(state, REG_AGC2_OUTPUT, 0x00);
 568         if (ret < 0)
 569                 goto error;
 570         ret = si2165_writereg8(state, REG_AGC2_CLKDIV, 0x07);
 571         if (ret < 0)
 572                 goto error;
 573         /* rssi pad */
 574         ret = si2165_writereg8(state, REG_RSSI_PAD_CTRL, 0x00);
 575         if (ret < 0)
 576                 goto error;
 577         ret = si2165_writereg8(state, REG_RSSI_ENABLE, 0x00);
 578         if (ret < 0)
 579                 goto error;
 580
 581         ret = si2165_init_pll(state);
 582         if (ret < 0)
 583                 goto error;
 584
 585         /* enable chip_init */
 586         ret = si2165_writereg8(state, REG_CHIP_INIT, 0x01);
 587         if (ret < 0)
 588                 goto error;
 589         /* set start_init */
 590         ret = si2165_writereg8(state, REG_START_INIT, 0x01);
 591         if (ret < 0)
 592                 goto error;
 593         ret = si2165_wait_init_done(state);
 594         if (ret < 0)
 595                 goto error;
 596
 597         /* disable chip_init */
 598         ret = si2165_writereg8(state, REG_CHIP_INIT, 0x00);
 599         if (ret < 0)
 600                 goto error;
 601
 602         /* ber_pkt - default 65535 */
 603         ret = si2165_writereg16(state, REG_BER_PKT,
 604                                 STATISTICS_PERIOD_PKT_COUNT);
 605         if (ret < 0)
 606                 goto error;
 607
 608         ret = si2165_readreg8(state, REG_PATCH_VERSION, &patch_version);
 609         if (ret < 0)
 610                 goto error;
 611
 612         ret = si2165_writereg8(state, REG_AUTO_RESET, 0x00);
 613         if (ret < 0)
 614                 goto error;
 615
 616         /* dsp_addr_jump */
 617         ret = si2165_writereg32(state, REG_ADDR_JUMP, 0xf4000000);
 618         if (ret < 0)
 619                 goto error;
 620         /* boot/wdog status */
 621         ret = si2165_readreg8(state, REG_WDOG_AND_BOOT, &val);
 622         if (ret < 0)
 623                 goto error;
 624
 625         if (patch_version == 0x00) {
 626                 ret = si2165_upload_firmware(state);
 627                 if (ret < 0)
 628                         goto error;
 629         }
 630
 631         /* ts output config */
 632         ret = si2165_writereg8(state, REG_TS_DATA_MODE, 0x20);
 633         if (ret < 0)
 634                 return ret;
 635         ret = si2165_writereg16(state, REG_TS_TRI, 0x00fe);
 636         if (ret < 0)
 637                 return ret;
 638         ret = si2165_writereg24(state, REG_TS_SLR, 0x555555);
 639         if (ret < 0)
 640                 return ret;
 641         ret = si2165_writereg8(state, REG_TS_CLK_MODE, 0x01);
 642         if (ret < 0)
 643                 return ret;
 644         ret = si2165_writereg8(state, REG_TS_PARALLEL_MODE, 0x00);
 645         if (ret < 0)
 646                 return ret;
 647
 648         c = &state->fe.dtv_property_cache;
 649         c->cnr.len = 1;
 650         c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
 651         c->post_bit_error.len = 1;
 652         c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
 653         c->post_bit_count.len = 1;
 654         c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
 655
 656         return 0;
 657 error:
 658         return ret;
 659 }
 660
 661 static int si2165_sleep(struct dvb_frontend *fe)
 662 {
 663         int ret;
 664         struct si2165_state *state = fe->demodulator_priv;
 665
 666         /* dsp clock disable */
 667         ret = si2165_writereg8(state, REG_DSP_CLOCK, 0x00);
 668         if (ret < 0)
 669                 return ret;
 670         /* chip mode */
 671         ret = si2165_writereg8(state, REG_CHIP_MODE, SI2165_MODE_OFF);
 672         if (ret < 0)
 673                 return ret;
 674         return 0;
 675 }
 676
 677 static int si2165_read_status(struct dvb_frontend *fe, enum fe_status *status)
 678 {
 679         int ret;
 680         u8 u8tmp;
 681         u32 u32tmp;
 682         struct si2165_state *state = fe->demodulator_priv;
 683         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 684         u32 delsys = c->delivery_system;
 685
 686         *status = 0;
 687
 688         switch (delsys) {
 689         case SYS_DVBT:
 690                 /* check fast signal type */
 691                 ret = si2165_readreg8(state, REG_CHECK_SIGNAL, &u8tmp);
 692                 if (ret < 0)
 693                         return ret;
 694                 switch (u8tmp & 0x3) {
 695                 case 0: /* searching */
 696                 case 1: /* nothing */
 697                         break;
 698                 case 2: /* digital signal */
 699                         *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER;
 700                         break;
 701                 }
 702                 break;
 703         case SYS_DVBC_ANNEX_A:
 704                 /* check packet sync lock */
 705                 ret = si2165_readreg8(state, REG_PS_LOCK, &u8tmp);
 706                 if (ret < 0)
 707                         return ret;
 708                 if (u8tmp & 0x01) {
 709                         *status |= FE_HAS_SIGNAL;
 710                         *status |= FE_HAS_CARRIER;
 711                         *status |= FE_HAS_VITERBI;
 712                         *status |= FE_HAS_SYNC;
 713                 }
 714                 break;
 715         }
 716
 717         /* check fec_lock */
 718         ret = si2165_readreg8(state, REG_FEC_LOCK, &u8tmp);
 719         if (ret < 0)
 720                 return ret;
 721         if (u8tmp & 0x01) {
 722                 *status |= FE_HAS_SIGNAL;
 723                 *status |= FE_HAS_CARRIER;
 724                 *status |= FE_HAS_VITERBI;
 725                 *status |= FE_HAS_SYNC;
 726                 *status |= FE_HAS_LOCK;
 727         }
 728
 729         /* CNR */
 730         if (delsys == SYS_DVBC_ANNEX_A && *status & FE_HAS_VITERBI) {
 731                 ret = si2165_readreg24(state, REG_C_N, &u32tmp);
 732                 if (ret < 0)
 733                         return ret;
 734                 /*
 735                  * svalue =
 736                  * 1000 * c_n/dB =
 737                  * 1000 * 10 * log10(2^24 / regval) =
 738                  * 1000 * 10 * (log10(2^24) - log10(regval)) =
 739                  * 1000 * 10 * (intlog10(2^24) - intlog10(regval)) / 2^24
 740                  *
 741                  * intlog10(x) = log10(x) * 2^24
 742                  * intlog10(2^24) = log10(2^24) * 2^24 = 121210686
 743                  */
 744                 u32tmp = (1000 * 10 * (121210686 - (u64)intlog10(u32tmp)))
 745                                 >> 24;
 746                 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
 747                 c->cnr.stat[0].svalue = u32tmp;
 748         } else
 749                 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
 750
 751         /* BER */
 752         if (*status & FE_HAS_VITERBI) {
 753                 if (c->post_bit_error.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
 754                         /* start new sampling period to get rid of old data*/
 755                         ret = si2165_writereg8(state, REG_BER_RST, 0x01);
 756                         if (ret < 0)
 757                                 return ret;
 758
 759                         /* set scale to enter read code on next call */
 760                         c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
 761                         c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
 762                         c->post_bit_error.stat[0].uvalue = 0;
 763                         c->post_bit_count.stat[0].uvalue = 0;
 764
 765                         /*
 766                          * reset DVBv3 value to deliver a good result
 767                          * for the first call
 768                          */
 769                         state->ber_prev = 0;
 770
 771                 } else {
 772                         ret = si2165_readreg8(state, REG_BER_AVAIL, &u8tmp);
 773                         if (ret < 0)
 774                                 return ret;
 775
 776                         if (u8tmp & 1) {
 777                                 u32 biterrcnt;
 778
 779                                 ret = si2165_readreg24(state, REG_BER_BIT,
 780                                                         &biterrcnt);
 781                                 if (ret < 0)
 782                                         return ret;
 783
 784                                 c->post_bit_error.stat[0].uvalue +=
 785                                         biterrcnt;
 786                                 c->post_bit_count.stat[0].uvalue +=
 787                                         STATISTICS_PERIOD_BIT_COUNT;
 788
 789                                 /* start new sampling period */
 790                                 ret = si2165_writereg8(state,
 791                                                         REG_BER_RST, 0x01);
 792                                 if (ret < 0)
 793                                         return ret;
 794
 795                                 dev_dbg(&state->client->dev,
 796                                         "post_bit_error=%u post_bit_count=%u\n",
 797                                         biterrcnt, STATISTICS_PERIOD_BIT_COUNT);
 798                         }
 799                 }
 800         } else {
 801                 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
 802                 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
 803         }
 804
 805         return 0;
 806 }
 807
 808 static int si2165_read_snr(struct dvb_frontend *fe, u16 *snr)
 809 {
 810         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 811
 812         if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL)
 813                 *snr = div_s64(c->cnr.stat[0].svalue, 100);
 814         else
 815                 *snr = 0;
 816         return 0;
 817 }
 818
 819 static int si2165_read_ber(struct dvb_frontend *fe, u32 *ber)
 820 {
 821         struct si2165_state *state = fe->demodulator_priv;
 822         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 823
 824         if (c->post_bit_error.stat[0].scale != FE_SCALE_COUNTER) {
 825                 *ber = 0;
 826                 return 0;
 827         }
 828
 829         *ber = c->post_bit_error.stat[0].uvalue - state->ber_prev;
 830         state->ber_prev = c->post_bit_error.stat[0].uvalue;
 831
 832         return 0;
 833 }
 834
 835 static int si2165_set_oversamp(struct si2165_state *state, u32 dvb_rate)
 836 {
 837         u64 oversamp;
 838         u32 reg_value;
 839
 840         if (!dvb_rate)
 841                 return -EINVAL;
 842
 843         oversamp = si2165_get_fe_clk(state);
 844         oversamp <<= 23;
 845         do_div(oversamp, dvb_rate);
 846         reg_value = oversamp & 0x3fffffff;
 847
 848         dev_dbg(&state->client->dev, "Write oversamp=%#x\n", reg_value);
 849         return si2165_writereg32(state, REG_OVERSAMP, reg_value);
 850 }
 851
 852 static int si2165_set_if_freq_shift(struct si2165_state *state)
 853 {
 854         struct dvb_frontend *fe = &state->fe;
 855         u64 if_freq_shift;
 856         s32 reg_value = 0;
 857         u32 fe_clk = si2165_get_fe_clk(state);
 858         u32 IF = 0;
 859
 860         if (!fe->ops.tuner_ops.get_if_frequency) {
 861                 dev_err(&state->client->dev,
 862                         "Error: get_if_frequency() not defined at tuner. Can't work without it!\n");
 863                 return -EINVAL;
 864         }
 865
 866         if (!fe_clk)
 867                 return -EINVAL;
 868
 869         fe->ops.tuner_ops.get_if_frequency(fe, &IF);
 870         if_freq_shift = IF;
 871         if_freq_shift <<= 29;
 872
 873         do_div(if_freq_shift, fe_clk);
 874         reg_value = (s32)if_freq_shift;
 875
 876         if (state->config.inversion)
 877                 reg_value = -reg_value;
 878
 879         reg_value = reg_value & 0x1fffffff;
 880
 881         /* if_freq_shift, usbdump contained 0x023ee08f; */
 882         return si2165_writereg32(state, REG_IF_FREQ_SHIFT, reg_value);
 883 }
 884
 885 static const struct si2165_reg_value_pair dvbt_regs[] = {
 886         /* standard = DVB-T */
 887         { REG_DVB_STANDARD, 0x01 },
 888         /* impulsive_noise_remover */
 889         { REG_IMPULSIVE_NOISE_REM, 0x01 },
 890         { REG_AUTO_RESET, 0x00 },
 891         /* agc2 */
 892         { REG_AGC2_MIN, 0x41 },
 893         { REG_AGC2_KACQ, 0x0e },
 894         { REG_AGC2_KLOC, 0x10 },
 895         /* agc */
 896         { REG_AGC_UNFREEZE_THR, 0x03 },
 897         { REG_AGC_CRESTF_DBX8, 0x78 },
 898         /* agc */
 899         { REG_AAF_CRESTF_DBX8, 0x78 },
 900         { REG_ACI_CRESTF_DBX8, 0x68 },
 901         /* freq_sync_range */
 902         REG16(REG_FREQ_SYNC_RANGE, 0x0064),
 903         /* gp_reg0 */
 904         { REG_GP_REG0_MSB, 0x00 }
 905 };
 906
 907 static int si2165_set_frontend_dvbt(struct dvb_frontend *fe)
 908 {
 909         int ret;
 910         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
 911         struct si2165_state *state = fe->demodulator_priv;
 912         u32 dvb_rate = 0;
 913         u16 bw10k;
 914         u32 bw_hz = p->bandwidth_hz;
 915
 916         dev_dbg(&state->client->dev, "%s: called\n", __func__);
 917
 918         if (!state->has_dvbt)
 919                 return -EINVAL;
 920
 921         /* no bandwidth auto-detection */
 922         if (bw_hz == 0)
 923                 return -EINVAL;
 924
 925         dvb_rate = bw_hz * 8 / 7;
 926         bw10k = bw_hz / 10000;
 927
 928         ret = si2165_adjust_pll_divl(state, 12);
 929         if (ret < 0)
 930                 return ret;
 931
 932         /* bandwidth in 10KHz steps */
 933         ret = si2165_writereg16(state, REG_T_BANDWIDTH, bw10k);
 934         if (ret < 0)
 935                 return ret;
 936         ret = si2165_set_oversamp(state, dvb_rate);
 937         if (ret < 0)
 938                 return ret;
 939
 940         ret = si2165_write_reg_list(state, dvbt_regs, ARRAY_SIZE(dvbt_regs));
 941         if (ret < 0)
 942                 return ret;
 943
 944         return 0;
 945 }
 946
 947 static const struct si2165_reg_value_pair dvbc_regs[] = {
 948         /* standard = DVB-C */
 949         { REG_DVB_STANDARD, 0x05 },
 950
 951         /* agc2 */
 952         { REG_AGC2_MIN, 0x50 },
 953         { REG_AGC2_KACQ, 0x0e },
 954         { REG_AGC2_KLOC, 0x10 },
 955         /* agc */
 956         { REG_AGC_UNFREEZE_THR, 0x03 },
 957         { REG_AGC_CRESTF_DBX8, 0x68 },
 958         /* agc */
 959         { REG_AAF_CRESTF_DBX8, 0x68 },
 960         { REG_ACI_CRESTF_DBX8, 0x50 },
 961
 962         { REG_EQ_AUTO_CONTROL, 0x0d },
 963
 964         { REG_KP_LOCK, 0x05 },
 965         { REG_CENTRAL_TAP, 0x09 },
 966         REG16(REG_UNKNOWN_350, 0x3e80),
 967
 968         { REG_AUTO_RESET, 0x01 },
 969         REG16(REG_UNKNOWN_24C, 0x0000),
 970         REG16(REG_UNKNOWN_27C, 0x0000),
 971         { REG_SWEEP_STEP, 0x03 },
 972         { REG_AGC_IF_TRI, 0x00 },
 973 };
 974
 975 static int si2165_set_frontend_dvbc(struct dvb_frontend *fe)
 976 {
 977         struct si2165_state *state = fe->demodulator_priv;
 978         int ret;
 979         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
 980         const u32 dvb_rate = p->symbol_rate;
 981         u8 u8tmp;
 982
 983         if (!state->has_dvbc)
 984                 return -EINVAL;
 985
 986         if (dvb_rate == 0)
 987                 return -EINVAL;
 988
 989         ret = si2165_adjust_pll_divl(state, 14);
 990         if (ret < 0)
 991                 return ret;
 992
 993         /* Oversampling */
 994         ret = si2165_set_oversamp(state, dvb_rate);
 995         if (ret < 0)
 996                 return ret;
 997
 998         switch (p->modulation) {
 999         case QPSK:
1000                 u8tmp = 0x3;
1001                 break;
1002         case QAM_16:
1003                 u8tmp = 0x7;
1004                 break;
1005         case QAM_32:
1006                 u8tmp = 0x8;
1007                 break;
1008         case QAM_64:
1009                 u8tmp = 0x9;
1010                 break;
1011         case QAM_128:
1012                 u8tmp = 0xa;
1013                 break;
1014         case QAM_256:
1015         default:
1016                 u8tmp = 0xb;
1017                 break;
1018         }
1019         ret = si2165_writereg8(state, REG_REQ_CONSTELLATION, u8tmp);
1020         if (ret < 0)
1021                 return ret;
1022
1023         ret = si2165_writereg32(state, REG_LOCK_TIMEOUT, 0x007a1200);
1024         if (ret < 0)
1025                 return ret;
1026
1027         ret = si2165_write_reg_list(state, dvbc_regs, ARRAY_SIZE(dvbc_regs));
1028         if (ret < 0)
1029                 return ret;
1030
1031         return 0;
1032 }
1033
1034 static const struct si2165_reg_value_pair adc_rewrite[] = {
1035         { REG_ADC_RI1, 0x46 },
1036         { REG_ADC_RI3, 0x00 },
1037         { REG_ADC_RI5, 0x0a },
1038         { REG_ADC_RI6, 0xff },
1039         { REG_ADC_RI8, 0x70 }
1040 };
1041
1042 static int si2165_set_frontend(struct dvb_frontend *fe)
1043 {
1044         struct si2165_state *state = fe->demodulator_priv;
1045         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1046         u32 delsys = p->delivery_system;
1047         int ret;
1048         u8 val[3];
1049
1050         /* initial setting of if freq shift */
1051         ret = si2165_set_if_freq_shift(state);
1052         if (ret < 0)
1053                 return ret;
1054
1055         switch (delsys) {
1056         case SYS_DVBT:
1057                 ret = si2165_set_frontend_dvbt(fe);
1058                 if (ret < 0)
1059                         return ret;
1060                 break;
1061         case SYS_DVBC_ANNEX_A:
1062                 ret = si2165_set_frontend_dvbc(fe);
1063                 if (ret < 0)
1064                         return ret;
1065                 break;
1066         default:
1067                 return -EINVAL;
1068         }
1069
1070         /* dsp_addr_jump */
1071         ret = si2165_writereg32(state, REG_ADDR_JUMP, 0xf4000000);
1072         if (ret < 0)
1073                 return ret;
1074
1075         if (fe->ops.tuner_ops.set_params)
1076                 fe->ops.tuner_ops.set_params(fe);
1077
1078         /* recalc if_freq_shift if IF might has changed */
1079         ret = si2165_set_if_freq_shift(state);
1080         if (ret < 0)
1081                 return ret;
1082
1083         /* boot/wdog status */
1084         ret = si2165_readreg8(state, REG_WDOG_AND_BOOT, val);
1085         if (ret < 0)
1086                 return ret;
1087         ret = si2165_writereg8(state, REG_WDOG_AND_BOOT, 0x00);
1088         if (ret < 0)
1089                 return ret;
1090
1091         /* reset all */
1092         ret = si2165_writereg8(state, REG_RST_ALL, 0x00);
1093         if (ret < 0)
1094                 return ret;
1095         /* gp_reg0 */
1096         ret = si2165_writereg32(state, REG_GP_REG0_LSB, 0x00000000);
1097         if (ret < 0)
1098                 return ret;
1099
1100         /* write adc values after each reset*/
1101         ret = si2165_write_reg_list(state, adc_rewrite,
1102                                     ARRAY_SIZE(adc_rewrite));
1103         if (ret < 0)
1104                 return ret;
1105
1106         /* start_synchro */
1107         ret = si2165_writereg8(state, REG_START_SYNCHRO, 0x01);
1108         if (ret < 0)
1109                 return ret;
1110         /* boot/wdog status */
1111         ret = si2165_readreg8(state, REG_WDOG_AND_BOOT, val);
1112         if (ret < 0)
1113                 return ret;
1114
1115         return 0;
1116 }
1117
1118 static const struct dvb_frontend_ops si2165_ops = {
1119         .info = {
1120                 .name = "Silicon Labs ",
1121                  /* For DVB-C */
1122                 .symbol_rate_min = 1000000,
1123                 .symbol_rate_max = 7200000,
1124                 /* For DVB-T */
1125                 .frequency_stepsize_hz = 166667,
1126                 .caps = FE_CAN_FEC_1_2 |
1127                         FE_CAN_FEC_2_3 |
1128                         FE_CAN_FEC_3_4 |
1129                         FE_CAN_FEC_5_6 |
1130                         FE_CAN_FEC_7_8 |
1131                         FE_CAN_FEC_AUTO |
1132                         FE_CAN_QPSK |
1133                         FE_CAN_QAM_16 |
1134                         FE_CAN_QAM_32 |
1135                         FE_CAN_QAM_64 |
1136                         FE_CAN_QAM_128 |
1137                         FE_CAN_QAM_256 |
1138                         FE_CAN_GUARD_INTERVAL_AUTO |
1139                         FE_CAN_HIERARCHY_AUTO |
1140                         FE_CAN_MUTE_TS |
1141                         FE_CAN_TRANSMISSION_MODE_AUTO |
1142                         FE_CAN_RECOVER
1143         },
1144
1145         .get_tune_settings = si2165_get_tune_settings,
1146
1147         .init = si2165_init,
1148         .sleep = si2165_sleep,
1149
1150         .set_frontend      = si2165_set_frontend,
1151         .read_status       = si2165_read_status,
1152         .read_snr          = si2165_read_snr,
1153         .read_ber          = si2165_read_ber,
1154 };
1155
1156 static int si2165_probe(struct i2c_client *client,
1157                         const struct i2c_device_id *id)
1158 {
1159         struct si2165_state *state = NULL;
1160         struct si2165_platform_data *pdata = client->dev.platform_data;
1161         int n;
1162         int ret = 0;
1163         u8 val;
1164         char rev_char;
1165         const char *chip_name;
1166         static const struct regmap_config regmap_config = {
1167                 .reg_bits = 16,
1168                 .val_bits = 8,
1169                 .max_register = 0x08ff,
1170         };
1171
1172         /* allocate memory for the internal state */
1173         state = kzalloc(sizeof(*state), GFP_KERNEL);
1174         if (!state) {
1175                 ret = -ENOMEM;
1176                 goto error;
1177         }
1178
1179         /* create regmap */
1180         state->regmap = devm_regmap_init_i2c(client, &regmap_config);
1181         if (IS_ERR(state->regmap)) {
1182                 ret = PTR_ERR(state->regmap);
1183                 goto error;
1184         }
1185
1186         /* setup the state */
1187         state->client = client;
1188         state->config.i2c_addr = client->addr;
1189         state->config.chip_mode = pdata->chip_mode;
1190         state->config.ref_freq_hz = pdata->ref_freq_hz;
1191         state->config.inversion = pdata->inversion;
1192
1193         if (state->config.ref_freq_hz < 4000000 ||
1194             state->config.ref_freq_hz > 27000000) {
1195                 dev_err(&state->client->dev, "ref_freq of %d Hz not supported by this driver\n",
1196                         state->config.ref_freq_hz);
1197                 ret = -EINVAL;
1198                 goto error;
1199         }
1200
1201         /* create dvb_frontend */
1202         memcpy(&state->fe.ops, &si2165_ops,
1203                sizeof(struct dvb_frontend_ops));
1204         state->fe.ops.release = NULL;
1205         state->fe.demodulator_priv = state;
1206         i2c_set_clientdata(client, state);
1207
1208         /* powerup */
1209         ret = si2165_writereg8(state, REG_CHIP_MODE, state->config.chip_mode);
1210         if (ret < 0)
1211                 goto nodev_error;
1212
1213         ret = si2165_readreg8(state, REG_CHIP_MODE, &val);
1214         if (ret < 0)
1215                 goto nodev_error;
1216         if (val != state->config.chip_mode)
1217                 goto nodev_error;
1218
1219         ret = si2165_readreg8(state, REG_CHIP_REVCODE, &state->chip_revcode);
1220         if (ret < 0)
1221                 goto nodev_error;
1222
1223         ret = si2165_readreg8(state, REV_CHIP_TYPE, &state->chip_type);
1224         if (ret < 0)
1225                 goto nodev_error;
1226
1227         /* powerdown */
1228         ret = si2165_writereg8(state, REG_CHIP_MODE, SI2165_MODE_OFF);
1229         if (ret < 0)
1230                 goto nodev_error;
1231
1232         if (state->chip_revcode < 26)
1233                 rev_char = 'A' + state->chip_revcode;
1234         else
1235                 rev_char = '?';
1236
1237         switch (state->chip_type) {
1238         case 0x06:
1239                 chip_name = "Si2161";
1240                 state->has_dvbt = true;
1241                 break;
1242         case 0x07:
1243                 chip_name = "Si2165";
1244                 state->has_dvbt = true;
1245                 state->has_dvbc = true;
1246                 break;
1247         default:
1248                 dev_err(&state->client->dev, "Unsupported Silicon Labs chip (type %d, rev %d)\n",
1249                         state->chip_type, state->chip_revcode);
1250                 goto nodev_error;
1251         }
1252
1253         dev_info(&state->client->dev,
1254                  "Detected Silicon Labs %s-%c (type %d, rev %d)\n",
1255                 chip_name, rev_char, state->chip_type,
1256                 state->chip_revcode);
1257
1258         strlcat(state->fe.ops.info.name, chip_name,
1259                 sizeof(state->fe.ops.info.name));
1260
1261         n = 0;
1262         if (state->has_dvbt) {
1263                 state->fe.ops.delsys[n++] = SYS_DVBT;
1264                 strlcat(state->fe.ops.info.name, " DVB-T",
1265                         sizeof(state->fe.ops.info.name));
1266         }
1267         if (state->has_dvbc) {
1268                 state->fe.ops.delsys[n++] = SYS_DVBC_ANNEX_A;
1269                 strlcat(state->fe.ops.info.name, " DVB-C",
1270                         sizeof(state->fe.ops.info.name));
1271         }
1272
1273         /* return fe pointer */
1274         *pdata->fe = &state->fe;
1275
1276         return 0;
1277
1278 nodev_error:
1279         ret = -ENODEV;
1280 error:
1281         kfree(state);
1282         dev_dbg(&client->dev, "failed=%d\n", ret);
1283         return ret;
1284 }
1285
1286 static int si2165_remove(struct i2c_client *client)
1287 {
1288         struct si2165_state *state = i2c_get_clientdata(client);
1289
1290         dev_dbg(&client->dev, "\n");
1291
1292         kfree(state);
1293         return 0;
1294 }
1295
1296 static const struct i2c_device_id si2165_id_table[] = {
1297         {"si2165", 0},
1298         {}
1299 };
1300 MODULE_DEVICE_TABLE(i2c, si2165_id_table);
1301
1302 static struct i2c_driver si2165_driver = {
1303         .driver = {
1304                 .owner  = THIS_MODULE,
1305                 .name   = "si2165",
1306         },
1307         .probe          = si2165_probe,
1308         .remove         = si2165_remove,
1309         .id_table       = si2165_id_table,
1310 };
1311
1312 module_i2c_driver(si2165_driver);
1313
1314 MODULE_DESCRIPTION("Silicon Labs Si2165 DVB-C/-T Demodulator driver");
1315 MODULE_AUTHOR("Matthias Schwarzott <zzam@gentoo.org>");
1316 MODULE_LICENSE("GPL");
1317 /*(DEBLOBBED)*/