drivers/media/dvb-frontends/stv0367.c

   1 /*
   2  * stv0367.c
   3  *
   4  * Driver for ST STV0367 DVB-T & DVB-C demodulator IC.
   5  *
   6  * Copyright (C) ST Microelectronics.
   7  * Copyright (C) 2010,2011 NetUP Inc.
   8  * Copyright (C) 2010,2011 Igor M. Liplianin <liplianin@netup.ru>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24  */
  25
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/string.h>
  29 #include <linux/slab.h>
  30 #include <linux/i2c.h>
  31
  32 #include "stv0367.h"
  33 #include "stv0367_regs.h"
  34 #include "stv0367_priv.h"
  35
  36 /* Max transfer size done by I2C transfer functions */
  37 #define MAX_XFER_SIZE  64
  38
  39 static int stvdebug;
  40 module_param_named(debug, stvdebug, int, 0644);
  41
  42 static int i2cdebug;
  43 module_param_named(i2c_debug, i2cdebug, int, 0644);
  44
  45 #define dprintk(args...) \
  46         do { \
  47                 if (stvdebug) \
  48                         printk(KERN_DEBUG args); \
  49         } while (0)
  50         /* DVB-C */
  51
  52 struct stv0367cab_state {
  53         enum stv0367_cab_signal_type    state;
  54         u32     mclk;
  55         u32     adc_clk;
  56         s32     search_range;
  57         s32     derot_offset;
  58         /* results */
  59         int locked;                     /* channel found                */
  60         u32 freq_khz;                   /* found frequency (in kHz)     */
  61         u32 symbol_rate;                /* found symbol rate (in Bds)   */
  62         enum fe_spectral_inversion spect_inv; /* Spectrum Inversion     */
  63 };
  64
  65 struct stv0367ter_state {
  66         /* DVB-T */
  67         enum stv0367_ter_signal_type state;
  68         enum stv0367_ter_if_iq_mode if_iq_mode;
  69         enum stv0367_ter_mode mode;/* mode 2K or 8K */
  70         enum fe_guard_interval guard;
  71         enum stv0367_ter_hierarchy hierarchy;
  72         u32 frequency;
  73         enum fe_spectral_inversion sense; /*  current search spectrum */
  74         u8  force; /* force mode/guard */
  75         u8  bw; /* channel width 6, 7 or 8 in MHz */
  76         u8  pBW; /* channel width used during previous lock */
  77         u32 pBER;
  78         u32 pPER;
  79         u32 ucblocks;
  80         s8  echo_pos; /* echo position */
  81         u8  first_lock;
  82         u8  unlock_counter;
  83         u32 agc_val;
  84 };
  85
  86 struct stv0367_state {
  87         struct dvb_frontend fe;
  88         struct i2c_adapter *i2c;
  89         /* config settings */
  90         const struct stv0367_config *config;
  91         u8 chip_id;
  92         /* DVB-C */
  93         struct stv0367cab_state *cab_state;
  94         /* DVB-T */
  95         struct stv0367ter_state *ter_state;
  96 };
  97
  98 struct st_register {
  99         u16     addr;
 100         u8      value;
 101 };
 102
 103 /* values for STV4100 XTAL=30M int clk=53.125M*/
 104 static struct st_register def0367ter[STV0367TER_NBREGS] = {
 105         {R367TER_ID,            0x60},
 106         {R367TER_I2CRPT,        0xa0},
 107         /* {R367TER_I2CRPT,     0x22},*/
 108         {R367TER_TOPCTRL,       0x00},/* for xc5000; was 0x02 */
 109         {R367TER_IOCFG0,        0x40},
 110         {R367TER_DAC0R,         0x00},
 111         {R367TER_IOCFG1,        0x00},
 112         {R367TER_DAC1R,         0x00},
 113         {R367TER_IOCFG2,        0x62},
 114         {R367TER_SDFR,          0x00},
 115         {R367TER_STATUS,        0xf8},
 116         {R367TER_AUX_CLK,       0x0a},
 117         {R367TER_FREESYS1,      0x00},
 118         {R367TER_FREESYS2,      0x00},
 119         {R367TER_FREESYS3,      0x00},
 120         {R367TER_GPIO_CFG,      0x55},
 121         {R367TER_GPIO_CMD,      0x00},
 122         {R367TER_AGC2MAX,       0xff},
 123         {R367TER_AGC2MIN,       0x00},
 124         {R367TER_AGC1MAX,       0xff},
 125         {R367TER_AGC1MIN,       0x00},
 126         {R367TER_AGCR,          0xbc},
 127         {R367TER_AGC2TH,        0x00},
 128         {R367TER_AGC12C,        0x00},
 129         {R367TER_AGCCTRL1,      0x85},
 130         {R367TER_AGCCTRL2,      0x1f},
 131         {R367TER_AGC1VAL1,      0x00},
 132         {R367TER_AGC1VAL2,      0x00},
 133         {R367TER_AGC2VAL1,      0x6f},
 134         {R367TER_AGC2VAL2,      0x05},
 135         {R367TER_AGC2PGA,       0x00},
 136         {R367TER_OVF_RATE1,     0x00},
 137         {R367TER_OVF_RATE2,     0x00},
 138         {R367TER_GAIN_SRC1,     0xaa},/* for xc5000; was 0x2b */
 139         {R367TER_GAIN_SRC2,     0xd6},/* for xc5000; was 0x04 */
 140         {R367TER_INC_DEROT1,    0x55},
 141         {R367TER_INC_DEROT2,    0x55},
 142         {R367TER_PPM_CPAMP_DIR, 0x2c},
 143         {R367TER_PPM_CPAMP_INV, 0x00},
 144         {R367TER_FREESTFE_1,    0x00},
 145         {R367TER_FREESTFE_2,    0x1c},
 146         {R367TER_DCOFFSET,      0x00},
 147         {R367TER_EN_PROCESS,    0x05},
 148         {R367TER_SDI_SMOOTHER,  0x80},
 149         {R367TER_FE_LOOP_OPEN,  0x1c},
 150         {R367TER_FREQOFF1,      0x00},
 151         {R367TER_FREQOFF2,      0x00},
 152         {R367TER_FREQOFF3,      0x00},
 153         {R367TER_TIMOFF1,       0x00},
 154         {R367TER_TIMOFF2,       0x00},
 155         {R367TER_EPQ,           0x02},
 156         {R367TER_EPQAUTO,       0x01},
 157         {R367TER_SYR_UPDATE,    0xf5},
 158         {R367TER_CHPFREE,       0x00},
 159         {R367TER_PPM_STATE_MAC, 0x23},
 160         {R367TER_INR_THRESHOLD, 0xff},
 161         {R367TER_EPQ_TPS_ID_CELL, 0xf9},
 162         {R367TER_EPQ_CFG,       0x00},
 163         {R367TER_EPQ_STATUS,    0x01},
 164         {R367TER_AUTORELOCK,    0x81},
 165         {R367TER_BER_THR_VMSB,  0x00},
 166         {R367TER_BER_THR_MSB,   0x00},
 167         {R367TER_BER_THR_LSB,   0x00},
 168         {R367TER_CCD,           0x83},
 169         {R367TER_SPECTR_CFG,    0x00},
 170         {R367TER_CHC_DUMMY,     0x18},
 171         {R367TER_INC_CTL,       0x88},
 172         {R367TER_INCTHRES_COR1, 0xb4},
 173         {R367TER_INCTHRES_COR2, 0x96},
 174         {R367TER_INCTHRES_DET1, 0x0e},
 175         {R367TER_INCTHRES_DET2, 0x11},
 176         {R367TER_IIR_CELLNB,    0x8d},
 177         {R367TER_IIRCX_COEFF1_MSB, 0x00},
 178         {R367TER_IIRCX_COEFF1_LSB, 0x00},
 179         {R367TER_IIRCX_COEFF2_MSB, 0x09},
 180         {R367TER_IIRCX_COEFF2_LSB, 0x18},
 181         {R367TER_IIRCX_COEFF3_MSB, 0x14},
 182         {R367TER_IIRCX_COEFF3_LSB, 0x9c},
 183         {R367TER_IIRCX_COEFF4_MSB, 0x00},
 184         {R367TER_IIRCX_COEFF4_LSB, 0x00},
 185         {R367TER_IIRCX_COEFF5_MSB, 0x36},
 186         {R367TER_IIRCX_COEFF5_LSB, 0x42},
 187         {R367TER_FEPATH_CFG,    0x00},
 188         {R367TER_PMC1_FUNC,     0x65},
 189         {R367TER_PMC1_FOR,      0x00},
 190         {R367TER_PMC2_FUNC,     0x00},
 191         {R367TER_STATUS_ERR_DA, 0xe0},
 192         {R367TER_DIG_AGC_R,     0xfe},
 193         {R367TER_COMAGC_TARMSB, 0x0b},
 194         {R367TER_COM_AGC_TAR_ENMODE, 0x41},
 195         {R367TER_COM_AGC_CFG,   0x3e},
 196         {R367TER_COM_AGC_GAIN1, 0x39},
 197         {R367TER_AUT_AGC_TARGETMSB, 0x0b},
 198         {R367TER_LOCK_DET_MSB,  0x01},
 199         {R367TER_AGCTAR_LOCK_LSBS, 0x40},
 200         {R367TER_AUT_GAIN_EN,   0xf4},
 201         {R367TER_AUT_CFG,       0xf0},
 202         {R367TER_LOCKN,         0x23},
 203         {R367TER_INT_X_3,       0x00},
 204         {R367TER_INT_X_2,       0x03},
 205         {R367TER_INT_X_1,       0x8d},
 206         {R367TER_INT_X_0,       0xa0},
 207         {R367TER_MIN_ERRX_MSB,  0x00},
 208         {R367TER_COR_CTL,       0x23},
 209         {R367TER_COR_STAT,      0xf6},
 210         {R367TER_COR_INTEN,     0x00},
 211         {R367TER_COR_INTSTAT,   0x3f},
 212         {R367TER_COR_MODEGUARD, 0x03},
 213         {R367TER_AGC_CTL,       0x08},
 214         {R367TER_AGC_MANUAL1,   0x00},
 215         {R367TER_AGC_MANUAL2,   0x00},
 216         {R367TER_AGC_TARG,      0x16},
 217         {R367TER_AGC_GAIN1,     0x53},
 218         {R367TER_AGC_GAIN2,     0x1d},
 219         {R367TER_RESERVED_1,    0x00},
 220         {R367TER_RESERVED_2,    0x00},
 221         {R367TER_RESERVED_3,    0x00},
 222         {R367TER_CAS_CTL,       0x44},
 223         {R367TER_CAS_FREQ,      0xb3},
 224         {R367TER_CAS_DAGCGAIN,  0x12},
 225         {R367TER_SYR_CTL,       0x04},
 226         {R367TER_SYR_STAT,      0x10},
 227         {R367TER_SYR_NCO1,      0x00},
 228         {R367TER_SYR_NCO2,      0x00},
 229         {R367TER_SYR_OFFSET1,   0x00},
 230         {R367TER_SYR_OFFSET2,   0x00},
 231         {R367TER_FFT_CTL,       0x00},
 232         {R367TER_SCR_CTL,       0x70},
 233         {R367TER_PPM_CTL1,      0xf8},
 234         {R367TER_TRL_CTL,       0x14},/* for xc5000; was 0xac */
 235         {R367TER_TRL_NOMRATE1,  0xae},/* for xc5000; was 0x1e */
 236         {R367TER_TRL_NOMRATE2,  0x56},/* for xc5000; was 0x58 */
 237         {R367TER_TRL_TIME1,     0x1d},
 238         {R367TER_TRL_TIME2,     0xfc},
 239         {R367TER_CRL_CTL,       0x24},
 240         {R367TER_CRL_FREQ1,     0xad},
 241         {R367TER_CRL_FREQ2,     0x9d},
 242         {R367TER_CRL_FREQ3,     0xff},
 243         {R367TER_CHC_CTL,       0x01},
 244         {R367TER_CHC_SNR,       0xf0},
 245         {R367TER_BDI_CTL,       0x00},
 246         {R367TER_DMP_CTL,       0x00},
 247         {R367TER_TPS_RCVD1,     0x30},
 248         {R367TER_TPS_RCVD2,     0x02},
 249         {R367TER_TPS_RCVD3,     0x01},
 250         {R367TER_TPS_RCVD4,     0x00},
 251         {R367TER_TPS_ID_CELL1,  0x00},
 252         {R367TER_TPS_ID_CELL2,  0x00},
 253         {R367TER_TPS_RCVD5_SET1, 0x02},
 254         {R367TER_TPS_SET2,      0x02},
 255         {R367TER_TPS_SET3,      0x01},
 256         {R367TER_TPS_CTL,       0x00},
 257         {R367TER_CTL_FFTOSNUM,  0x34},
 258         {R367TER_TESTSELECT,    0x09},
 259         {R367TER_MSC_REV,       0x0a},
 260         {R367TER_PIR_CTL,       0x00},
 261         {R367TER_SNR_CARRIER1,  0xa1},
 262         {R367TER_SNR_CARRIER2,  0x9a},
 263         {R367TER_PPM_CPAMP,     0x2c},
 264         {R367TER_TSM_AP0,       0x00},
 265         {R367TER_TSM_AP1,       0x00},
 266         {R367TER_TSM_AP2 ,      0x00},
 267         {R367TER_TSM_AP3,       0x00},
 268         {R367TER_TSM_AP4,       0x00},
 269         {R367TER_TSM_AP5,       0x00},
 270         {R367TER_TSM_AP6,       0x00},
 271         {R367TER_TSM_AP7,       0x00},
 272         {R367TER_TSTRES,        0x00},
 273         {R367TER_ANACTRL,       0x0D},/* PLL stoped, restart at init!!! */
 274         {R367TER_TSTBUS,        0x00},
 275         {R367TER_TSTRATE,       0x00},
 276         {R367TER_CONSTMODE,     0x01},
 277         {R367TER_CONSTCARR1,    0x00},
 278         {R367TER_CONSTCARR2,    0x00},
 279         {R367TER_ICONSTEL,      0x0a},
 280         {R367TER_QCONSTEL,      0x15},
 281         {R367TER_TSTBISTRES0,   0x00},
 282         {R367TER_TSTBISTRES1,   0x00},
 283         {R367TER_TSTBISTRES2,   0x28},
 284         {R367TER_TSTBISTRES3,   0x00},
 285         {R367TER_RF_AGC1,       0xff},
 286         {R367TER_RF_AGC2,       0x83},
 287         {R367TER_ANADIGCTRL,    0x19},
 288         {R367TER_PLLMDIV,       0x01},/* for xc5000; was 0x0c */
 289         {R367TER_PLLNDIV,       0x06},/* for xc5000; was 0x55 */
 290         {R367TER_PLLSETUP,      0x18},
 291         {R367TER_DUAL_AD12,     0x0C},/* for xc5000 AGC voltage 1.6V */
 292         {R367TER_TSTBIST,       0x00},
 293         {R367TER_PAD_COMP_CTRL, 0x00},
 294         {R367TER_PAD_COMP_WR,   0x00},
 295         {R367TER_PAD_COMP_RD,   0xe0},
 296         {R367TER_SYR_TARGET_FFTADJT_MSB, 0x00},
 297         {R367TER_SYR_TARGET_FFTADJT_LSB, 0x00},
 298         {R367TER_SYR_TARGET_CHCADJT_MSB, 0x00},
 299         {R367TER_SYR_TARGET_CHCADJT_LSB, 0x00},
 300         {R367TER_SYR_FLAG,      0x00},
 301         {R367TER_CRL_TARGET1,   0x00},
 302         {R367TER_CRL_TARGET2,   0x00},
 303         {R367TER_CRL_TARGET3,   0x00},
 304         {R367TER_CRL_TARGET4,   0x00},
 305         {R367TER_CRL_FLAG,      0x00},
 306         {R367TER_TRL_TARGET1,   0x00},
 307         {R367TER_TRL_TARGET2,   0x00},
 308         {R367TER_TRL_CHC,       0x00},
 309         {R367TER_CHC_SNR_TARG,  0x00},
 310         {R367TER_TOP_TRACK,     0x00},
 311         {R367TER_TRACKER_FREE1, 0x00},
 312         {R367TER_ERROR_CRL1,    0x00},
 313         {R367TER_ERROR_CRL2,    0x00},
 314         {R367TER_ERROR_CRL3,    0x00},
 315         {R367TER_ERROR_CRL4,    0x00},
 316         {R367TER_DEC_NCO1,      0x2c},
 317         {R367TER_DEC_NCO2,      0x0f},
 318         {R367TER_DEC_NCO3,      0x20},
 319         {R367TER_SNR,           0xf1},
 320         {R367TER_SYR_FFTADJ1,   0x00},
 321         {R367TER_SYR_FFTADJ2,   0x00},
 322         {R367TER_SYR_CHCADJ1,   0x00},
 323         {R367TER_SYR_CHCADJ2,   0x00},
 324         {R367TER_SYR_OFF,       0x00},
 325         {R367TER_PPM_OFFSET1,   0x00},
 326         {R367TER_PPM_OFFSET2,   0x03},
 327         {R367TER_TRACKER_FREE2, 0x00},
 328         {R367TER_DEBG_LT10,     0x00},
 329         {R367TER_DEBG_LT11,     0x00},
 330         {R367TER_DEBG_LT12,     0x00},
 331         {R367TER_DEBG_LT13,     0x00},
 332         {R367TER_DEBG_LT14,     0x00},
 333         {R367TER_DEBG_LT15,     0x00},
 334         {R367TER_DEBG_LT16,     0x00},
 335         {R367TER_DEBG_LT17,     0x00},
 336         {R367TER_DEBG_LT18,     0x00},
 337         {R367TER_DEBG_LT19,     0x00},
 338         {R367TER_DEBG_LT1A,     0x00},
 339         {R367TER_DEBG_LT1B,     0x00},
 340         {R367TER_DEBG_LT1C,     0x00},
 341         {R367TER_DEBG_LT1D,     0x00},
 342         {R367TER_DEBG_LT1E,     0x00},
 343         {R367TER_DEBG_LT1F,     0x00},
 344         {R367TER_RCCFGH,        0x00},
 345         {R367TER_RCCFGM,        0x00},
 346         {R367TER_RCCFGL,        0x00},
 347         {R367TER_RCINSDELH,     0x00},
 348         {R367TER_RCINSDELM,     0x00},
 349         {R367TER_RCINSDELL,     0x00},
 350         {R367TER_RCSTATUS,      0x00},
 351         {R367TER_RCSPEED,       0x6f},
 352         {R367TER_RCDEBUGM,      0xe7},
 353         {R367TER_RCDEBUGL,      0x9b},
 354         {R367TER_RCOBSCFG,      0x00},
 355         {R367TER_RCOBSM,        0x00},
 356         {R367TER_RCOBSL,        0x00},
 357         {R367TER_RCFECSPY,      0x00},
 358         {R367TER_RCFSPYCFG,     0x00},
 359         {R367TER_RCFSPYDATA,    0x00},
 360         {R367TER_RCFSPYOUT,     0x00},
 361         {R367TER_RCFSTATUS,     0x00},
 362         {R367TER_RCFGOODPACK,   0x00},
 363         {R367TER_RCFPACKCNT,    0x00},
 364         {R367TER_RCFSPYMISC,    0x00},
 365         {R367TER_RCFBERCPT4,    0x00},
 366         {R367TER_RCFBERCPT3,    0x00},
 367         {R367TER_RCFBERCPT2,    0x00},
 368         {R367TER_RCFBERCPT1,    0x00},
 369         {R367TER_RCFBERCPT0,    0x00},
 370         {R367TER_RCFBERERR2,    0x00},
 371         {R367TER_RCFBERERR1,    0x00},
 372         {R367TER_RCFBERERR0,    0x00},
 373         {R367TER_RCFSTATESM,    0x00},
 374         {R367TER_RCFSTATESL,    0x00},
 375         {R367TER_RCFSPYBER,     0x00},
 376         {R367TER_RCFSPYDISTM,   0x00},
 377         {R367TER_RCFSPYDISTL,   0x00},
 378         {R367TER_RCFSPYOBS7,    0x00},
 379         {R367TER_RCFSPYOBS6,    0x00},
 380         {R367TER_RCFSPYOBS5,    0x00},
 381         {R367TER_RCFSPYOBS4,    0x00},
 382         {R367TER_RCFSPYOBS3,    0x00},
 383         {R367TER_RCFSPYOBS2,    0x00},
 384         {R367TER_RCFSPYOBS1,    0x00},
 385         {R367TER_RCFSPYOBS0,    0x00},
 386         {R367TER_TSGENERAL,     0x00},
 387         {R367TER_RC1SPEED,      0x6f},
 388         {R367TER_TSGSTATUS,     0x18},
 389         {R367TER_FECM,          0x01},
 390         {R367TER_VTH12,         0xff},
 391         {R367TER_VTH23,         0xa1},
 392         {R367TER_VTH34,         0x64},
 393         {R367TER_VTH56,         0x40},
 394         {R367TER_VTH67,         0x00},
 395         {R367TER_VTH78,         0x2c},
 396         {R367TER_VITCURPUN,     0x12},
 397         {R367TER_VERROR,        0x01},
 398         {R367TER_PRVIT,         0x3f},
 399         {R367TER_VAVSRVIT,      0x00},
 400         {R367TER_VSTATUSVIT,    0xbd},
 401         {R367TER_VTHINUSE,      0xa1},
 402         {R367TER_KDIV12,        0x20},
 403         {R367TER_KDIV23,        0x40},
 404         {R367TER_KDIV34,        0x20},
 405         {R367TER_KDIV56,        0x30},
 406         {R367TER_KDIV67,        0x00},
 407         {R367TER_KDIV78,        0x30},
 408         {R367TER_SIGPOWER,      0x54},
 409         {R367TER_DEMAPVIT,      0x40},
 410         {R367TER_VITSCALE,      0x00},
 411         {R367TER_FFEC1PRG,      0x00},
 412         {R367TER_FVITCURPUN,    0x12},
 413         {R367TER_FVERROR,       0x01},
 414         {R367TER_FVSTATUSVIT,   0xbd},
 415         {R367TER_DEBUG_LT1,     0x00},
 416         {R367TER_DEBUG_LT2,     0x00},
 417         {R367TER_DEBUG_LT3,     0x00},
 418         {R367TER_TSTSFMET,      0x00},
 419         {R367TER_SELOUT,        0x00},
 420         {R367TER_TSYNC,         0x00},
 421         {R367TER_TSTERR,        0x00},
 422         {R367TER_TSFSYNC,       0x00},
 423         {R367TER_TSTSFERR,      0x00},
 424         {R367TER_TSTTSSF1,      0x01},
 425         {R367TER_TSTTSSF2,      0x1f},
 426         {R367TER_TSTTSSF3,      0x00},
 427         {R367TER_TSTTS1,        0x00},
 428         {R367TER_TSTTS2,        0x1f},
 429         {R367TER_TSTTS3,        0x01},
 430         {R367TER_TSTTS4,        0x00},
 431         {R367TER_TSTTSRC,       0x00},
 432         {R367TER_TSTTSRS,       0x00},
 433         {R367TER_TSSTATEM,      0xb0},
 434         {R367TER_TSSTATEL,      0x40},
 435         {R367TER_TSCFGH,        0xC0},
 436         {R367TER_TSCFGM,        0xc0},/* for xc5000; was 0x00 */
 437         {R367TER_TSCFGL,        0x20},
 438         {R367TER_TSSYNC,        0x00},
 439         {R367TER_TSINSDELH,     0x00},
 440         {R367TER_TSINSDELM,     0x00},
 441         {R367TER_TSINSDELL,     0x00},
 442         {R367TER_TSDIVN,        0x03},
 443         {R367TER_TSDIVPM,       0x00},
 444         {R367TER_TSDIVPL,       0x00},
 445         {R367TER_TSDIVQM,       0x00},
 446         {R367TER_TSDIVQL,       0x00},
 447         {R367TER_TSDILSTKM,     0x00},
 448         {R367TER_TSDILSTKL,     0x00},
 449         {R367TER_TSSPEED,       0x40},/* for xc5000; was 0x6f */
 450         {R367TER_TSSTATUS,      0x81},
 451         {R367TER_TSSTATUS2,     0x6a},
 452         {R367TER_TSBITRATEM,    0x0f},
 453         {R367TER_TSBITRATEL,    0xc6},
 454         {R367TER_TSPACKLENM,    0x00},
 455         {R367TER_TSPACKLENL,    0xfc},
 456         {R367TER_TSBLOCLENM,    0x0a},
 457         {R367TER_TSBLOCLENL,    0x80},
 458         {R367TER_TSDLYH,        0x90},
 459         {R367TER_TSDLYM,        0x68},
 460         {R367TER_TSDLYL,        0x01},
 461         {R367TER_TSNPDAV,       0x00},
 462         {R367TER_TSBUFSTATH,    0x00},
 463         {R367TER_TSBUFSTATM,    0x00},
 464         {R367TER_TSBUFSTATL,    0x00},
 465         {R367TER_TSDEBUGM,      0xcf},
 466         {R367TER_TSDEBUGL,      0x1e},
 467         {R367TER_TSDLYSETH,     0x00},
 468         {R367TER_TSDLYSETM,     0x68},
 469         {R367TER_TSDLYSETL,     0x00},
 470         {R367TER_TSOBSCFG,      0x00},
 471         {R367TER_TSOBSM,        0x47},
 472         {R367TER_TSOBSL,        0x1f},
 473         {R367TER_ERRCTRL1,      0x95},
 474         {R367TER_ERRCNT1H,      0x80},
 475         {R367TER_ERRCNT1M,      0x00},
 476         {R367TER_ERRCNT1L,      0x00},
 477         {R367TER_ERRCTRL2,      0x95},
 478         {R367TER_ERRCNT2H,      0x00},
 479         {R367TER_ERRCNT2M,      0x00},
 480         {R367TER_ERRCNT2L,      0x00},
 481         {R367TER_FECSPY,        0x88},
 482         {R367TER_FSPYCFG,       0x2c},
 483         {R367TER_FSPYDATA,      0x3a},
 484         {R367TER_FSPYOUT,       0x06},
 485         {R367TER_FSTATUS,       0x61},
 486         {R367TER_FGOODPACK,     0xff},
 487         {R367TER_FPACKCNT,      0xff},
 488         {R367TER_FSPYMISC,      0x66},
 489         {R367TER_FBERCPT4,      0x00},
 490         {R367TER_FBERCPT3,      0x00},
 491         {R367TER_FBERCPT2,      0x36},
 492         {R367TER_FBERCPT1,      0x36},
 493         {R367TER_FBERCPT0,      0x14},
 494         {R367TER_FBERERR2,      0x00},
 495         {R367TER_FBERERR1,      0x03},
 496         {R367TER_FBERERR0,      0x28},
 497         {R367TER_FSTATESM,      0x00},
 498         {R367TER_FSTATESL,      0x02},
 499         {R367TER_FSPYBER,       0x00},
 500         {R367TER_FSPYDISTM,     0x01},
 501         {R367TER_FSPYDISTL,     0x9f},
 502         {R367TER_FSPYOBS7,      0xc9},
 503         {R367TER_FSPYOBS6,      0x99},
 504         {R367TER_FSPYOBS5,      0x08},
 505         {R367TER_FSPYOBS4,      0xec},
 506         {R367TER_FSPYOBS3,      0x01},
 507         {R367TER_FSPYOBS2,      0x0f},
 508         {R367TER_FSPYOBS1,      0xf5},
 509         {R367TER_FSPYOBS0,      0x08},
 510         {R367TER_SFDEMAP,       0x40},
 511         {R367TER_SFERROR,       0x00},
 512         {R367TER_SFAVSR,        0x30},
 513         {R367TER_SFECSTATUS,    0xcc},
 514         {R367TER_SFKDIV12,      0x20},
 515         {R367TER_SFKDIV23,      0x40},
 516         {R367TER_SFKDIV34,      0x20},
 517         {R367TER_SFKDIV56,      0x20},
 518         {R367TER_SFKDIV67,      0x00},
 519         {R367TER_SFKDIV78,      0x20},
 520         {R367TER_SFDILSTKM,     0x00},
 521         {R367TER_SFDILSTKL,     0x00},
 522         {R367TER_SFSTATUS,      0xb5},
 523         {R367TER_SFDLYH,        0x90},
 524         {R367TER_SFDLYM,        0x60},
 525         {R367TER_SFDLYL,        0x01},
 526         {R367TER_SFDLYSETH,     0xc0},
 527         {R367TER_SFDLYSETM,     0x60},
 528         {R367TER_SFDLYSETL,     0x00},
 529         {R367TER_SFOBSCFG,      0x00},
 530         {R367TER_SFOBSM,        0x47},
 531         {R367TER_SFOBSL,        0x05},
 532         {R367TER_SFECINFO,      0x40},
 533         {R367TER_SFERRCTRL,     0x74},
 534         {R367TER_SFERRCNTH,     0x80},
 535         {R367TER_SFERRCNTM ,    0x00},
 536         {R367TER_SFERRCNTL,     0x00},
 537         {R367TER_SYMBRATEM,     0x2f},
 538         {R367TER_SYMBRATEL,     0x50},
 539         {R367TER_SYMBSTATUS,    0x7f},
 540         {R367TER_SYMBCFG,       0x00},
 541         {R367TER_SYMBFIFOM,     0xf4},
 542         {R367TER_SYMBFIFOL,     0x0d},
 543         {R367TER_SYMBOFFSM,     0xf0},
 544         {R367TER_SYMBOFFSL,     0x2d},
 545         {R367TER_DEBUG_LT4,     0x00},
 546         {R367TER_DEBUG_LT5,     0x00},
 547         {R367TER_DEBUG_LT6,     0x00},
 548         {R367TER_DEBUG_LT7,     0x00},
 549         {R367TER_DEBUG_LT8,     0x00},
 550         {R367TER_DEBUG_LT9,     0x00},
 551 };
 552
 553 #define RF_LOOKUP_TABLE_SIZE  31
 554 #define RF_LOOKUP_TABLE2_SIZE 16
 555 /* RF Level (for RF AGC->AGC1) Lookup Table, depends on the board and tuner.*/
 556 static const s32 stv0367cab_RF_LookUp1[RF_LOOKUP_TABLE_SIZE][RF_LOOKUP_TABLE_SIZE] = {
 557         {/*AGC1*/
 558                 48, 50, 51, 53, 54, 56, 57, 58, 60, 61, 62, 63,
 559                 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,
 560                 76, 77, 78, 80, 83, 85, 88,
 561         }, {/*RF(dbm)*/
 562                 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
 563                 34, 35, 36, 37, 38, 39, 41, 42, 43, 44, 46, 47,
 564                 49, 50, 52, 53, 54, 55, 56,
 565         }
 566 };
 567 /* RF Level (for IF AGC->AGC2) Lookup Table, depends on the board and tuner.*/
 568 static const s32 stv0367cab_RF_LookUp2[RF_LOOKUP_TABLE2_SIZE][RF_LOOKUP_TABLE2_SIZE] = {
 569         {/*AGC2*/
 570                 28, 29, 31, 32, 34, 35, 36, 37,
 571                 38, 39, 40, 41, 42, 43, 44, 45,
 572         }, {/*RF(dbm)*/
 573                 57, 58, 59, 60, 61, 62, 63, 64,
 574                 65, 66, 67, 68, 69, 70, 71, 72,
 575         }
 576 };
 577
 578 static struct st_register def0367cab[STV0367CAB_NBREGS] = {
 579         {R367CAB_ID,            0x60},
 580         {R367CAB_I2CRPT,        0xa0},
 581         /*{R367CAB_I2CRPT,      0x22},*/
 582         {R367CAB_TOPCTRL,       0x10},
 583         {R367CAB_IOCFG0,        0x80},
 584         {R367CAB_DAC0R,         0x00},
 585         {R367CAB_IOCFG1,        0x00},
 586         {R367CAB_DAC1R,         0x00},
 587         {R367CAB_IOCFG2,        0x00},
 588         {R367CAB_SDFR,          0x00},
 589         {R367CAB_AUX_CLK,       0x00},
 590         {R367CAB_FREESYS1,      0x00},
 591         {R367CAB_FREESYS2,      0x00},
 592         {R367CAB_FREESYS3,      0x00},
 593         {R367CAB_GPIO_CFG,      0x55},
 594         {R367CAB_GPIO_CMD,      0x01},
 595         {R367CAB_TSTRES,        0x00},
 596         {R367CAB_ANACTRL,       0x0d},/* was 0x00 need to check - I.M.L.*/
 597         {R367CAB_TSTBUS,        0x00},
 598         {R367CAB_RF_AGC1,       0xea},
 599         {R367CAB_RF_AGC2,       0x82},
 600         {R367CAB_ANADIGCTRL,    0x0b},
 601         {R367CAB_PLLMDIV,       0x01},
 602         {R367CAB_PLLNDIV,       0x08},
 603         {R367CAB_PLLSETUP,      0x18},
 604         {R367CAB_DUAL_AD12,     0x0C}, /* for xc5000 AGC voltage 1.6V */
 605         {R367CAB_TSTBIST,       0x00},
 606         {R367CAB_CTRL_1,        0x00},
 607         {R367CAB_CTRL_2,        0x03},
 608         {R367CAB_IT_STATUS1,    0x2b},
 609         {R367CAB_IT_STATUS2,    0x08},
 610         {R367CAB_IT_EN1,        0x00},
 611         {R367CAB_IT_EN2,        0x00},
 612         {R367CAB_CTRL_STATUS,   0x04},
 613         {R367CAB_TEST_CTL,      0x00},
 614         {R367CAB_AGC_CTL,       0x73},
 615         {R367CAB_AGC_IF_CFG,    0x50},
 616         {R367CAB_AGC_RF_CFG,    0x00},
 617         {R367CAB_AGC_PWM_CFG,   0x03},
 618         {R367CAB_AGC_PWR_REF_L, 0x5a},
 619         {R367CAB_AGC_PWR_REF_H, 0x00},
 620         {R367CAB_AGC_RF_TH_L,   0xff},
 621         {R367CAB_AGC_RF_TH_H,   0x07},
 622         {R367CAB_AGC_IF_LTH_L,  0x00},
 623         {R367CAB_AGC_IF_LTH_H,  0x08},
 624         {R367CAB_AGC_IF_HTH_L,  0xff},
 625         {R367CAB_AGC_IF_HTH_H,  0x07},
 626         {R367CAB_AGC_PWR_RD_L,  0xa0},
 627         {R367CAB_AGC_PWR_RD_M,  0xe9},
 628         {R367CAB_AGC_PWR_RD_H,  0x03},
 629         {R367CAB_AGC_PWM_IFCMD_L,       0xe4},
 630         {R367CAB_AGC_PWM_IFCMD_H,       0x00},
 631         {R367CAB_AGC_PWM_RFCMD_L,       0xff},
 632         {R367CAB_AGC_PWM_RFCMD_H,       0x07},
 633         {R367CAB_IQDEM_CFG,     0x01},
 634         {R367CAB_MIX_NCO_LL,    0x22},
 635         {R367CAB_MIX_NCO_HL,    0x96},
 636         {R367CAB_MIX_NCO_HH,    0x55},
 637         {R367CAB_SRC_NCO_LL,    0xff},
 638         {R367CAB_SRC_NCO_LH,    0x0c},
 639         {R367CAB_SRC_NCO_HL,    0xf5},
 640         {R367CAB_SRC_NCO_HH,    0x20},
 641         {R367CAB_IQDEM_GAIN_SRC_L,      0x06},
 642         {R367CAB_IQDEM_GAIN_SRC_H,      0x01},
 643         {R367CAB_IQDEM_DCRM_CFG_LL,     0xfe},
 644         {R367CAB_IQDEM_DCRM_CFG_LH,     0xff},
 645         {R367CAB_IQDEM_DCRM_CFG_HL,     0x0f},
 646         {R367CAB_IQDEM_DCRM_CFG_HH,     0x00},
 647         {R367CAB_IQDEM_ADJ_COEFF0,      0x34},
 648         {R367CAB_IQDEM_ADJ_COEFF1,      0xae},
 649         {R367CAB_IQDEM_ADJ_COEFF2,      0x46},
 650         {R367CAB_IQDEM_ADJ_COEFF3,      0x77},
 651         {R367CAB_IQDEM_ADJ_COEFF4,      0x96},
 652         {R367CAB_IQDEM_ADJ_COEFF5,      0x69},
 653         {R367CAB_IQDEM_ADJ_COEFF6,      0xc7},
 654         {R367CAB_IQDEM_ADJ_COEFF7,      0x01},
 655         {R367CAB_IQDEM_ADJ_EN,  0x04},
 656         {R367CAB_IQDEM_ADJ_AGC_REF,     0x94},
 657         {R367CAB_ALLPASSFILT1,  0xc9},
 658         {R367CAB_ALLPASSFILT2,  0x2d},
 659         {R367CAB_ALLPASSFILT3,  0xa3},
 660         {R367CAB_ALLPASSFILT4,  0xfb},
 661         {R367CAB_ALLPASSFILT5,  0xf6},
 662         {R367CAB_ALLPASSFILT6,  0x45},
 663         {R367CAB_ALLPASSFILT7,  0x6f},
 664         {R367CAB_ALLPASSFILT8,  0x7e},
 665         {R367CAB_ALLPASSFILT9,  0x05},
 666         {R367CAB_ALLPASSFILT10, 0x0a},
 667         {R367CAB_ALLPASSFILT11, 0x51},
 668         {R367CAB_TRL_AGC_CFG,   0x20},
 669         {R367CAB_TRL_LPF_CFG,   0x28},
 670         {R367CAB_TRL_LPF_ACQ_GAIN,      0x44},
 671         {R367CAB_TRL_LPF_TRK_GAIN,      0x22},
 672         {R367CAB_TRL_LPF_OUT_GAIN,      0x03},
 673         {R367CAB_TRL_LOCKDET_LTH,       0x04},
 674         {R367CAB_TRL_LOCKDET_HTH,       0x11},
 675         {R367CAB_TRL_LOCKDET_TRGVAL,    0x20},
 676         {R367CAB_IQ_QAM,        0x01},
 677         {R367CAB_FSM_STATE,     0xa0},
 678         {R367CAB_FSM_CTL,       0x08},
 679         {R367CAB_FSM_STS,       0x0c},
 680         {R367CAB_FSM_SNR0_HTH,  0x00},
 681         {R367CAB_FSM_SNR1_HTH,  0x00},
 682         {R367CAB_FSM_SNR2_HTH,  0x23},/* 0x00 */
 683         {R367CAB_FSM_SNR0_LTH,  0x00},
 684         {R367CAB_FSM_SNR1_LTH,  0x00},
 685         {R367CAB_FSM_EQA1_HTH,  0x00},
 686         {R367CAB_FSM_TEMPO,     0x32},
 687         {R367CAB_FSM_CONFIG,    0x03},
 688         {R367CAB_EQU_I_TESTTAP_L,       0x11},
 689         {R367CAB_EQU_I_TESTTAP_M,       0x00},
 690         {R367CAB_EQU_I_TESTTAP_H,       0x00},
 691         {R367CAB_EQU_TESTAP_CFG,        0x00},
 692         {R367CAB_EQU_Q_TESTTAP_L,       0xff},
 693         {R367CAB_EQU_Q_TESTTAP_M,       0x00},
 694         {R367CAB_EQU_Q_TESTTAP_H,       0x00},
 695         {R367CAB_EQU_TAP_CTRL,  0x00},
 696         {R367CAB_EQU_CTR_CRL_CONTROL_L, 0x11},
 697         {R367CAB_EQU_CTR_CRL_CONTROL_H, 0x05},
 698         {R367CAB_EQU_CTR_HIPOW_L,       0x00},
 699         {R367CAB_EQU_CTR_HIPOW_H,       0x00},
 700         {R367CAB_EQU_I_EQU_LO,  0xef},
 701         {R367CAB_EQU_I_EQU_HI,  0x00},
 702         {R367CAB_EQU_Q_EQU_LO,  0xee},
 703         {R367CAB_EQU_Q_EQU_HI,  0x00},
 704         {R367CAB_EQU_MAPPER,    0xc5},
 705         {R367CAB_EQU_SWEEP_RATE,        0x80},
 706         {R367CAB_EQU_SNR_LO,    0x64},
 707         {R367CAB_EQU_SNR_HI,    0x03},
 708         {R367CAB_EQU_GAMMA_LO,  0x00},
 709         {R367CAB_EQU_GAMMA_HI,  0x00},
 710         {R367CAB_EQU_ERR_GAIN,  0x36},
 711         {R367CAB_EQU_RADIUS,    0xaa},
 712         {R367CAB_EQU_FFE_MAINTAP,       0x00},
 713         {R367CAB_EQU_FFE_LEAKAGE,       0x63},
 714         {R367CAB_EQU_FFE_MAINTAP_POS,   0xdf},
 715         {R367CAB_EQU_GAIN_WIDE, 0x88},
 716         {R367CAB_EQU_GAIN_NARROW,       0x41},
 717         {R367CAB_EQU_CTR_LPF_GAIN,      0xd1},
 718         {R367CAB_EQU_CRL_LPF_GAIN,      0xa7},
 719         {R367CAB_EQU_GLOBAL_GAIN,       0x06},
 720         {R367CAB_EQU_CRL_LD_SEN,        0x85},
 721         {R367CAB_EQU_CRL_LD_VAL,        0xe2},
 722         {R367CAB_EQU_CRL_TFR,   0x20},
 723         {R367CAB_EQU_CRL_BISTH_LO,      0x00},
 724         {R367CAB_EQU_CRL_BISTH_HI,      0x00},
 725         {R367CAB_EQU_SWEEP_RANGE_LO,    0x00},
 726         {R367CAB_EQU_SWEEP_RANGE_HI,    0x00},
 727         {R367CAB_EQU_CRL_LIMITER,       0x40},
 728         {R367CAB_EQU_MODULUS_MAP,       0x90},
 729         {R367CAB_EQU_PNT_GAIN,  0xa7},
 730         {R367CAB_FEC_AC_CTR_0,  0x16},
 731         {R367CAB_FEC_AC_CTR_1,  0x0b},
 732         {R367CAB_FEC_AC_CTR_2,  0x88},
 733         {R367CAB_FEC_AC_CTR_3,  0x02},
 734         {R367CAB_FEC_STATUS,    0x12},
 735         {R367CAB_RS_COUNTER_0,  0x7d},
 736         {R367CAB_RS_COUNTER_1,  0xd0},
 737         {R367CAB_RS_COUNTER_2,  0x19},
 738         {R367CAB_RS_COUNTER_3,  0x0b},
 739         {R367CAB_RS_COUNTER_4,  0xa3},
 740         {R367CAB_RS_COUNTER_5,  0x00},
 741         {R367CAB_BERT_0,        0x01},
 742         {R367CAB_BERT_1,        0x25},
 743         {R367CAB_BERT_2,        0x41},
 744         {R367CAB_BERT_3,        0x39},
 745         {R367CAB_OUTFORMAT_0,   0xc2},
 746         {R367CAB_OUTFORMAT_1,   0x22},
 747         {R367CAB_SMOOTHER_2,    0x28},
 748         {R367CAB_TSMF_CTRL_0,   0x01},
 749         {R367CAB_TSMF_CTRL_1,   0xc6},
 750         {R367CAB_TSMF_CTRL_3,   0x43},
 751         {R367CAB_TS_ON_ID_0,    0x00},
 752         {R367CAB_TS_ON_ID_1,    0x00},
 753         {R367CAB_TS_ON_ID_2,    0x00},
 754         {R367CAB_TS_ON_ID_3,    0x00},
 755         {R367CAB_RE_STATUS_0,   0x00},
 756         {R367CAB_RE_STATUS_1,   0x00},
 757         {R367CAB_RE_STATUS_2,   0x00},
 758         {R367CAB_RE_STATUS_3,   0x00},
 759         {R367CAB_TS_STATUS_0,   0x00},
 760         {R367CAB_TS_STATUS_1,   0x00},
 761         {R367CAB_TS_STATUS_2,   0xa0},
 762         {R367CAB_TS_STATUS_3,   0x00},
 763         {R367CAB_T_O_ID_0,      0x00},
 764         {R367CAB_T_O_ID_1,      0x00},
 765         {R367CAB_T_O_ID_2,      0x00},
 766         {R367CAB_T_O_ID_3,      0x00},
 767 };
 768
 769 static
 770 int stv0367_writeregs(struct stv0367_state *state, u16 reg, u8 *data, int len)
 771 {
 772         u8 buf[MAX_XFER_SIZE];
 773         struct i2c_msg msg = {
 774                 .addr = state->config->demod_address,
 775                 .flags = 0,
 776                 .buf = buf,
 777                 .len = len + 2
 778         };
 779         int ret;
 780
 781         if (2 + len > sizeof(buf)) {
 782                 printk(KERN_WARNING
 783                        "%s: i2c wr reg=%04x: len=%d is too big!\n",
 784                        KBUILD_MODNAME, reg, len);
 785                 return -EINVAL;
 786         }
 787
 788
 789         buf[0] = MSB(reg);
 790         buf[1] = LSB(reg);
 791         memcpy(buf + 2, data, len);
 792
 793         if (i2cdebug)
 794                 printk(KERN_DEBUG "%s: [%02x] %02x: %02x\n", __func__,
 795                         state->config->demod_address, reg, buf[2]);
 796
 797         ret = i2c_transfer(state->i2c, &msg, 1);
 798         if (ret != 1)
 799                 printk(KERN_ERR "%s: i2c write error! ([%02x] %02x: %02x)\n",
 800                         __func__, state->config->demod_address, reg, buf[2]);
 801
 802         return (ret != 1) ? -EREMOTEIO : 0;
 803 }
 804
 805 static int stv0367_writereg(struct stv0367_state *state, u16 reg, u8 data)
 806 {
 807         u8 tmp = data; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
 808
 809         return stv0367_writeregs(state, reg, &tmp, 1);
 810 }
 811
 812 static u8 stv0367_readreg(struct stv0367_state *state, u16 reg)
 813 {
 814         u8 b0[] = { 0, 0 };
 815         u8 b1[] = { 0 };
 816         struct i2c_msg msg[] = {
 817                 {
 818                         .addr = state->config->demod_address,
 819                         .flags = 0,
 820                         .buf = b0,
 821                         .len = 2
 822                 }, {
 823                         .addr = state->config->demod_address,
 824                         .flags = I2C_M_RD,
 825                         .buf = b1,
 826                         .len = 1
 827                 }
 828         };
 829         int ret;
 830
 831         b0[0] = MSB(reg);
 832         b0[1] = LSB(reg);
 833
 834         ret = i2c_transfer(state->i2c, msg, 2);
 835         if (ret != 2)
 836                 printk(KERN_ERR "%s: i2c read error ([%02x] %02x: %02x)\n",
 837                         __func__, state->config->demod_address, reg, b1[0]);
 838
 839         if (i2cdebug)
 840                 printk(KERN_DEBUG "%s: [%02x] %02x: %02x\n", __func__,
 841                         state->config->demod_address, reg, b1[0]);
 842
 843         return b1[0];
 844 }
 845
 846 static void extract_mask_pos(u32 label, u8 *mask, u8 *pos)
 847 {
 848         u8 position = 0, i = 0;
 849
 850         (*mask) = label & 0xff;
 851
 852         while ((position == 0) && (i < 8)) {
 853                 position = ((*mask) >> i) & 0x01;
 854                 i++;
 855         }
 856
 857         (*pos) = (i - 1);
 858 }
 859
 860 static void stv0367_writebits(struct stv0367_state *state, u32 label, u8 val)
 861 {
 862         u8 reg, mask, pos;
 863
 864         reg = stv0367_readreg(state, (label >> 16) & 0xffff);
 865         extract_mask_pos(label, &mask, &pos);
 866
 867         val = mask & (val << pos);
 868
 869         reg = (reg & (~mask)) | val;
 870         stv0367_writereg(state, (label >> 16) & 0xffff, reg);
 871
 872 }
 873
 874 static void stv0367_setbits(u8 *reg, u32 label, u8 val)
 875 {
 876         u8 mask, pos;
 877
 878         extract_mask_pos(label, &mask, &pos);
 879
 880         val = mask & (val << pos);
 881
 882         (*reg) = ((*reg) & (~mask)) | val;
 883 }
 884
 885 static u8 stv0367_readbits(struct stv0367_state *state, u32 label)
 886 {
 887         u8 val = 0xff;
 888         u8 mask, pos;
 889
 890         extract_mask_pos(label, &mask, &pos);
 891
 892         val = stv0367_readreg(state, label >> 16);
 893         val = (val & mask) >> pos;
 894
 895         return val;
 896 }
 897
 898 #if 0 /* Currently, unused */
 899 static u8 stv0367_getbits(u8 reg, u32 label)
 900 {
 901         u8 mask, pos;
 902
 903         extract_mask_pos(label, &mask, &pos);
 904
 905         return (reg & mask) >> pos;
 906 }
 907 #endif
 908 static int stv0367ter_gate_ctrl(struct dvb_frontend *fe, int enable)
 909 {
 910         struct stv0367_state *state = fe->demodulator_priv;
 911         u8 tmp = stv0367_readreg(state, R367TER_I2CRPT);
 912
 913         dprintk("%s:\n", __func__);
 914
 915         if (enable) {
 916                 stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 0);
 917                 stv0367_setbits(&tmp, F367TER_I2CT_ON, 1);
 918         } else {
 919                 stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 1);
 920                 stv0367_setbits(&tmp, F367TER_I2CT_ON, 0);
 921         }
 922
 923         stv0367_writereg(state, R367TER_I2CRPT, tmp);
 924
 925         return 0;
 926 }
 927
 928 static u32 stv0367_get_tuner_freq(struct dvb_frontend *fe)
 929 {
 930         struct dvb_frontend_ops *frontend_ops = &fe->ops;
 931         struct dvb_tuner_ops    *tuner_ops = &frontend_ops->tuner_ops;
 932         u32 freq = 0;
 933         int err = 0;
 934
 935         dprintk("%s:\n", __func__);
 936
 937         if (tuner_ops->get_frequency) {
 938                 err = tuner_ops->get_frequency(fe, &freq);
 939                 if (err < 0) {
 940                         printk(KERN_ERR "%s: Invalid parameter\n", __func__);
 941                         return err;
 942                 }
 943
 944                 dprintk("%s: frequency=%d\n", __func__, freq);
 945
 946         } else
 947                 return -1;
 948
 949         return freq;
 950 }
 951
 952 static u16 CellsCoeffs_8MHz_367cofdm[3][6][5] = {
 953         {
 954                 {0x10EF, 0xE205, 0x10EF, 0xCE49, 0x6DA7}, /* CELL 1 COEFFS 27M*/
 955                 {0x2151, 0xc557, 0x2151, 0xc705, 0x6f93}, /* CELL 2 COEFFS */
 956                 {0x2503, 0xc000, 0x2503, 0xc375, 0x7194}, /* CELL 3 COEFFS */
 957                 {0x20E9, 0xca94, 0x20e9, 0xc153, 0x7194}, /* CELL 4 COEFFS */
 958                 {0x06EF, 0xF852, 0x06EF, 0xC057, 0x7207}, /* CELL 5 COEFFS */
 959                 {0x0000, 0x0ECC, 0x0ECC, 0x0000, 0x3647} /* CELL 6 COEFFS */
 960         }, {
 961                 {0x10A0, 0xE2AF, 0x10A1, 0xCE76, 0x6D6D}, /* CELL 1 COEFFS 25M*/
 962                 {0x20DC, 0xC676, 0x20D9, 0xC80A, 0x6F29},
 963                 {0x2532, 0xC000, 0x251D, 0xC391, 0x706F},
 964                 {0x1F7A, 0xCD2B, 0x2032, 0xC15E, 0x711F},
 965                 {0x0698, 0xFA5E, 0x0568, 0xC059, 0x7193},
 966                 {0x0000, 0x0918, 0x149C, 0x0000, 0x3642} /* CELL 6 COEFFS */
 967         }, {
 968                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
 969                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 970                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 971                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 972                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 973                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
 974         }
 975 };
 976
 977 static u16 CellsCoeffs_7MHz_367cofdm[3][6][5] = {
 978         {
 979                 {0x12CA, 0xDDAF, 0x12CA, 0xCCEB, 0x6FB1}, /* CELL 1 COEFFS 27M*/
 980                 {0x2329, 0xC000, 0x2329, 0xC6B0, 0x725F}, /* CELL 2 COEFFS */
 981                 {0x2394, 0xC000, 0x2394, 0xC2C7, 0x7410}, /* CELL 3 COEFFS */
 982                 {0x251C, 0xC000, 0x251C, 0xC103, 0x74D9}, /* CELL 4 COEFFS */
 983                 {0x0804, 0xF546, 0x0804, 0xC040, 0x7544}, /* CELL 5 COEFFS */
 984                 {0x0000, 0x0CD9, 0x0CD9, 0x0000, 0x370A} /* CELL 6 COEFFS */
 985         }, {
 986                 {0x1285, 0xDE47, 0x1285, 0xCD17, 0x6F76}, /*25M*/
 987                 {0x234C, 0xC000, 0x2348, 0xC6DA, 0x7206},
 988                 {0x23B4, 0xC000, 0x23AC, 0xC2DB, 0x73B3},
 989                 {0x253D, 0xC000, 0x25B6, 0xC10B, 0x747F},
 990                 {0x0721, 0xF79C, 0x065F, 0xC041, 0x74EB},
 991                 {0x0000, 0x08FA, 0x1162, 0x0000, 0x36FF}
 992         }, {
 993                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
 994                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 995                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 996                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 997                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 998                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
 999         }
1000 };
1001
1002 static u16 CellsCoeffs_6MHz_367cofdm[3][6][5] = {
1003         {
1004                 {0x1699, 0xD5B8, 0x1699, 0xCBC3, 0x713B}, /* CELL 1 COEFFS 27M*/
1005                 {0x2245, 0xC000, 0x2245, 0xC568, 0x74D5}, /* CELL 2 COEFFS */
1006                 {0x227F, 0xC000, 0x227F, 0xC1FC, 0x76C6}, /* CELL 3 COEFFS */
1007                 {0x235E, 0xC000, 0x235E, 0xC0A7, 0x778A}, /* CELL 4 COEFFS */
1008                 {0x0ECB, 0xEA0B, 0x0ECB, 0xC027, 0x77DD}, /* CELL 5 COEFFS */
1009                 {0x0000, 0x0B68, 0x0B68, 0x0000, 0xC89A}, /* CELL 6 COEFFS */
1010         }, {
1011                 {0x1655, 0xD64E, 0x1658, 0xCBEF, 0x70FE}, /*25M*/
1012                 {0x225E, 0xC000, 0x2256, 0xC589, 0x7489},
1013                 {0x2293, 0xC000, 0x2295, 0xC209, 0x767E},
1014                 {0x2377, 0xC000, 0x23AA, 0xC0AB, 0x7746},
1015                 {0x0DC7, 0xEBC8, 0x0D07, 0xC027, 0x7799},
1016                 {0x0000, 0x0888, 0x0E9C, 0x0000, 0x3757}
1017
1018         }, {
1019                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
1020                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
1021                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
1022                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
1023                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
1024                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
1025         }
1026 };
1027
1028 static u32 stv0367ter_get_mclk(struct stv0367_state *state, u32 ExtClk_Hz)
1029 {
1030         u32 mclk_Hz = 0; /* master clock frequency (Hz) */
1031         u32 m, n, p;
1032
1033         dprintk("%s:\n", __func__);
1034
1035         if (stv0367_readbits(state, F367TER_BYPASS_PLLXN) == 0) {
1036                 n = (u32)stv0367_readbits(state, F367TER_PLL_NDIV);
1037                 if (n == 0)
1038                         n = n + 1;
1039
1040                 m = (u32)stv0367_readbits(state, F367TER_PLL_MDIV);
1041                 if (m == 0)
1042                         m = m + 1;
1043
1044                 p = (u32)stv0367_readbits(state, F367TER_PLL_PDIV);
1045                 if (p > 5)
1046                         p = 5;
1047
1048                 mclk_Hz = ((ExtClk_Hz / 2) * n) / (m * (1 << p));
1049
1050                 dprintk("N=%d M=%d P=%d mclk_Hz=%d ExtClk_Hz=%d\n",
1051                                 n, m, p, mclk_Hz, ExtClk_Hz);
1052         } else
1053                 mclk_Hz = ExtClk_Hz;
1054
1055         dprintk("%s: mclk_Hz=%d\n", __func__, mclk_Hz);
1056
1057         return mclk_Hz;
1058 }
1059
1060 static int stv0367ter_filt_coeff_init(struct stv0367_state *state,
1061                                 u16 CellsCoeffs[3][6][5], u32 DemodXtal)
1062 {
1063         int i, j, k, freq;
1064
1065         dprintk("%s:\n", __func__);
1066
1067         freq = stv0367ter_get_mclk(state, DemodXtal);
1068
1069         if (freq == 53125000)
1070                 k = 1; /* equivalent to Xtal 25M on 362*/
1071         else if (freq == 54000000)
1072                 k = 0; /* equivalent to Xtal 27M on 362*/
1073         else if (freq == 52500000)
1074                 k = 2; /* equivalent to Xtal 30M on 362*/
1075         else
1076                 return 0;
1077
1078         for (i = 1; i <= 6; i++) {
1079                 stv0367_writebits(state, F367TER_IIR_CELL_NB, i - 1);
1080
1081                 for (j = 1; j <= 5; j++) {
1082                         stv0367_writereg(state,
1083                                 (R367TER_IIRCX_COEFF1_MSB + 2 * (j - 1)),
1084                                 MSB(CellsCoeffs[k][i-1][j-1]));
1085                         stv0367_writereg(state,
1086                                 (R367TER_IIRCX_COEFF1_LSB + 2 * (j - 1)),
1087                                 LSB(CellsCoeffs[k][i-1][j-1]));
1088                 }
1089         }
1090
1091         return 1;
1092
1093 }
1094
1095 static void stv0367ter_agc_iir_lock_detect_set(struct stv0367_state *state)
1096 {
1097         dprintk("%s:\n", __func__);
1098
1099         stv0367_writebits(state, F367TER_LOCK_DETECT_LSB, 0x00);
1100
1101         /* Lock detect 1 */
1102         stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x00);
1103         stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
1104         stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
1105
1106         /* Lock detect 2 */
1107         stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x01);
1108         stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
1109         stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
1110
1111         /* Lock detect 3 */
1112         stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x02);
1113         stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
1114         stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
1115
1116         /* Lock detect 4 */
1117         stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x03);
1118         stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
1119         stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
1120
1121 }
1122
1123 static int stv0367_iir_filt_init(struct stv0367_state *state, u8 Bandwidth,
1124                                                         u32 DemodXtalValue)
1125 {
1126         dprintk("%s:\n", __func__);
1127
1128         stv0367_writebits(state, F367TER_NRST_IIR, 0);
1129
1130         switch (Bandwidth) {
1131         case 6:
1132                 if (!stv0367ter_filt_coeff_init(state,
1133                                 CellsCoeffs_6MHz_367cofdm,
1134                                 DemodXtalValue))
1135                         return 0;
1136                 break;
1137         case 7:
1138                 if (!stv0367ter_filt_coeff_init(state,
1139                                 CellsCoeffs_7MHz_367cofdm,
1140                                 DemodXtalValue))
1141                         return 0;
1142                 break;
1143         case 8:
1144                 if (!stv0367ter_filt_coeff_init(state,
1145                                 CellsCoeffs_8MHz_367cofdm,
1146                                 DemodXtalValue))
1147                         return 0;
1148                 break;
1149         default:
1150                 return 0;
1151         }
1152
1153         stv0367_writebits(state, F367TER_NRST_IIR, 1);
1154
1155         return 1;
1156 }
1157
1158 static void stv0367ter_agc_iir_rst(struct stv0367_state *state)
1159 {
1160
1161         u8 com_n;
1162
1163         dprintk("%s:\n", __func__);
1164
1165         com_n = stv0367_readbits(state, F367TER_COM_N);
1166
1167         stv0367_writebits(state, F367TER_COM_N, 0x07);
1168
1169         stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x00);
1170         stv0367_writebits(state, F367TER_COM_AGC_ON, 0x00);
1171
1172         stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x01);
1173         stv0367_writebits(state, F367TER_COM_AGC_ON, 0x01);
1174
1175         stv0367_writebits(state, F367TER_COM_N, com_n);
1176
1177 }
1178
1179 static int stv0367ter_duration(s32 mode, int tempo1, int tempo2, int tempo3)
1180 {
1181         int local_tempo = 0;
1182         switch (mode) {
1183         case 0:
1184                 local_tempo = tempo1;
1185                 break;
1186         case 1:
1187                 local_tempo = tempo2;
1188                 break ;
1189
1190         case 2:
1191                 local_tempo = tempo3;
1192                 break;
1193
1194         default:
1195                 break;
1196         }
1197         /*      msleep(local_tempo);  */
1198         return local_tempo;
1199 }
1200
1201 static enum
1202 stv0367_ter_signal_type stv0367ter_check_syr(struct stv0367_state *state)
1203 {
1204         int wd = 100;
1205         unsigned short int SYR_var;
1206         s32 SYRStatus;
1207
1208         dprintk("%s:\n", __func__);
1209
1210         SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
1211
1212         while ((!SYR_var) && (wd > 0)) {
1213                 usleep_range(2000, 3000);
1214                 wd -= 2;
1215                 SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
1216         }
1217
1218         if (!SYR_var)
1219                 SYRStatus = FE_TER_NOSYMBOL;
1220         else
1221                 SYRStatus =  FE_TER_SYMBOLOK;
1222
1223         dprintk("stv0367ter_check_syr SYRStatus %s\n",
1224                                 SYR_var == 0 ? "No Symbol" : "OK");
1225
1226         return SYRStatus;
1227 }
1228
1229 static enum
1230 stv0367_ter_signal_type stv0367ter_check_cpamp(struct stv0367_state *state,
1231                                                                 s32 FFTmode)
1232 {
1233
1234         s32  CPAMPvalue = 0, CPAMPStatus, CPAMPMin;
1235         int wd = 0;
1236
1237         dprintk("%s:\n", __func__);
1238
1239         switch (FFTmode) {
1240         case 0: /*2k mode*/
1241                 CPAMPMin = 20;
1242                 wd = 10;
1243                 break;
1244         case 1: /*8k mode*/
1245                 CPAMPMin = 80;
1246                 wd = 55;
1247                 break;
1248         case 2: /*4k mode*/
1249                 CPAMPMin = 40;
1250                 wd = 30;
1251                 break;
1252         default:
1253                 CPAMPMin = 0xffff;  /*drives to NOCPAMP */
1254                 break;
1255         }
1256
1257         dprintk("%s: CPAMPMin=%d wd=%d\n", __func__, CPAMPMin, wd);
1258
1259         CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
1260         while ((CPAMPvalue < CPAMPMin) && (wd > 0)) {
1261                 usleep_range(1000, 2000);
1262                 wd -= 1;
1263                 CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
1264                 /*dprintk("CPAMPvalue= %d at wd=%d\n",CPAMPvalue,wd); */
1265         }
1266         dprintk("******last CPAMPvalue= %d at wd=%d\n", CPAMPvalue, wd);
1267         if (CPAMPvalue < CPAMPMin) {
1268                 CPAMPStatus = FE_TER_NOCPAMP;
1269                 printk(KERN_ERR "CPAMP failed\n");
1270         } else {
1271                 printk(KERN_ERR "CPAMP OK !\n");
1272                 CPAMPStatus = FE_TER_CPAMPOK;
1273         }
1274
1275         return CPAMPStatus;
1276 }
1277
1278 static enum stv0367_ter_signal_type
1279 stv0367ter_lock_algo(struct stv0367_state *state)
1280 {
1281         enum stv0367_ter_signal_type ret_flag;
1282         short int wd, tempo;
1283         u8 try, u_var1 = 0, u_var2 = 0, u_var3 = 0, u_var4 = 0, mode, guard;
1284         u8 tmp, tmp2;
1285
1286         dprintk("%s:\n", __func__);
1287
1288         if (state == NULL)
1289                 return FE_TER_SWNOK;
1290
1291         try = 0;
1292         do {
1293                 ret_flag = FE_TER_LOCKOK;
1294
1295                 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1296
1297                 if (state->config->if_iq_mode != 0)
1298                         stv0367_writebits(state, F367TER_COM_N, 0x07);
1299
1300                 stv0367_writebits(state, F367TER_GUARD, 3);/* suggest 2k 1/4 */
1301                 stv0367_writebits(state, F367TER_MODE, 0);
1302                 stv0367_writebits(state, F367TER_SYR_TR_DIS, 0);
1303                 usleep_range(5000, 10000);
1304
1305                 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1306
1307
1308                 if (stv0367ter_check_syr(state) == FE_TER_NOSYMBOL)
1309                         return FE_TER_NOSYMBOL;
1310                 else { /*
1311                         if chip locked on wrong mode first try,
1312                         it must lock correctly second try */
1313                         mode = stv0367_readbits(state, F367TER_SYR_MODE);
1314                         if (stv0367ter_check_cpamp(state, mode) ==
1315                                                         FE_TER_NOCPAMP) {
1316                                 if (try == 0)
1317                                         ret_flag = FE_TER_NOCPAMP;
1318
1319                         }
1320                 }
1321
1322                 try++;
1323         } while ((try < 10) && (ret_flag != FE_TER_LOCKOK));
1324
1325         tmp  = stv0367_readreg(state, R367TER_SYR_STAT);
1326         tmp2 = stv0367_readreg(state, R367TER_STATUS);
1327         dprintk("state=%p\n", state);
1328         dprintk("LOCK OK! mode=%d SYR_STAT=0x%x R367TER_STATUS=0x%x\n",
1329                                                         mode, tmp, tmp2);
1330
1331         tmp  = stv0367_readreg(state, R367TER_PRVIT);
1332         tmp2 = stv0367_readreg(state, R367TER_I2CRPT);
1333         dprintk("PRVIT=0x%x I2CRPT=0x%x\n", tmp, tmp2);
1334
1335         tmp  = stv0367_readreg(state, R367TER_GAIN_SRC1);
1336         dprintk("GAIN_SRC1=0x%x\n", tmp);
1337
1338         if ((mode != 0) && (mode != 1) && (mode != 2))
1339                 return FE_TER_SWNOK;
1340
1341         /*guard=stv0367_readbits(state,F367TER_SYR_GUARD); */
1342
1343         /*suppress EPQ auto for SYR_GARD 1/16 or 1/32
1344         and set channel predictor in automatic */
1345 #if 0
1346         switch (guard) {
1347
1348         case 0:
1349         case 1:
1350                 stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
1351                 stv0367_writereg(state, R367TER_CHC_CTL, 0x01);
1352                 break;
1353         case 2:
1354         case 3:
1355                 stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
1356                 stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
1357                 break;
1358
1359         default:
1360                 return FE_TER_SWNOK;
1361         }
1362 #endif
1363
1364         /*reset fec an reedsolo FOR 367 only*/
1365         stv0367_writebits(state, F367TER_RST_SFEC, 1);
1366         stv0367_writebits(state, F367TER_RST_REEDSOLO, 1);
1367         usleep_range(1000, 2000);
1368         stv0367_writebits(state, F367TER_RST_SFEC, 0);
1369         stv0367_writebits(state, F367TER_RST_REEDSOLO, 0);
1370
1371         u_var1 = stv0367_readbits(state, F367TER_LK);
1372         u_var2 = stv0367_readbits(state, F367TER_PRF);
1373         u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
1374         /*      u_var4=stv0367_readbits(state,F367TER_TSFIFO_LINEOK); */
1375
1376         wd = stv0367ter_duration(mode, 125, 500, 250);
1377         tempo = stv0367ter_duration(mode, 4, 16, 8);
1378
1379         /*while ( ((!u_var1)||(!u_var2)||(!u_var3)||(!u_var4))  && (wd>=0)) */
1380         while (((!u_var1) || (!u_var2) || (!u_var3)) && (wd >= 0)) {
1381                 usleep_range(1000 * tempo, 1000 * (tempo + 1));
1382                 wd -= tempo;
1383                 u_var1 = stv0367_readbits(state, F367TER_LK);
1384                 u_var2 = stv0367_readbits(state, F367TER_PRF);
1385                 u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
1386                 /*u_var4=stv0367_readbits(state, F367TER_TSFIFO_LINEOK); */
1387         }
1388
1389         if (!u_var1)
1390                 return FE_TER_NOLOCK;
1391
1392
1393         if (!u_var2)
1394                 return FE_TER_NOPRFOUND;
1395
1396         if (!u_var3)
1397                 return FE_TER_NOTPS;
1398
1399         guard = stv0367_readbits(state, F367TER_SYR_GUARD);
1400         stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
1401         switch (guard) {
1402         case 0:
1403         case 1:
1404                 stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
1405                 /*stv0367_writereg(state,R367TER_CHC_CTL, 0x1);*/
1406                 stv0367_writebits(state, F367TER_SYR_FILTER, 0);
1407                 break;
1408         case 2:
1409         case 3:
1410                 stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
1411                 /*stv0367_writereg(state,R367TER_CHC_CTL, 0x11);*/
1412                 stv0367_writebits(state, F367TER_SYR_FILTER, 1);
1413                 break;
1414
1415         default:
1416                 return FE_TER_SWNOK;
1417         }
1418
1419         /* apply Sfec workaround if 8K 64QAM CR!=1/2*/
1420         if ((stv0367_readbits(state, F367TER_TPS_CONST) == 2) &&
1421                         (mode == 1) &&
1422                         (stv0367_readbits(state, F367TER_TPS_HPCODE) != 0)) {
1423                 stv0367_writereg(state, R367TER_SFDLYSETH, 0xc0);
1424                 stv0367_writereg(state, R367TER_SFDLYSETM, 0x60);
1425                 stv0367_writereg(state, R367TER_SFDLYSETL, 0x0);
1426         } else
1427                 stv0367_writereg(state, R367TER_SFDLYSETH, 0x0);
1428
1429         wd = stv0367ter_duration(mode, 125, 500, 250);
1430         u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
1431
1432         while ((!u_var4) && (wd >= 0)) {
1433                 usleep_range(1000 * tempo, 1000 * (tempo + 1));
1434                 wd -= tempo;
1435                 u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
1436         }
1437
1438         if (!u_var4)
1439                 return FE_TER_NOLOCK;
1440
1441         /* for 367 leave COM_N at 0x7 for IQ_mode*/
1442         /*if(ter_state->if_iq_mode!=FE_TER_NORMAL_IF_TUNER) {
1443                 tempo=0;
1444                 while ((stv0367_readbits(state,F367TER_COM_USEGAINTRK)!=1) &&
1445                 (stv0367_readbits(state,F367TER_COM_AGCLOCK)!=1)&&(tempo<100)) {
1446                         ChipWaitOrAbort(state,1);
1447                         tempo+=1;
1448                 }
1449
1450                 stv0367_writebits(state,F367TER_COM_N,0x17);
1451         } */
1452
1453         stv0367_writebits(state, F367TER_SYR_TR_DIS, 1);
1454
1455         dprintk("FE_TER_LOCKOK !!!\n");
1456
1457         return  FE_TER_LOCKOK;
1458
1459 }
1460
1461 static void stv0367ter_set_ts_mode(struct stv0367_state *state,
1462                                         enum stv0367_ts_mode PathTS)
1463 {
1464
1465         dprintk("%s:\n", __func__);
1466
1467         if (state == NULL)
1468                 return;
1469
1470         stv0367_writebits(state, F367TER_TS_DIS, 0);
1471         switch (PathTS) {
1472         default:
1473                 /*for removing warning :default we can assume in parallel mode*/
1474         case STV0367_PARALLEL_PUNCT_CLOCK:
1475                 stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 0);
1476                 stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 0);
1477                 break;
1478         case STV0367_SERIAL_PUNCT_CLOCK:
1479                 stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 1);
1480                 stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 1);
1481                 break;
1482         }
1483 }
1484
1485 static void stv0367ter_set_clk_pol(struct stv0367_state *state,
1486                                         enum stv0367_clk_pol clock)
1487 {
1488
1489         dprintk("%s:\n", __func__);
1490
1491         if (state == NULL)
1492                 return;
1493
1494         switch (clock) {
1495         case STV0367_RISINGEDGE_CLOCK:
1496                 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 1);
1497                 break;
1498         case STV0367_FALLINGEDGE_CLOCK:
1499                 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
1500                 break;
1501                 /*case FE_TER_CLOCK_POLARITY_DEFAULT:*/
1502         default:
1503                 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
1504                 break;
1505         }
1506 }
1507
1508 #if 0
1509 static void stv0367ter_core_sw(struct stv0367_state *state)
1510 {
1511
1512         dprintk("%s:\n", __func__);
1513
1514         stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1515         stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1516         msleep(350);
1517 }
1518 #endif
1519 static int stv0367ter_standby(struct dvb_frontend *fe, u8 standby_on)
1520 {
1521         struct stv0367_state *state = fe->demodulator_priv;
1522
1523         dprintk("%s:\n", __func__);
1524
1525         if (standby_on) {
1526                 stv0367_writebits(state, F367TER_STDBY, 1);
1527                 stv0367_writebits(state, F367TER_STDBY_FEC, 1);
1528                 stv0367_writebits(state, F367TER_STDBY_CORE, 1);
1529         } else {
1530                 stv0367_writebits(state, F367TER_STDBY, 0);
1531                 stv0367_writebits(state, F367TER_STDBY_FEC, 0);
1532                 stv0367_writebits(state, F367TER_STDBY_CORE, 0);
1533         }
1534
1535         return 0;
1536 }
1537
1538 static int stv0367ter_sleep(struct dvb_frontend *fe)
1539 {
1540         return stv0367ter_standby(fe, 1);
1541 }
1542
1543 static int stv0367ter_init(struct dvb_frontend *fe)
1544 {
1545         struct stv0367_state *state = fe->demodulator_priv;
1546         struct stv0367ter_state *ter_state = state->ter_state;
1547         int i;
1548
1549         dprintk("%s:\n", __func__);
1550
1551         ter_state->pBER = 0;
1552
1553         for (i = 0; i < STV0367TER_NBREGS; i++)
1554                 stv0367_writereg(state, def0367ter[i].addr,
1555                                         def0367ter[i].value);
1556
1557         switch (state->config->xtal) {
1558                 /*set internal freq to 53.125MHz */
1559         case 16000000:
1560                 stv0367_writereg(state, R367TER_PLLMDIV, 0x2);
1561                 stv0367_writereg(state, R367TER_PLLNDIV, 0x1b);
1562                 stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
1563                 break;
1564         case 25000000:
1565                 stv0367_writereg(state, R367TER_PLLMDIV, 0xa);
1566                 stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
1567                 stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
1568                 break;
1569         default:
1570         case 27000000:
1571                 dprintk("FE_STV0367TER_SetCLKgen for 27Mhz\n");
1572                 stv0367_writereg(state, R367TER_PLLMDIV, 0x1);
1573                 stv0367_writereg(state, R367TER_PLLNDIV, 0x8);
1574                 stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
1575                 break;
1576         case 30000000:
1577                 stv0367_writereg(state, R367TER_PLLMDIV, 0xc);
1578                 stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
1579                 stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
1580                 break;
1581         }
1582
1583         stv0367_writereg(state, R367TER_I2CRPT, 0xa0);
1584         stv0367_writereg(state, R367TER_ANACTRL, 0x00);
1585
1586         /*Set TS1 and TS2 to serial or parallel mode */
1587         stv0367ter_set_ts_mode(state, state->config->ts_mode);
1588         stv0367ter_set_clk_pol(state, state->config->clk_pol);
1589
1590         state->chip_id = stv0367_readreg(state, R367TER_ID);
1591         ter_state->first_lock = 0;
1592         ter_state->unlock_counter = 2;
1593
1594         return 0;
1595 }
1596
1597 static int stv0367ter_algo(struct dvb_frontend *fe)
1598 {
1599         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1600         struct stv0367_state *state = fe->demodulator_priv;
1601         struct stv0367ter_state *ter_state = state->ter_state;
1602         int offset = 0, tempo = 0;
1603         u8 u_var;
1604         u8 /*constell,*/ counter;
1605         s8 step;
1606         s32 timing_offset = 0;
1607         u32 trl_nomrate = 0, InternalFreq = 0, temp = 0;
1608
1609         dprintk("%s:\n", __func__);
1610
1611         ter_state->frequency = p->frequency;
1612         ter_state->force = FE_TER_FORCENONE
1613                         + stv0367_readbits(state, F367TER_FORCE) * 2;
1614         ter_state->if_iq_mode = state->config->if_iq_mode;
1615         switch (state->config->if_iq_mode) {
1616         case FE_TER_NORMAL_IF_TUNER:  /* Normal IF mode */
1617                 dprintk("ALGO: FE_TER_NORMAL_IF_TUNER selected\n");
1618                 stv0367_writebits(state, F367TER_TUNER_BB, 0);
1619                 stv0367_writebits(state, F367TER_LONGPATH_IF, 0);
1620                 stv0367_writebits(state, F367TER_DEMUX_SWAP, 0);
1621                 break;
1622         case FE_TER_LONGPATH_IF_TUNER:  /* Long IF mode */
1623                 dprintk("ALGO: FE_TER_LONGPATH_IF_TUNER selected\n");
1624                 stv0367_writebits(state, F367TER_TUNER_BB, 0);
1625                 stv0367_writebits(state, F367TER_LONGPATH_IF, 1);
1626                 stv0367_writebits(state, F367TER_DEMUX_SWAP, 1);
1627                 break;
1628         case FE_TER_IQ_TUNER:  /* IQ mode */
1629                 dprintk("ALGO: FE_TER_IQ_TUNER selected\n");
1630                 stv0367_writebits(state, F367TER_TUNER_BB, 1);
1631                 stv0367_writebits(state, F367TER_PPM_INVSEL, 0);
1632                 break;
1633         default:
1634                 printk(KERN_ERR "ALGO: wrong TUNER type selected\n");
1635                 return -EINVAL;
1636         }
1637
1638         usleep_range(5000, 7000);
1639
1640         switch (p->inversion) {
1641         case INVERSION_AUTO:
1642         default:
1643                 dprintk("%s: inversion AUTO\n", __func__);
1644                 if (ter_state->if_iq_mode == FE_TER_IQ_TUNER)
1645                         stv0367_writebits(state, F367TER_IQ_INVERT,
1646                                                 ter_state->sense);
1647                 else
1648                         stv0367_writebits(state, F367TER_INV_SPECTR,
1649                                                 ter_state->sense);
1650
1651                 break;
1652         case INVERSION_ON:
1653         case INVERSION_OFF:
1654                 if (ter_state->if_iq_mode == FE_TER_IQ_TUNER)
1655                         stv0367_writebits(state, F367TER_IQ_INVERT,
1656                                                 p->inversion);
1657                 else
1658                         stv0367_writebits(state, F367TER_INV_SPECTR,
1659                                                 p->inversion);
1660
1661                 break;
1662         }
1663
1664         if ((ter_state->if_iq_mode != FE_TER_NORMAL_IF_TUNER) &&
1665                                 (ter_state->pBW != ter_state->bw)) {
1666                 stv0367ter_agc_iir_lock_detect_set(state);
1667
1668                 /*set fine agc target to 180 for LPIF or IQ mode*/
1669                 /* set Q_AGCTarget */
1670                 stv0367_writebits(state, F367TER_SEL_IQNTAR, 1);
1671                 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
1672                 /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
1673
1674                 /* set Q_AGCTarget */
1675                 stv0367_writebits(state, F367TER_SEL_IQNTAR, 0);
1676                 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
1677                 /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
1678
1679                 if (!stv0367_iir_filt_init(state, ter_state->bw,
1680                                                 state->config->xtal))
1681                         return -EINVAL;
1682                 /*set IIR filter once for 6,7 or 8MHz BW*/
1683                 ter_state->pBW = ter_state->bw;
1684
1685                 stv0367ter_agc_iir_rst(state);
1686         }
1687
1688         if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO)
1689                 stv0367_writebits(state, F367TER_BDI_LPSEL, 0x01);
1690         else
1691                 stv0367_writebits(state, F367TER_BDI_LPSEL, 0x00);
1692
1693         InternalFreq = stv0367ter_get_mclk(state, state->config->xtal) / 1000;
1694         temp = (int)
1695                 ((((ter_state->bw * 64 * (1 << 15) * 100)
1696                                                 / (InternalFreq)) * 10) / 7);
1697
1698         stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB, temp % 2);
1699         temp = temp / 2;
1700         stv0367_writebits(state, F367TER_TRL_NOMRATE_HI, temp / 256);
1701         stv0367_writebits(state, F367TER_TRL_NOMRATE_LO, temp % 256);
1702
1703         temp = stv0367_readbits(state, F367TER_TRL_NOMRATE_HI) * 512 +
1704                         stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2 +
1705                         stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB);
1706         temp = (int)(((1 << 17) * ter_state->bw * 1000) / (7 * (InternalFreq)));
1707         stv0367_writebits(state, F367TER_GAIN_SRC_HI, temp / 256);
1708         stv0367_writebits(state, F367TER_GAIN_SRC_LO, temp % 256);
1709         temp = stv0367_readbits(state, F367TER_GAIN_SRC_HI) * 256 +
1710                         stv0367_readbits(state, F367TER_GAIN_SRC_LO);
1711
1712         temp = (int)
1713                 ((InternalFreq - state->config->if_khz) * (1 << 16)
1714                                                         / (InternalFreq));
1715
1716         dprintk("DEROT temp=0x%x\n", temp);
1717         stv0367_writebits(state, F367TER_INC_DEROT_HI, temp / 256);
1718         stv0367_writebits(state, F367TER_INC_DEROT_LO, temp % 256);
1719
1720         ter_state->echo_pos = 0;
1721         ter_state->ucblocks = 0; /* liplianin */
1722         ter_state->pBER = 0; /* liplianin */
1723         stv0367_writebits(state, F367TER_LONG_ECHO, ter_state->echo_pos);
1724
1725         if (stv0367ter_lock_algo(state) != FE_TER_LOCKOK)
1726                 return 0;
1727
1728         ter_state->state = FE_TER_LOCKOK;
1729
1730         ter_state->mode = stv0367_readbits(state, F367TER_SYR_MODE);
1731         ter_state->guard = stv0367_readbits(state, F367TER_SYR_GUARD);
1732
1733         ter_state->first_lock = 1; /* we know sense now :) */
1734
1735         ter_state->agc_val =
1736                         (stv0367_readbits(state, F367TER_AGC1_VAL_LO) << 16) +
1737                         (stv0367_readbits(state, F367TER_AGC1_VAL_HI) << 24) +
1738                         stv0367_readbits(state, F367TER_AGC2_VAL_LO) +
1739                         (stv0367_readbits(state, F367TER_AGC2_VAL_HI) << 8);
1740
1741         /* Carrier offset calculation */
1742         stv0367_writebits(state, F367TER_FREEZE, 1);
1743         offset = (stv0367_readbits(state, F367TER_CRL_FOFFSET_VHI) << 16) ;
1744         offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_HI) << 8);
1745         offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_LO));
1746         stv0367_writebits(state, F367TER_FREEZE, 0);
1747         if (offset > 8388607)
1748                 offset -= 16777216;
1749
1750         offset = offset * 2 / 16384;
1751
1752         if (ter_state->mode == FE_TER_MODE_2K)
1753                 offset = (offset * 4464) / 1000;/*** 1 FFT BIN=4.464khz***/
1754         else if (ter_state->mode == FE_TER_MODE_4K)
1755                 offset = (offset * 223) / 100;/*** 1 FFT BIN=2.23khz***/
1756         else  if (ter_state->mode == FE_TER_MODE_8K)
1757                 offset = (offset * 111) / 100;/*** 1 FFT BIN=1.1khz***/
1758
1759         if (stv0367_readbits(state, F367TER_PPM_INVSEL) == 1) {
1760                 if ((stv0367_readbits(state, F367TER_INV_SPECTR) ==
1761                                 (stv0367_readbits(state,
1762                                         F367TER_STATUS_INV_SPECRUM) == 1)))
1763                         offset = offset * -1;
1764         }
1765
1766         if (ter_state->bw == 6)
1767                 offset = (offset * 6) / 8;
1768         else if (ter_state->bw == 7)
1769                 offset = (offset * 7) / 8;
1770
1771         ter_state->frequency += offset;
1772
1773         tempo = 10;  /* exit even if timing_offset stays null */
1774         while ((timing_offset == 0) && (tempo > 0)) {
1775                 usleep_range(10000, 20000);     /*was 20ms  */
1776                 /* fine tuning of timing offset if required */
1777                 timing_offset = stv0367_readbits(state, F367TER_TRL_TOFFSET_LO)
1778                                 + 256 * stv0367_readbits(state,
1779                                                         F367TER_TRL_TOFFSET_HI);
1780                 if (timing_offset >= 32768)
1781                         timing_offset -= 65536;
1782                 trl_nomrate = (512 * stv0367_readbits(state,
1783                                                         F367TER_TRL_NOMRATE_HI)
1784                         + stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2
1785                         + stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB));
1786
1787                 timing_offset = ((signed)(1000000 / trl_nomrate) *
1788                                                         timing_offset) / 2048;
1789                 tempo--;
1790         }
1791
1792         if (timing_offset <= 0) {
1793                 timing_offset = (timing_offset - 11) / 22;
1794                 step = -1;
1795         } else {
1796                 timing_offset = (timing_offset + 11) / 22;
1797                 step = 1;
1798         }
1799
1800         for (counter = 0; counter < abs(timing_offset); counter++) {
1801                 trl_nomrate += step;
1802                 stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB,
1803                                                 trl_nomrate % 2);
1804                 stv0367_writebits(state, F367TER_TRL_NOMRATE_LO,
1805                                                 trl_nomrate / 2);
1806                 usleep_range(1000, 2000);
1807         }
1808
1809         usleep_range(5000, 6000);
1810         /* unlocks could happen in case of trl centring big step,
1811         then a core off/on restarts demod */
1812         u_var = stv0367_readbits(state, F367TER_LK);
1813
1814         if (!u_var) {
1815                 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1816                 msleep(20);
1817                 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1818         }
1819
1820         return 0;
1821 }
1822
1823 static int stv0367ter_set_frontend(struct dvb_frontend *fe)
1824 {
1825         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1826         struct stv0367_state *state = fe->demodulator_priv;
1827         struct stv0367ter_state *ter_state = state->ter_state;
1828
1829         /*u8 trials[2]; */
1830         s8 num_trials, index;
1831         u8 SenseTrials[] = { INVERSION_ON, INVERSION_OFF };
1832
1833         stv0367ter_init(fe);
1834
1835         if (fe->ops.tuner_ops.set_params) {
1836                 if (fe->ops.i2c_gate_ctrl)
1837                         fe->ops.i2c_gate_ctrl(fe, 1);
1838                 fe->ops.tuner_ops.set_params(fe);
1839                 if (fe->ops.i2c_gate_ctrl)
1840                         fe->ops.i2c_gate_ctrl(fe, 0);
1841         }
1842
1843         switch (p->transmission_mode) {
1844         default:
1845         case TRANSMISSION_MODE_AUTO:
1846         case TRANSMISSION_MODE_2K:
1847                 ter_state->mode = FE_TER_MODE_2K;
1848                 break;
1849 /*      case TRANSMISSION_MODE_4K:
1850                 pLook.mode = FE_TER_MODE_4K;
1851                 break;*/
1852         case TRANSMISSION_MODE_8K:
1853                 ter_state->mode = FE_TER_MODE_8K;
1854                 break;
1855         }
1856
1857         switch (p->guard_interval) {
1858         default:
1859         case GUARD_INTERVAL_1_32:
1860         case GUARD_INTERVAL_1_16:
1861         case GUARD_INTERVAL_1_8:
1862         case GUARD_INTERVAL_1_4:
1863                 ter_state->guard = p->guard_interval;
1864                 break;
1865         case GUARD_INTERVAL_AUTO:
1866                 ter_state->guard = GUARD_INTERVAL_1_32;
1867                 break;
1868         }
1869
1870         switch (p->bandwidth_hz) {
1871         case 6000000:
1872                 ter_state->bw = FE_TER_CHAN_BW_6M;
1873                 break;
1874         case 7000000:
1875                 ter_state->bw = FE_TER_CHAN_BW_7M;
1876                 break;
1877         case 8000000:
1878         default:
1879                 ter_state->bw = FE_TER_CHAN_BW_8M;
1880         }
1881
1882         ter_state->hierarchy = FE_TER_HIER_NONE;
1883
1884         switch (p->inversion) {
1885         case INVERSION_OFF:
1886         case INVERSION_ON:
1887                 num_trials = 1;
1888                 break;
1889         default:
1890                 num_trials = 2;
1891                 if (ter_state->first_lock)
1892                         num_trials = 1;
1893                 break;
1894         }
1895
1896         ter_state->state = FE_TER_NOLOCK;
1897         index = 0;
1898
1899         while (((index) < num_trials) && (ter_state->state != FE_TER_LOCKOK)) {
1900                 if (!ter_state->first_lock) {
1901                         if (p->inversion == INVERSION_AUTO)
1902                                 ter_state->sense = SenseTrials[index];
1903
1904                 }
1905                 stv0367ter_algo(fe);
1906
1907                 if ((ter_state->state == FE_TER_LOCKOK) &&
1908                                 (p->inversion == INVERSION_AUTO) &&
1909                                                                 (index == 1)) {
1910                         /* invert spectrum sense */
1911                         SenseTrials[index] = SenseTrials[0];
1912                         SenseTrials[(index + 1) % 2] = (SenseTrials[1] + 1) % 2;
1913                 }
1914
1915                 index++;
1916         }
1917
1918         return 0;
1919 }
1920
1921 static int stv0367ter_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1922 {
1923         struct stv0367_state *state = fe->demodulator_priv;
1924         struct stv0367ter_state *ter_state = state->ter_state;
1925         u32 errs = 0;
1926
1927         /*wait for counting completion*/
1928         if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0) {
1929                 errs =
1930                         ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
1931                         * (1 << 16))
1932                         + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
1933                         * (1 << 8))
1934                         + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
1935                 ter_state->ucblocks = errs;
1936         }
1937
1938         (*ucblocks) = ter_state->ucblocks;
1939
1940         return 0;
1941 }
1942
1943 static int stv0367ter_get_frontend(struct dvb_frontend *fe,
1944                                    struct dtv_frontend_properties *p)
1945 {
1946         struct stv0367_state *state = fe->demodulator_priv;
1947         struct stv0367ter_state *ter_state = state->ter_state;
1948         enum stv0367_ter_mode mode;
1949         int constell = 0,/* snr = 0,*/ Data = 0;
1950
1951         p->frequency = stv0367_get_tuner_freq(fe);
1952         if ((int)p->frequency < 0)
1953                 p->frequency = -p->frequency;
1954
1955         constell = stv0367_readbits(state, F367TER_TPS_CONST);
1956         if (constell == 0)
1957                 p->modulation = QPSK;
1958         else if (constell == 1)
1959                 p->modulation = QAM_16;
1960         else
1961                 p->modulation = QAM_64;
1962
1963         p->inversion = stv0367_readbits(state, F367TER_INV_SPECTR);
1964
1965         /* Get the Hierarchical mode */
1966         Data = stv0367_readbits(state, F367TER_TPS_HIERMODE);
1967
1968         switch (Data) {
1969         case 0:
1970                 p->hierarchy = HIERARCHY_NONE;
1971                 break;
1972         case 1:
1973                 p->hierarchy = HIERARCHY_1;
1974                 break;
1975         case 2:
1976                 p->hierarchy = HIERARCHY_2;
1977                 break;
1978         case 3:
1979                 p->hierarchy = HIERARCHY_4;
1980                 break;
1981         default:
1982                 p->hierarchy = HIERARCHY_AUTO;
1983                 break; /* error */
1984         }
1985
1986         /* Get the FEC Rate */
1987         if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO)
1988                 Data = stv0367_readbits(state, F367TER_TPS_LPCODE);
1989         else
1990                 Data = stv0367_readbits(state, F367TER_TPS_HPCODE);
1991
1992         switch (Data) {
1993         case 0:
1994                 p->code_rate_HP = FEC_1_2;
1995                 break;
1996         case 1:
1997                 p->code_rate_HP = FEC_2_3;
1998                 break;
1999         case 2:
2000                 p->code_rate_HP = FEC_3_4;
2001                 break;
2002         case 3:
2003                 p->code_rate_HP = FEC_5_6;
2004                 break;
2005         case 4:
2006                 p->code_rate_HP = FEC_7_8;
2007                 break;
2008         default:
2009                 p->code_rate_HP = FEC_AUTO;
2010                 break; /* error */
2011         }
2012
2013         mode = stv0367_readbits(state, F367TER_SYR_MODE);
2014
2015         switch (mode) {
2016         case FE_TER_MODE_2K:
2017                 p->transmission_mode = TRANSMISSION_MODE_2K;
2018                 break;
2019 /*      case FE_TER_MODE_4K:
2020                 p->transmission_mode = TRANSMISSION_MODE_4K;
2021                 break;*/
2022         case FE_TER_MODE_8K:
2023                 p->transmission_mode = TRANSMISSION_MODE_8K;
2024                 break;
2025         default:
2026                 p->transmission_mode = TRANSMISSION_MODE_AUTO;
2027         }
2028
2029         p->guard_interval = stv0367_readbits(state, F367TER_SYR_GUARD);
2030
2031         return 0;
2032 }
2033
2034 static int stv0367ter_read_snr(struct dvb_frontend *fe, u16 *snr)
2035 {
2036         struct stv0367_state *state = fe->demodulator_priv;
2037         u32 snru32 = 0;
2038         int cpt = 0;
2039         u8 cut = stv0367_readbits(state, F367TER_IDENTIFICATIONREG);
2040
2041         while (cpt < 10) {
2042                 usleep_range(2000, 3000);
2043                 if (cut == 0x50) /*cut 1.0 cut 1.1*/
2044                         snru32 += stv0367_readbits(state, F367TER_CHCSNR) / 4;
2045                 else /*cu2.0*/
2046                         snru32 += 125 * stv0367_readbits(state, F367TER_CHCSNR);
2047
2048                 cpt++;
2049         }
2050
2051         snru32 /= 10;/*average on 10 values*/
2052
2053         *snr = snru32 / 1000;
2054
2055         return 0;
2056 }
2057
2058 #if 0
2059 static int stv0367ter_status(struct dvb_frontend *fe)
2060 {
2061
2062         struct stv0367_state *state = fe->demodulator_priv;
2063         struct stv0367ter_state *ter_state = state->ter_state;
2064         int locked = FALSE;
2065
2066         locked = (stv0367_readbits(state, F367TER_LK));
2067         if (!locked)
2068                 ter_state->unlock_counter += 1;
2069         else
2070                 ter_state->unlock_counter = 0;
2071
2072         if (ter_state->unlock_counter > 2) {
2073                 if (!stv0367_readbits(state, F367TER_TPS_LOCK) ||
2074                                 (!stv0367_readbits(state, F367TER_LK))) {
2075                         stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
2076                         usleep_range(2000, 3000);
2077                         stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
2078                         msleep(350);
2079                         locked = (stv0367_readbits(state, F367TER_TPS_LOCK)) &&
2080                                         (stv0367_readbits(state, F367TER_LK));
2081                 }
2082
2083         }
2084
2085         return locked;
2086 }
2087 #endif
2088 static int stv0367ter_read_status(struct dvb_frontend *fe,
2089                                   enum fe_status *status)
2090 {
2091         struct stv0367_state *state = fe->demodulator_priv;
2092
2093         dprintk("%s:\n", __func__);
2094
2095         *status = 0;
2096
2097         if (stv0367_readbits(state, F367TER_LK)) {
2098                 *status |= FE_HAS_LOCK;
2099                 dprintk("%s: stv0367 has locked\n", __func__);
2100         }
2101
2102         return 0;
2103 }
2104
2105 static int stv0367ter_read_ber(struct dvb_frontend *fe, u32 *ber)
2106 {
2107         struct stv0367_state *state = fe->demodulator_priv;
2108         struct stv0367ter_state *ter_state = state->ter_state;
2109         u32 Errors = 0, tber = 0, temporary = 0;
2110         int abc = 0, def = 0;
2111
2112
2113         /*wait for counting completion*/
2114         if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0)
2115                 Errors = ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT)
2116                         * (1 << 16))
2117                         + ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT_HI)
2118                         * (1 << 8))
2119                         + ((u32)stv0367_readbits(state,
2120                                                 F367TER_SFEC_ERR_CNT_LO));
2121         /*measurement not completed, load previous value*/
2122         else {
2123                 tber = ter_state->pBER;
2124                 return 0;
2125         }
2126
2127         abc = stv0367_readbits(state, F367TER_SFEC_ERR_SOURCE);
2128         def = stv0367_readbits(state, F367TER_SFEC_NUM_EVENT);
2129
2130         if (Errors == 0) {
2131                 tber = 0;
2132         } else if (abc == 0x7) {
2133                 if (Errors <= 4) {
2134                         temporary = (Errors * 1000000000) / (8 * (1 << 14));
2135                         temporary =  temporary;
2136                 } else if (Errors <= 42) {
2137                         temporary = (Errors * 100000000) / (8 * (1 << 14));
2138                         temporary = temporary * 10;
2139                 } else if (Errors <= 429) {
2140                         temporary = (Errors * 10000000) / (8 * (1 << 14));
2141                         temporary = temporary * 100;
2142                 } else if (Errors <= 4294) {
2143                         temporary = (Errors * 1000000) / (8 * (1 << 14));
2144                         temporary = temporary * 1000;
2145                 } else if (Errors <= 42949) {
2146                         temporary = (Errors * 100000) / (8 * (1 << 14));
2147                         temporary = temporary * 10000;
2148                 } else if (Errors <= 429496) {
2149                         temporary = (Errors * 10000) / (8 * (1 << 14));
2150                         temporary = temporary * 100000;
2151                 } else { /*if (Errors<4294967) 2^22 max error*/
2152                         temporary = (Errors * 1000) / (8 * (1 << 14));
2153                         temporary = temporary * 100000; /* still to *10 */
2154                 }
2155
2156                 /* Byte error*/
2157                 if (def == 2)
2158                         /*tber=Errors/(8*(1 <<14));*/
2159                         tber = temporary;
2160                 else if (def == 3)
2161                         /*tber=Errors/(8*(1 <<16));*/
2162                         tber = temporary / 4;
2163                 else if (def == 4)
2164                         /*tber=Errors/(8*(1 <<18));*/
2165                         tber = temporary / 16;
2166                 else if (def == 5)
2167                         /*tber=Errors/(8*(1 <<20));*/
2168                         tber = temporary / 64;
2169                 else if (def == 6)
2170                         /*tber=Errors/(8*(1 <<22));*/
2171                         tber = temporary / 256;
2172                 else
2173                         /* should not pass here*/
2174                         tber = 0;
2175
2176                 if ((Errors < 4294967) && (Errors > 429496))
2177                         tber *= 10;
2178
2179         }
2180
2181         /* save actual value */
2182         ter_state->pBER = tber;
2183
2184         (*ber) = tber;
2185
2186         return 0;
2187 }
2188 #if 0
2189 static u32 stv0367ter_get_per(struct stv0367_state *state)
2190 {
2191         struct stv0367ter_state *ter_state = state->ter_state;
2192         u32 Errors = 0, Per = 0, temporary = 0;
2193         int abc = 0, def = 0, cpt = 0;
2194
2195         while (((stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 1) &&
2196                         (cpt < 400)) || ((Errors == 0) && (cpt < 400))) {
2197                 usleep_range(1000, 2000);
2198                 Errors = ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
2199                         * (1 << 16))
2200                         + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
2201                         * (1 << 8))
2202                         + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
2203                 cpt++;
2204         }
2205         abc = stv0367_readbits(state, F367TER_ERR_SRC1);
2206         def = stv0367_readbits(state, F367TER_NUM_EVT1);
2207
2208         if (Errors == 0)
2209                 Per = 0;
2210         else if (abc == 0x9) {
2211                 if (Errors <= 4) {
2212                         temporary = (Errors * 1000000000) / (8 * (1 << 8));
2213                         temporary =  temporary;
2214                 } else if (Errors <= 42) {
2215                         temporary = (Errors * 100000000) / (8 * (1 << 8));
2216                         temporary = temporary * 10;
2217                 } else if (Errors <= 429) {
2218                         temporary = (Errors * 10000000) / (8 * (1 << 8));
2219                         temporary = temporary * 100;
2220                 } else if (Errors <= 4294) {
2221                         temporary = (Errors * 1000000) / (8 * (1 << 8));
2222                         temporary = temporary * 1000;
2223                 } else if (Errors <= 42949) {
2224                         temporary = (Errors * 100000) / (8 * (1 << 8));
2225                         temporary = temporary * 10000;
2226                 } else { /*if(Errors<=429496)  2^16 errors max*/
2227                         temporary = (Errors * 10000) / (8 * (1 << 8));
2228                         temporary = temporary * 100000;
2229                 }
2230
2231                 /* pkt error*/
2232                 if (def == 2)
2233                         /*Per=Errors/(1 << 8);*/
2234                         Per = temporary;
2235                 else if (def == 3)
2236                         /*Per=Errors/(1 << 10);*/
2237                         Per = temporary / 4;
2238                 else if (def == 4)
2239                         /*Per=Errors/(1 << 12);*/
2240                         Per = temporary / 16;
2241                 else if (def == 5)
2242                         /*Per=Errors/(1 << 14);*/
2243                         Per = temporary / 64;
2244                 else if (def == 6)
2245                         /*Per=Errors/(1 << 16);*/
2246                         Per = temporary / 256;
2247                 else
2248                         Per = 0;
2249
2250         }
2251         /* save actual value */
2252         ter_state->pPER = Per;
2253
2254         return Per;
2255 }
2256 #endif
2257 static int stv0367_get_tune_settings(struct dvb_frontend *fe,
2258                                         struct dvb_frontend_tune_settings
2259                                         *fe_tune_settings)
2260 {
2261         fe_tune_settings->min_delay_ms = 1000;
2262         fe_tune_settings->step_size = 0;
2263         fe_tune_settings->max_drift = 0;
2264
2265         return 0;
2266 }
2267
2268 static void stv0367_release(struct dvb_frontend *fe)
2269 {
2270         struct stv0367_state *state = fe->demodulator_priv;
2271
2272         kfree(state->ter_state);
2273         kfree(state->cab_state);
2274         kfree(state);
2275 }
2276
2277 static struct dvb_frontend_ops stv0367ter_ops = {
2278         .delsys = { SYS_DVBT },
2279         .info = {
2280                 .name                   = "ST STV0367 DVB-T",
2281                 .frequency_min          = 47000000,
2282                 .frequency_max          = 862000000,
2283                 .frequency_stepsize     = 15625,
2284                 .frequency_tolerance    = 0,
2285                 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
2286                         FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
2287                         FE_CAN_FEC_AUTO |
2288                         FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
2289                         FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_QAM_AUTO |
2290                         FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
2291                         FE_CAN_INVERSION_AUTO |
2292                         FE_CAN_MUTE_TS
2293         },
2294         .release = stv0367_release,
2295         .init = stv0367ter_init,
2296         .sleep = stv0367ter_sleep,
2297         .i2c_gate_ctrl = stv0367ter_gate_ctrl,
2298         .set_frontend = stv0367ter_set_frontend,
2299         .get_frontend = stv0367ter_get_frontend,
2300         .get_tune_settings = stv0367_get_tune_settings,
2301         .read_status = stv0367ter_read_status,
2302         .read_ber = stv0367ter_read_ber,/* too slow */
2303 /*      .read_signal_strength = stv0367_read_signal_strength,*/
2304         .read_snr = stv0367ter_read_snr,
2305         .read_ucblocks = stv0367ter_read_ucblocks,
2306 };
2307
2308 struct dvb_frontend *stv0367ter_attach(const struct stv0367_config *config,
2309                                    struct i2c_adapter *i2c)
2310 {
2311         struct stv0367_state *state = NULL;
2312         struct stv0367ter_state *ter_state = NULL;
2313
2314         /* allocate memory for the internal state */
2315         state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
2316         if (state == NULL)
2317                 goto error;
2318         ter_state = kzalloc(sizeof(struct stv0367ter_state), GFP_KERNEL);
2319         if (ter_state == NULL)
2320                 goto error;
2321
2322         /* setup the state */
2323         state->i2c = i2c;
2324         state->config = config;
2325         state->ter_state = ter_state;
2326         state->fe.ops = stv0367ter_ops;
2327         state->fe.demodulator_priv = state;
2328         state->chip_id = stv0367_readreg(state, 0xf000);
2329
2330         dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
2331
2332         /* check if the demod is there */
2333         if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
2334                 goto error;
2335
2336         return &state->fe;
2337
2338 error:
2339         kfree(ter_state);
2340         kfree(state);
2341         return NULL;
2342 }
2343 EXPORT_SYMBOL(stv0367ter_attach);
2344
2345 static int stv0367cab_gate_ctrl(struct dvb_frontend *fe, int enable)
2346 {
2347         struct stv0367_state *state = fe->demodulator_priv;
2348
2349         dprintk("%s:\n", __func__);
2350
2351         stv0367_writebits(state, F367CAB_I2CT_ON, (enable > 0) ? 1 : 0);
2352
2353         return 0;
2354 }
2355
2356 static u32 stv0367cab_get_mclk(struct dvb_frontend *fe, u32 ExtClk_Hz)
2357 {
2358         struct stv0367_state *state = fe->demodulator_priv;
2359         u32 mclk_Hz = 0;/* master clock frequency (Hz) */
2360         u32 M, N, P;
2361
2362
2363         if (stv0367_readbits(state, F367CAB_BYPASS_PLLXN) == 0) {
2364                 N = (u32)stv0367_readbits(state, F367CAB_PLL_NDIV);
2365                 if (N == 0)
2366                         N = N + 1;
2367
2368                 M = (u32)stv0367_readbits(state, F367CAB_PLL_MDIV);
2369                 if (M == 0)
2370                         M = M + 1;
2371
2372                 P = (u32)stv0367_readbits(state, F367CAB_PLL_PDIV);
2373
2374                 if (P > 5)
2375                         P = 5;
2376
2377                 mclk_Hz = ((ExtClk_Hz / 2) * N) / (M * (1 << P));
2378                 dprintk("stv0367cab_get_mclk BYPASS_PLLXN mclk_Hz=%d\n",
2379                                                                 mclk_Hz);
2380         } else
2381                 mclk_Hz = ExtClk_Hz;
2382
2383         dprintk("stv0367cab_get_mclk final mclk_Hz=%d\n", mclk_Hz);
2384
2385         return mclk_Hz;
2386 }
2387
2388 static u32 stv0367cab_get_adc_freq(struct dvb_frontend *fe, u32 ExtClk_Hz)
2389 {
2390         u32 ADCClk_Hz = ExtClk_Hz;
2391
2392         ADCClk_Hz = stv0367cab_get_mclk(fe, ExtClk_Hz);
2393
2394         return ADCClk_Hz;
2395 }
2396
2397 static enum stv0367cab_mod stv0367cab_SetQamSize(struct stv0367_state *state,
2398                                                  u32 SymbolRate,
2399                                                  enum stv0367cab_mod QAMSize)
2400 {
2401         /* Set QAM size */
2402         stv0367_writebits(state, F367CAB_QAM_MODE, QAMSize);
2403
2404         /* Set Registers settings specific to the QAM size */
2405         switch (QAMSize) {
2406         case FE_CAB_MOD_QAM4:
2407                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2408                 break;
2409         case FE_CAB_MOD_QAM16:
2410                 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x64);
2411                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2412                 stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
2413                 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2414                 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
2415                 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
2416                 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
2417                 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x8a);
2418                 break;
2419         case FE_CAB_MOD_QAM32:
2420                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2421                 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x6e);
2422                 stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
2423                 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2424                 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xb7);
2425                 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x9d);
2426                 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
2427                 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
2428                 break;
2429         case FE_CAB_MOD_QAM64:
2430                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x82);
2431                 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
2432                 if (SymbolRate > 45000000) {
2433                         stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
2434                         stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2435                         stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa5);
2436                 } else if (SymbolRate > 25000000) {
2437                         stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
2438                         stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2439                         stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
2440                 } else {
2441                         stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
2442                         stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
2443                         stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
2444                 }
2445                 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
2446                 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
2447                 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x99);
2448                 break;
2449         case FE_CAB_MOD_QAM128:
2450                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2451                 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x76);
2452                 stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
2453                 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xb1);
2454                 if (SymbolRate > 45000000)
2455                         stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
2456                 else if (SymbolRate > 25000000)
2457                         stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
2458                 else
2459                         stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0x97);
2460
2461                 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x8e);
2462                 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
2463                 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
2464                 break;
2465         case FE_CAB_MOD_QAM256:
2466                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x94);
2467                 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
2468                 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
2469                 if (SymbolRate > 45000000)
2470                         stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2471                 else if (SymbolRate > 25000000)
2472                         stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2473                 else
2474                         stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
2475
2476                 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
2477                 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x85);
2478                 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
2479                 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
2480                 break;
2481         case FE_CAB_MOD_QAM512:
2482                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2483                 break;
2484         case FE_CAB_MOD_QAM1024:
2485                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2486                 break;
2487         default:
2488                 break;
2489         }
2490
2491         return QAMSize;
2492 }
2493
2494 static u32 stv0367cab_set_derot_freq(struct stv0367_state *state,
2495                                         u32 adc_hz, s32 derot_hz)
2496 {
2497         u32 sampled_if = 0;
2498         u32 adc_khz;
2499
2500         adc_khz = adc_hz / 1000;
2501
2502         dprintk("%s: adc_hz=%d derot_hz=%d\n", __func__, adc_hz, derot_hz);
2503
2504         if (adc_khz != 0) {
2505                 if (derot_hz < 1000000)
2506                         derot_hz = adc_hz / 4; /* ZIF operation */
2507                 if (derot_hz > adc_hz)
2508                         derot_hz = derot_hz - adc_hz;
2509                 sampled_if = (u32)derot_hz / 1000;
2510                 sampled_if *= 32768;
2511                 sampled_if /= adc_khz;
2512                 sampled_if *= 256;
2513         }
2514
2515         if (sampled_if > 8388607)
2516                 sampled_if = 8388607;
2517
2518         dprintk("%s: sampled_if=0x%x\n", __func__, sampled_if);
2519
2520         stv0367_writereg(state, R367CAB_MIX_NCO_LL, sampled_if);
2521         stv0367_writereg(state, R367CAB_MIX_NCO_HL, (sampled_if >> 8));
2522         stv0367_writebits(state, F367CAB_MIX_NCO_INC_HH, (sampled_if >> 16));
2523
2524         return derot_hz;
2525 }
2526
2527 static u32 stv0367cab_get_derot_freq(struct stv0367_state *state, u32 adc_hz)
2528 {
2529         u32 sampled_if;
2530
2531         sampled_if = stv0367_readbits(state, F367CAB_MIX_NCO_INC_LL) +
2532                         (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HL) << 8) +
2533                         (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HH) << 16);
2534
2535         sampled_if /= 256;
2536         sampled_if *= (adc_hz / 1000);
2537         sampled_if += 1;
2538         sampled_if /= 32768;
2539
2540         return sampled_if;
2541 }
2542
2543 static u32 stv0367cab_set_srate(struct stv0367_state *state, u32 adc_hz,
2544                         u32 mclk_hz, u32 SymbolRate,
2545                         enum stv0367cab_mod QAMSize)
2546 {
2547         u32 QamSizeCorr = 0;
2548         u32 u32_tmp = 0, u32_tmp1 = 0;
2549         u32 adp_khz;
2550
2551         dprintk("%s:\n", __func__);
2552
2553         /* Set Correction factor of SRC gain */
2554         switch (QAMSize) {
2555         case FE_CAB_MOD_QAM4:
2556                 QamSizeCorr = 1110;
2557                 break;
2558         case FE_CAB_MOD_QAM16:
2559                 QamSizeCorr = 1032;
2560                 break;
2561         case FE_CAB_MOD_QAM32:
2562                 QamSizeCorr =  954;
2563                 break;
2564         case FE_CAB_MOD_QAM64:
2565                 QamSizeCorr =  983;
2566                 break;
2567         case FE_CAB_MOD_QAM128:
2568                 QamSizeCorr =  957;
2569                 break;
2570         case FE_CAB_MOD_QAM256:
2571                 QamSizeCorr =  948;
2572                 break;
2573         case FE_CAB_MOD_QAM512:
2574                 QamSizeCorr =    0;
2575                 break;
2576         case FE_CAB_MOD_QAM1024:
2577                 QamSizeCorr =  944;
2578                 break;
2579         default:
2580                 break;
2581         }
2582
2583         /* Transfer ratio calculation */
2584         if (adc_hz != 0) {
2585                 u32_tmp = 256 * SymbolRate;
2586                 u32_tmp = u32_tmp / adc_hz;
2587         }
2588         stv0367_writereg(state, R367CAB_EQU_CRL_TFR, (u8)u32_tmp);
2589
2590         /* Symbol rate and SRC gain calculation */
2591         adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */
2592         if (adp_khz != 0) {
2593                 u32_tmp = SymbolRate;
2594                 u32_tmp1 = SymbolRate;
2595
2596                 if (u32_tmp < 2097152) { /* 2097152 = 2^21 */
2597                         /* Symbol rate calculation */
2598                         u32_tmp *= 2048; /* 2048 = 2^11 */
2599                         u32_tmp = u32_tmp / adp_khz;
2600                         u32_tmp = u32_tmp * 16384; /* 16384 = 2^14 */
2601                         u32_tmp /= 125 ; /* 125 = 1000/2^3 */
2602                         u32_tmp = u32_tmp * 8; /* 8 = 2^3 */
2603
2604                         /* SRC Gain Calculation */
2605                         u32_tmp1 *= 2048; /* *2*2^10 */
2606                         u32_tmp1 /= 439; /* *2/878 */
2607                         u32_tmp1 *= 256; /* *2^8 */
2608                         u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2609                         u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2610                         u32_tmp1 = u32_tmp1 / 10000000;
2611
2612                 } else if (u32_tmp < 4194304) { /* 4194304 = 2**22 */
2613                         /* Symbol rate calculation */
2614                         u32_tmp *= 1024 ; /* 1024 = 2**10 */
2615                         u32_tmp = u32_tmp / adp_khz;
2616                         u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */
2617                         u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2618                         u32_tmp = u32_tmp * 16; /* 16 = 2**4 */
2619
2620                         /* SRC Gain Calculation */
2621                         u32_tmp1 *= 1024; /* *2*2^9 */
2622                         u32_tmp1 /= 439; /* *2/878 */
2623                         u32_tmp1 *= 256; /* *2^8 */
2624                         u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz)*/
2625                         u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2626                         u32_tmp1 = u32_tmp1 / 5000000;
2627                 } else if (u32_tmp < 8388607) { /* 8388607 = 2**23 */
2628                         /* Symbol rate calculation */
2629                         u32_tmp *= 512 ; /* 512 = 2**9 */
2630                         u32_tmp = u32_tmp / adp_khz;
2631                         u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */
2632                         u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2633                         u32_tmp = u32_tmp * 32; /* 32 = 2**5 */
2634
2635                         /* SRC Gain Calculation */
2636                         u32_tmp1 *= 512; /* *2*2^8 */
2637                         u32_tmp1 /= 439; /* *2/878 */
2638                         u32_tmp1 *= 256; /* *2^8 */
2639                         u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2640                         u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2641                         u32_tmp1 = u32_tmp1 / 2500000;
2642                 } else {
2643                         /* Symbol rate calculation */
2644                         u32_tmp *= 256 ; /* 256 = 2**8 */
2645                         u32_tmp = u32_tmp / adp_khz;
2646                         u32_tmp = u32_tmp * 16384; /* 16384 = 2**13 */
2647                         u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2648                         u32_tmp = u32_tmp * 64; /* 64 = 2**6 */
2649
2650                         /* SRC Gain Calculation */
2651                         u32_tmp1 *= 256; /* 2*2^7 */
2652                         u32_tmp1 /= 439; /* *2/878 */
2653                         u32_tmp1 *= 256; /* *2^8 */
2654                         u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2655                         u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2656                         u32_tmp1 = u32_tmp1 / 1250000;
2657                 }
2658         }
2659 #if 0
2660         /* Filters' coefficients are calculated and written
2661         into registers only if the filters are enabled */
2662         if (stv0367_readbits(state, F367CAB_ADJ_EN)) {
2663                 stv0367cab_SetIirAdjacentcoefficient(state, mclk_hz,
2664                                                                 SymbolRate);
2665                 /* AllPass filter must be enabled
2666                 when the adjacents filter is used */
2667                 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 1);
2668                 stv0367cab_SetAllPasscoefficient(state, mclk_hz, SymbolRate);
2669         } else
2670                 /* AllPass filter must be disabled
2671                 when the adjacents filter is not used */
2672 #endif
2673         stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
2674
2675         stv0367_writereg(state, R367CAB_SRC_NCO_LL, u32_tmp);
2676         stv0367_writereg(state, R367CAB_SRC_NCO_LH, (u32_tmp >> 8));
2677         stv0367_writereg(state, R367CAB_SRC_NCO_HL, (u32_tmp >> 16));
2678         stv0367_writereg(state, R367CAB_SRC_NCO_HH, (u32_tmp >> 24));
2679
2680         stv0367_writereg(state, R367CAB_IQDEM_GAIN_SRC_L, u32_tmp1 & 0x00ff);
2681         stv0367_writebits(state, F367CAB_GAIN_SRC_HI, (u32_tmp1 >> 8) & 0x00ff);
2682
2683         return SymbolRate ;
2684 }
2685
2686 static u32 stv0367cab_GetSymbolRate(struct stv0367_state *state, u32 mclk_hz)
2687 {
2688         u32 regsym;
2689         u32 adp_khz;
2690
2691         regsym = stv0367_readreg(state, R367CAB_SRC_NCO_LL) +
2692                 (stv0367_readreg(state, R367CAB_SRC_NCO_LH) << 8) +
2693                 (stv0367_readreg(state, R367CAB_SRC_NCO_HL) << 16) +
2694                 (stv0367_readreg(state, R367CAB_SRC_NCO_HH) << 24);
2695
2696         adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */
2697
2698         if (regsym < 134217728) {               /* 134217728L = 2**27*/
2699                 regsym = regsym * 32;           /* 32 = 2**5 */
2700                 regsym = regsym / 32768;        /* 32768L = 2**15 */
2701                 regsym = adp_khz * regsym;      /* AdpClk in kHz */
2702                 regsym = regsym / 128;          /* 128 = 2**7 */
2703                 regsym *= 125 ;                 /* 125 = 1000/2**3 */
2704                 regsym /= 2048 ;                /* 2048 = 2**11 */
2705         } else if (regsym < 268435456) {        /* 268435456L = 2**28 */
2706                 regsym = regsym * 16;           /* 16 = 2**4 */
2707                 regsym = regsym / 32768;        /* 32768L = 2**15 */
2708                 regsym = adp_khz * regsym;      /* AdpClk in kHz */
2709                 regsym = regsym / 128;          /* 128 = 2**7 */
2710                 regsym *= 125 ;                 /* 125 = 1000/2**3*/
2711                 regsym /= 1024 ;                /* 256 = 2**10*/
2712         } else if (regsym < 536870912) {        /* 536870912L = 2**29*/
2713                 regsym = regsym * 8;            /* 8 = 2**3 */
2714                 regsym = regsym / 32768;        /* 32768L = 2**15 */
2715                 regsym = adp_khz * regsym;      /* AdpClk in kHz */
2716                 regsym = regsym / 128;          /* 128 = 2**7 */
2717                 regsym *= 125 ;                 /* 125 = 1000/2**3 */
2718                 regsym /= 512 ;                 /* 128 = 2**9 */
2719         } else {
2720                 regsym = regsym * 4;            /* 4 = 2**2 */
2721                 regsym = regsym / 32768;        /* 32768L = 2**15 */
2722                 regsym = adp_khz * regsym;      /* AdpClk in kHz */
2723                 regsym = regsym / 128;          /* 128 = 2**7 */
2724                 regsym *= 125 ;                 /* 125 = 1000/2**3 */
2725                 regsym /= 256 ;                 /* 64 = 2**8 */
2726         }
2727
2728         return regsym;
2729 }
2730
2731 static int stv0367cab_read_status(struct dvb_frontend *fe,
2732                                   enum fe_status *status)
2733 {
2734         struct stv0367_state *state = fe->demodulator_priv;
2735
2736         dprintk("%s:\n", __func__);
2737
2738         *status = 0;
2739
2740         if (stv0367_readbits(state, F367CAB_QAMFEC_LOCK)) {
2741                 *status |= FE_HAS_LOCK;
2742                 dprintk("%s: stv0367 has locked\n", __func__);
2743         }
2744
2745         return 0;
2746 }
2747
2748 static int stv0367cab_standby(struct dvb_frontend *fe, u8 standby_on)
2749 {
2750         struct stv0367_state *state = fe->demodulator_priv;
2751
2752         dprintk("%s:\n", __func__);
2753
2754         if (standby_on) {
2755                 stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x03);
2756                 stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x01);
2757                 stv0367_writebits(state, F367CAB_STDBY, 1);
2758                 stv0367_writebits(state, F367CAB_STDBY_CORE, 1);
2759                 stv0367_writebits(state, F367CAB_EN_BUFFER_I, 0);
2760                 stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 0);
2761                 stv0367_writebits(state, F367CAB_POFFQ, 1);
2762                 stv0367_writebits(state, F367CAB_POFFI, 1);
2763         } else {
2764                 stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x00);
2765                 stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x00);
2766                 stv0367_writebits(state, F367CAB_STDBY, 0);
2767                 stv0367_writebits(state, F367CAB_STDBY_CORE, 0);
2768                 stv0367_writebits(state, F367CAB_EN_BUFFER_I, 1);
2769                 stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 1);
2770                 stv0367_writebits(state, F367CAB_POFFQ, 0);
2771                 stv0367_writebits(state, F367CAB_POFFI, 0);
2772         }
2773
2774         return 0;
2775 }
2776
2777 static int stv0367cab_sleep(struct dvb_frontend *fe)
2778 {
2779         return stv0367cab_standby(fe, 1);
2780 }
2781
2782 static int stv0367cab_init(struct dvb_frontend *fe)
2783 {
2784         struct stv0367_state *state = fe->demodulator_priv;
2785         struct stv0367cab_state *cab_state = state->cab_state;
2786         int i;
2787
2788         dprintk("%s:\n", __func__);
2789
2790         for (i = 0; i < STV0367CAB_NBREGS; i++)
2791                 stv0367_writereg(state, def0367cab[i].addr,
2792                                                 def0367cab[i].value);
2793
2794         switch (state->config->ts_mode) {
2795         case STV0367_DVBCI_CLOCK:
2796                 dprintk("Setting TSMode = STV0367_DVBCI_CLOCK\n");
2797                 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x03);
2798                 break;
2799         case STV0367_SERIAL_PUNCT_CLOCK:
2800         case STV0367_SERIAL_CONT_CLOCK:
2801                 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x01);
2802                 break;
2803         case STV0367_PARALLEL_PUNCT_CLOCK:
2804         case STV0367_OUTPUTMODE_DEFAULT:
2805                 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x00);
2806                 break;
2807         }
2808
2809         switch (state->config->clk_pol) {
2810         case STV0367_RISINGEDGE_CLOCK:
2811                 stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x00);
2812                 break;
2813         case STV0367_FALLINGEDGE_CLOCK:
2814         case STV0367_CLOCKPOLARITY_DEFAULT:
2815                 stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x01);
2816                 break;
2817         }
2818
2819         stv0367_writebits(state, F367CAB_SYNC_STRIP, 0x00);
2820
2821         stv0367_writebits(state, F367CAB_CT_NBST, 0x01);
2822
2823         stv0367_writebits(state, F367CAB_TS_SWAP, 0x01);
2824
2825         stv0367_writebits(state, F367CAB_FIFO_BYPASS, 0x00);
2826
2827         stv0367_writereg(state, R367CAB_ANACTRL, 0x00);/*PLL enabled and used */
2828
2829         cab_state->mclk = stv0367cab_get_mclk(fe, state->config->xtal);
2830         cab_state->adc_clk = stv0367cab_get_adc_freq(fe, state->config->xtal);
2831
2832         return 0;
2833 }
2834 static
2835 enum stv0367_cab_signal_type stv0367cab_algo(struct stv0367_state *state,
2836                                              struct dtv_frontend_properties *p)
2837 {
2838         struct stv0367cab_state *cab_state = state->cab_state;
2839         enum stv0367_cab_signal_type signalType = FE_CAB_NOAGC;
2840         u32     QAMFEC_Lock, QAM_Lock, u32_tmp,
2841                 LockTime, TRLTimeOut, AGCTimeOut, CRLSymbols,
2842                 CRLTimeOut, EQLTimeOut, DemodTimeOut, FECTimeOut;
2843         u8      TrackAGCAccum;
2844         s32     tmp;
2845
2846         dprintk("%s:\n", __func__);
2847
2848         /* Timeouts calculation */
2849         /* A max lock time of 25 ms is allowed for delayed AGC */
2850         AGCTimeOut = 25;
2851         /* 100000 symbols needed by the TRL as a maximum value */
2852         TRLTimeOut = 100000000 / p->symbol_rate;
2853         /* CRLSymbols is the needed number of symbols to achieve a lock
2854            within [-4%, +4%] of the symbol rate.
2855            CRL timeout is calculated
2856            for a lock within [-search_range, +search_range].
2857            EQL timeout can be changed depending on
2858            the micro-reflections we want to handle.
2859            A characterization must be performed
2860            with these echoes to get new timeout values.
2861         */
2862         switch (p->modulation) {
2863         case QAM_16:
2864                 CRLSymbols = 150000;
2865                 EQLTimeOut = 100;
2866                 break;
2867         case QAM_32:
2868                 CRLSymbols = 250000;
2869                 EQLTimeOut = 100;
2870                 break;
2871         case QAM_64:
2872                 CRLSymbols = 200000;
2873                 EQLTimeOut = 100;
2874                 break;
2875         case QAM_128:
2876                 CRLSymbols = 250000;
2877                 EQLTimeOut = 100;
2878                 break;
2879         case QAM_256:
2880                 CRLSymbols = 250000;
2881                 EQLTimeOut = 100;
2882                 break;
2883         default:
2884                 CRLSymbols = 200000;
2885                 EQLTimeOut = 100;
2886                 break;
2887         }
2888 #if 0
2889         if (pIntParams->search_range < 0) {
2890                 CRLTimeOut = (25 * CRLSymbols *
2891                                 (-pIntParams->search_range / 1000)) /
2892                                         (pIntParams->symbol_rate / 1000);
2893         } else
2894 #endif
2895         CRLTimeOut = (25 * CRLSymbols * (cab_state->search_range / 1000)) /
2896                                         (p->symbol_rate / 1000);
2897
2898         CRLTimeOut = (1000 * CRLTimeOut) / p->symbol_rate;
2899         /* Timeouts below 50ms are coerced */
2900         if (CRLTimeOut < 50)
2901                 CRLTimeOut = 50;
2902         /* A maximum of 100 TS packets is needed to get FEC lock even in case
2903         the spectrum inversion needs to be changed.
2904            This is equal to 20 ms in case of the lowest symbol rate of 0.87Msps
2905         */
2906         FECTimeOut = 20;
2907         DemodTimeOut = AGCTimeOut + TRLTimeOut + CRLTimeOut + EQLTimeOut;
2908
2909         dprintk("%s: DemodTimeOut=%d\n", __func__, DemodTimeOut);
2910
2911         /* Reset the TRL to ensure nothing starts until the
2912            AGC is stable which ensures a better lock time
2913         */
2914         stv0367_writereg(state, R367CAB_CTRL_1, 0x04);
2915         /* Set AGC accumulation time to minimum and lock threshold to maximum
2916         in order to speed up the AGC lock */
2917         TrackAGCAccum = stv0367_readbits(state, F367CAB_AGC_ACCUMRSTSEL);
2918         stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, 0x0);
2919         /* Modulus Mapper is disabled */
2920         stv0367_writebits(state, F367CAB_MODULUSMAP_EN, 0);
2921         /* Disable the sweep function */
2922         stv0367_writebits(state, F367CAB_SWEEP_EN, 0);
2923         /* The sweep function is never used, Sweep rate must be set to 0 */
2924         /* Set the derotator frequency in Hz */
2925         stv0367cab_set_derot_freq(state, cab_state->adc_clk,
2926                 (1000 * (s32)state->config->if_khz + cab_state->derot_offset));
2927         /* Disable the Allpass Filter when the symbol rate is out of range */
2928         if ((p->symbol_rate > 10800000) | (p->symbol_rate < 1800000)) {
2929                 stv0367_writebits(state, F367CAB_ADJ_EN, 0);
2930                 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
2931         }
2932 #if 0
2933         /* Check if the tuner is locked */
2934         tuner_lock = stv0367cab_tuner_get_status(fe);
2935         if (tuner_lock == 0)
2936                 return FE_367CAB_NOTUNER;
2937 #endif
2938         /* Release the TRL to start demodulator acquisition */
2939         /* Wait for QAM lock */
2940         LockTime = 0;
2941         stv0367_writereg(state, R367CAB_CTRL_1, 0x00);
2942         do {
2943                 QAM_Lock = stv0367_readbits(state, F367CAB_FSM_STATUS);
2944                 if ((LockTime >= (DemodTimeOut - EQLTimeOut)) &&
2945                                                         (QAM_Lock == 0x04))
2946                         /*
2947                          * We don't wait longer, the frequency/phase offset
2948                          * must be too big
2949                          */
2950                         LockTime = DemodTimeOut;
2951                 else if ((LockTime >= (AGCTimeOut + TRLTimeOut)) &&
2952                                                         (QAM_Lock == 0x02))
2953                         /*
2954                          * We don't wait longer, either there is no signal or
2955                          * it is not the right symbol rate or it is an analog
2956                          * carrier
2957                          */
2958                 {
2959                         LockTime = DemodTimeOut;
2960                         u32_tmp = stv0367_readbits(state,
2961                                                 F367CAB_AGC_PWR_WORD_LO) +
2962                                         (stv0367_readbits(state,
2963                                                 F367CAB_AGC_PWR_WORD_ME) << 8) +
2964                                         (stv0367_readbits(state,
2965                                                 F367CAB_AGC_PWR_WORD_HI) << 16);
2966                         if (u32_tmp >= 131072)
2967                                 u32_tmp = 262144 - u32_tmp;
2968                         u32_tmp = u32_tmp / (1 << (11 - stv0367_readbits(state,
2969                                                         F367CAB_AGC_IF_BWSEL)));
2970
2971                         if (u32_tmp < stv0367_readbits(state,
2972                                                 F367CAB_AGC_PWRREF_LO) +
2973                                         256 * stv0367_readbits(state,
2974                                                 F367CAB_AGC_PWRREF_HI) - 10)
2975                                 QAM_Lock = 0x0f;
2976                 } else {
2977                         usleep_range(10000, 20000);
2978                         LockTime += 10;
2979                 }
2980                 dprintk("QAM_Lock=0x%x LockTime=%d\n", QAM_Lock, LockTime);
2981                 tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
2982
2983                 dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp);
2984
2985         } while (((QAM_Lock != 0x0c) && (QAM_Lock != 0x0b)) &&
2986                                                 (LockTime < DemodTimeOut));
2987
2988         dprintk("QAM_Lock=0x%x\n", QAM_Lock);
2989
2990         tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
2991         dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp);
2992         tmp = stv0367_readreg(state, R367CAB_IT_STATUS2);
2993         dprintk("R367CAB_IT_STATUS2=0x%x\n", tmp);
2994
2995         tmp  = stv0367cab_get_derot_freq(state, cab_state->adc_clk);
2996         dprintk("stv0367cab_get_derot_freq=0x%x\n", tmp);
2997
2998         if ((QAM_Lock == 0x0c) || (QAM_Lock == 0x0b)) {
2999                 /* Wait for FEC lock */
3000                 LockTime = 0;
3001                 do {
3002                         usleep_range(5000, 7000);
3003                         LockTime += 5;
3004                         QAMFEC_Lock = stv0367_readbits(state,
3005                                                         F367CAB_QAMFEC_LOCK);
3006                 } while (!QAMFEC_Lock && (LockTime < FECTimeOut));
3007         } else
3008                 QAMFEC_Lock = 0;
3009
3010         if (QAMFEC_Lock) {
3011                 signalType = FE_CAB_DATAOK;
3012                 cab_state->spect_inv = stv0367_readbits(state,
3013                                                         F367CAB_QUAD_INV);
3014 #if 0
3015 /* not clear for me */
3016                 if (state->config->if_khz != 0) {
3017                         if (state->config->if_khz > cab_state->adc_clk / 1000) {
3018                                 cab_state->freq_khz =
3019                                         FE_Cab_TunerGetFrequency(pIntParams->hTuner)
3020                                 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
3021                                 - cab_state->adc_clk / 1000 + state->config->if_khz;
3022                         } else {
3023                                 cab_state->freq_khz =
3024                                                 FE_Cab_TunerGetFrequency(pIntParams->hTuner)
3025                                                 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
3026                                                                                 + state->config->if_khz;
3027                         }
3028                 } else {
3029                         cab_state->freq_khz =
3030                                 FE_Cab_TunerGetFrequency(pIntParams->hTuner) +
3031                                 stv0367cab_get_derot_freq(state,
3032                                                         cab_state->adc_clk) -
3033                                 cab_state->adc_clk / 4000;
3034                 }
3035 #endif
3036                 cab_state->symbol_rate = stv0367cab_GetSymbolRate(state,
3037                                                         cab_state->mclk);
3038                 cab_state->locked = 1;
3039
3040                 /* stv0367_setbits(state, F367CAB_AGC_ACCUMRSTSEL,7);*/
3041         } else {
3042                 switch (QAM_Lock) {
3043                 case 1:
3044                         signalType = FE_CAB_NOAGC;
3045                         break;
3046                 case 2:
3047                         signalType = FE_CAB_NOTIMING;
3048                         break;
3049                 case 3:
3050                         signalType = FE_CAB_TIMINGOK;
3051                         break;
3052                 case 4:
3053                         signalType = FE_CAB_NOCARRIER;
3054                         break;
3055                 case 5:
3056                         signalType = FE_CAB_CARRIEROK;
3057                         break;
3058                 case 7:
3059                         signalType = FE_CAB_NOBLIND;
3060                         break;
3061                 case 8:
3062                         signalType = FE_CAB_BLINDOK;
3063                         break;
3064                 case 10:
3065                         signalType = FE_CAB_NODEMOD;
3066                         break;
3067                 case 11:
3068                         signalType = FE_CAB_DEMODOK;
3069                         break;
3070                 case 12:
3071                         signalType = FE_CAB_DEMODOK;
3072                         break;
3073                 case 13:
3074                         signalType = FE_CAB_NODEMOD;
3075                         break;
3076                 case 14:
3077                         signalType = FE_CAB_NOBLIND;
3078                         break;
3079                 case 15:
3080                         signalType = FE_CAB_NOSIGNAL;
3081                         break;
3082                 default:
3083                         break;
3084                 }
3085
3086         }
3087
3088         /* Set the AGC control values to tracking values */
3089         stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, TrackAGCAccum);
3090         return signalType;
3091 }
3092
3093 static int stv0367cab_set_frontend(struct dvb_frontend *fe)
3094 {
3095         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3096         struct stv0367_state *state = fe->demodulator_priv;
3097         struct stv0367cab_state *cab_state = state->cab_state;
3098         enum stv0367cab_mod QAMSize = 0;
3099
3100         dprintk("%s: freq = %d, srate = %d\n", __func__,
3101                                         p->frequency, p->symbol_rate);
3102
3103         cab_state->derot_offset = 0;
3104
3105         switch (p->modulation) {
3106         case QAM_16:
3107                 QAMSize = FE_CAB_MOD_QAM16;
3108                 break;
3109         case QAM_32:
3110                 QAMSize = FE_CAB_MOD_QAM32;
3111                 break;
3112         case QAM_64:
3113                 QAMSize = FE_CAB_MOD_QAM64;
3114                 break;
3115         case QAM_128:
3116                 QAMSize = FE_CAB_MOD_QAM128;
3117                 break;
3118         case QAM_256:
3119                 QAMSize = FE_CAB_MOD_QAM256;
3120                 break;
3121         default:
3122                 break;
3123         }
3124
3125         stv0367cab_init(fe);
3126
3127         /* Tuner Frequency Setting */
3128         if (fe->ops.tuner_ops.set_params) {
3129                 if (fe->ops.i2c_gate_ctrl)
3130                         fe->ops.i2c_gate_ctrl(fe, 1);
3131                 fe->ops.tuner_ops.set_params(fe);
3132                 if (fe->ops.i2c_gate_ctrl)
3133                         fe->ops.i2c_gate_ctrl(fe, 0);
3134         }
3135
3136         stv0367cab_SetQamSize(
3137                         state,
3138                         p->symbol_rate,
3139                         QAMSize);
3140
3141         stv0367cab_set_srate(state,
3142                         cab_state->adc_clk,
3143                         cab_state->mclk,
3144                         p->symbol_rate,
3145                         QAMSize);
3146         /* Search algorithm launch, [-1.1*RangeOffset, +1.1*RangeOffset] scan */
3147         cab_state->state = stv0367cab_algo(state, p);
3148         return 0;
3149 }
3150
3151 static int stv0367cab_get_frontend(struct dvb_frontend *fe,
3152                                    struct dtv_frontend_properties *p)
3153 {
3154         struct stv0367_state *state = fe->demodulator_priv;
3155         struct stv0367cab_state *cab_state = state->cab_state;
3156
3157         enum stv0367cab_mod QAMSize;
3158
3159         dprintk("%s:\n", __func__);
3160
3161         p->symbol_rate = stv0367cab_GetSymbolRate(state, cab_state->mclk);
3162
3163         QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
3164         switch (QAMSize) {
3165         case FE_CAB_MOD_QAM16:
3166                 p->modulation = QAM_16;
3167                 break;
3168         case FE_CAB_MOD_QAM32:
3169                 p->modulation = QAM_32;
3170                 break;
3171         case FE_CAB_MOD_QAM64:
3172                 p->modulation = QAM_64;
3173                 break;
3174         case FE_CAB_MOD_QAM128:
3175                 p->modulation = QAM_128;
3176                 break;
3177         case FE_CAB_MOD_QAM256:
3178                 p->modulation = QAM_256;
3179                 break;
3180         default:
3181                 break;
3182         }
3183
3184         p->frequency = stv0367_get_tuner_freq(fe);
3185
3186         dprintk("%s: tuner frequency = %d\n", __func__, p->frequency);
3187
3188         if (state->config->if_khz == 0) {
3189                 p->frequency +=
3190                         (stv0367cab_get_derot_freq(state, cab_state->adc_clk) -
3191                         cab_state->adc_clk / 4000);
3192                 return 0;
3193         }
3194
3195         if (state->config->if_khz > cab_state->adc_clk / 1000)
3196                 p->frequency += (state->config->if_khz
3197                         - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
3198                         - cab_state->adc_clk / 1000);
3199         else
3200                 p->frequency += (state->config->if_khz
3201                         - stv0367cab_get_derot_freq(state, cab_state->adc_clk));
3202
3203         return 0;
3204 }
3205
3206 #if 0
3207 void stv0367cab_GetErrorCount(state, enum stv0367cab_mod QAMSize,
3208                         u32 symbol_rate, FE_367qam_Monitor *Monitor_results)
3209 {
3210         stv0367cab_OptimiseNByteAndGetBER(state, QAMSize, symbol_rate, Monitor_results);
3211         stv0367cab_GetPacketsCount(state, Monitor_results);
3212
3213         return;
3214 }
3215
3216 static int stv0367cab_read_ber(struct dvb_frontend *fe, u32 *ber)
3217 {
3218         struct stv0367_state *state = fe->demodulator_priv;
3219
3220         return 0;
3221 }
3222 #endif
3223 static s32 stv0367cab_get_rf_lvl(struct stv0367_state *state)
3224 {
3225         s32 rfLevel = 0;
3226         s32 RfAgcPwm = 0, IfAgcPwm = 0;
3227         u8 i;
3228
3229         stv0367_writebits(state, F367CAB_STDBY_ADCGP, 0x0);
3230
3231         RfAgcPwm =
3232                 (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_LO) & 0x03) +
3233                 (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_HI) << 2);
3234         RfAgcPwm = 100 * RfAgcPwm / 1023;
3235
3236         IfAgcPwm =
3237                 stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_LO) +
3238                 (stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_HI) << 8);
3239         if (IfAgcPwm >= 2048)
3240                 IfAgcPwm -= 2048;
3241         else
3242                 IfAgcPwm += 2048;
3243
3244         IfAgcPwm = 100 * IfAgcPwm / 4095;
3245
3246         /* For DTT75467 on NIM */
3247         if (RfAgcPwm < 90  && IfAgcPwm < 28) {
3248                 for (i = 0; i < RF_LOOKUP_TABLE_SIZE; i++) {
3249                         if (RfAgcPwm <= stv0367cab_RF_LookUp1[0][i]) {
3250                                 rfLevel = (-1) * stv0367cab_RF_LookUp1[1][i];
3251                                 break;
3252                         }
3253                 }
3254                 if (i == RF_LOOKUP_TABLE_SIZE)
3255                         rfLevel = -56;
3256         } else { /*if IF AGC>10*/
3257                 for (i = 0; i < RF_LOOKUP_TABLE2_SIZE; i++) {
3258                         if (IfAgcPwm <= stv0367cab_RF_LookUp2[0][i]) {
3259                                 rfLevel = (-1) * stv0367cab_RF_LookUp2[1][i];
3260                                 break;
3261                         }
3262                 }
3263                 if (i == RF_LOOKUP_TABLE2_SIZE)
3264                         rfLevel = -72;
3265         }
3266         return rfLevel;
3267 }
3268
3269 static int stv0367cab_read_strength(struct dvb_frontend *fe, u16 *strength)
3270 {
3271         struct stv0367_state *state = fe->demodulator_priv;
3272
3273         s32 signal =  stv0367cab_get_rf_lvl(state);
3274
3275         dprintk("%s: signal=%d dBm\n", __func__, signal);
3276
3277         if (signal <= -72)
3278                 *strength = 65535;
3279         else
3280                 *strength = (22 + signal) * (-1311);
3281
3282         dprintk("%s: strength=%d\n", __func__, (*strength));
3283
3284         return 0;
3285 }
3286
3287 static int stv0367cab_read_snr(struct dvb_frontend *fe, u16 *snr)
3288 {
3289         struct stv0367_state *state = fe->demodulator_priv;
3290         u32 noisepercentage;
3291         enum stv0367cab_mod QAMSize;
3292         u32 regval = 0, temp = 0;
3293         int power, i;
3294
3295         QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
3296         switch (QAMSize) {
3297         case FE_CAB_MOD_QAM4:
3298                 power = 21904;
3299                 break;
3300         case FE_CAB_MOD_QAM16:
3301                 power = 20480;
3302                 break;
3303         case FE_CAB_MOD_QAM32:
3304                 power = 23040;
3305                 break;
3306         case FE_CAB_MOD_QAM64:
3307                 power = 21504;
3308                 break;
3309         case FE_CAB_MOD_QAM128:
3310                 power = 23616;
3311                 break;
3312         case FE_CAB_MOD_QAM256:
3313                 power = 21760;
3314                 break;
3315         case FE_CAB_MOD_QAM512:
3316                 power = 1;
3317                 break;
3318         case FE_CAB_MOD_QAM1024:
3319                 power = 21280;
3320                 break;
3321         default:
3322                 power = 1;
3323                 break;
3324         }
3325
3326         for (i = 0; i < 10; i++) {
3327                 regval += (stv0367_readbits(state, F367CAB_SNR_LO)
3328                         + 256 * stv0367_readbits(state, F367CAB_SNR_HI));
3329         }
3330
3331         regval /= 10; /*for average over 10 times in for loop above*/
3332         if (regval != 0) {
3333                 temp = power
3334                         * (1 << (3 + stv0367_readbits(state, F367CAB_SNR_PER)));
3335                 temp /= regval;
3336         }
3337
3338         /* table values, not needed to calculate logarithms */
3339         if (temp >= 5012)
3340                 noisepercentage = 100;
3341         else if (temp >= 3981)
3342                 noisepercentage = 93;
3343         else if (temp >= 3162)
3344                 noisepercentage = 86;
3345         else if (temp >= 2512)
3346                 noisepercentage = 79;
3347         else if (temp >= 1995)
3348                 noisepercentage = 72;
3349         else if (temp >= 1585)
3350                 noisepercentage = 65;
3351         else if (temp >= 1259)
3352                 noisepercentage = 58;
3353         else if (temp >= 1000)
3354                 noisepercentage = 50;
3355         else if (temp >= 794)
3356                 noisepercentage = 43;
3357         else if (temp >= 501)
3358                 noisepercentage = 36;
3359         else if (temp >= 316)
3360                 noisepercentage = 29;
3361         else if (temp >= 200)
3362                 noisepercentage = 22;
3363         else if (temp >= 158)
3364                 noisepercentage = 14;
3365         else if (temp >= 126)
3366                 noisepercentage = 7;
3367         else
3368                 noisepercentage = 0;
3369
3370         dprintk("%s: noisepercentage=%d\n", __func__, noisepercentage);
3371
3372         *snr = (noisepercentage * 65535) / 100;
3373
3374         return 0;
3375 }
3376
3377 static int stv0367cab_read_ucblcks(struct dvb_frontend *fe, u32 *ucblocks)
3378 {
3379         struct stv0367_state *state = fe->demodulator_priv;
3380         int corrected, tscount;
3381
3382         *ucblocks = (stv0367_readreg(state, R367CAB_RS_COUNTER_5) << 8)
3383                         | stv0367_readreg(state, R367CAB_RS_COUNTER_4);
3384         corrected = (stv0367_readreg(state, R367CAB_RS_COUNTER_3) << 8)
3385                         | stv0367_readreg(state, R367CAB_RS_COUNTER_2);
3386         tscount = (stv0367_readreg(state, R367CAB_RS_COUNTER_2) << 8)
3387                         | stv0367_readreg(state, R367CAB_RS_COUNTER_1);
3388
3389         dprintk("%s: uncorrected blocks=%d corrected blocks=%d tscount=%d\n",
3390                                 __func__, *ucblocks, corrected, tscount);
3391
3392         return 0;
3393 };
3394
3395 static struct dvb_frontend_ops stv0367cab_ops = {
3396         .delsys = { SYS_DVBC_ANNEX_A },
3397         .info = {
3398                 .name = "ST STV0367 DVB-C",
3399                 .frequency_min = 47000000,
3400                 .frequency_max = 862000000,
3401                 .frequency_stepsize = 62500,
3402                 .symbol_rate_min = 870000,
3403                 .symbol_rate_max = 11700000,
3404                 .caps = 0x400 |/* FE_CAN_QAM_4 */
3405                         FE_CAN_QAM_16 | FE_CAN_QAM_32  |
3406                         FE_CAN_QAM_64 | FE_CAN_QAM_128 |
3407                         FE_CAN_QAM_256 | FE_CAN_FEC_AUTO
3408         },
3409         .release                                = stv0367_release,
3410         .init                                   = stv0367cab_init,
3411         .sleep                                  = stv0367cab_sleep,
3412         .i2c_gate_ctrl                          = stv0367cab_gate_ctrl,
3413         .set_frontend                           = stv0367cab_set_frontend,
3414         .get_frontend                           = stv0367cab_get_frontend,
3415         .read_status                            = stv0367cab_read_status,
3416 /*      .read_ber                               = stv0367cab_read_ber, */
3417         .read_signal_strength                   = stv0367cab_read_strength,
3418         .read_snr                               = stv0367cab_read_snr,
3419         .read_ucblocks                          = stv0367cab_read_ucblcks,
3420         .get_tune_settings                      = stv0367_get_tune_settings,
3421 };
3422
3423 struct dvb_frontend *stv0367cab_attach(const struct stv0367_config *config,
3424                                    struct i2c_adapter *i2c)
3425 {
3426         struct stv0367_state *state = NULL;
3427         struct stv0367cab_state *cab_state = NULL;
3428
3429         /* allocate memory for the internal state */
3430         state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
3431         if (state == NULL)
3432                 goto error;
3433         cab_state = kzalloc(sizeof(struct stv0367cab_state), GFP_KERNEL);
3434         if (cab_state == NULL)
3435                 goto error;
3436
3437         /* setup the state */
3438         state->i2c = i2c;
3439         state->config = config;
3440         cab_state->search_range = 280000;
3441         state->cab_state = cab_state;
3442         state->fe.ops = stv0367cab_ops;
3443         state->fe.demodulator_priv = state;
3444         state->chip_id = stv0367_readreg(state, 0xf000);
3445
3446         dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
3447
3448         /* check if the demod is there */
3449         if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
3450                 goto error;
3451
3452         return &state->fe;
3453
3454 error:
3455         kfree(cab_state);
3456         kfree(state);
3457         return NULL;
3458 }
3459 EXPORT_SYMBOL(stv0367cab_attach);
3460
3461 MODULE_PARM_DESC(debug, "Set debug");
3462 MODULE_PARM_DESC(i2c_debug, "Set i2c debug");
3463
3464 MODULE_AUTHOR("Igor M. Liplianin");
3465 MODULE_DESCRIPTION("ST STV0367 DVB-C/T demodulator driver");
3466 MODULE_LICENSE("GPL");