drivers/media/i2c/adv7604.c

   1 /*
   2  * adv7604 - Analog Devices ADV7604 video decoder driver
   3  *
   4  * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
   5  *
   6  * This program is free software; you may redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  11  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  12  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  13  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  14  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  15  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  16  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  17  * SOFTWARE.
  18  *
  19  */
  20
  21 /*
  22  * References (c = chapter, p = page):
  23  * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
  24  *              Revision 2.5, June 2010
  25  * REF_02 - Analog devices, Register map documentation, Documentation of
  26  *              the register maps, Software manual, Rev. F, June 2010
  27  * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
  28  */
  29
  30 #include <linux/delay.h>
  31 #include <linux/gpio/consumer.h>
  32 #include <linux/hdmi.h>
  33 #include <linux/i2c.h>
  34 #include <linux/kernel.h>
  35 #include <linux/module.h>
  36 #include <linux/slab.h>
  37 #include <linux/v4l2-dv-timings.h>
  38 #include <linux/videodev2.h>
  39 #include <linux/workqueue.h>
  40 #include <linux/regmap.h>
  41
  42 #include <media/i2c/adv7604.h>
  43 #include <media/cec.h>
  44 #include <media/v4l2-ctrls.h>
  45 #include <media/v4l2-device.h>
  46 #include <media/v4l2-event.h>
  47 #include <media/v4l2-dv-timings.h>
  48 #include <media/v4l2-of.h>
  49
  50 static int debug;
  51 module_param(debug, int, 0644);
  52 MODULE_PARM_DESC(debug, "debug level (0-2)");
  53
  54 MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
  55 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
  56 MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
  57 MODULE_LICENSE("GPL");
  58
  59 /* ADV7604 system clock frequency */
  60 #define ADV76XX_FSC (28636360)
  61
  62 #define ADV76XX_RGB_OUT                                 (1 << 1)
  63
  64 #define ADV76XX_OP_FORMAT_SEL_8BIT                      (0 << 0)
  65 #define ADV7604_OP_FORMAT_SEL_10BIT                     (1 << 0)
  66 #define ADV76XX_OP_FORMAT_SEL_12BIT                     (2 << 0)
  67
  68 #define ADV76XX_OP_MODE_SEL_SDR_422                     (0 << 5)
  69 #define ADV7604_OP_MODE_SEL_DDR_422                     (1 << 5)
  70 #define ADV76XX_OP_MODE_SEL_SDR_444                     (2 << 5)
  71 #define ADV7604_OP_MODE_SEL_DDR_444                     (3 << 5)
  72 #define ADV76XX_OP_MODE_SEL_SDR_422_2X                  (4 << 5)
  73 #define ADV7604_OP_MODE_SEL_ADI_CM                      (5 << 5)
  74
  75 #define ADV76XX_OP_CH_SEL_GBR                           (0 << 5)
  76 #define ADV76XX_OP_CH_SEL_GRB                           (1 << 5)
  77 #define ADV76XX_OP_CH_SEL_BGR                           (2 << 5)
  78 #define ADV76XX_OP_CH_SEL_RGB                           (3 << 5)
  79 #define ADV76XX_OP_CH_SEL_BRG                           (4 << 5)
  80 #define ADV76XX_OP_CH_SEL_RBG                           (5 << 5)
  81
  82 #define ADV76XX_OP_SWAP_CB_CR                           (1 << 0)
  83
  84 #define ADV76XX_MAX_ADDRS (3)
  85
  86 enum adv76xx_type {
  87         ADV7604,
  88         ADV7611,
  89         ADV7612,
  90 };
  91
  92 struct adv76xx_reg_seq {
  93         unsigned int reg;
  94         u8 val;
  95 };
  96
  97 struct adv76xx_format_info {
  98         u32 code;
  99         u8 op_ch_sel;
 100         bool rgb_out;
 101         bool swap_cb_cr;
 102         u8 op_format_sel;
 103 };
 104
 105 struct adv76xx_cfg_read_infoframe {
 106         const char *desc;
 107         u8 present_mask;
 108         u8 head_addr;
 109         u8 payload_addr;
 110 };
 111
 112 struct adv76xx_chip_info {
 113         enum adv76xx_type type;
 114
 115         bool has_afe;
 116         unsigned int max_port;
 117         unsigned int num_dv_ports;
 118
 119         unsigned int edid_enable_reg;
 120         unsigned int edid_status_reg;
 121         unsigned int lcf_reg;
 122
 123         unsigned int cable_det_mask;
 124         unsigned int tdms_lock_mask;
 125         unsigned int fmt_change_digital_mask;
 126         unsigned int cp_csc;
 127
 128         const struct adv76xx_format_info *formats;
 129         unsigned int nformats;
 130
 131         void (*set_termination)(struct v4l2_subdev *sd, bool enable);
 132         void (*setup_irqs)(struct v4l2_subdev *sd);
 133         unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd);
 134         unsigned int (*read_cable_det)(struct v4l2_subdev *sd);
 135
 136         /* 0 = AFE, 1 = HDMI */
 137         const struct adv76xx_reg_seq *recommended_settings[2];
 138         unsigned int num_recommended_settings[2];
 139
 140         unsigned long page_mask;
 141
 142         /* Masks for timings */
 143         unsigned int linewidth_mask;
 144         unsigned int field0_height_mask;
 145         unsigned int field1_height_mask;
 146         unsigned int hfrontporch_mask;
 147         unsigned int hsync_mask;
 148         unsigned int hbackporch_mask;
 149         unsigned int field0_vfrontporch_mask;
 150         unsigned int field1_vfrontporch_mask;
 151         unsigned int field0_vsync_mask;
 152         unsigned int field1_vsync_mask;
 153         unsigned int field0_vbackporch_mask;
 154         unsigned int field1_vbackporch_mask;
 155 };
 156
 157 /*
 158  **********************************************************************
 159  *
 160  *  Arrays with configuration parameters for the ADV7604
 161  *
 162  **********************************************************************
 163  */
 164
 165 struct adv76xx_state {
 166         const struct adv76xx_chip_info *info;
 167         struct adv76xx_platform_data pdata;
 168
 169         struct gpio_desc *hpd_gpio[4];
 170         struct gpio_desc *reset_gpio;
 171
 172         struct v4l2_subdev sd;
 173         struct media_pad pads[ADV76XX_PAD_MAX];
 174         unsigned int source_pad;
 175
 176         struct v4l2_ctrl_handler hdl;
 177
 178         enum adv76xx_pad selected_input;
 179
 180         struct v4l2_dv_timings timings;
 181         const struct adv76xx_format_info *format;
 182
 183         struct {
 184                 u8 edid[256];
 185                 u32 present;
 186                 unsigned blocks;
 187         } edid;
 188         u16 spa_port_a[2];
 189         struct v4l2_fract aspect_ratio;
 190         u32 rgb_quantization_range;
 191         struct delayed_work delayed_work_enable_hotplug;
 192         bool restart_stdi_once;
 193
 194         /* CEC */
 195         struct cec_adapter *cec_adap;
 196         u8   cec_addr[ADV76XX_MAX_ADDRS];
 197         u8   cec_valid_addrs;
 198         bool cec_enabled_adap;
 199
 200         /* i2c clients */
 201         struct i2c_client *i2c_clients[ADV76XX_PAGE_MAX];
 202
 203         /* Regmaps */
 204         struct regmap *regmap[ADV76XX_PAGE_MAX];
 205
 206         /* controls */
 207         struct v4l2_ctrl *detect_tx_5v_ctrl;
 208         struct v4l2_ctrl *analog_sampling_phase_ctrl;
 209         struct v4l2_ctrl *free_run_color_manual_ctrl;
 210         struct v4l2_ctrl *free_run_color_ctrl;
 211         struct v4l2_ctrl *rgb_quantization_range_ctrl;
 212 };
 213
 214 static bool adv76xx_has_afe(struct adv76xx_state *state)
 215 {
 216         return state->info->has_afe;
 217 }
 218
 219 /* Unsupported timings. This device cannot support 720p30. */
 220 static const struct v4l2_dv_timings adv76xx_timings_exceptions[] = {
 221         V4L2_DV_BT_CEA_1280X720P30,
 222         { }
 223 };
 224
 225 static bool adv76xx_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl)
 226 {
 227         int i;
 228
 229         for (i = 0; adv76xx_timings_exceptions[i].bt.width; i++)
 230                 if (v4l2_match_dv_timings(t, adv76xx_timings_exceptions + i, 0, false))
 231                         return false;
 232         return true;
 233 }
 234
 235 struct adv76xx_video_standards {
 236         struct v4l2_dv_timings timings;
 237         u8 vid_std;
 238         u8 v_freq;
 239 };
 240
 241 /* sorted by number of lines */
 242 static const struct adv76xx_video_standards adv7604_prim_mode_comp[] = {
 243         /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
 244         { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
 245         { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
 246         { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
 247         { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
 248         { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
 249         { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
 250         { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
 251         { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
 252         /* TODO add 1920x1080P60_RB (CVT timing) */
 253         { },
 254 };
 255
 256 /* sorted by number of lines */
 257 static const struct adv76xx_video_standards adv7604_prim_mode_gr[] = {
 258         { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
 259         { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
 260         { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
 261         { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
 262         { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
 263         { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
 264         { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
 265         { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
 266         { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
 267         { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
 268         { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
 269         { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
 270         { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
 271         { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
 272         { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
 273         { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
 274         { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
 275         { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
 276         { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
 277         { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
 278         /* TODO add 1600X1200P60_RB (not a DMT timing) */
 279         { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
 280         { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
 281         { },
 282 };
 283
 284 /* sorted by number of lines */
 285 static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_comp[] = {
 286         { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
 287         { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
 288         { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
 289         { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
 290         { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
 291         { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
 292         { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
 293         { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
 294         { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
 295         { },
 296 };
 297
 298 /* sorted by number of lines */
 299 static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_gr[] = {
 300         { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
 301         { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
 302         { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
 303         { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
 304         { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
 305         { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
 306         { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
 307         { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
 308         { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
 309         { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
 310         { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
 311         { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
 312         { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
 313         { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
 314         { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
 315         { },
 316 };
 317
 318 static const struct v4l2_event adv76xx_ev_fmt = {
 319         .type = V4L2_EVENT_SOURCE_CHANGE,
 320         .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
 321 };
 322
 323 /* ----------------------------------------------------------------------- */
 324
 325 static inline struct adv76xx_state *to_state(struct v4l2_subdev *sd)
 326 {
 327         return container_of(sd, struct adv76xx_state, sd);
 328 }
 329
 330 static inline unsigned htotal(const struct v4l2_bt_timings *t)
 331 {
 332         return V4L2_DV_BT_FRAME_WIDTH(t);
 333 }
 334
 335 static inline unsigned vtotal(const struct v4l2_bt_timings *t)
 336 {
 337         return V4L2_DV_BT_FRAME_HEIGHT(t);
 338 }
 339
 340 /* ----------------------------------------------------------------------- */
 341
 342 static int adv76xx_read_check(struct adv76xx_state *state,
 343                              int client_page, u8 reg)
 344 {
 345         struct i2c_client *client = state->i2c_clients[client_page];
 346         int err;
 347         unsigned int val;
 348
 349         err = regmap_read(state->regmap[client_page], reg, &val);
 350
 351         if (err) {
 352                 v4l_err(client, "error reading %02x, %02x\n",
 353                                 client->addr, reg);
 354                 return err;
 355         }
 356         return val;
 357 }
 358
 359 /* adv76xx_write_block(): Write raw data with a maximum of I2C_SMBUS_BLOCK_MAX
 360  * size to one or more registers.
 361  *
 362  * A value of zero will be returned on success, a negative errno will
 363  * be returned in error cases.
 364  */
 365 static int adv76xx_write_block(struct adv76xx_state *state, int client_page,
 366                               unsigned int init_reg, const void *val,
 367                               size_t val_len)
 368 {
 369         struct regmap *regmap = state->regmap[client_page];
 370
 371         if (val_len > I2C_SMBUS_BLOCK_MAX)
 372                 val_len = I2C_SMBUS_BLOCK_MAX;
 373
 374         return regmap_raw_write(regmap, init_reg, val, val_len);
 375 }
 376
 377 /* ----------------------------------------------------------------------- */
 378
 379 static inline int io_read(struct v4l2_subdev *sd, u8 reg)
 380 {
 381         struct adv76xx_state *state = to_state(sd);
 382
 383         return adv76xx_read_check(state, ADV76XX_PAGE_IO, reg);
 384 }
 385
 386 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 387 {
 388         struct adv76xx_state *state = to_state(sd);
 389
 390         return regmap_write(state->regmap[ADV76XX_PAGE_IO], reg, val);
 391 }
 392
 393 static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask,
 394                                    u8 val)
 395 {
 396         return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
 397 }
 398
 399 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
 400 {
 401         struct adv76xx_state *state = to_state(sd);
 402
 403         return adv76xx_read_check(state, ADV7604_PAGE_AVLINK, reg);
 404 }
 405
 406 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 407 {
 408         struct adv76xx_state *state = to_state(sd);
 409
 410         return regmap_write(state->regmap[ADV7604_PAGE_AVLINK], reg, val);
 411 }
 412
 413 static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
 414 {
 415         struct adv76xx_state *state = to_state(sd);
 416
 417         return adv76xx_read_check(state, ADV76XX_PAGE_CEC, reg);
 418 }
 419
 420 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 421 {
 422         struct adv76xx_state *state = to_state(sd);
 423
 424         return regmap_write(state->regmap[ADV76XX_PAGE_CEC], reg, val);
 425 }
 426
 427 static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask,
 428                                    u8 val)
 429 {
 430         return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val);
 431 }
 432
 433 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
 434 {
 435         struct adv76xx_state *state = to_state(sd);
 436
 437         return adv76xx_read_check(state, ADV76XX_PAGE_INFOFRAME, reg);
 438 }
 439
 440 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 441 {
 442         struct adv76xx_state *state = to_state(sd);
 443
 444         return regmap_write(state->regmap[ADV76XX_PAGE_INFOFRAME], reg, val);
 445 }
 446
 447 static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
 448 {
 449         struct adv76xx_state *state = to_state(sd);
 450
 451         return adv76xx_read_check(state, ADV76XX_PAGE_AFE, reg);
 452 }
 453
 454 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 455 {
 456         struct adv76xx_state *state = to_state(sd);
 457
 458         return regmap_write(state->regmap[ADV76XX_PAGE_AFE], reg, val);
 459 }
 460
 461 static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
 462 {
 463         struct adv76xx_state *state = to_state(sd);
 464
 465         return adv76xx_read_check(state, ADV76XX_PAGE_REP, reg);
 466 }
 467
 468 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 469 {
 470         struct adv76xx_state *state = to_state(sd);
 471
 472         return regmap_write(state->regmap[ADV76XX_PAGE_REP], reg, val);
 473 }
 474
 475 static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 476 {
 477         return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val);
 478 }
 479
 480 static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
 481 {
 482         struct adv76xx_state *state = to_state(sd);
 483
 484         return adv76xx_read_check(state, ADV76XX_PAGE_EDID, reg);
 485 }
 486
 487 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 488 {
 489         struct adv76xx_state *state = to_state(sd);
 490
 491         return regmap_write(state->regmap[ADV76XX_PAGE_EDID], reg, val);
 492 }
 493
 494 static inline int edid_write_block(struct v4l2_subdev *sd,
 495                                         unsigned int total_len, const u8 *val)
 496 {
 497         struct adv76xx_state *state = to_state(sd);
 498         int err = 0;
 499         int i = 0;
 500         int len = 0;
 501
 502         v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n",
 503                                 __func__, total_len);
 504
 505         while (!err && i < total_len) {
 506                 len = (total_len - i) > I2C_SMBUS_BLOCK_MAX ?
 507                                 I2C_SMBUS_BLOCK_MAX :
 508                                 (total_len - i);
 509
 510                 err = adv76xx_write_block(state, ADV76XX_PAGE_EDID,
 511                                 i, val + i, len);
 512                 i += len;
 513         }
 514
 515         return err;
 516 }
 517
 518 static void adv76xx_set_hpd(struct adv76xx_state *state, unsigned int hpd)
 519 {
 520         unsigned int i;
 521
 522         for (i = 0; i < state->info->num_dv_ports; ++i)
 523                 gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i));
 524
 525         v4l2_subdev_notify(&state->sd, ADV76XX_HOTPLUG, &hpd);
 526 }
 527
 528 static void adv76xx_delayed_work_enable_hotplug(struct work_struct *work)
 529 {
 530         struct delayed_work *dwork = to_delayed_work(work);
 531         struct adv76xx_state *state = container_of(dwork, struct adv76xx_state,
 532                                                 delayed_work_enable_hotplug);
 533         struct v4l2_subdev *sd = &state->sd;
 534
 535         v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
 536
 537         adv76xx_set_hpd(state, state->edid.present);
 538 }
 539
 540 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
 541 {
 542         struct adv76xx_state *state = to_state(sd);
 543
 544         return adv76xx_read_check(state, ADV76XX_PAGE_HDMI, reg);
 545 }
 546
 547 static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
 548 {
 549         return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask;
 550 }
 551
 552 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 553 {
 554         struct adv76xx_state *state = to_state(sd);
 555
 556         return regmap_write(state->regmap[ADV76XX_PAGE_HDMI], reg, val);
 557 }
 558
 559 static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 560 {
 561         return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val);
 562 }
 563
 564 static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 565 {
 566         struct adv76xx_state *state = to_state(sd);
 567
 568         return regmap_write(state->regmap[ADV76XX_PAGE_TEST], reg, val);
 569 }
 570
 571 static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
 572 {
 573         struct adv76xx_state *state = to_state(sd);
 574
 575         return adv76xx_read_check(state, ADV76XX_PAGE_CP, reg);
 576 }
 577
 578 static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
 579 {
 580         return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask;
 581 }
 582
 583 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 584 {
 585         struct adv76xx_state *state = to_state(sd);
 586
 587         return regmap_write(state->regmap[ADV76XX_PAGE_CP], reg, val);
 588 }
 589
 590 static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 591 {
 592         return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val);
 593 }
 594
 595 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
 596 {
 597         struct adv76xx_state *state = to_state(sd);
 598
 599         return adv76xx_read_check(state, ADV7604_PAGE_VDP, reg);
 600 }
 601
 602 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 603 {
 604         struct adv76xx_state *state = to_state(sd);
 605
 606         return regmap_write(state->regmap[ADV7604_PAGE_VDP], reg, val);
 607 }
 608
 609 #define ADV76XX_REG(page, offset)       (((page) << 8) | (offset))
 610 #define ADV76XX_REG_SEQ_TERM            0xffff
 611
 612 #ifdef CONFIG_VIDEO_ADV_DEBUG
 613 static int adv76xx_read_reg(struct v4l2_subdev *sd, unsigned int reg)
 614 {
 615         struct adv76xx_state *state = to_state(sd);
 616         unsigned int page = reg >> 8;
 617         unsigned int val;
 618         int err;
 619
 620         if (!(BIT(page) & state->info->page_mask))
 621                 return -EINVAL;
 622
 623         reg &= 0xff;
 624         err = regmap_read(state->regmap[page], reg, &val);
 625
 626         return err ? err : val;
 627 }
 628 #endif
 629
 630 static int adv76xx_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val)
 631 {
 632         struct adv76xx_state *state = to_state(sd);
 633         unsigned int page = reg >> 8;
 634
 635         if (!(BIT(page) & state->info->page_mask))
 636                 return -EINVAL;
 637
 638         reg &= 0xff;
 639
 640         return regmap_write(state->regmap[page], reg, val);
 641 }
 642
 643 static void adv76xx_write_reg_seq(struct v4l2_subdev *sd,
 644                                   const struct adv76xx_reg_seq *reg_seq)
 645 {
 646         unsigned int i;
 647
 648         for (i = 0; reg_seq[i].reg != ADV76XX_REG_SEQ_TERM; i++)
 649                 adv76xx_write_reg(sd, reg_seq[i].reg, reg_seq[i].val);
 650 }
 651
 652 /* -----------------------------------------------------------------------------
 653  * Format helpers
 654  */
 655
 656 static const struct adv76xx_format_info adv7604_formats[] = {
 657         { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
 658           ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
 659         { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
 660           ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
 661         { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
 662           ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
 663         { MEDIA_BUS_FMT_YUYV10_2X10, ADV76XX_OP_CH_SEL_RGB, false, false,
 664           ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
 665         { MEDIA_BUS_FMT_YVYU10_2X10, ADV76XX_OP_CH_SEL_RGB, false, true,
 666           ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
 667         { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
 668           ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
 669         { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
 670           ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
 671         { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
 672           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 673         { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
 674           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 675         { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
 676           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 677         { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
 678           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 679         { MEDIA_BUS_FMT_UYVY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, false,
 680           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
 681         { MEDIA_BUS_FMT_VYUY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, true,
 682           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
 683         { MEDIA_BUS_FMT_YUYV10_1X20, ADV76XX_OP_CH_SEL_RGB, false, false,
 684           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
 685         { MEDIA_BUS_FMT_YVYU10_1X20, ADV76XX_OP_CH_SEL_RGB, false, true,
 686           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
 687         { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
 688           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
 689         { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
 690           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
 691         { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
 692           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
 693         { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
 694           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
 695 };
 696
 697 static const struct adv76xx_format_info adv7611_formats[] = {
 698         { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
 699           ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
 700         { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
 701           ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
 702         { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
 703           ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
 704         { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
 705           ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
 706         { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
 707           ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
 708         { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
 709           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 710         { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
 711           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 712         { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
 713           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 714         { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
 715           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 716         { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
 717           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
 718         { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
 719           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
 720         { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
 721           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
 722         { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
 723           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
 724 };
 725
 726 static const struct adv76xx_format_info adv7612_formats[] = {
 727         { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
 728           ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
 729         { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
 730           ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
 731         { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
 732           ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
 733         { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
 734           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 735         { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
 736           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 737         { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
 738           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 739         { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
 740           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 741 };
 742
 743 static const struct adv76xx_format_info *
 744 adv76xx_format_info(struct adv76xx_state *state, u32 code)
 745 {
 746         unsigned int i;
 747
 748         for (i = 0; i < state->info->nformats; ++i) {
 749                 if (state->info->formats[i].code == code)
 750                         return &state->info->formats[i];
 751         }
 752
 753         return NULL;
 754 }
 755
 756 /* ----------------------------------------------------------------------- */
 757
 758 static inline bool is_analog_input(struct v4l2_subdev *sd)
 759 {
 760         struct adv76xx_state *state = to_state(sd);
 761
 762         return state->selected_input == ADV7604_PAD_VGA_RGB ||
 763                state->selected_input == ADV7604_PAD_VGA_COMP;
 764 }
 765
 766 static inline bool is_digital_input(struct v4l2_subdev *sd)
 767 {
 768         struct adv76xx_state *state = to_state(sd);
 769
 770         return state->selected_input == ADV76XX_PAD_HDMI_PORT_A ||
 771                state->selected_input == ADV7604_PAD_HDMI_PORT_B ||
 772                state->selected_input == ADV7604_PAD_HDMI_PORT_C ||
 773                state->selected_input == ADV7604_PAD_HDMI_PORT_D;
 774 }
 775
 776 static const struct v4l2_dv_timings_cap adv7604_timings_cap_analog = {
 777         .type = V4L2_DV_BT_656_1120,
 778         /* keep this initialization for compatibility with GCC < 4.4.6 */
 779         .reserved = { 0 },
 780         V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000,
 781                 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
 782                         V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
 783                 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
 784                         V4L2_DV_BT_CAP_CUSTOM)
 785 };
 786
 787 static const struct v4l2_dv_timings_cap adv76xx_timings_cap_digital = {
 788         .type = V4L2_DV_BT_656_1120,
 789         /* keep this initialization for compatibility with GCC < 4.4.6 */
 790         .reserved = { 0 },
 791         V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 225000000,
 792                 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
 793                         V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
 794                 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
 795                         V4L2_DV_BT_CAP_CUSTOM)
 796 };
 797
 798 /*
 799  * Return the DV timings capabilities for the requested sink pad. As a special
 800  * case, pad value -1 returns the capabilities for the currently selected input.
 801  */
 802 static const struct v4l2_dv_timings_cap *
 803 adv76xx_get_dv_timings_cap(struct v4l2_subdev *sd, int pad)
 804 {
 805         if (pad == -1) {
 806                 struct adv76xx_state *state = to_state(sd);
 807
 808                 pad = state->selected_input;
 809         }
 810
 811         switch (pad) {
 812         case ADV76XX_PAD_HDMI_PORT_A:
 813         case ADV7604_PAD_HDMI_PORT_B:
 814         case ADV7604_PAD_HDMI_PORT_C:
 815         case ADV7604_PAD_HDMI_PORT_D:
 816                 return &adv76xx_timings_cap_digital;
 817
 818         case ADV7604_PAD_VGA_RGB:
 819         case ADV7604_PAD_VGA_COMP:
 820         default:
 821                 return &adv7604_timings_cap_analog;
 822         }
 823 }
 824
 825
 826 /* ----------------------------------------------------------------------- */
 827
 828 #ifdef CONFIG_VIDEO_ADV_DEBUG
 829 static void adv76xx_inv_register(struct v4l2_subdev *sd)
 830 {
 831         v4l2_info(sd, "0x000-0x0ff: IO Map\n");
 832         v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
 833         v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
 834         v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
 835         v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
 836         v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
 837         v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
 838         v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
 839         v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
 840         v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
 841         v4l2_info(sd, "0xa00-0xaff: Test Map\n");
 842         v4l2_info(sd, "0xb00-0xbff: CP Map\n");
 843         v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
 844 }
 845
 846 static int adv76xx_g_register(struct v4l2_subdev *sd,
 847                                         struct v4l2_dbg_register *reg)
 848 {
 849         int ret;
 850
 851         ret = adv76xx_read_reg(sd, reg->reg);
 852         if (ret < 0) {
 853                 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
 854                 adv76xx_inv_register(sd);
 855                 return ret;
 856         }
 857
 858         reg->size = 1;
 859         reg->val = ret;
 860
 861         return 0;
 862 }
 863
 864 static int adv76xx_s_register(struct v4l2_subdev *sd,
 865                                         const struct v4l2_dbg_register *reg)
 866 {
 867         int ret;
 868
 869         ret = adv76xx_write_reg(sd, reg->reg, reg->val);
 870         if (ret < 0) {
 871                 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
 872                 adv76xx_inv_register(sd);
 873                 return ret;
 874         }
 875
 876         return 0;
 877 }
 878 #endif
 879
 880 static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd)
 881 {
 882         u8 value = io_read(sd, 0x6f);
 883
 884         return ((value & 0x10) >> 4)
 885              | ((value & 0x08) >> 2)
 886              | ((value & 0x04) << 0)
 887              | ((value & 0x02) << 2);
 888 }
 889
 890 static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd)
 891 {
 892         u8 value = io_read(sd, 0x6f);
 893
 894         return value & 1;
 895 }
 896
 897 static unsigned int adv7612_read_cable_det(struct v4l2_subdev *sd)
 898 {
 899         /*  Reads CABLE_DET_A_RAW. For input B support, need to
 900          *  account for bit 7 [MSB] of 0x6a (ie. CABLE_DET_B_RAW)
 901          */
 902         u8 value = io_read(sd, 0x6f);
 903
 904         return value & 1;
 905 }
 906
 907 static int adv76xx_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
 908 {
 909         struct adv76xx_state *state = to_state(sd);
 910         const struct adv76xx_chip_info *info = state->info;
 911         u16 cable_det = info->read_cable_det(sd);
 912
 913         return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, cable_det);
 914 }
 915
 916 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
 917                 u8 prim_mode,
 918                 const struct adv76xx_video_standards *predef_vid_timings,
 919                 const struct v4l2_dv_timings *timings)
 920 {
 921         int i;
 922
 923         for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
 924                 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
 925                                 is_digital_input(sd) ? 250000 : 1000000, false))
 926                         continue;
 927                 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
 928                 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
 929                                 prim_mode); /* v_freq and prim mode */
 930                 return 0;
 931         }
 932
 933         return -1;
 934 }
 935
 936 static int configure_predefined_video_timings(struct v4l2_subdev *sd,
 937                 struct v4l2_dv_timings *timings)
 938 {
 939         struct adv76xx_state *state = to_state(sd);
 940         int err;
 941
 942         v4l2_dbg(1, debug, sd, "%s", __func__);
 943
 944         if (adv76xx_has_afe(state)) {
 945                 /* reset to default values */
 946                 io_write(sd, 0x16, 0x43);
 947                 io_write(sd, 0x17, 0x5a);
 948         }
 949         /* disable embedded syncs for auto graphics mode */
 950         cp_write_clr_set(sd, 0x81, 0x10, 0x00);
 951         cp_write(sd, 0x8f, 0x00);
 952         cp_write(sd, 0x90, 0x00);
 953         cp_write(sd, 0xa2, 0x00);
 954         cp_write(sd, 0xa3, 0x00);
 955         cp_write(sd, 0xa4, 0x00);
 956         cp_write(sd, 0xa5, 0x00);
 957         cp_write(sd, 0xa6, 0x00);
 958         cp_write(sd, 0xa7, 0x00);
 959         cp_write(sd, 0xab, 0x00);
 960         cp_write(sd, 0xac, 0x00);
 961
 962         if (is_analog_input(sd)) {
 963                 err = find_and_set_predefined_video_timings(sd,
 964                                 0x01, adv7604_prim_mode_comp, timings);
 965                 if (err)
 966                         err = find_and_set_predefined_video_timings(sd,
 967                                         0x02, adv7604_prim_mode_gr, timings);
 968         } else if (is_digital_input(sd)) {
 969                 err = find_and_set_predefined_video_timings(sd,
 970                                 0x05, adv76xx_prim_mode_hdmi_comp, timings);
 971                 if (err)
 972                         err = find_and_set_predefined_video_timings(sd,
 973                                         0x06, adv76xx_prim_mode_hdmi_gr, timings);
 974         } else {
 975                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
 976                                 __func__, state->selected_input);
 977                 err = -1;
 978         }
 979
 980
 981         return err;
 982 }
 983
 984 static void configure_custom_video_timings(struct v4l2_subdev *sd,
 985                 const struct v4l2_bt_timings *bt)
 986 {
 987         struct adv76xx_state *state = to_state(sd);
 988         u32 width = htotal(bt);
 989         u32 height = vtotal(bt);
 990         u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
 991         u16 cp_start_eav = width - bt->hfrontporch;
 992         u16 cp_start_vbi = height - bt->vfrontporch;
 993         u16 cp_end_vbi = bt->vsync + bt->vbackporch;
 994         u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
 995                 ((width * (ADV76XX_FSC / 100)) / ((u32)bt->pixelclock / 100)) : 0;
 996         const u8 pll[2] = {
 997                 0xc0 | ((width >> 8) & 0x1f),
 998                 width & 0xff
 999         };
1000
1001         v4l2_dbg(2, debug, sd, "%s\n", __func__);
1002
1003         if (is_analog_input(sd)) {
1004                 /* auto graphics */
1005                 io_write(sd, 0x00, 0x07); /* video std */
1006                 io_write(sd, 0x01, 0x02); /* prim mode */
1007                 /* enable embedded syncs for auto graphics mode */
1008                 cp_write_clr_set(sd, 0x81, 0x10, 0x10);
1009
1010                 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
1011                 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
1012                 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
1013                 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_IO],
1014                                         0x16, pll, 2))
1015                         v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
1016
1017                 /* active video - horizontal timing */
1018                 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
1019                 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
1020                                    ((cp_start_eav >> 8) & 0x0f));
1021                 cp_write(sd, 0xa4, cp_start_eav & 0xff);
1022
1023                 /* active video - vertical timing */
1024                 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
1025                 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
1026                                    ((cp_end_vbi >> 8) & 0xf));
1027                 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
1028         } else if (is_digital_input(sd)) {
1029                 /* set default prim_mode/vid_std for HDMI
1030                    according to [REF_03, c. 4.2] */
1031                 io_write(sd, 0x00, 0x02); /* video std */
1032                 io_write(sd, 0x01, 0x06); /* prim mode */
1033         } else {
1034                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1035                                 __func__, state->selected_input);
1036         }
1037
1038         cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
1039         cp_write(sd, 0x90, ch1_fr_ll & 0xff);
1040         cp_write(sd, 0xab, (height >> 4) & 0xff);
1041         cp_write(sd, 0xac, (height & 0x0f) << 4);
1042 }
1043
1044 static void adv76xx_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
1045 {
1046         struct adv76xx_state *state = to_state(sd);
1047         u8 offset_buf[4];
1048
1049         if (auto_offset) {
1050                 offset_a = 0x3ff;
1051                 offset_b = 0x3ff;
1052                 offset_c = 0x3ff;
1053         }
1054
1055         v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
1056                         __func__, auto_offset ? "Auto" : "Manual",
1057                         offset_a, offset_b, offset_c);
1058
1059         offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
1060         offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
1061         offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
1062         offset_buf[3] = offset_c & 0x0ff;
1063
1064         /* Registers must be written in this order with no i2c access in between */
1065         if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP],
1066                         0x77, offset_buf, 4))
1067                 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
1068 }
1069
1070 static void adv76xx_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
1071 {
1072         struct adv76xx_state *state = to_state(sd);
1073         u8 gain_buf[4];
1074         u8 gain_man = 1;
1075         u8 agc_mode_man = 1;
1076
1077         if (auto_gain) {
1078                 gain_man = 0;
1079                 agc_mode_man = 0;
1080                 gain_a = 0x100;
1081                 gain_b = 0x100;
1082                 gain_c = 0x100;
1083         }
1084
1085         v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
1086                         __func__, auto_gain ? "Auto" : "Manual",
1087                         gain_a, gain_b, gain_c);
1088
1089         gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
1090         gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
1091         gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
1092         gain_buf[3] = ((gain_c & 0x0ff));
1093
1094         /* Registers must be written in this order with no i2c access in between */
1095         if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP],
1096                              0x73, gain_buf, 4))
1097                 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
1098 }
1099
1100 static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1101 {
1102         struct adv76xx_state *state = to_state(sd);
1103         bool rgb_output = io_read(sd, 0x02) & 0x02;
1104         bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1105         u8 y = HDMI_COLORSPACE_RGB;
1106
1107         if (hdmi_signal && (io_read(sd, 0x60) & 1))
1108                 y = infoframe_read(sd, 0x01) >> 5;
1109
1110         v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
1111                         __func__, state->rgb_quantization_range,
1112                         rgb_output, hdmi_signal);
1113
1114         adv76xx_set_gain(sd, true, 0x0, 0x0, 0x0);
1115         adv76xx_set_offset(sd, true, 0x0, 0x0, 0x0);
1116         io_write_clr_set(sd, 0x02, 0x04, rgb_output ? 0 : 4);
1117
1118         switch (state->rgb_quantization_range) {
1119         case V4L2_DV_RGB_RANGE_AUTO:
1120                 if (state->selected_input == ADV7604_PAD_VGA_RGB) {
1121                         /* Receiving analog RGB signal
1122                          * Set RGB full range (0-255) */
1123                         io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1124                         break;
1125                 }
1126
1127                 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1128                         /* Receiving analog YPbPr signal
1129                          * Set automode */
1130                         io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
1131                         break;
1132                 }
1133
1134                 if (hdmi_signal) {
1135                         /* Receiving HDMI signal
1136                          * Set automode */
1137                         io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
1138                         break;
1139                 }
1140
1141                 /* Receiving DVI-D signal
1142                  * ADV7604 selects RGB limited range regardless of
1143                  * input format (CE/IT) in automatic mode */
1144                 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
1145                         /* RGB limited range (16-235) */
1146                         io_write_clr_set(sd, 0x02, 0xf0, 0x00);
1147                 } else {
1148                         /* RGB full range (0-255) */
1149                         io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1150
1151                         if (is_digital_input(sd) && rgb_output) {
1152                                 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
1153                         } else {
1154                                 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1155                                 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
1156                         }
1157                 }
1158                 break;
1159         case V4L2_DV_RGB_RANGE_LIMITED:
1160                 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1161                         /* YCrCb limited range (16-235) */
1162                         io_write_clr_set(sd, 0x02, 0xf0, 0x20);
1163                         break;
1164                 }
1165
1166                 if (y != HDMI_COLORSPACE_RGB)
1167                         break;
1168
1169                 /* RGB limited range (16-235) */
1170                 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
1171
1172                 break;
1173         case V4L2_DV_RGB_RANGE_FULL:
1174                 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1175                         /* YCrCb full range (0-255) */
1176                         io_write_clr_set(sd, 0x02, 0xf0, 0x60);
1177                         break;
1178                 }
1179
1180                 if (y != HDMI_COLORSPACE_RGB)
1181                         break;
1182
1183                 /* RGB full range (0-255) */
1184                 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1185
1186                 if (is_analog_input(sd) || hdmi_signal)
1187                         break;
1188
1189                 /* Adjust gain/offset for DVI-D signals only */
1190                 if (rgb_output) {
1191                         adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
1192                 } else {
1193                         adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1194                         adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
1195                 }
1196                 break;
1197         }
1198 }
1199
1200 static int adv76xx_s_ctrl(struct v4l2_ctrl *ctrl)
1201 {
1202         struct v4l2_subdev *sd =
1203                 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd;
1204
1205         struct adv76xx_state *state = to_state(sd);
1206
1207         switch (ctrl->id) {
1208         case V4L2_CID_BRIGHTNESS:
1209                 cp_write(sd, 0x3c, ctrl->val);
1210                 return 0;
1211         case V4L2_CID_CONTRAST:
1212                 cp_write(sd, 0x3a, ctrl->val);
1213                 return 0;
1214         case V4L2_CID_SATURATION:
1215                 cp_write(sd, 0x3b, ctrl->val);
1216                 return 0;
1217         case V4L2_CID_HUE:
1218                 cp_write(sd, 0x3d, ctrl->val);
1219                 return 0;
1220         case  V4L2_CID_DV_RX_RGB_RANGE:
1221                 state->rgb_quantization_range = ctrl->val;
1222                 set_rgb_quantization_range(sd);
1223                 return 0;
1224         case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1225                 if (!adv76xx_has_afe(state))
1226                         return -EINVAL;
1227                 /* Set the analog sampling phase. This is needed to find the
1228                    best sampling phase for analog video: an application or
1229                    driver has to try a number of phases and analyze the picture
1230                    quality before settling on the best performing phase. */
1231                 afe_write(sd, 0xc8, ctrl->val);
1232                 return 0;
1233         case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1234                 /* Use the default blue color for free running mode,
1235                    or supply your own. */
1236                 cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2);
1237                 return 0;
1238         case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
1239                 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
1240                 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
1241                 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
1242                 return 0;
1243         }
1244         return -EINVAL;
1245 }
1246
1247 static int adv76xx_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
1248 {
1249         struct v4l2_subdev *sd =
1250                 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd;
1251
1252         if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) {
1253                 ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC;
1254                 if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80))
1255                         ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3;
1256                 return 0;
1257         }
1258         return -EINVAL;
1259 }
1260
1261 /* ----------------------------------------------------------------------- */
1262
1263 static inline bool no_power(struct v4l2_subdev *sd)
1264 {
1265         /* Entire chip or CP powered off */
1266         return io_read(sd, 0x0c) & 0x24;
1267 }
1268
1269 static inline bool no_signal_tmds(struct v4l2_subdev *sd)
1270 {
1271         struct adv76xx_state *state = to_state(sd);
1272
1273         return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
1274 }
1275
1276 static inline bool no_lock_tmds(struct v4l2_subdev *sd)
1277 {
1278         struct adv76xx_state *state = to_state(sd);
1279         const struct adv76xx_chip_info *info = state->info;
1280
1281         return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask;
1282 }
1283
1284 static inline bool is_hdmi(struct v4l2_subdev *sd)
1285 {
1286         return hdmi_read(sd, 0x05) & 0x80;
1287 }
1288
1289 static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1290 {
1291         struct adv76xx_state *state = to_state(sd);
1292
1293         /*
1294          * Chips without a AFE don't expose registers for the SSPD, so just assume
1295          * that we have a lock.
1296          */
1297         if (adv76xx_has_afe(state))
1298                 return false;
1299
1300         /* TODO channel 2 */
1301         return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
1302 }
1303
1304 static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1305 {
1306         /* TODO channel 2 */
1307         return !(cp_read(sd, 0xb1) & 0x80);
1308 }
1309
1310 static inline bool no_signal(struct v4l2_subdev *sd)
1311 {
1312         bool ret;
1313
1314         ret = no_power(sd);
1315
1316         ret |= no_lock_stdi(sd);
1317         ret |= no_lock_sspd(sd);
1318
1319         if (is_digital_input(sd)) {
1320                 ret |= no_lock_tmds(sd);
1321                 ret |= no_signal_tmds(sd);
1322         }
1323
1324         return ret;
1325 }
1326
1327 static inline bool no_lock_cp(struct v4l2_subdev *sd)
1328 {
1329         struct adv76xx_state *state = to_state(sd);
1330
1331         if (!adv76xx_has_afe(state))
1332                 return false;
1333
1334         /* CP has detected a non standard number of lines on the incoming
1335            video compared to what it is configured to receive by s_dv_timings */
1336         return io_read(sd, 0x12) & 0x01;
1337 }
1338
1339 static inline bool in_free_run(struct v4l2_subdev *sd)
1340 {
1341         return cp_read(sd, 0xff) & 0x10;
1342 }
1343
1344 static int adv76xx_g_input_status(struct v4l2_subdev *sd, u32 *status)
1345 {
1346         *status = 0;
1347         *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1348         *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1349         if (!in_free_run(sd) && no_lock_cp(sd))
1350                 *status |= is_digital_input(sd) ?
1351                            V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
1352
1353         v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1354
1355         return 0;
1356 }
1357
1358 /* ----------------------------------------------------------------------- */
1359
1360 struct stdi_readback {
1361         u16 bl, lcf, lcvs;
1362         u8 hs_pol, vs_pol;
1363         bool interlaced;
1364 };
1365
1366 static int stdi2dv_timings(struct v4l2_subdev *sd,
1367                 struct stdi_readback *stdi,
1368                 struct v4l2_dv_timings *timings)
1369 {
1370         struct adv76xx_state *state = to_state(sd);
1371         u32 hfreq = (ADV76XX_FSC * 8) / stdi->bl;
1372         u32 pix_clk;
1373         int i;
1374
1375         for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
1376                 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt;
1377
1378                 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i],
1379                                            adv76xx_get_dv_timings_cap(sd, -1),
1380                                            adv76xx_check_dv_timings, NULL))
1381                         continue;
1382                 if (vtotal(bt) != stdi->lcf + 1)
1383                         continue;
1384                 if (bt->vsync != stdi->lcvs)
1385                         continue;
1386
1387                 pix_clk = hfreq * htotal(bt);
1388
1389                 if ((pix_clk < bt->pixelclock + 1000000) &&
1390                     (pix_clk > bt->pixelclock - 1000000)) {
1391                         *timings = v4l2_dv_timings_presets[i];
1392                         return 0;
1393                 }
1394         }
1395
1396         if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0,
1397                         (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1398                         (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1399                         false, timings))
1400                 return 0;
1401         if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1402                         (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1403                         (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1404                         false, state->aspect_ratio, timings))
1405                 return 0;
1406
1407         v4l2_dbg(2, debug, sd,
1408                 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1409                 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1410                 stdi->hs_pol, stdi->vs_pol);
1411         return -1;
1412 }
1413
1414
1415 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1416 {
1417         struct adv76xx_state *state = to_state(sd);
1418         const struct adv76xx_chip_info *info = state->info;
1419         u8 polarity;
1420
1421         if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1422                 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1423                 return -1;
1424         }
1425
1426         /* read STDI */
1427         stdi->bl = cp_read16(sd, 0xb1, 0x3fff);
1428         stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff);
1429         stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1430         stdi->interlaced = io_read(sd, 0x12) & 0x10;
1431
1432         if (adv76xx_has_afe(state)) {
1433                 /* read SSPD */
1434                 polarity = cp_read(sd, 0xb5);
1435                 if ((polarity & 0x03) == 0x01) {
1436                         stdi->hs_pol = polarity & 0x10
1437                                      ? (polarity & 0x08 ? '+' : '-') : 'x';
1438                         stdi->vs_pol = polarity & 0x40
1439                                      ? (polarity & 0x20 ? '+' : '-') : 'x';
1440                 } else {
1441                         stdi->hs_pol = 'x';
1442                         stdi->vs_pol = 'x';
1443                 }
1444         } else {
1445                 polarity = hdmi_read(sd, 0x05);
1446                 stdi->hs_pol = polarity & 0x20 ? '+' : '-';
1447                 stdi->vs_pol = polarity & 0x10 ? '+' : '-';
1448         }
1449
1450         if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1451                 v4l2_dbg(2, debug, sd,
1452                         "%s: signal lost during readout of STDI/SSPD\n", __func__);
1453                 return -1;
1454         }
1455
1456         if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1457                 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1458                 memset(stdi, 0, sizeof(struct stdi_readback));
1459                 return -1;
1460         }
1461
1462         v4l2_dbg(2, debug, sd,
1463                 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1464                 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1465                 stdi->hs_pol, stdi->vs_pol,
1466                 stdi->interlaced ? "interlaced" : "progressive");
1467
1468         return 0;
1469 }
1470
1471 static int adv76xx_enum_dv_timings(struct v4l2_subdev *sd,
1472                         struct v4l2_enum_dv_timings *timings)
1473 {
1474         struct adv76xx_state *state = to_state(sd);
1475
1476         if (timings->pad >= state->source_pad)
1477                 return -EINVAL;
1478
1479         return v4l2_enum_dv_timings_cap(timings,
1480                 adv76xx_get_dv_timings_cap(sd, timings->pad),
1481                 adv76xx_check_dv_timings, NULL);
1482 }
1483
1484 static int adv76xx_dv_timings_cap(struct v4l2_subdev *sd,
1485                         struct v4l2_dv_timings_cap *cap)
1486 {
1487         struct adv76xx_state *state = to_state(sd);
1488         unsigned int pad = cap->pad;
1489
1490         if (cap->pad >= state->source_pad)
1491                 return -EINVAL;
1492
1493         *cap = *adv76xx_get_dv_timings_cap(sd, pad);
1494         cap->pad = pad;
1495
1496         return 0;
1497 }
1498
1499 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1500    if the format is listed in adv76xx_timings[] */
1501 static void adv76xx_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1502                 struct v4l2_dv_timings *timings)
1503 {
1504         v4l2_find_dv_timings_cap(timings, adv76xx_get_dv_timings_cap(sd, -1),
1505                                  is_digital_input(sd) ? 250000 : 1000000,
1506                                  adv76xx_check_dv_timings, NULL);
1507 }
1508
1509 static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1510 {
1511         unsigned int freq;
1512         int a, b;
1513
1514         a = hdmi_read(sd, 0x06);
1515         b = hdmi_read(sd, 0x3b);
1516         if (a < 0 || b < 0)
1517                 return 0;
1518         freq =  a * 1000000 + ((b & 0x30) >> 4) * 250000;
1519
1520         if (is_hdmi(sd)) {
1521                 /* adjust for deep color mode */
1522                 unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8;
1523
1524                 freq = freq * 8 / bits_per_channel;
1525         }
1526
1527         return freq;
1528 }
1529
1530 static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1531 {
1532         int a, b;
1533
1534         a = hdmi_read(sd, 0x51);
1535         b = hdmi_read(sd, 0x52);
1536         if (a < 0 || b < 0)
1537                 return 0;
1538         return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128;
1539 }
1540
1541 static int adv76xx_query_dv_timings(struct v4l2_subdev *sd,
1542                         struct v4l2_dv_timings *timings)
1543 {
1544         struct adv76xx_state *state = to_state(sd);
1545         const struct adv76xx_chip_info *info = state->info;
1546         struct v4l2_bt_timings *bt = &timings->bt;
1547         struct stdi_readback stdi;
1548
1549         if (!timings)
1550                 return -EINVAL;
1551
1552         memset(timings, 0, sizeof(struct v4l2_dv_timings));
1553
1554         if (no_signal(sd)) {
1555                 state->restart_stdi_once = true;
1556                 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1557                 return -ENOLINK;
1558         }
1559
1560         /* read STDI */
1561         if (read_stdi(sd, &stdi)) {
1562                 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1563                 return -ENOLINK;
1564         }
1565         bt->interlaced = stdi.interlaced ?
1566                 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1567
1568         if (is_digital_input(sd)) {
1569                 timings->type = V4L2_DV_BT_656_1120;
1570
1571                 bt->width = hdmi_read16(sd, 0x07, info->linewidth_mask);
1572                 bt->height = hdmi_read16(sd, 0x09, info->field0_height_mask);
1573                 bt->pixelclock = info->read_hdmi_pixelclock(sd);
1574                 bt->hfrontporch = hdmi_read16(sd, 0x20, info->hfrontporch_mask);
1575                 bt->hsync = hdmi_read16(sd, 0x22, info->hsync_mask);
1576                 bt->hbackporch = hdmi_read16(sd, 0x24, info->hbackporch_mask);
1577                 bt->vfrontporch = hdmi_read16(sd, 0x2a,
1578                         info->field0_vfrontporch_mask) / 2;
1579                 bt->vsync = hdmi_read16(sd, 0x2e, info->field0_vsync_mask) / 2;
1580                 bt->vbackporch = hdmi_read16(sd, 0x32,
1581                         info->field0_vbackporch_mask) / 2;
1582                 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1583                         ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1584                 if (bt->interlaced == V4L2_DV_INTERLACED) {
1585                         bt->height += hdmi_read16(sd, 0x0b,
1586                                 info->field1_height_mask);
1587                         bt->il_vfrontporch = hdmi_read16(sd, 0x2c,
1588                                 info->field1_vfrontporch_mask) / 2;
1589                         bt->il_vsync = hdmi_read16(sd, 0x30,
1590                                 info->field1_vsync_mask) / 2;
1591                         bt->il_vbackporch = hdmi_read16(sd, 0x34,
1592                                 info->field1_vbackporch_mask) / 2;
1593                 }
1594                 adv76xx_fill_optional_dv_timings_fields(sd, timings);
1595         } else {
1596                 /* find format
1597                  * Since LCVS values are inaccurate [REF_03, p. 275-276],
1598                  * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1599                  */
1600                 if (!stdi2dv_timings(sd, &stdi, timings))
1601                         goto found;
1602                 stdi.lcvs += 1;
1603                 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1604                 if (!stdi2dv_timings(sd, &stdi, timings))
1605                         goto found;
1606                 stdi.lcvs -= 2;
1607                 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1608                 if (stdi2dv_timings(sd, &stdi, timings)) {
1609                         /*
1610                          * The STDI block may measure wrong values, especially
1611                          * for lcvs and lcf. If the driver can not find any
1612                          * valid timing, the STDI block is restarted to measure
1613                          * the video timings again. The function will return an
1614                          * error, but the restart of STDI will generate a new
1615                          * STDI interrupt and the format detection process will
1616                          * restart.
1617                          */
1618                         if (state->restart_stdi_once) {
1619                                 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1620                                 /* TODO restart STDI for Sync Channel 2 */
1621                                 /* enter one-shot mode */
1622                                 cp_write_clr_set(sd, 0x86, 0x06, 0x00);
1623                                 /* trigger STDI restart */
1624                                 cp_write_clr_set(sd, 0x86, 0x06, 0x04);
1625                                 /* reset to continuous mode */
1626                                 cp_write_clr_set(sd, 0x86, 0x06, 0x02);
1627                                 state->restart_stdi_once = false;
1628                                 return -ENOLINK;
1629                         }
1630                         v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1631                         return -ERANGE;
1632                 }
1633                 state->restart_stdi_once = true;
1634         }
1635 found:
1636
1637         if (no_signal(sd)) {
1638                 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1639                 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1640                 return -ENOLINK;
1641         }
1642
1643         if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1644                         (is_digital_input(sd) && bt->pixelclock > 225000000)) {
1645                 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1646                                 __func__, (u32)bt->pixelclock);
1647                 return -ERANGE;
1648         }
1649
1650         if (debug > 1)
1651                 v4l2_print_dv_timings(sd->name, "adv76xx_query_dv_timings: ",
1652                                       timings, true);
1653
1654         return 0;
1655 }
1656
1657 static int adv76xx_s_dv_timings(struct v4l2_subdev *sd,
1658                 struct v4l2_dv_timings *timings)
1659 {
1660         struct adv76xx_state *state = to_state(sd);
1661         struct v4l2_bt_timings *bt;
1662         int err;
1663
1664         if (!timings)
1665                 return -EINVAL;
1666
1667         if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) {
1668                 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1669                 return 0;
1670         }
1671
1672         bt = &timings->bt;
1673
1674         if (!v4l2_valid_dv_timings(timings, adv76xx_get_dv_timings_cap(sd, -1),
1675                                    adv76xx_check_dv_timings, NULL))
1676                 return -ERANGE;
1677
1678         adv76xx_fill_optional_dv_timings_fields(sd, timings);
1679
1680         state->timings = *timings;
1681
1682         cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00);
1683
1684         /* Use prim_mode and vid_std when available */
1685         err = configure_predefined_video_timings(sd, timings);
1686         if (err) {
1687                 /* custom settings when the video format
1688                  does not have prim_mode/vid_std */
1689                 configure_custom_video_timings(sd, bt);
1690         }
1691
1692         set_rgb_quantization_range(sd);
1693
1694         if (debug > 1)
1695                 v4l2_print_dv_timings(sd->name, "adv76xx_s_dv_timings: ",
1696                                       timings, true);
1697         return 0;
1698 }
1699
1700 static int adv76xx_g_dv_timings(struct v4l2_subdev *sd,
1701                 struct v4l2_dv_timings *timings)
1702 {
1703         struct adv76xx_state *state = to_state(sd);
1704
1705         *timings = state->timings;
1706         return 0;
1707 }
1708
1709 static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable)
1710 {
1711         hdmi_write(sd, 0x01, enable ? 0x00 : 0x78);
1712 }
1713
1714 static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable)
1715 {
1716         hdmi_write(sd, 0x83, enable ? 0xfe : 0xff);
1717 }
1718
1719 static void enable_input(struct v4l2_subdev *sd)
1720 {
1721         struct adv76xx_state *state = to_state(sd);
1722
1723         if (is_analog_input(sd)) {
1724                 io_write(sd, 0x15, 0xb0);   /* Disable Tristate of Pins (no audio) */
1725         } else if (is_digital_input(sd)) {
1726                 hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input);
1727                 state->info->set_termination(sd, true);
1728                 io_write(sd, 0x15, 0xa0);   /* Disable Tristate of Pins */
1729                 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */
1730         } else {
1731                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1732                                 __func__, state->selected_input);
1733         }
1734 }
1735
1736 static void disable_input(struct v4l2_subdev *sd)
1737 {
1738         struct adv76xx_state *state = to_state(sd);
1739
1740         hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */
1741         msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */
1742         io_write(sd, 0x15, 0xbe);   /* Tristate all outputs from video core */
1743         state->info->set_termination(sd, false);
1744 }
1745
1746 static void select_input(struct v4l2_subdev *sd)
1747 {
1748         struct adv76xx_state *state = to_state(sd);
1749         const struct adv76xx_chip_info *info = state->info;
1750
1751         if (is_analog_input(sd)) {
1752                 adv76xx_write_reg_seq(sd, info->recommended_settings[0]);
1753
1754                 afe_write(sd, 0x00, 0x08); /* power up ADC */
1755                 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
1756                 afe_write(sd, 0xc8, 0x00); /* phase control */
1757         } else if (is_digital_input(sd)) {
1758                 hdmi_write(sd, 0x00, state->selected_input & 0x03);
1759
1760                 adv76xx_write_reg_seq(sd, info->recommended_settings[1]);
1761
1762                 if (adv76xx_has_afe(state)) {
1763                         afe_write(sd, 0x00, 0xff); /* power down ADC */
1764                         afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1765                         afe_write(sd, 0xc8, 0x40); /* phase control */
1766                 }
1767
1768                 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1769                 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1770                 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
1771         } else {
1772                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1773                                 __func__, state->selected_input);
1774         }
1775 }
1776
1777 static int adv76xx_s_routing(struct v4l2_subdev *sd,
1778                 u32 input, u32 output, u32 config)
1779 {
1780         struct adv76xx_state *state = to_state(sd);
1781
1782         v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d",
1783                         __func__, input, state->selected_input);
1784
1785         if (input == state->selected_input)
1786                 return 0;
1787
1788         if (input > state->info->max_port)
1789                 return -EINVAL;
1790
1791         state->selected_input = input;
1792
1793         disable_input(sd);
1794         select_input(sd);
1795         enable_input(sd);
1796
1797         v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt);
1798
1799         return 0;
1800 }
1801
1802 static int adv76xx_enum_mbus_code(struct v4l2_subdev *sd,
1803                                   struct v4l2_subdev_pad_config *cfg,
1804                                   struct v4l2_subdev_mbus_code_enum *code)
1805 {
1806         struct adv76xx_state *state = to_state(sd);
1807
1808         if (code->index >= state->info->nformats)
1809                 return -EINVAL;
1810
1811         code->code = state->info->formats[code->index].code;
1812
1813         return 0;
1814 }
1815
1816 static void adv76xx_fill_format(struct adv76xx_state *state,
1817                                 struct v4l2_mbus_framefmt *format)
1818 {
1819         memset(format, 0, sizeof(*format));
1820
1821         format->width = state->timings.bt.width;
1822         format->height = state->timings.bt.height;
1823         format->field = V4L2_FIELD_NONE;
1824         format->colorspace = V4L2_COLORSPACE_SRGB;
1825
1826         if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO)
1827                 format->colorspace = (state->timings.bt.height <= 576) ?
1828                         V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1829 }
1830
1831 /*
1832  * Compute the op_ch_sel value required to obtain on the bus the component order
1833  * corresponding to the selected format taking into account bus reordering
1834  * applied by the board at the output of the device.
1835  *
1836  * The following table gives the op_ch_value from the format component order
1837  * (expressed as op_ch_sel value in column) and the bus reordering (expressed as
1838  * adv76xx_bus_order value in row).
1839  *
1840  *           |  GBR(0)  GRB(1)  BGR(2)  RGB(3)  BRG(4)  RBG(5)
1841  * ----------+-------------------------------------------------
1842  * RGB (NOP) |  GBR     GRB     BGR     RGB     BRG     RBG
1843  * GRB (1-2) |  BGR     RGB     GBR     GRB     RBG     BRG
1844  * RBG (2-3) |  GRB     GBR     BRG     RBG     BGR     RGB
1845  * BGR (1-3) |  RBG     BRG     RGB     BGR     GRB     GBR
1846  * BRG (ROR) |  BRG     RBG     GRB     GBR     RGB     BGR
1847  * GBR (ROL) |  RGB     BGR     RBG     BRG     GBR     GRB
1848  */
1849 static unsigned int adv76xx_op_ch_sel(struct adv76xx_state *state)
1850 {
1851 #define _SEL(a,b,c,d,e,f)       { \
1852         ADV76XX_OP_CH_SEL_##a, ADV76XX_OP_CH_SEL_##b, ADV76XX_OP_CH_SEL_##c, \
1853         ADV76XX_OP_CH_SEL_##d, ADV76XX_OP_CH_SEL_##e, ADV76XX_OP_CH_SEL_##f }
1854 #define _BUS(x)                 [ADV7604_BUS_ORDER_##x]
1855
1856         static const unsigned int op_ch_sel[6][6] = {
1857                 _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG),
1858                 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),
1859                 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),
1860                 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),
1861                 _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR),
1862                 _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB),
1863         };
1864
1865         return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
1866 }
1867
1868 static void adv76xx_setup_format(struct adv76xx_state *state)
1869 {
1870         struct v4l2_subdev *sd = &state->sd;
1871
1872         io_write_clr_set(sd, 0x02, 0x02,
1873                         state->format->rgb_out ? ADV76XX_RGB_OUT : 0);
1874         io_write(sd, 0x03, state->format->op_format_sel |
1875                  state->pdata.op_format_mode_sel);
1876         io_write_clr_set(sd, 0x04, 0xe0, adv76xx_op_ch_sel(state));
1877         io_write_clr_set(sd, 0x05, 0x01,
1878                         state->format->swap_cb_cr ? ADV76XX_OP_SWAP_CB_CR : 0);
1879         set_rgb_quantization_range(sd);
1880 }
1881
1882 static int adv76xx_get_format(struct v4l2_subdev *sd,
1883                               struct v4l2_subdev_pad_config *cfg,
1884                               struct v4l2_subdev_format *format)
1885 {
1886         struct adv76xx_state *state = to_state(sd);
1887
1888         if (format->pad != state->source_pad)
1889                 return -EINVAL;
1890
1891         adv76xx_fill_format(state, &format->format);
1892
1893         if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1894                 struct v4l2_mbus_framefmt *fmt;
1895
1896                 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
1897                 format->format.code = fmt->code;
1898         } else {
1899                 format->format.code = state->format->code;
1900         }
1901
1902         return 0;
1903 }
1904
1905 static int adv76xx_get_selection(struct v4l2_subdev *sd,
1906                                  struct v4l2_subdev_pad_config *cfg,
1907                                  struct v4l2_subdev_selection *sel)
1908 {
1909         struct adv76xx_state *state = to_state(sd);
1910
1911         if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
1912                 return -EINVAL;
1913         /* Only CROP, CROP_DEFAULT and CROP_BOUNDS are supported */
1914         if (sel->target > V4L2_SEL_TGT_CROP_BOUNDS)
1915                 return -EINVAL;
1916
1917         sel->r.left     = 0;
1918         sel->r.top      = 0;
1919         sel->r.width    = state->timings.bt.width;
1920         sel->r.height   = state->timings.bt.height;
1921
1922         return 0;
1923 }
1924
1925 static int adv76xx_set_format(struct v4l2_subdev *sd,
1926                               struct v4l2_subdev_pad_config *cfg,
1927                               struct v4l2_subdev_format *format)
1928 {
1929         struct adv76xx_state *state = to_state(sd);
1930         const struct adv76xx_format_info *info;
1931
1932         if (format->pad != state->source_pad)
1933                 return -EINVAL;
1934
1935         info = adv76xx_format_info(state, format->format.code);
1936         if (info == NULL)
1937                 info = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
1938
1939         adv76xx_fill_format(state, &format->format);
1940         format->format.code = info->code;
1941
1942         if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1943                 struct v4l2_mbus_framefmt *fmt;
1944
1945                 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
1946                 fmt->code = format->format.code;
1947         } else {
1948                 state->format = info;
1949                 adv76xx_setup_format(state);
1950         }
1951
1952         return 0;
1953 }
1954
1955 #if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC)
1956 static void adv76xx_cec_tx_raw_status(struct v4l2_subdev *sd, u8 tx_raw_status)
1957 {
1958         struct adv76xx_state *state = to_state(sd);
1959
1960         if ((cec_read(sd, 0x11) & 0x01) == 0) {
1961                 v4l2_dbg(1, debug, sd, "%s: tx raw: tx disabled\n", __func__);
1962                 return;
1963         }
1964
1965         if (tx_raw_status & 0x02) {
1966                 v4l2_dbg(1, debug, sd, "%s: tx raw: arbitration lost\n",
1967                          __func__);
1968                 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_ARB_LOST,
1969                                   1, 0, 0, 0);
1970         }
1971         if (tx_raw_status & 0x04) {
1972                 u8 status;
1973                 u8 nack_cnt;
1974                 u8 low_drive_cnt;
1975
1976                 v4l2_dbg(1, debug, sd, "%s: tx raw: retry failed\n", __func__);
1977                 /*
1978                  * We set this status bit since this hardware performs
1979                  * retransmissions.
1980                  */
1981                 status = CEC_TX_STATUS_MAX_RETRIES;
1982                 nack_cnt = cec_read(sd, 0x14) & 0xf;
1983                 if (nack_cnt)
1984                         status |= CEC_TX_STATUS_NACK;
1985                 low_drive_cnt = cec_read(sd, 0x14) >> 4;
1986                 if (low_drive_cnt)
1987                         status |= CEC_TX_STATUS_LOW_DRIVE;
1988                 cec_transmit_done(state->cec_adap, status,
1989                                   0, nack_cnt, low_drive_cnt, 0);
1990                 return;
1991         }
1992         if (tx_raw_status & 0x01) {
1993                 v4l2_dbg(1, debug, sd, "%s: tx raw: ready ok\n", __func__);
1994                 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_OK, 0, 0, 0, 0);
1995                 return;
1996         }
1997 }
1998
1999 static void adv76xx_cec_isr(struct v4l2_subdev *sd, bool *handled)
2000 {
2001         struct adv76xx_state *state = to_state(sd);
2002         u8 cec_irq;
2003
2004         /* cec controller */
2005         cec_irq = io_read(sd, 0x4d) & 0x0f;
2006         if (!cec_irq)
2007                 return;
2008
2009         v4l2_dbg(1, debug, sd, "%s: cec: irq 0x%x\n", __func__, cec_irq);
2010         adv76xx_cec_tx_raw_status(sd, cec_irq);
2011         if (cec_irq & 0x08) {
2012                 struct cec_msg msg;
2013
2014                 msg.len = cec_read(sd, 0x25) & 0x1f;
2015                 if (msg.len > 16)
2016                         msg.len = 16;
2017
2018                 if (msg.len) {
2019                         u8 i;
2020
2021                         for (i = 0; i < msg.len; i++)
2022                                 msg.msg[i] = cec_read(sd, i + 0x15);
2023                         cec_write(sd, 0x26, 0x01); /* re-enable rx */
2024                         cec_received_msg(state->cec_adap, &msg);
2025                 }
2026         }
2027
2028         /* note: the bit order is swapped between 0x4d and 0x4e */
2029         cec_irq = ((cec_irq & 0x08) >> 3) | ((cec_irq & 0x04) >> 1) |
2030                   ((cec_irq & 0x02) << 1) | ((cec_irq & 0x01) << 3);
2031         io_write(sd, 0x4e, cec_irq);
2032
2033         if (handled)
2034                 *handled = true;
2035 }
2036
2037 static int adv76xx_cec_adap_enable(struct cec_adapter *adap, bool enable)
2038 {
2039         struct adv76xx_state *state = adap->priv;
2040         struct v4l2_subdev *sd = &state->sd;
2041
2042         if (!state->cec_enabled_adap && enable) {
2043                 cec_write_clr_set(sd, 0x2a, 0x01, 0x01); /* power up cec */
2044                 cec_write(sd, 0x2c, 0x01);      /* cec soft reset */
2045                 cec_write_clr_set(sd, 0x11, 0x01, 0); /* initially disable tx */
2046                 /* enabled irqs: */
2047                 /* tx: ready */
2048                 /* tx: arbitration lost */
2049                 /* tx: retry timeout */
2050                 /* rx: ready */
2051                 io_write_clr_set(sd, 0x50, 0x0f, 0x0f);
2052                 cec_write(sd, 0x26, 0x01);            /* enable rx */
2053         } else if (state->cec_enabled_adap && !enable) {
2054                 /* disable cec interrupts */
2055                 io_write_clr_set(sd, 0x50, 0x0f, 0x00);
2056                 /* disable address mask 1-3 */
2057                 cec_write_clr_set(sd, 0x27, 0x70, 0x00);
2058                 /* power down cec section */
2059                 cec_write_clr_set(sd, 0x2a, 0x01, 0x00);
2060                 state->cec_valid_addrs = 0;
2061         }
2062         state->cec_enabled_adap = enable;
2063         adv76xx_s_detect_tx_5v_ctrl(sd);
2064         return 0;
2065 }
2066
2067 static int adv76xx_cec_adap_log_addr(struct cec_adapter *adap, u8 addr)
2068 {
2069         struct adv76xx_state *state = adap->priv;
2070         struct v4l2_subdev *sd = &state->sd;
2071         unsigned int i, free_idx = ADV76XX_MAX_ADDRS;
2072
2073         if (!state->cec_enabled_adap)
2074                 return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO;
2075
2076         if (addr == CEC_LOG_ADDR_INVALID) {
2077                 cec_write_clr_set(sd, 0x27, 0x70, 0);
2078                 state->cec_valid_addrs = 0;
2079                 return 0;
2080         }
2081
2082         for (i = 0; i < ADV76XX_MAX_ADDRS; i++) {
2083                 bool is_valid = state->cec_valid_addrs & (1 << i);
2084
2085                 if (free_idx == ADV76XX_MAX_ADDRS && !is_valid)
2086                         free_idx = i;
2087                 if (is_valid && state->cec_addr[i] == addr)
2088                         return 0;
2089         }
2090         if (i == ADV76XX_MAX_ADDRS) {
2091                 i = free_idx;
2092                 if (i == ADV76XX_MAX_ADDRS)
2093                         return -ENXIO;
2094         }
2095         state->cec_addr[i] = addr;
2096         state->cec_valid_addrs |= 1 << i;
2097
2098         switch (i) {
2099         case 0:
2100                 /* enable address mask 0 */
2101                 cec_write_clr_set(sd, 0x27, 0x10, 0x10);
2102                 /* set address for mask 0 */
2103                 cec_write_clr_set(sd, 0x28, 0x0f, addr);
2104                 break;
2105         case 1:
2106                 /* enable address mask 1 */
2107                 cec_write_clr_set(sd, 0x27, 0x20, 0x20);
2108                 /* set address for mask 1 */
2109                 cec_write_clr_set(sd, 0x28, 0xf0, addr << 4);
2110                 break;
2111         case 2:
2112                 /* enable address mask 2 */
2113                 cec_write_clr_set(sd, 0x27, 0x40, 0x40);
2114                 /* set address for mask 1 */
2115                 cec_write_clr_set(sd, 0x29, 0x0f, addr);
2116                 break;
2117         }
2118         return 0;
2119 }
2120
2121 static int adv76xx_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2122                                      u32 signal_free_time, struct cec_msg *msg)
2123 {
2124         struct adv76xx_state *state = adap->priv;
2125         struct v4l2_subdev *sd = &state->sd;
2126         u8 len = msg->len;
2127         unsigned int i;
2128
2129         /*
2130          * The number of retries is the number of attempts - 1, but retry
2131          * at least once. It's not clear if a value of 0 is allowed, so
2132          * let's do at least one retry.
2133          */
2134         cec_write_clr_set(sd, 0x12, 0x70, max(1, attempts - 1) << 4);
2135
2136         if (len > 16) {
2137                 v4l2_err(sd, "%s: len exceeded 16 (%d)\n", __func__, len);
2138                 return -EINVAL;
2139         }
2140
2141         /* write data */
2142         for (i = 0; i < len; i++)
2143                 cec_write(sd, i, msg->msg[i]);
2144
2145         /* set length (data + header) */
2146         cec_write(sd, 0x10, len);
2147         /* start transmit, enable tx */
2148         cec_write(sd, 0x11, 0x01);
2149         return 0;
2150 }
2151
2152 static const struct cec_adap_ops adv76xx_cec_adap_ops = {
2153         .adap_enable = adv76xx_cec_adap_enable,
2154         .adap_log_addr = adv76xx_cec_adap_log_addr,
2155         .adap_transmit = adv76xx_cec_adap_transmit,
2156 };
2157 #endif
2158
2159 static int adv76xx_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
2160 {
2161         struct adv76xx_state *state = to_state(sd);
2162         const struct adv76xx_chip_info *info = state->info;
2163         const u8 irq_reg_0x43 = io_read(sd, 0x43);
2164         const u8 irq_reg_0x6b = io_read(sd, 0x6b);
2165         const u8 irq_reg_0x70 = io_read(sd, 0x70);
2166         u8 fmt_change_digital;
2167         u8 fmt_change;
2168         u8 tx_5v;
2169
2170         if (irq_reg_0x43)
2171                 io_write(sd, 0x44, irq_reg_0x43);
2172         if (irq_reg_0x70)
2173                 io_write(sd, 0x71, irq_reg_0x70);
2174         if (irq_reg_0x6b)
2175                 io_write(sd, 0x6c, irq_reg_0x6b);
2176
2177         v4l2_dbg(2, debug, sd, "%s: ", __func__);
2178
2179         /* format change */
2180         fmt_change = irq_reg_0x43 & 0x98;
2181         fmt_change_digital = is_digital_input(sd)
2182                            ? irq_reg_0x6b & info->fmt_change_digital_mask
2183                            : 0;
2184
2185         if (fmt_change || fmt_change_digital) {
2186                 v4l2_dbg(1, debug, sd,
2187                         "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
2188                         __func__, fmt_change, fmt_change_digital);
2189
2190                 v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt);
2191
2192                 if (handled)
2193                         *handled = true;
2194         }
2195         /* HDMI/DVI mode */
2196         if (irq_reg_0x6b & 0x01) {
2197                 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
2198                         (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI");
2199                 set_rgb_quantization_range(sd);
2200                 if (handled)
2201                         *handled = true;
2202         }
2203
2204 #if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC)
2205         /* cec */
2206         adv76xx_cec_isr(sd, handled);
2207 #endif
2208
2209         /* tx 5v detect */
2210         tx_5v = irq_reg_0x70 & info->cable_det_mask;
2211         if (tx_5v) {
2212                 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
2213                 adv76xx_s_detect_tx_5v_ctrl(sd);
2214                 if (handled)
2215                         *handled = true;
2216         }
2217         return 0;
2218 }
2219
2220 static int adv76xx_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2221 {
2222         struct adv76xx_state *state = to_state(sd);
2223         u8 *data = NULL;
2224
2225         memset(edid->reserved, 0, sizeof(edid->reserved));
2226
2227         switch (edid->pad) {
2228         case ADV76XX_PAD_HDMI_PORT_A:
2229         case ADV7604_PAD_HDMI_PORT_B:
2230         case ADV7604_PAD_HDMI_PORT_C:
2231         case ADV7604_PAD_HDMI_PORT_D:
2232                 if (state->edid.present & (1 << edid->pad))
2233                         data = state->edid.edid;
2234                 break;
2235         default:
2236                 return -EINVAL;
2237         }
2238
2239         if (edid->start_block == 0 && edid->blocks == 0) {
2240                 edid->blocks = data ? state->edid.blocks : 0;
2241                 return 0;
2242         }
2243
2244         if (data == NULL)
2245                 return -ENODATA;
2246
2247         if (edid->start_block >= state->edid.blocks)
2248                 return -EINVAL;
2249
2250         if (edid->start_block + edid->blocks > state->edid.blocks)
2251                 edid->blocks = state->edid.blocks - edid->start_block;
2252
2253         memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128);
2254
2255         return 0;
2256 }
2257
2258 static int adv76xx_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2259 {
2260         struct adv76xx_state *state = to_state(sd);
2261         const struct adv76xx_chip_info *info = state->info;
2262         unsigned int spa_loc;
2263         u16 pa;
2264         int err;
2265         int i;
2266
2267         memset(edid->reserved, 0, sizeof(edid->reserved));
2268
2269         if (edid->pad > ADV7604_PAD_HDMI_PORT_D)
2270                 return -EINVAL;
2271         if (edid->start_block != 0)
2272                 return -EINVAL;
2273         if (edid->blocks == 0) {
2274                 /* Disable hotplug and I2C access to EDID RAM from DDC port */
2275                 state->edid.present &= ~(1 << edid->pad);
2276                 adv76xx_set_hpd(state, state->edid.present);
2277                 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
2278
2279                 /* Fall back to a 16:9 aspect ratio */
2280                 state->aspect_ratio.numerator = 16;
2281                 state->aspect_ratio.denominator = 9;
2282
2283                 if (!state->edid.present)
2284                         state->edid.blocks = 0;
2285
2286                 v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n",
2287                                 __func__, edid->pad, state->edid.present);
2288                 return 0;
2289         }
2290         if (edid->blocks > 2) {
2291                 edid->blocks = 2;
2292                 return -E2BIG;
2293         }
2294         pa = cec_get_edid_phys_addr(edid->edid, edid->blocks * 128, &spa_loc);
2295         err = cec_phys_addr_validate(pa, &pa, NULL);
2296         if (err)
2297                 return err;
2298
2299         v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n",
2300                         __func__, edid->pad, state->edid.present);
2301
2302         /* Disable hotplug and I2C access to EDID RAM from DDC port */
2303         cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
2304         adv76xx_set_hpd(state, 0);
2305         rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00);
2306
2307         /*
2308          * Return an error if no location of the source physical address
2309          * was found.
2310          */
2311         if (spa_loc == 0)
2312                 return -EINVAL;
2313
2314         switch (edid->pad) {
2315         case ADV76XX_PAD_HDMI_PORT_A:
2316                 state->spa_port_a[0] = edid->edid[spa_loc];
2317                 state->spa_port_a[1] = edid->edid[spa_loc + 1];
2318                 break;
2319         case ADV7604_PAD_HDMI_PORT_B:
2320                 rep_write(sd, 0x70, edid->edid[spa_loc]);
2321                 rep_write(sd, 0x71, edid->edid[spa_loc + 1]);
2322                 break;
2323         case ADV7604_PAD_HDMI_PORT_C:
2324                 rep_write(sd, 0x72, edid->edid[spa_loc]);
2325                 rep_write(sd, 0x73, edid->edid[spa_loc + 1]);
2326                 break;
2327         case ADV7604_PAD_HDMI_PORT_D:
2328                 rep_write(sd, 0x74, edid->edid[spa_loc]);
2329                 rep_write(sd, 0x75, edid->edid[spa_loc + 1]);
2330                 break;
2331         default:
2332                 return -EINVAL;
2333         }
2334
2335         if (info->type == ADV7604) {
2336                 rep_write(sd, 0x76, spa_loc & 0xff);
2337                 rep_write_clr_set(sd, 0x77, 0x40, (spa_loc & 0x100) >> 2);
2338         } else {
2339                 /* ADV7612 Software Manual Rev. A, p. 15 */
2340                 rep_write(sd, 0x70, spa_loc & 0xff);
2341                 rep_write_clr_set(sd, 0x71, 0x01, (spa_loc & 0x100) >> 8);
2342         }
2343
2344         edid->edid[spa_loc] = state->spa_port_a[0];
2345         edid->edid[spa_loc + 1] = state->spa_port_a[1];
2346
2347         memcpy(state->edid.edid, edid->edid, 128 * edid->blocks);
2348         state->edid.blocks = edid->blocks;
2349         state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
2350                         edid->edid[0x16]);
2351         state->edid.present |= 1 << edid->pad;
2352
2353         err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid);
2354         if (err < 0) {
2355                 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad);
2356                 return err;
2357         }
2358
2359         /* adv76xx calculates the checksums and enables I2C access to internal
2360            EDID RAM from DDC port. */
2361         rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
2362
2363         for (i = 0; i < 1000; i++) {
2364                 if (rep_read(sd, info->edid_status_reg) & state->edid.present)
2365                         break;
2366                 mdelay(1);
2367         }
2368         if (i == 1000) {
2369                 v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present);
2370                 return -EIO;
2371         }
2372         cec_s_phys_addr(state->cec_adap, pa, false);
2373
2374         /* enable hotplug after 100 ms */
2375         schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 10);
2376         return 0;
2377 }
2378
2379 /*********** avi info frame CEA-861-E **************/
2380
2381 static const struct adv76xx_cfg_read_infoframe adv76xx_cri[] = {
2382         { "AVI", 0x01, 0xe0, 0x00 },
2383         { "Audio", 0x02, 0xe3, 0x1c },
2384         { "SDP", 0x04, 0xe6, 0x2a },
2385         { "Vendor", 0x10, 0xec, 0x54 }
2386 };
2387
2388 static int adv76xx_read_infoframe(struct v4l2_subdev *sd, int index,
2389                                   union hdmi_infoframe *frame)
2390 {
2391         uint8_t buffer[32];
2392         u8 len;
2393         int i;
2394
2395         if (!(io_read(sd, 0x60) & adv76xx_cri[index].present_mask)) {
2396                 v4l2_info(sd, "%s infoframe not received\n",
2397                           adv76xx_cri[index].desc);
2398                 return -ENOENT;
2399         }
2400
2401         for (i = 0; i < 3; i++)
2402                 buffer[i] = infoframe_read(sd,
2403                                            adv76xx_cri[index].head_addr + i);
2404
2405         len = buffer[2] + 1;
2406
2407         if (len + 3 > sizeof(buffer)) {
2408                 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__,
2409                          adv76xx_cri[index].desc, len);
2410                 return -ENOENT;
2411         }
2412
2413         for (i = 0; i < len; i++)
2414                 buffer[i + 3] = infoframe_read(sd,
2415                                        adv76xx_cri[index].payload_addr + i);
2416
2417         if (hdmi_infoframe_unpack(frame, buffer) < 0) {
2418                 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__,
2419                          adv76xx_cri[index].desc);
2420                 return -ENOENT;
2421         }
2422         return 0;
2423 }
2424
2425 static void adv76xx_log_infoframes(struct v4l2_subdev *sd)
2426 {
2427         int i;
2428
2429         if (!is_hdmi(sd)) {
2430                 v4l2_info(sd, "receive DVI-D signal, no infoframes\n");
2431                 return;
2432         }
2433
2434         for (i = 0; i < ARRAY_SIZE(adv76xx_cri); i++) {
2435                 union hdmi_infoframe frame;
2436                 struct i2c_client *client = v4l2_get_subdevdata(sd);
2437
2438                 if (adv76xx_read_infoframe(sd, i, &frame))
2439                         return;
2440                 hdmi_infoframe_log(KERN_INFO, &client->dev, &frame);
2441         }
2442 }
2443
2444 static int adv76xx_log_status(struct v4l2_subdev *sd)
2445 {
2446         struct adv76xx_state *state = to_state(sd);
2447         const struct adv76xx_chip_info *info = state->info;
2448         struct v4l2_dv_timings timings;
2449         struct stdi_readback stdi;
2450         u8 reg_io_0x02 = io_read(sd, 0x02);
2451         u8 edid_enabled;
2452         u8 cable_det;
2453
2454         static const char * const csc_coeff_sel_rb[16] = {
2455                 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2456                 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2457                 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2458                 "reserved", "reserved", "reserved", "reserved", "manual"
2459         };
2460         static const char * const input_color_space_txt[16] = {
2461                 "RGB limited range (16-235)", "RGB full range (0-255)",
2462                 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2463                 "xvYCC Bt.601", "xvYCC Bt.709",
2464                 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2465                 "invalid", "invalid", "invalid", "invalid", "invalid",
2466                 "invalid", "invalid", "automatic"
2467         };
2468         static const char * const hdmi_color_space_txt[16] = {
2469                 "RGB limited range (16-235)", "RGB full range (0-255)",
2470                 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2471                 "xvYCC Bt.601", "xvYCC Bt.709",
2472                 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2473                 "sYCC", "Adobe YCC 601", "AdobeRGB", "invalid", "invalid",
2474                 "invalid", "invalid", "invalid"
2475         };
2476         static const char * const rgb_quantization_range_txt[] = {
2477                 "Automatic",
2478                 "RGB limited range (16-235)",
2479                 "RGB full range (0-255)",
2480         };
2481         static const char * const deep_color_mode_txt[4] = {
2482                 "8-bits per channel",
2483                 "10-bits per channel",
2484                 "12-bits per channel",
2485                 "16-bits per channel (not supported)"
2486         };
2487
2488         v4l2_info(sd, "-----Chip status-----\n");
2489         v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
2490         edid_enabled = rep_read(sd, info->edid_status_reg);
2491         v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n",
2492                         ((edid_enabled & 0x01) ? "Yes" : "No"),
2493                         ((edid_enabled & 0x02) ? "Yes" : "No"),
2494                         ((edid_enabled & 0x04) ? "Yes" : "No"),
2495                         ((edid_enabled & 0x08) ? "Yes" : "No"));
2496         v4l2_info(sd, "CEC: %s\n", state->cec_enabled_adap ?
2497                         "enabled" : "disabled");
2498         if (state->cec_enabled_adap) {
2499                 int i;
2500
2501                 for (i = 0; i < ADV76XX_MAX_ADDRS; i++) {
2502                         bool is_valid = state->cec_valid_addrs & (1 << i);
2503
2504                         if (is_valid)
2505                                 v4l2_info(sd, "CEC Logical Address: 0x%x\n",
2506                                           state->cec_addr[i]);
2507                 }
2508         }
2509
2510         v4l2_info(sd, "-----Signal status-----\n");
2511         cable_det = info->read_cable_det(sd);
2512         v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n",
2513                         ((cable_det & 0x01) ? "Yes" : "No"),
2514                         ((cable_det & 0x02) ? "Yes" : "No"),
2515                         ((cable_det & 0x04) ? "Yes" : "No"),
2516                         ((cable_det & 0x08) ? "Yes" : "No"));
2517         v4l2_info(sd, "TMDS signal detected: %s\n",
2518                         no_signal_tmds(sd) ? "false" : "true");
2519         v4l2_info(sd, "TMDS signal locked: %s\n",
2520                         no_lock_tmds(sd) ? "false" : "true");
2521         v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
2522         v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
2523         v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
2524         v4l2_info(sd, "CP free run: %s\n",
2525                         (in_free_run(sd)) ? "on" : "off");
2526         v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2527                         io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2528                         (io_read(sd, 0x01) & 0x70) >> 4);
2529
2530         v4l2_info(sd, "-----Video Timings-----\n");
2531         if (read_stdi(sd, &stdi))
2532                 v4l2_info(sd, "STDI: not locked\n");
2533         else
2534                 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
2535                                 stdi.lcf, stdi.bl, stdi.lcvs,
2536                                 stdi.interlaced ? "interlaced" : "progressive",
2537                                 stdi.hs_pol, stdi.vs_pol);
2538         if (adv76xx_query_dv_timings(sd, &timings))
2539                 v4l2_info(sd, "No video detected\n");
2540         else
2541                 v4l2_print_dv_timings(sd->name, "Detected format: ",
2542                                       &timings, true);
2543         v4l2_print_dv_timings(sd->name, "Configured format: ",
2544                               &state->timings, true);
2545
2546         if (no_signal(sd))
2547                 return 0;
2548
2549         v4l2_info(sd, "-----Color space-----\n");
2550         v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2551                         rgb_quantization_range_txt[state->rgb_quantization_range]);
2552         v4l2_info(sd, "Input color space: %s\n",
2553                         input_color_space_txt[reg_io_0x02 >> 4]);
2554         v4l2_info(sd, "Output color space: %s %s, alt-gamma %s\n",
2555                         (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2556                         (((reg_io_0x02 >> 2) & 0x01) ^ (reg_io_0x02 & 0x01)) ?
2557                                 "(16-235)" : "(0-255)",
2558                         (reg_io_0x02 & 0x08) ? "enabled" : "disabled");
2559         v4l2_info(sd, "Color space conversion: %s\n",
2560                         csc_coeff_sel_rb[cp_read(sd, info->cp_csc) >> 4]);
2561
2562         if (!is_digital_input(sd))
2563                 return 0;
2564
2565         v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
2566         v4l2_info(sd, "Digital video port selected: %c\n",
2567                         (hdmi_read(sd, 0x00) & 0x03) + 'A');
2568         v4l2_info(sd, "HDCP encrypted content: %s\n",
2569                         (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
2570         v4l2_info(sd, "HDCP keys read: %s%s\n",
2571                         (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2572                         (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
2573         if (is_hdmi(sd)) {
2574                 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2575                 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2576                 bool audio_mute = io_read(sd, 0x65) & 0x40;
2577
2578                 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2579                                 audio_pll_locked ? "locked" : "not locked",
2580                                 audio_sample_packet_detect ? "detected" : "not detected",
2581                                 audio_mute ? "muted" : "enabled");
2582                 if (audio_pll_locked && audio_sample_packet_detect) {
2583                         v4l2_info(sd, "Audio format: %s\n",
2584                                         (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo");
2585                 }
2586                 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2587                                 (hdmi_read(sd, 0x5c) << 8) +
2588                                 (hdmi_read(sd, 0x5d) & 0xf0));
2589                 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2590                                 (hdmi_read(sd, 0x5e) << 8) +
2591                                 hdmi_read(sd, 0x5f));
2592                 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2593
2594                 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]);
2595                 v4l2_info(sd, "HDMI colorspace: %s\n", hdmi_color_space_txt[hdmi_read(sd, 0x53) & 0xf]);
2596
2597                 adv76xx_log_infoframes(sd);
2598         }
2599
2600         return 0;
2601 }
2602
2603 static int adv76xx_subscribe_event(struct v4l2_subdev *sd,
2604                                    struct v4l2_fh *fh,
2605                                    struct v4l2_event_subscription *sub)
2606 {
2607         switch (sub->type) {
2608         case V4L2_EVENT_SOURCE_CHANGE:
2609                 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
2610         case V4L2_EVENT_CTRL:
2611                 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
2612         default:
2613                 return -EINVAL;
2614         }
2615 }
2616
2617 static int adv76xx_registered(struct v4l2_subdev *sd)
2618 {
2619         struct adv76xx_state *state = to_state(sd);
2620         int err;
2621
2622         err = cec_register_adapter(state->cec_adap);
2623         if (err)
2624                 cec_delete_adapter(state->cec_adap);
2625         return err;
2626 }
2627
2628 static void adv76xx_unregistered(struct v4l2_subdev *sd)
2629 {
2630         struct adv76xx_state *state = to_state(sd);
2631
2632         cec_unregister_adapter(state->cec_adap);
2633 }
2634
2635 /* ----------------------------------------------------------------------- */
2636
2637 static const struct v4l2_ctrl_ops adv76xx_ctrl_ops = {
2638         .s_ctrl = adv76xx_s_ctrl,
2639         .g_volatile_ctrl = adv76xx_g_volatile_ctrl,
2640 };
2641
2642 static const struct v4l2_subdev_core_ops adv76xx_core_ops = {
2643         .log_status = adv76xx_log_status,
2644         .interrupt_service_routine = adv76xx_isr,
2645         .subscribe_event = adv76xx_subscribe_event,
2646         .unsubscribe_event = v4l2_event_subdev_unsubscribe,
2647 #ifdef CONFIG_VIDEO_ADV_DEBUG
2648         .g_register = adv76xx_g_register,
2649         .s_register = adv76xx_s_register,
2650 #endif
2651 };
2652
2653 static const struct v4l2_subdev_video_ops adv76xx_video_ops = {
2654         .s_routing = adv76xx_s_routing,
2655         .g_input_status = adv76xx_g_input_status,
2656         .s_dv_timings = adv76xx_s_dv_timings,
2657         .g_dv_timings = adv76xx_g_dv_timings,
2658         .query_dv_timings = adv76xx_query_dv_timings,
2659 };
2660
2661 static const struct v4l2_subdev_pad_ops adv76xx_pad_ops = {
2662         .enum_mbus_code = adv76xx_enum_mbus_code,
2663         .get_selection = adv76xx_get_selection,
2664         .get_fmt = adv76xx_get_format,
2665         .set_fmt = adv76xx_set_format,
2666         .get_edid = adv76xx_get_edid,
2667         .set_edid = adv76xx_set_edid,
2668         .dv_timings_cap = adv76xx_dv_timings_cap,
2669         .enum_dv_timings = adv76xx_enum_dv_timings,
2670 };
2671
2672 static const struct v4l2_subdev_ops adv76xx_ops = {
2673         .core = &adv76xx_core_ops,
2674         .video = &adv76xx_video_ops,
2675         .pad = &adv76xx_pad_ops,
2676 };
2677
2678 static const struct v4l2_subdev_internal_ops adv76xx_int_ops = {
2679         .registered = adv76xx_registered,
2680         .unregistered = adv76xx_unregistered,
2681 };
2682
2683 /* -------------------------- custom ctrls ---------------------------------- */
2684
2685 static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
2686         .ops = &adv76xx_ctrl_ops,
2687         .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
2688         .name = "Analog Sampling Phase",
2689         .type = V4L2_CTRL_TYPE_INTEGER,
2690         .min = 0,
2691         .max = 0x1f,
2692         .step = 1,
2693         .def = 0,
2694 };
2695
2696 static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color_manual = {
2697         .ops = &adv76xx_ctrl_ops,
2698         .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
2699         .name = "Free Running Color, Manual",
2700         .type = V4L2_CTRL_TYPE_BOOLEAN,
2701         .min = false,
2702         .max = true,
2703         .step = 1,
2704         .def = false,
2705 };
2706
2707 static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color = {
2708         .ops = &adv76xx_ctrl_ops,
2709         .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
2710         .name = "Free Running Color",
2711         .type = V4L2_CTRL_TYPE_INTEGER,
2712         .min = 0x0,
2713         .max = 0xffffff,
2714         .step = 0x1,
2715         .def = 0x0,
2716 };
2717
2718 /* ----------------------------------------------------------------------- */
2719
2720 static int adv76xx_core_init(struct v4l2_subdev *sd)
2721 {
2722         struct adv76xx_state *state = to_state(sd);
2723         const struct adv76xx_chip_info *info = state->info;
2724         struct adv76xx_platform_data *pdata = &state->pdata;
2725
2726         hdmi_write(sd, 0x48,
2727                 (pdata->disable_pwrdnb ? 0x80 : 0) |
2728                 (pdata->disable_cable_det_rst ? 0x40 : 0));
2729
2730         disable_input(sd);
2731
2732         if (pdata->default_input >= 0 &&
2733             pdata->default_input < state->source_pad) {
2734                 state->selected_input = pdata->default_input;
2735                 select_input(sd);
2736                 enable_input(sd);
2737         }
2738
2739         /* power */
2740         io_write(sd, 0x0c, 0x42);   /* Power up part and power down VDP */
2741         io_write(sd, 0x0b, 0x44);   /* Power down ESDP block */
2742         cp_write(sd, 0xcf, 0x01);   /* Power down macrovision */
2743
2744         /* video format */
2745         io_write_clr_set(sd, 0x02, 0x0f, pdata->alt_gamma << 3);
2746         io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 |
2747                         pdata->insert_av_codes << 2 |
2748                         pdata->replicate_av_codes << 1);
2749         adv76xx_setup_format(state);
2750
2751         cp_write(sd, 0x69, 0x30);   /* Enable CP CSC */
2752
2753         /* VS, HS polarities */
2754         io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 |
2755                  pdata->inv_hs_pol << 1 | pdata->inv_llc_pol);
2756
2757         /* Adjust drive strength */
2758         io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 |
2759                                 pdata->dr_str_clk << 2 |
2760                                 pdata->dr_str_sync);
2761
2762         cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
2763         cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2764         cp_write(sd, 0xf9, 0x23); /*  STDI ch. 1 - LCVS change threshold -
2765                                       ADI recommended setting [REF_01, c. 2.3.3] */
2766         cp_write(sd, 0x45, 0x23); /*  STDI ch. 2 - LCVS change threshold -
2767                                       ADI recommended setting [REF_01, c. 2.3.3] */
2768         cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
2769                                      for digital formats */
2770
2771         /* HDMI audio */
2772         hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */
2773         hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */
2774         hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */
2775
2776         /* TODO from platform data */
2777         afe_write(sd, 0xb5, 0x01);  /* Setting MCLK to 256Fs */
2778
2779         if (adv76xx_has_afe(state)) {
2780                 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
2781                 io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4);
2782         }
2783
2784         /* interrupts */
2785         io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */
2786         io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
2787         io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
2788         io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */
2789         info->setup_irqs(sd);
2790
2791         return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2792 }
2793
2794 static void adv7604_setup_irqs(struct v4l2_subdev *sd)
2795 {
2796         io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
2797 }
2798
2799 static void adv7611_setup_irqs(struct v4l2_subdev *sd)
2800 {
2801         io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */
2802 }
2803
2804 static void adv7612_setup_irqs(struct v4l2_subdev *sd)
2805 {
2806         io_write(sd, 0x41, 0xd0); /* disable INT2 */
2807 }
2808
2809 static void adv76xx_unregister_clients(struct adv76xx_state *state)
2810 {
2811         unsigned int i;
2812
2813         for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i) {
2814                 if (state->i2c_clients[i])
2815                         i2c_unregister_device(state->i2c_clients[i]);
2816         }
2817 }
2818
2819 static struct i2c_client *adv76xx_dummy_client(struct v4l2_subdev *sd,
2820                                                         u8 addr, u8 io_reg)
2821 {
2822         struct i2c_client *client = v4l2_get_subdevdata(sd);
2823
2824         if (addr)
2825                 io_write(sd, io_reg, addr << 1);
2826         return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
2827 }
2828
2829 static const struct adv76xx_reg_seq adv7604_recommended_settings_afe[] = {
2830         /* reset ADI recommended settings for HDMI: */
2831         /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
2832         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2833         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2834         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */
2835         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */
2836         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2837         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */
2838         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */
2839         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2840         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2841         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */
2842         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */
2843         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */
2844
2845         /* set ADI recommended settings for digitizer */
2846         /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
2847         { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */
2848         { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */
2849         { ADV76XX_REG(ADV76XX_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */
2850         { ADV76XX_REG(ADV76XX_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */
2851         { ADV76XX_REG(ADV76XX_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */
2852
2853         { ADV76XX_REG_SEQ_TERM, 0 },
2854 };
2855
2856 static const struct adv76xx_reg_seq adv7604_recommended_settings_hdmi[] = {
2857         /* set ADI recommended settings for HDMI: */
2858         /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
2859         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */
2860         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */
2861         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */
2862         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2863         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */
2864         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */
2865         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2866         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2867         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */
2868         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */
2869         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */
2870
2871         /* reset ADI recommended settings for digitizer */
2872         /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
2873         { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */
2874         { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */
2875
2876         { ADV76XX_REG_SEQ_TERM, 0 },
2877 };
2878
2879 static const struct adv76xx_reg_seq adv7611_recommended_settings_hdmi[] = {
2880         /* ADV7611 Register Settings Recommendations Rev 1.5, May 2014 */
2881         { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
2882         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
2883         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
2884         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
2885         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
2886         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
2887         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
2888         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
2889         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },
2890         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x04 },
2891         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x1e },
2892
2893         { ADV76XX_REG_SEQ_TERM, 0 },
2894 };
2895
2896 static const struct adv76xx_reg_seq adv7612_recommended_settings_hdmi[] = {
2897         { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
2898         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
2899         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
2900         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
2901         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
2902         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
2903         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
2904         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
2905         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },
2906         { ADV76XX_REG_SEQ_TERM, 0 },
2907 };
2908
2909 static const struct adv76xx_chip_info adv76xx_chip_info[] = {
2910         [ADV7604] = {
2911                 .type = ADV7604,
2912                 .has_afe = true,
2913                 .max_port = ADV7604_PAD_VGA_COMP,
2914                 .num_dv_ports = 4,
2915                 .edid_enable_reg = 0x77,
2916                 .edid_status_reg = 0x7d,
2917                 .lcf_reg = 0xb3,
2918                 .tdms_lock_mask = 0xe0,
2919                 .cable_det_mask = 0x1e,
2920                 .fmt_change_digital_mask = 0xc1,
2921                 .cp_csc = 0xfc,
2922                 .formats = adv7604_formats,
2923                 .nformats = ARRAY_SIZE(adv7604_formats),
2924                 .set_termination = adv7604_set_termination,
2925                 .setup_irqs = adv7604_setup_irqs,
2926                 .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock,
2927                 .read_cable_det = adv7604_read_cable_det,
2928                 .recommended_settings = {
2929                     [0] = adv7604_recommended_settings_afe,
2930                     [1] = adv7604_recommended_settings_hdmi,
2931                 },
2932                 .num_recommended_settings = {
2933                     [0] = ARRAY_SIZE(adv7604_recommended_settings_afe),
2934                     [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi),
2935                 },
2936                 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) |
2937                         BIT(ADV76XX_PAGE_CEC) | BIT(ADV76XX_PAGE_INFOFRAME) |
2938                         BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) |
2939                         BIT(ADV76XX_PAGE_AFE) | BIT(ADV76XX_PAGE_REP) |
2940                         BIT(ADV76XX_PAGE_EDID) | BIT(ADV76XX_PAGE_HDMI) |
2941                         BIT(ADV76XX_PAGE_TEST) | BIT(ADV76XX_PAGE_CP) |
2942                         BIT(ADV7604_PAGE_VDP),
2943                 .linewidth_mask = 0xfff,
2944                 .field0_height_mask = 0xfff,
2945                 .field1_height_mask = 0xfff,
2946                 .hfrontporch_mask = 0x3ff,
2947                 .hsync_mask = 0x3ff,
2948                 .hbackporch_mask = 0x3ff,
2949                 .field0_vfrontporch_mask = 0x1fff,
2950                 .field0_vsync_mask = 0x1fff,
2951                 .field0_vbackporch_mask = 0x1fff,
2952                 .field1_vfrontporch_mask = 0x1fff,
2953                 .field1_vsync_mask = 0x1fff,
2954                 .field1_vbackporch_mask = 0x1fff,
2955         },
2956         [ADV7611] = {
2957                 .type = ADV7611,
2958                 .has_afe = false,
2959                 .max_port = ADV76XX_PAD_HDMI_PORT_A,
2960                 .num_dv_ports = 1,
2961                 .edid_enable_reg = 0x74,
2962                 .edid_status_reg = 0x76,
2963                 .lcf_reg = 0xa3,
2964                 .tdms_lock_mask = 0x43,
2965                 .cable_det_mask = 0x01,
2966                 .fmt_change_digital_mask = 0x03,
2967                 .cp_csc = 0xf4,
2968                 .formats = adv7611_formats,
2969                 .nformats = ARRAY_SIZE(adv7611_formats),
2970                 .set_termination = adv7611_set_termination,
2971                 .setup_irqs = adv7611_setup_irqs,
2972                 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
2973                 .read_cable_det = adv7611_read_cable_det,
2974                 .recommended_settings = {
2975                     [1] = adv7611_recommended_settings_hdmi,
2976                 },
2977                 .num_recommended_settings = {
2978                     [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi),
2979                 },
2980                 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) |
2981                         BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) |
2982                         BIT(ADV76XX_PAGE_REP) |  BIT(ADV76XX_PAGE_EDID) |
2983                         BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP),
2984                 .linewidth_mask = 0x1fff,
2985                 .field0_height_mask = 0x1fff,
2986                 .field1_height_mask = 0x1fff,
2987                 .hfrontporch_mask = 0x1fff,
2988                 .hsync_mask = 0x1fff,
2989                 .hbackporch_mask = 0x1fff,
2990                 .field0_vfrontporch_mask = 0x3fff,
2991                 .field0_vsync_mask = 0x3fff,
2992                 .field0_vbackporch_mask = 0x3fff,
2993                 .field1_vfrontporch_mask = 0x3fff,
2994                 .field1_vsync_mask = 0x3fff,
2995                 .field1_vbackporch_mask = 0x3fff,
2996         },
2997         [ADV7612] = {
2998                 .type = ADV7612,
2999                 .has_afe = false,
3000                 .max_port = ADV76XX_PAD_HDMI_PORT_A,    /* B not supported */
3001                 .num_dv_ports = 1,                      /* normally 2 */
3002                 .edid_enable_reg = 0x74,
3003                 .edid_status_reg = 0x76,
3004                 .lcf_reg = 0xa3,
3005                 .tdms_lock_mask = 0x43,
3006                 .cable_det_mask = 0x01,
3007                 .fmt_change_digital_mask = 0x03,
3008                 .cp_csc = 0xf4,
3009                 .formats = adv7612_formats,
3010                 .nformats = ARRAY_SIZE(adv7612_formats),
3011                 .set_termination = adv7611_set_termination,
3012                 .setup_irqs = adv7612_setup_irqs,
3013                 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
3014                 .read_cable_det = adv7612_read_cable_det,
3015                 .recommended_settings = {
3016                     [1] = adv7612_recommended_settings_hdmi,
3017                 },
3018                 .num_recommended_settings = {
3019                     [1] = ARRAY_SIZE(adv7612_recommended_settings_hdmi),
3020                 },
3021                 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) |
3022                         BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) |
3023                         BIT(ADV76XX_PAGE_REP) |  BIT(ADV76XX_PAGE_EDID) |
3024                         BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP),
3025                 .linewidth_mask = 0x1fff,
3026                 .field0_height_mask = 0x1fff,
3027                 .field1_height_mask = 0x1fff,
3028                 .hfrontporch_mask = 0x1fff,
3029                 .hsync_mask = 0x1fff,
3030                 .hbackporch_mask = 0x1fff,
3031                 .field0_vfrontporch_mask = 0x3fff,
3032                 .field0_vsync_mask = 0x3fff,
3033                 .field0_vbackporch_mask = 0x3fff,
3034                 .field1_vfrontporch_mask = 0x3fff,
3035                 .field1_vsync_mask = 0x3fff,
3036                 .field1_vbackporch_mask = 0x3fff,
3037         },
3038 };
3039
3040 static const struct i2c_device_id adv76xx_i2c_id[] = {
3041         { "adv7604", (kernel_ulong_t)&adv76xx_chip_info[ADV7604] },
3042         { "adv7611", (kernel_ulong_t)&adv76xx_chip_info[ADV7611] },
3043         { "adv7612", (kernel_ulong_t)&adv76xx_chip_info[ADV7612] },
3044         { }
3045 };
3046 MODULE_DEVICE_TABLE(i2c, adv76xx_i2c_id);
3047
3048 static const struct of_device_id adv76xx_of_id[] __maybe_unused = {
3049         { .compatible = "adi,adv7611", .data = &adv76xx_chip_info[ADV7611] },
3050         { .compatible = "adi,adv7612", .data = &adv76xx_chip_info[ADV7612] },
3051         { }
3052 };
3053 MODULE_DEVICE_TABLE(of, adv76xx_of_id);
3054
3055 static int adv76xx_parse_dt(struct adv76xx_state *state)
3056 {
3057         struct v4l2_of_endpoint bus_cfg;
3058         struct device_node *endpoint;
3059         struct device_node *np;
3060         unsigned int flags;
3061         int ret;
3062         u32 v;
3063
3064         np = state->i2c_clients[ADV76XX_PAGE_IO]->dev.of_node;
3065
3066         /* Parse the endpoint. */
3067         endpoint = of_graph_get_next_endpoint(np, NULL);
3068         if (!endpoint)
3069                 return -EINVAL;
3070
3071         ret = v4l2_of_parse_endpoint(endpoint, &bus_cfg);
3072         if (ret) {
3073                 of_node_put(endpoint);
3074                 return ret;
3075         }
3076
3077         if (!of_property_read_u32(endpoint, "default-input", &v))
3078                 state->pdata.default_input = v;
3079         else
3080                 state->pdata.default_input = -1;
3081
3082         of_node_put(endpoint);
3083
3084         flags = bus_cfg.bus.parallel.flags;
3085
3086         if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
3087                 state->pdata.inv_hs_pol = 1;
3088
3089         if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
3090                 state->pdata.inv_vs_pol = 1;
3091
3092         if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
3093                 state->pdata.inv_llc_pol = 1;
3094
3095         if (bus_cfg.bus_type == V4L2_MBUS_BT656)
3096                 state->pdata.insert_av_codes = 1;
3097
3098         /* Disable the interrupt for now as no DT-based board uses it. */
3099         state->pdata.int1_config = ADV76XX_INT1_CONFIG_DISABLED;
3100
3101         /* Use the default I2C addresses. */
3102         state->pdata.i2c_addresses[ADV7604_PAGE_AVLINK] = 0x42;
3103         state->pdata.i2c_addresses[ADV76XX_PAGE_CEC] = 0x40;
3104         state->pdata.i2c_addresses[ADV76XX_PAGE_INFOFRAME] = 0x3e;
3105         state->pdata.i2c_addresses[ADV7604_PAGE_ESDP] = 0x38;
3106         state->pdata.i2c_addresses[ADV7604_PAGE_DPP] = 0x3c;
3107         state->pdata.i2c_addresses[ADV76XX_PAGE_AFE] = 0x26;
3108         state->pdata.i2c_addresses[ADV76XX_PAGE_REP] = 0x32;
3109         state->pdata.i2c_addresses[ADV76XX_PAGE_EDID] = 0x36;
3110         state->pdata.i2c_addresses[ADV76XX_PAGE_HDMI] = 0x34;
3111         state->pdata.i2c_addresses[ADV76XX_PAGE_TEST] = 0x30;
3112         state->pdata.i2c_addresses[ADV76XX_PAGE_CP] = 0x22;
3113         state->pdata.i2c_addresses[ADV7604_PAGE_VDP] = 0x24;
3114
3115         /* Hardcode the remaining platform data fields. */
3116         state->pdata.disable_pwrdnb = 0;
3117         state->pdata.disable_cable_det_rst = 0;
3118         state->pdata.blank_data = 1;
3119         state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0;
3120         state->pdata.bus_order = ADV7604_BUS_ORDER_RGB;
3121
3122         return 0;
3123 }
3124
3125 static const struct regmap_config adv76xx_regmap_cnf[] = {
3126         {
3127                 .name                   = "io",
3128                 .reg_bits               = 8,
3129                 .val_bits               = 8,
3130
3131                 .max_register           = 0xff,
3132                 .cache_type             = REGCACHE_NONE,
3133         },
3134         {
3135                 .name                   = "avlink",
3136                 .reg_bits               = 8,
3137                 .val_bits               = 8,
3138
3139                 .max_register           = 0xff,
3140                 .cache_type             = REGCACHE_NONE,
3141         },
3142         {
3143                 .name                   = "cec",
3144                 .reg_bits               = 8,
3145                 .val_bits               = 8,
3146
3147                 .max_register           = 0xff,
3148                 .cache_type             = REGCACHE_NONE,
3149         },
3150         {
3151                 .name                   = "infoframe",
3152                 .reg_bits               = 8,
3153                 .val_bits               = 8,
3154
3155                 .max_register           = 0xff,
3156                 .cache_type             = REGCACHE_NONE,
3157         },
3158         {
3159                 .name                   = "esdp",
3160                 .reg_bits               = 8,
3161                 .val_bits               = 8,
3162
3163                 .max_register           = 0xff,
3164                 .cache_type             = REGCACHE_NONE,
3165         },
3166         {
3167                 .name                   = "epp",
3168                 .reg_bits               = 8,
3169                 .val_bits               = 8,
3170
3171                 .max_register           = 0xff,
3172                 .cache_type             = REGCACHE_NONE,
3173         },
3174         {
3175                 .name                   = "afe",
3176                 .reg_bits               = 8,
3177                 .val_bits               = 8,
3178
3179                 .max_register           = 0xff,
3180                 .cache_type             = REGCACHE_NONE,
3181         },
3182         {
3183                 .name                   = "rep",
3184                 .reg_bits               = 8,
3185                 .val_bits               = 8,
3186
3187                 .max_register           = 0xff,
3188                 .cache_type             = REGCACHE_NONE,
3189         },
3190         {
3191                 .name                   = "edid",
3192                 .reg_bits               = 8,
3193                 .val_bits               = 8,
3194
3195                 .max_register           = 0xff,
3196                 .cache_type             = REGCACHE_NONE,
3197         },
3198
3199         {
3200                 .name                   = "hdmi",
3201                 .reg_bits               = 8,
3202                 .val_bits               = 8,
3203
3204                 .max_register           = 0xff,
3205                 .cache_type             = REGCACHE_NONE,
3206         },
3207         {
3208                 .name                   = "test",
3209                 .reg_bits               = 8,
3210                 .val_bits               = 8,
3211
3212                 .max_register           = 0xff,
3213                 .cache_type             = REGCACHE_NONE,
3214         },
3215         {
3216                 .name                   = "cp",
3217                 .reg_bits               = 8,
3218                 .val_bits               = 8,
3219
3220                 .max_register           = 0xff,
3221                 .cache_type             = REGCACHE_NONE,
3222         },
3223         {
3224                 .name                   = "vdp",
3225                 .reg_bits               = 8,
3226                 .val_bits               = 8,
3227
3228                 .max_register           = 0xff,
3229                 .cache_type             = REGCACHE_NONE,
3230         },
3231 };
3232
3233 static int configure_regmap(struct adv76xx_state *state, int region)
3234 {
3235         int err;
3236
3237         if (!state->i2c_clients[region])
3238                 return -ENODEV;
3239
3240         state->regmap[region] =
3241                 devm_regmap_init_i2c(state->i2c_clients[region],
3242                                      &adv76xx_regmap_cnf[region]);
3243
3244         if (IS_ERR(state->regmap[region])) {
3245                 err = PTR_ERR(state->regmap[region]);
3246                 v4l_err(state->i2c_clients[region],
3247                         "Error initializing regmap %d with error %d\n",
3248                         region, err);
3249                 return -EINVAL;
3250         }
3251
3252         return 0;
3253 }
3254
3255 static int configure_regmaps(struct adv76xx_state *state)
3256 {
3257         int i, err;
3258
3259         for (i = ADV7604_PAGE_AVLINK ; i < ADV76XX_PAGE_MAX; i++) {
3260                 err = configure_regmap(state, i);
3261                 if (err && (err != -ENODEV))
3262                         return err;
3263         }
3264         return 0;
3265 }
3266
3267 static void adv76xx_reset(struct adv76xx_state *state)
3268 {
3269         if (state->reset_gpio) {
3270                 /* ADV76XX can be reset by a low reset pulse of minimum 5 ms. */
3271                 gpiod_set_value_cansleep(state->reset_gpio, 0);
3272                 usleep_range(5000, 10000);
3273                 gpiod_set_value_cansleep(state->reset_gpio, 1);
3274                 /* It is recommended to wait 5 ms after the low pulse before */
3275                 /* an I2C write is performed to the ADV76XX. */
3276                 usleep_range(5000, 10000);
3277         }
3278 }
3279
3280 static int adv76xx_probe(struct i2c_client *client,
3281                          const struct i2c_device_id *id)
3282 {
3283         static const struct v4l2_dv_timings cea640x480 =
3284                 V4L2_DV_BT_CEA_640X480P59_94;
3285         struct adv76xx_state *state;
3286         struct v4l2_ctrl_handler *hdl;
3287         struct v4l2_ctrl *ctrl;
3288         struct v4l2_subdev *sd;
3289         unsigned int i;
3290         unsigned int val, val2;
3291         int err;
3292
3293         /* Check if the adapter supports the needed features */
3294         if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
3295                 return -EIO;
3296         v4l_dbg(1, debug, client, "detecting adv76xx client on address 0x%x\n",
3297                         client->addr << 1);
3298
3299         state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
3300         if (!state) {
3301                 v4l_err(client, "Could not allocate adv76xx_state memory!\n");
3302                 return -ENOMEM;
3303         }
3304
3305         state->i2c_clients[ADV76XX_PAGE_IO] = client;
3306
3307         /* initialize variables */
3308         state->restart_stdi_once = true;
3309         state->selected_input = ~0;
3310
3311         if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) {
3312                 const struct of_device_id *oid;
3313
3314                 oid = of_match_node(adv76xx_of_id, client->dev.of_node);
3315                 state->info = oid->data;
3316
3317                 err = adv76xx_parse_dt(state);
3318                 if (err < 0) {
3319                         v4l_err(client, "DT parsing error\n");
3320                         return err;
3321                 }
3322         } else if (client->dev.platform_data) {
3323                 struct adv76xx_platform_data *pdata = client->dev.platform_data;
3324
3325                 state->info = (const struct adv76xx_chip_info *)id->driver_data;
3326                 state->pdata = *pdata;
3327         } else {
3328                 v4l_err(client, "No platform data!\n");
3329                 return -ENODEV;
3330         }
3331
3332         /* Request GPIOs. */
3333         for (i = 0; i < state->info->num_dv_ports; ++i) {
3334                 state->hpd_gpio[i] =
3335                         devm_gpiod_get_index_optional(&client->dev, "hpd", i,
3336                                                       GPIOD_OUT_LOW);
3337                 if (IS_ERR(state->hpd_gpio[i]))
3338                         return PTR_ERR(state->hpd_gpio[i]);
3339
3340                 if (state->hpd_gpio[i])
3341                         v4l_info(client, "Handling HPD %u GPIO\n", i);
3342         }
3343         state->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
3344                                                                 GPIOD_OUT_HIGH);
3345         if (IS_ERR(state->reset_gpio))
3346                 return PTR_ERR(state->reset_gpio);
3347
3348         adv76xx_reset(state);
3349
3350         state->timings = cea640x480;
3351         state->format = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
3352
3353         sd = &state->sd;
3354         v4l2_i2c_subdev_init(sd, client, &adv76xx_ops);
3355         snprintf(sd->name, sizeof(sd->name), "%s %d-%04x",
3356                 id->name, i2c_adapter_id(client->adapter),
3357                 client->addr);
3358         sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
3359         sd->internal_ops = &adv76xx_int_ops;
3360
3361         /* Configure IO Regmap region */
3362         err = configure_regmap(state, ADV76XX_PAGE_IO);
3363
3364         if (err) {
3365                 v4l2_err(sd, "Error configuring IO regmap region\n");
3366                 return -ENODEV;
3367         }
3368
3369         /*
3370          * Verify that the chip is present. On ADV7604 the RD_INFO register only
3371          * identifies the revision, while on ADV7611 it identifies the model as
3372          * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611.
3373          */
3374         switch (state->info->type) {
3375         case ADV7604:
3376                 err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 0xfb, &val);
3377                 if (err) {
3378                         v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3379                         return -ENODEV;
3380                 }
3381                 if (val != 0x68) {
3382                         v4l2_err(sd, "not an adv7604 on address 0x%x\n",
3383                                         client->addr << 1);
3384                         return -ENODEV;
3385                 }
3386                 break;
3387         case ADV7611:
3388         case ADV7612:
3389                 err = regmap_read(state->regmap[ADV76XX_PAGE_IO],
3390                                 0xea,
3391                                 &val);
3392                 if (err) {
3393                         v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3394                         return -ENODEV;
3395                 }
3396                 val2 = val << 8;
3397                 err = regmap_read(state->regmap[ADV76XX_PAGE_IO],
3398                             0xeb,
3399                             &val);
3400                 if (err) {
3401                         v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3402                         return -ENODEV;
3403                 }
3404                 val |= val2;
3405                 if ((state->info->type == ADV7611 && val != 0x2051) ||
3406                         (state->info->type == ADV7612 && val != 0x2041)) {
3407                         v4l2_err(sd, "not an adv761x on address 0x%x\n",
3408                                         client->addr << 1);
3409                         return -ENODEV;
3410                 }
3411                 break;
3412         }
3413
3414         /* control handlers */
3415         hdl = &state->hdl;
3416         v4l2_ctrl_handler_init(hdl, adv76xx_has_afe(state) ? 9 : 8);
3417
3418         v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3419                         V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
3420         v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3421                         V4L2_CID_CONTRAST, 0, 255, 1, 128);
3422         v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3423                         V4L2_CID_SATURATION, 0, 255, 1, 128);
3424         v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3425                         V4L2_CID_HUE, 0, 128, 1, 0);
3426         ctrl = v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops,
3427                         V4L2_CID_DV_RX_IT_CONTENT_TYPE, V4L2_DV_IT_CONTENT_TYPE_NO_ITC,
3428                         0, V4L2_DV_IT_CONTENT_TYPE_NO_ITC);
3429         if (ctrl)
3430                 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
3431
3432         state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
3433                         V4L2_CID_DV_RX_POWER_PRESENT, 0,
3434                         (1 << state->info->num_dv_ports) - 1, 0, 0);
3435         state->rgb_quantization_range_ctrl =
3436                 v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops,
3437                         V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
3438                         0, V4L2_DV_RGB_RANGE_AUTO);
3439
3440         /* custom controls */
3441         if (adv76xx_has_afe(state))
3442                 state->analog_sampling_phase_ctrl =
3443                         v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
3444         state->free_run_color_manual_ctrl =
3445                 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color_manual, NULL);
3446         state->free_run_color_ctrl =
3447                 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color, NULL);
3448
3449         sd->ctrl_handler = hdl;
3450         if (hdl->error) {
3451                 err = hdl->error;
3452                 goto err_hdl;
3453         }
3454         if (adv76xx_s_detect_tx_5v_ctrl(sd)) {
3455                 err = -ENODEV;
3456                 goto err_hdl;
3457         }
3458
3459         for (i = 1; i < ADV76XX_PAGE_MAX; ++i) {
3460                 if (!(BIT(i) & state->info->page_mask))
3461                         continue;
3462
3463                 state->i2c_clients[i] =
3464                         adv76xx_dummy_client(sd, state->pdata.i2c_addresses[i],
3465                                              0xf2 + i);
3466                 if (state->i2c_clients[i] == NULL) {
3467                         err = -ENOMEM;
3468                         v4l2_err(sd, "failed to create i2c client %u\n", i);
3469                         goto err_i2c;
3470                 }
3471         }
3472
3473         INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
3474                         adv76xx_delayed_work_enable_hotplug);
3475
3476         state->source_pad = state->info->num_dv_ports
3477                           + (state->info->has_afe ? 2 : 0);
3478         for (i = 0; i < state->source_pad; ++i)
3479                 state->pads[i].flags = MEDIA_PAD_FL_SINK;
3480         state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE;
3481
3482         err = media_entity_pads_init(&sd->entity, state->source_pad + 1,
3483                                 state->pads);
3484         if (err)
3485                 goto err_work_queues;
3486
3487         /* Configure regmaps */
3488         err = configure_regmaps(state);
3489         if (err)
3490                 goto err_entity;
3491
3492         err = adv76xx_core_init(sd);
3493         if (err)
3494                 goto err_entity;
3495
3496 #if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC)
3497         state->cec_adap = cec_allocate_adapter(&adv76xx_cec_adap_ops,
3498                 state, dev_name(&client->dev),
3499                 CEC_CAP_TRANSMIT | CEC_CAP_LOG_ADDRS |
3500                 CEC_CAP_PASSTHROUGH | CEC_CAP_RC, ADV76XX_MAX_ADDRS,
3501                 &client->dev);
3502         err = PTR_ERR_OR_ZERO(state->cec_adap);
3503         if (err)
3504                 goto err_entity;
3505 #endif
3506
3507         v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
3508                         client->addr << 1, client->adapter->name);
3509
3510         err = v4l2_async_register_subdev(sd);
3511         if (err)
3512                 goto err_entity;
3513
3514         return 0;
3515
3516 err_entity:
3517         media_entity_cleanup(&sd->entity);
3518 err_work_queues:
3519         cancel_delayed_work(&state->delayed_work_enable_hotplug);
3520 err_i2c:
3521         adv76xx_unregister_clients(state);
3522 err_hdl:
3523         v4l2_ctrl_handler_free(hdl);
3524         return err;
3525 }
3526
3527 /* ----------------------------------------------------------------------- */
3528
3529 static int adv76xx_remove(struct i2c_client *client)
3530 {
3531         struct v4l2_subdev *sd = i2c_get_clientdata(client);
3532         struct adv76xx_state *state = to_state(sd);
3533
3534         /* disable interrupts */
3535         io_write(sd, 0x40, 0);
3536         io_write(sd, 0x41, 0);
3537         io_write(sd, 0x46, 0);
3538         io_write(sd, 0x6e, 0);
3539         io_write(sd, 0x73, 0);
3540
3541         cancel_delayed_work(&state->delayed_work_enable_hotplug);
3542         v4l2_async_unregister_subdev(sd);
3543         media_entity_cleanup(&sd->entity);
3544         adv76xx_unregister_clients(to_state(sd));
3545         v4l2_ctrl_handler_free(sd->ctrl_handler);
3546         return 0;
3547 }
3548
3549 /* ----------------------------------------------------------------------- */
3550
3551 static struct i2c_driver adv76xx_driver = {
3552         .driver = {
3553                 .name = "adv7604",
3554                 .of_match_table = of_match_ptr(adv76xx_of_id),
3555         },
3556         .probe = adv76xx_probe,
3557         .remove = adv76xx_remove,
3558         .id_table = adv76xx_i2c_id,
3559 };
3560
3561 module_i2c_driver(adv76xx_driver);