drivers/media/i2c/soc_camera/ov6650.c

   1 /*
   2  * V4L2 SoC Camera driver for OmniVision OV6650 Camera Sensor
   3  *
   4  * Copyright (C) 2010 Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
   5  *
   6  * Based on OmniVision OV96xx Camera Driver
   7  * Copyright (C) 2009 Marek Vasut <marek.vasut@gmail.com>
   8  *
   9  * Based on ov772x camera driver:
  10  * Copyright (C) 2008 Renesas Solutions Corp.
  11  * Kuninori Morimoto <morimoto.kuninori@renesas.com>
  12  *
  13  * Based on ov7670 and soc_camera_platform driver,
  14  * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
  15  * Copyright (C) 2008 Magnus Damm
  16  * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
  17  *
  18  * Hardware specific bits initialy based on former work by Matt Callow
  19  * drivers/media/video/omap/sensor_ov6650.c
  20  * Copyright (C) 2006 Matt Callow
  21  *
  22  * This program is free software; you can redistribute it and/or modify
  23  * it under the terms of the GNU General Public License version 2 as
  24  * published by the Free Software Foundation.
  25  */
  26
  27 #include <linux/bitops.h>
  28 #include <linux/delay.h>
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31 #include <linux/v4l2-mediabus.h>
  32 #include <linux/module.h>
  33
  34 #include <media/soc_camera.h>
  35 #include <media/v4l2-clk.h>
  36 #include <media/v4l2-ctrls.h>
  37
  38 /* Register definitions */
  39 #define REG_GAIN                0x00    /* range 00 - 3F */
  40 #define REG_BLUE                0x01
  41 #define REG_RED                 0x02
  42 #define REG_SAT                 0x03    /* [7:4] saturation [0:3] reserved */
  43 #define REG_HUE                 0x04    /* [7:6] rsrvd [5] hue en [4:0] hue */
  44
  45 #define REG_BRT                 0x06
  46
  47 #define REG_PIDH                0x0a
  48 #define REG_PIDL                0x0b
  49
  50 #define REG_AECH                0x10
  51 #define REG_CLKRC               0x11    /* Data Format and Internal Clock */
  52                                         /* [7:6] Input system clock (MHz)*/
  53                                         /*   00=8, 01=12, 10=16, 11=24 */
  54                                         /* [5:0]: Internal Clock Pre-Scaler */
  55 #define REG_COMA                0x12    /* [7] Reset */
  56 #define REG_COMB                0x13
  57 #define REG_COMC                0x14
  58 #define REG_COMD                0x15
  59 #define REG_COML                0x16
  60 #define REG_HSTRT               0x17
  61 #define REG_HSTOP               0x18
  62 #define REG_VSTRT               0x19
  63 #define REG_VSTOP               0x1a
  64 #define REG_PSHFT               0x1b
  65 #define REG_MIDH                0x1c
  66 #define REG_MIDL                0x1d
  67 #define REG_HSYNS               0x1e
  68 #define REG_HSYNE               0x1f
  69 #define REG_COME                0x20
  70 #define REG_YOFF                0x21
  71 #define REG_UOFF                0x22
  72 #define REG_VOFF                0x23
  73 #define REG_AEW                 0x24
  74 #define REG_AEB                 0x25
  75 #define REG_COMF                0x26
  76 #define REG_COMG                0x27
  77 #define REG_COMH                0x28
  78 #define REG_COMI                0x29
  79
  80 #define REG_FRARL               0x2b
  81 #define REG_COMJ                0x2c
  82 #define REG_COMK                0x2d
  83 #define REG_AVGY                0x2e
  84 #define REG_REF0                0x2f
  85 #define REG_REF1                0x30
  86 #define REG_REF2                0x31
  87 #define REG_FRAJH               0x32
  88 #define REG_FRAJL               0x33
  89 #define REG_FACT                0x34
  90 #define REG_L1AEC               0x35
  91 #define REG_AVGU                0x36
  92 #define REG_AVGV                0x37
  93
  94 #define REG_SPCB                0x60
  95 #define REG_SPCC                0x61
  96 #define REG_GAM1                0x62
  97 #define REG_GAM2                0x63
  98 #define REG_GAM3                0x64
  99 #define REG_SPCD                0x65
 100
 101 #define REG_SPCE                0x68
 102 #define REG_ADCL                0x69
 103
 104 #define REG_RMCO                0x6c
 105 #define REG_GMCO                0x6d
 106 #define REG_BMCO                0x6e
 107
 108
 109 /* Register bits, values, etc. */
 110 #define OV6650_PIDH             0x66    /* high byte of product ID number */
 111 #define OV6650_PIDL             0x50    /* low byte of product ID number */
 112 #define OV6650_MIDH             0x7F    /* high byte of mfg ID */
 113 #define OV6650_MIDL             0xA2    /* low byte of mfg ID */
 114
 115 #define DEF_GAIN                0x00
 116 #define DEF_BLUE                0x80
 117 #define DEF_RED                 0x80
 118
 119 #define SAT_SHIFT               4
 120 #define SAT_MASK                (0xf << SAT_SHIFT)
 121 #define SET_SAT(x)              (((x) << SAT_SHIFT) & SAT_MASK)
 122
 123 #define HUE_EN                  BIT(5)
 124 #define HUE_MASK                0x1f
 125 #define DEF_HUE                 0x10
 126 #define SET_HUE(x)              (HUE_EN | ((x) & HUE_MASK))
 127
 128 #define DEF_AECH                0x4D
 129
 130 #define CLKRC_6MHz              0x00
 131 #define CLKRC_12MHz             0x40
 132 #define CLKRC_16MHz             0x80
 133 #define CLKRC_24MHz             0xc0
 134 #define CLKRC_DIV_MASK          0x3f
 135 #define GET_CLKRC_DIV(x)        (((x) & CLKRC_DIV_MASK) + 1)
 136
 137 #define COMA_RESET              BIT(7)
 138 #define COMA_QCIF               BIT(5)
 139 #define COMA_RAW_RGB            BIT(4)
 140 #define COMA_RGB                BIT(3)
 141 #define COMA_BW                 BIT(2)
 142 #define COMA_WORD_SWAP          BIT(1)
 143 #define COMA_BYTE_SWAP          BIT(0)
 144 #define DEF_COMA                0x00
 145
 146 #define COMB_FLIP_V             BIT(7)
 147 #define COMB_FLIP_H             BIT(5)
 148 #define COMB_BAND_FILTER        BIT(4)
 149 #define COMB_AWB                BIT(2)
 150 #define COMB_AGC                BIT(1)
 151 #define COMB_AEC                BIT(0)
 152 #define DEF_COMB                0x5f
 153
 154 #define COML_ONE_CHANNEL        BIT(7)
 155
 156 #define DEF_HSTRT               0x24
 157 #define DEF_HSTOP               0xd4
 158 #define DEF_VSTRT               0x04
 159 #define DEF_VSTOP               0x94
 160
 161 #define COMF_HREF_LOW           BIT(4)
 162
 163 #define COMJ_PCLK_RISING        BIT(4)
 164 #define COMJ_VSYNC_HIGH         BIT(0)
 165
 166 /* supported resolutions */
 167 #define W_QCIF                  (DEF_HSTOP - DEF_HSTRT)
 168 #define W_CIF                   (W_QCIF << 1)
 169 #define H_QCIF                  (DEF_VSTOP - DEF_VSTRT)
 170 #define H_CIF                   (H_QCIF << 1)
 171
 172 #define FRAME_RATE_MAX          30
 173
 174
 175 struct ov6650_reg {
 176         u8      reg;
 177         u8      val;
 178 };
 179
 180 struct ov6650 {
 181         struct v4l2_subdev      subdev;
 182         struct v4l2_ctrl_handler hdl;
 183         struct {
 184                 /* exposure/autoexposure cluster */
 185                 struct v4l2_ctrl *autoexposure;
 186                 struct v4l2_ctrl *exposure;
 187         };
 188         struct {
 189                 /* gain/autogain cluster */
 190                 struct v4l2_ctrl *autogain;
 191                 struct v4l2_ctrl *gain;
 192         };
 193         struct {
 194                 /* blue/red/autowhitebalance cluster */
 195                 struct v4l2_ctrl *autowb;
 196                 struct v4l2_ctrl *blue;
 197                 struct v4l2_ctrl *red;
 198         };
 199         struct v4l2_clk         *clk;
 200         bool                    half_scale;     /* scale down output by 2 */
 201         struct v4l2_rect        rect;           /* sensor cropping window */
 202         unsigned long           pclk_limit;     /* from host */
 203         unsigned long           pclk_max;       /* from resolution and format */
 204         struct v4l2_fract       tpf;            /* as requested with s_parm */
 205         u32 code;
 206 };
 207
 208
 209 static u32 ov6650_codes[] = {
 210         MEDIA_BUS_FMT_YUYV8_2X8,
 211         MEDIA_BUS_FMT_UYVY8_2X8,
 212         MEDIA_BUS_FMT_YVYU8_2X8,
 213         MEDIA_BUS_FMT_VYUY8_2X8,
 214         MEDIA_BUS_FMT_SBGGR8_1X8,
 215         MEDIA_BUS_FMT_Y8_1X8,
 216 };
 217
 218 static const struct v4l2_mbus_framefmt ov6650_def_fmt = {
 219         .width          = W_CIF,
 220         .height         = H_CIF,
 221         .code           = MEDIA_BUS_FMT_SBGGR8_1X8,
 222         .colorspace     = V4L2_COLORSPACE_SRGB,
 223         .field          = V4L2_FIELD_NONE,
 224         .ycbcr_enc      = V4L2_YCBCR_ENC_DEFAULT,
 225         .quantization   = V4L2_QUANTIZATION_DEFAULT,
 226         .xfer_func      = V4L2_XFER_FUNC_DEFAULT,
 227 };
 228
 229 /* read a register */
 230 static int ov6650_reg_read(struct i2c_client *client, u8 reg, u8 *val)
 231 {
 232         int ret;
 233         u8 data = reg;
 234         struct i2c_msg msg = {
 235                 .addr   = client->addr,
 236                 .flags  = 0,
 237                 .len    = 1,
 238                 .buf    = &data,
 239         };
 240
 241         ret = i2c_transfer(client->adapter, &msg, 1);
 242         if (ret < 0)
 243                 goto err;
 244
 245         msg.flags = I2C_M_RD;
 246         ret = i2c_transfer(client->adapter, &msg, 1);
 247         if (ret < 0)
 248                 goto err;
 249
 250         *val = data;
 251         return 0;
 252
 253 err:
 254         dev_err(&client->dev, "Failed reading register 0x%02x!\n", reg);
 255         return ret;
 256 }
 257
 258 /* write a register */
 259 static int ov6650_reg_write(struct i2c_client *client, u8 reg, u8 val)
 260 {
 261         int ret;
 262         unsigned char data[2] = { reg, val };
 263         struct i2c_msg msg = {
 264                 .addr   = client->addr,
 265                 .flags  = 0,
 266                 .len    = 2,
 267                 .buf    = data,
 268         };
 269
 270         ret = i2c_transfer(client->adapter, &msg, 1);
 271         udelay(100);
 272
 273         if (ret < 0) {
 274                 dev_err(&client->dev, "Failed writing register 0x%02x!\n", reg);
 275                 return ret;
 276         }
 277         return 0;
 278 }
 279
 280
 281 /* Read a register, alter its bits, write it back */
 282 static int ov6650_reg_rmw(struct i2c_client *client, u8 reg, u8 set, u8 mask)
 283 {
 284         u8 val;
 285         int ret;
 286
 287         ret = ov6650_reg_read(client, reg, &val);
 288         if (ret) {
 289                 dev_err(&client->dev,
 290                         "[Read]-Modify-Write of register 0x%02x failed!\n",
 291                         reg);
 292                 return ret;
 293         }
 294
 295         val &= ~mask;
 296         val |= set;
 297
 298         ret = ov6650_reg_write(client, reg, val);
 299         if (ret)
 300                 dev_err(&client->dev,
 301                         "Read-Modify-[Write] of register 0x%02x failed!\n",
 302                         reg);
 303
 304         return ret;
 305 }
 306
 307 static struct ov6650 *to_ov6650(const struct i2c_client *client)
 308 {
 309         return container_of(i2c_get_clientdata(client), struct ov6650, subdev);
 310 }
 311
 312 /* Start/Stop streaming from the device */
 313 static int ov6650_s_stream(struct v4l2_subdev *sd, int enable)
 314 {
 315         return 0;
 316 }
 317
 318 /* Get status of additional camera capabilities */
 319 static int ov6550_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
 320 {
 321         struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl);
 322         struct v4l2_subdev *sd = &priv->subdev;
 323         struct i2c_client *client = v4l2_get_subdevdata(sd);
 324         uint8_t reg, reg2;
 325         int ret;
 326
 327         switch (ctrl->id) {
 328         case V4L2_CID_AUTOGAIN:
 329                 ret = ov6650_reg_read(client, REG_GAIN, &reg);
 330                 if (!ret)
 331                         priv->gain->val = reg;
 332                 return ret;
 333         case V4L2_CID_AUTO_WHITE_BALANCE:
 334                 ret = ov6650_reg_read(client, REG_BLUE, &reg);
 335                 if (!ret)
 336                         ret = ov6650_reg_read(client, REG_RED, &reg2);
 337                 if (!ret) {
 338                         priv->blue->val = reg;
 339                         priv->red->val = reg2;
 340                 }
 341                 return ret;
 342         case V4L2_CID_EXPOSURE_AUTO:
 343                 ret = ov6650_reg_read(client, REG_AECH, &reg);
 344                 if (!ret)
 345                         priv->exposure->val = reg;
 346                 return ret;
 347         }
 348         return -EINVAL;
 349 }
 350
 351 /* Set status of additional camera capabilities */
 352 static int ov6550_s_ctrl(struct v4l2_ctrl *ctrl)
 353 {
 354         struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl);
 355         struct v4l2_subdev *sd = &priv->subdev;
 356         struct i2c_client *client = v4l2_get_subdevdata(sd);
 357         int ret;
 358
 359         switch (ctrl->id) {
 360         case V4L2_CID_AUTOGAIN:
 361                 ret = ov6650_reg_rmw(client, REG_COMB,
 362                                 ctrl->val ? COMB_AGC : 0, COMB_AGC);
 363                 if (!ret && !ctrl->val)
 364                         ret = ov6650_reg_write(client, REG_GAIN, priv->gain->val);
 365                 return ret;
 366         case V4L2_CID_AUTO_WHITE_BALANCE:
 367                 ret = ov6650_reg_rmw(client, REG_COMB,
 368                                 ctrl->val ? COMB_AWB : 0, COMB_AWB);
 369                 if (!ret && !ctrl->val) {
 370                         ret = ov6650_reg_write(client, REG_BLUE, priv->blue->val);
 371                         if (!ret)
 372                                 ret = ov6650_reg_write(client, REG_RED,
 373                                                         priv->red->val);
 374                 }
 375                 return ret;
 376         case V4L2_CID_SATURATION:
 377                 return ov6650_reg_rmw(client, REG_SAT, SET_SAT(ctrl->val),
 378                                 SAT_MASK);
 379         case V4L2_CID_HUE:
 380                 return ov6650_reg_rmw(client, REG_HUE, SET_HUE(ctrl->val),
 381                                 HUE_MASK);
 382         case V4L2_CID_BRIGHTNESS:
 383                 return ov6650_reg_write(client, REG_BRT, ctrl->val);
 384         case V4L2_CID_EXPOSURE_AUTO:
 385                 ret = ov6650_reg_rmw(client, REG_COMB, ctrl->val ==
 386                                 V4L2_EXPOSURE_AUTO ? COMB_AEC : 0, COMB_AEC);
 387                 if (!ret && ctrl->val == V4L2_EXPOSURE_MANUAL)
 388                         ret = ov6650_reg_write(client, REG_AECH,
 389                                                 priv->exposure->val);
 390                 return ret;
 391         case V4L2_CID_GAMMA:
 392                 return ov6650_reg_write(client, REG_GAM1, ctrl->val);
 393         case V4L2_CID_VFLIP:
 394                 return ov6650_reg_rmw(client, REG_COMB,
 395                                 ctrl->val ? COMB_FLIP_V : 0, COMB_FLIP_V);
 396         case V4L2_CID_HFLIP:
 397                 return ov6650_reg_rmw(client, REG_COMB,
 398                                 ctrl->val ? COMB_FLIP_H : 0, COMB_FLIP_H);
 399         }
 400
 401         return -EINVAL;
 402 }
 403
 404 #ifdef CONFIG_VIDEO_ADV_DEBUG
 405 static int ov6650_get_register(struct v4l2_subdev *sd,
 406                                 struct v4l2_dbg_register *reg)
 407 {
 408         struct i2c_client *client = v4l2_get_subdevdata(sd);
 409         int ret;
 410         u8 val;
 411
 412         if (reg->reg & ~0xff)
 413                 return -EINVAL;
 414
 415         reg->size = 1;
 416
 417         ret = ov6650_reg_read(client, reg->reg, &val);
 418         if (!ret)
 419                 reg->val = (__u64)val;
 420
 421         return ret;
 422 }
 423
 424 static int ov6650_set_register(struct v4l2_subdev *sd,
 425                                 const struct v4l2_dbg_register *reg)
 426 {
 427         struct i2c_client *client = v4l2_get_subdevdata(sd);
 428
 429         if (reg->reg & ~0xff || reg->val & ~0xff)
 430                 return -EINVAL;
 431
 432         return ov6650_reg_write(client, reg->reg, reg->val);
 433 }
 434 #endif
 435
 436 static int ov6650_s_power(struct v4l2_subdev *sd, int on)
 437 {
 438         struct i2c_client *client = v4l2_get_subdevdata(sd);
 439         struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
 440         struct ov6650 *priv = to_ov6650(client);
 441
 442         return soc_camera_set_power(&client->dev, ssdd, priv->clk, on);
 443 }
 444
 445 static int ov6650_get_selection(struct v4l2_subdev *sd,
 446                 struct v4l2_subdev_pad_config *cfg,
 447                 struct v4l2_subdev_selection *sel)
 448 {
 449         struct i2c_client *client = v4l2_get_subdevdata(sd);
 450         struct ov6650 *priv = to_ov6650(client);
 451
 452         if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
 453                 return -EINVAL;
 454
 455         switch (sel->target) {
 456         case V4L2_SEL_TGT_CROP_BOUNDS:
 457         case V4L2_SEL_TGT_CROP_DEFAULT:
 458                 sel->r.left = DEF_HSTRT << 1;
 459                 sel->r.top = DEF_VSTRT << 1;
 460                 sel->r.width = W_CIF;
 461                 sel->r.height = H_CIF;
 462                 return 0;
 463         case V4L2_SEL_TGT_CROP:
 464                 sel->r = priv->rect;
 465                 return 0;
 466         default:
 467                 return -EINVAL;
 468         }
 469 }
 470
 471 static int ov6650_set_selection(struct v4l2_subdev *sd,
 472                 struct v4l2_subdev_pad_config *cfg,
 473                 struct v4l2_subdev_selection *sel)
 474 {
 475         struct i2c_client *client = v4l2_get_subdevdata(sd);
 476         struct ov6650 *priv = to_ov6650(client);
 477         struct v4l2_rect rect = sel->r;
 478         int ret;
 479
 480         if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE ||
 481             sel->target != V4L2_SEL_TGT_CROP)
 482                 return -EINVAL;
 483
 484         rect.left   = ALIGN(rect.left,   2);
 485         rect.width  = ALIGN(rect.width,  2);
 486         rect.top    = ALIGN(rect.top,    2);
 487         rect.height = ALIGN(rect.height, 2);
 488         soc_camera_limit_side(&rect.left, &rect.width,
 489                         DEF_HSTRT << 1, 2, W_CIF);
 490         soc_camera_limit_side(&rect.top, &rect.height,
 491                         DEF_VSTRT << 1, 2, H_CIF);
 492
 493         ret = ov6650_reg_write(client, REG_HSTRT, rect.left >> 1);
 494         if (!ret) {
 495                 priv->rect.left = rect.left;
 496                 ret = ov6650_reg_write(client, REG_HSTOP,
 497                                 (rect.left + rect.width) >> 1);
 498         }
 499         if (!ret) {
 500                 priv->rect.width = rect.width;
 501                 ret = ov6650_reg_write(client, REG_VSTRT, rect.top >> 1);
 502         }
 503         if (!ret) {
 504                 priv->rect.top = rect.top;
 505                 ret = ov6650_reg_write(client, REG_VSTOP,
 506                                 (rect.top + rect.height) >> 1);
 507         }
 508         if (!ret)
 509                 priv->rect.height = rect.height;
 510
 511         return ret;
 512 }
 513
 514 static int ov6650_get_fmt(struct v4l2_subdev *sd,
 515                 struct v4l2_subdev_pad_config *cfg,
 516                 struct v4l2_subdev_format *format)
 517 {
 518         struct v4l2_mbus_framefmt *mf = &format->format;
 519         struct i2c_client *client = v4l2_get_subdevdata(sd);
 520         struct ov6650 *priv = to_ov6650(client);
 521
 522         if (format->pad)
 523                 return -EINVAL;
 524
 525         /* initialize response with default media bus frame format */
 526         *mf = ov6650_def_fmt;
 527
 528         /* update media bus format code and frame size */
 529         if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
 530                 mf->width = cfg->try_fmt.width;
 531                 mf->height = cfg->try_fmt.height;
 532                 mf->code = cfg->try_fmt.code;
 533
 534         } else {
 535                 mf->width = priv->rect.width >> priv->half_scale;
 536                 mf->height = priv->rect.height >> priv->half_scale;
 537                 mf->code = priv->code;
 538         }
 539         return 0;
 540 }
 541
 542 static bool is_unscaled_ok(int width, int height, struct v4l2_rect *rect)
 543 {
 544         return width > rect->width >> 1 || height > rect->height >> 1;
 545 }
 546
 547 static u8 to_clkrc(struct v4l2_fract *timeperframe,
 548                 unsigned long pclk_limit, unsigned long pclk_max)
 549 {
 550         unsigned long pclk;
 551
 552         if (timeperframe->numerator && timeperframe->denominator)
 553                 pclk = pclk_max * timeperframe->denominator /
 554                                 (FRAME_RATE_MAX * timeperframe->numerator);
 555         else
 556                 pclk = pclk_max;
 557
 558         if (pclk_limit && pclk_limit < pclk)
 559                 pclk = pclk_limit;
 560
 561         return (pclk_max - 1) / pclk;
 562 }
 563
 564 /* set the format we will capture in */
 565 static int ov6650_s_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *mf)
 566 {
 567         struct i2c_client *client = v4l2_get_subdevdata(sd);
 568         struct soc_camera_device *icd = v4l2_get_subdev_hostdata(sd);
 569         struct soc_camera_sense *sense = icd->sense;
 570         struct ov6650 *priv = to_ov6650(client);
 571         bool half_scale = !is_unscaled_ok(mf->width, mf->height, &priv->rect);
 572         struct v4l2_subdev_selection sel = {
 573                 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
 574                 .target = V4L2_SEL_TGT_CROP,
 575                 .r.left = priv->rect.left + (priv->rect.width >> 1) -
 576                         (mf->width >> (1 - half_scale)),
 577                 .r.top = priv->rect.top + (priv->rect.height >> 1) -
 578                         (mf->height >> (1 - half_scale)),
 579                 .r.width = mf->width << half_scale,
 580                 .r.height = mf->height << half_scale,
 581         };
 582         u32 code = mf->code;
 583         unsigned long mclk, pclk;
 584         u8 coma_set = 0, coma_mask = 0, coml_set, coml_mask, clkrc;
 585         int ret;
 586
 587         /* select color matrix configuration for given color encoding */
 588         switch (code) {
 589         case MEDIA_BUS_FMT_Y8_1X8:
 590                 dev_dbg(&client->dev, "pixel format GREY8_1X8\n");
 591                 coma_mask |= COMA_RGB | COMA_WORD_SWAP | COMA_BYTE_SWAP;
 592                 coma_set |= COMA_BW;
 593                 break;
 594         case MEDIA_BUS_FMT_YUYV8_2X8:
 595                 dev_dbg(&client->dev, "pixel format YUYV8_2X8_LE\n");
 596                 coma_mask |= COMA_RGB | COMA_BW | COMA_BYTE_SWAP;
 597                 coma_set |= COMA_WORD_SWAP;
 598                 break;
 599         case MEDIA_BUS_FMT_YVYU8_2X8:
 600                 dev_dbg(&client->dev, "pixel format YVYU8_2X8_LE (untested)\n");
 601                 coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP |
 602                                 COMA_BYTE_SWAP;
 603                 break;
 604         case MEDIA_BUS_FMT_UYVY8_2X8:
 605                 dev_dbg(&client->dev, "pixel format YUYV8_2X8_BE\n");
 606                 if (half_scale) {
 607                         coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP;
 608                         coma_set |= COMA_BYTE_SWAP;
 609                 } else {
 610                         coma_mask |= COMA_RGB | COMA_BW;
 611                         coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP;
 612                 }
 613                 break;
 614         case MEDIA_BUS_FMT_VYUY8_2X8:
 615                 dev_dbg(&client->dev, "pixel format YVYU8_2X8_BE (untested)\n");
 616                 if (half_scale) {
 617                         coma_mask |= COMA_RGB | COMA_BW;
 618                         coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP;
 619                 } else {
 620                         coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP;
 621                         coma_set |= COMA_BYTE_SWAP;
 622                 }
 623                 break;
 624         case MEDIA_BUS_FMT_SBGGR8_1X8:
 625                 dev_dbg(&client->dev, "pixel format SBGGR8_1X8 (untested)\n");
 626                 coma_mask |= COMA_BW | COMA_BYTE_SWAP | COMA_WORD_SWAP;
 627                 coma_set |= COMA_RAW_RGB | COMA_RGB;
 628                 break;
 629         default:
 630                 dev_err(&client->dev, "Pixel format not handled: 0x%x\n", code);
 631                 return -EINVAL;
 632         }
 633
 634         if (code == MEDIA_BUS_FMT_Y8_1X8 ||
 635                         code == MEDIA_BUS_FMT_SBGGR8_1X8) {
 636                 coml_mask = COML_ONE_CHANNEL;
 637                 coml_set = 0;
 638                 priv->pclk_max = 4000000;
 639         } else {
 640                 coml_mask = 0;
 641                 coml_set = COML_ONE_CHANNEL;
 642                 priv->pclk_max = 8000000;
 643         }
 644
 645         if (half_scale) {
 646                 dev_dbg(&client->dev, "max resolution: QCIF\n");
 647                 coma_set |= COMA_QCIF;
 648                 priv->pclk_max /= 2;
 649         } else {
 650                 dev_dbg(&client->dev, "max resolution: CIF\n");
 651                 coma_mask |= COMA_QCIF;
 652         }
 653
 654         if (sense) {
 655                 if (sense->master_clock == 8000000) {
 656                         dev_dbg(&client->dev, "8MHz input clock\n");
 657                         clkrc = CLKRC_6MHz;
 658                 } else if (sense->master_clock == 12000000) {
 659                         dev_dbg(&client->dev, "12MHz input clock\n");
 660                         clkrc = CLKRC_12MHz;
 661                 } else if (sense->master_clock == 16000000) {
 662                         dev_dbg(&client->dev, "16MHz input clock\n");
 663                         clkrc = CLKRC_16MHz;
 664                 } else if (sense->master_clock == 24000000) {
 665                         dev_dbg(&client->dev, "24MHz input clock\n");
 666                         clkrc = CLKRC_24MHz;
 667                 } else {
 668                         dev_err(&client->dev,
 669                                 "unsupported input clock, check platform data\n");
 670                         return -EINVAL;
 671                 }
 672                 mclk = sense->master_clock;
 673                 priv->pclk_limit = sense->pixel_clock_max;
 674         } else {
 675                 clkrc = CLKRC_24MHz;
 676                 mclk = 24000000;
 677                 priv->pclk_limit = 0;
 678                 dev_dbg(&client->dev, "using default 24MHz input clock\n");
 679         }
 680
 681         clkrc |= to_clkrc(&priv->tpf, priv->pclk_limit, priv->pclk_max);
 682
 683         pclk = priv->pclk_max / GET_CLKRC_DIV(clkrc);
 684         dev_dbg(&client->dev, "pixel clock divider: %ld.%ld\n",
 685                         mclk / pclk, 10 * mclk % pclk / pclk);
 686
 687         ret = ov6650_set_selection(sd, NULL, &sel);
 688         if (!ret)
 689                 ret = ov6650_reg_rmw(client, REG_COMA, coma_set, coma_mask);
 690         if (!ret)
 691                 ret = ov6650_reg_write(client, REG_CLKRC, clkrc);
 692         if (!ret) {
 693                 priv->half_scale = half_scale;
 694
 695                 ret = ov6650_reg_rmw(client, REG_COML, coml_set, coml_mask);
 696         }
 697         if (!ret)
 698                 priv->code = code;
 699
 700         return ret;
 701 }
 702
 703 static int ov6650_set_fmt(struct v4l2_subdev *sd,
 704                 struct v4l2_subdev_pad_config *cfg,
 705                 struct v4l2_subdev_format *format)
 706 {
 707         struct v4l2_mbus_framefmt *mf = &format->format;
 708         struct i2c_client *client = v4l2_get_subdevdata(sd);
 709         struct ov6650 *priv = to_ov6650(client);
 710
 711         if (format->pad)
 712                 return -EINVAL;
 713
 714         if (is_unscaled_ok(mf->width, mf->height, &priv->rect))
 715                 v4l_bound_align_image(&mf->width, 2, W_CIF, 1,
 716                                 &mf->height, 2, H_CIF, 1, 0);
 717
 718         switch (mf->code) {
 719         case MEDIA_BUS_FMT_Y10_1X10:
 720                 mf->code = MEDIA_BUS_FMT_Y8_1X8;
 721         case MEDIA_BUS_FMT_Y8_1X8:
 722         case MEDIA_BUS_FMT_YVYU8_2X8:
 723         case MEDIA_BUS_FMT_YUYV8_2X8:
 724         case MEDIA_BUS_FMT_VYUY8_2X8:
 725         case MEDIA_BUS_FMT_UYVY8_2X8:
 726                 break;
 727         default:
 728                 mf->code = MEDIA_BUS_FMT_SBGGR8_1X8;
 729         case MEDIA_BUS_FMT_SBGGR8_1X8:
 730                 break;
 731         }
 732
 733         if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
 734                 /* store media bus format code and frame size in pad config */
 735                 cfg->try_fmt.width = mf->width;
 736                 cfg->try_fmt.height = mf->height;
 737                 cfg->try_fmt.code = mf->code;
 738
 739                 /* return default mbus frame format updated with pad config */
 740                 *mf = ov6650_def_fmt;
 741                 mf->width = cfg->try_fmt.width;
 742                 mf->height = cfg->try_fmt.height;
 743                 mf->code = cfg->try_fmt.code;
 744
 745         } else {
 746                 /* apply new media bus format code and frame size */
 747                 int ret = ov6650_s_fmt(sd, mf);
 748
 749                 if (ret)
 750                         return ret;
 751
 752                 /* return default format updated with active size and code */
 753                 *mf = ov6650_def_fmt;
 754                 mf->width = priv->rect.width >> priv->half_scale;
 755                 mf->height = priv->rect.height >> priv->half_scale;
 756                 mf->code = priv->code;
 757         }
 758         return 0;
 759 }
 760
 761 static int ov6650_enum_mbus_code(struct v4l2_subdev *sd,
 762                 struct v4l2_subdev_pad_config *cfg,
 763                 struct v4l2_subdev_mbus_code_enum *code)
 764 {
 765         if (code->pad || code->index >= ARRAY_SIZE(ov6650_codes))
 766                 return -EINVAL;
 767
 768         code->code = ov6650_codes[code->index];
 769         return 0;
 770 }
 771
 772 static int ov6650_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
 773 {
 774         struct i2c_client *client = v4l2_get_subdevdata(sd);
 775         struct ov6650 *priv = to_ov6650(client);
 776         struct v4l2_captureparm *cp = &parms->parm.capture;
 777
 778         if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
 779                 return -EINVAL;
 780
 781         memset(cp, 0, sizeof(*cp));
 782         cp->capability = V4L2_CAP_TIMEPERFRAME;
 783         cp->timeperframe.numerator = GET_CLKRC_DIV(to_clkrc(&priv->tpf,
 784                         priv->pclk_limit, priv->pclk_max));
 785         cp->timeperframe.denominator = FRAME_RATE_MAX;
 786
 787         dev_dbg(&client->dev, "Frame interval: %u/%u s\n",
 788                 cp->timeperframe.numerator, cp->timeperframe.denominator);
 789
 790         return 0;
 791 }
 792
 793 static int ov6650_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
 794 {
 795         struct i2c_client *client = v4l2_get_subdevdata(sd);
 796         struct ov6650 *priv = to_ov6650(client);
 797         struct v4l2_captureparm *cp = &parms->parm.capture;
 798         struct v4l2_fract *tpf = &cp->timeperframe;
 799         int div, ret;
 800         u8 clkrc;
 801
 802         if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
 803                 return -EINVAL;
 804
 805         if (cp->extendedmode != 0)
 806                 return -EINVAL;
 807
 808         if (tpf->numerator == 0 || tpf->denominator == 0)
 809                 div = 1;  /* Reset to full rate */
 810         else
 811                 div = (tpf->numerator * FRAME_RATE_MAX) / tpf->denominator;
 812
 813         if (div == 0)
 814                 div = 1;
 815         else if (div > GET_CLKRC_DIV(CLKRC_DIV_MASK))
 816                 div = GET_CLKRC_DIV(CLKRC_DIV_MASK);
 817
 818         /*
 819          * Keep result to be used as tpf limit
 820          * for subseqent clock divider calculations
 821          */
 822         priv->tpf.numerator = div;
 823         priv->tpf.denominator = FRAME_RATE_MAX;
 824
 825         clkrc = to_clkrc(&priv->tpf, priv->pclk_limit, priv->pclk_max);
 826
 827         ret = ov6650_reg_rmw(client, REG_CLKRC, clkrc, CLKRC_DIV_MASK);
 828         if (!ret) {
 829                 tpf->numerator = GET_CLKRC_DIV(clkrc);
 830                 tpf->denominator = FRAME_RATE_MAX;
 831         }
 832
 833         return ret;
 834 }
 835
 836 /* Soft reset the camera. This has nothing to do with the RESET pin! */
 837 static int ov6650_reset(struct i2c_client *client)
 838 {
 839         int ret;
 840
 841         dev_dbg(&client->dev, "reset\n");
 842
 843         ret = ov6650_reg_rmw(client, REG_COMA, COMA_RESET, 0);
 844         if (ret)
 845                 dev_err(&client->dev,
 846                         "An error occurred while entering soft reset!\n");
 847
 848         return ret;
 849 }
 850
 851 /* program default register values */
 852 static int ov6650_prog_dflt(struct i2c_client *client)
 853 {
 854         int ret;
 855
 856         dev_dbg(&client->dev, "initializing\n");
 857
 858         ret = ov6650_reg_write(client, REG_COMA, 0);    /* ~COMA_RESET */
 859         if (!ret)
 860                 ret = ov6650_reg_rmw(client, REG_COMB, 0, COMB_BAND_FILTER);
 861
 862         return ret;
 863 }
 864
 865 static int ov6650_video_probe(struct i2c_client *client)
 866 {
 867         struct ov6650 *priv = to_ov6650(client);
 868         u8              pidh, pidl, midh, midl;
 869         int             ret;
 870
 871         priv->clk = v4l2_clk_get(&client->dev, NULL);
 872         if (IS_ERR(priv->clk)) {
 873                 ret = PTR_ERR(priv->clk);
 874                 dev_err(&client->dev, "v4l2_clk request err: %d\n", ret);
 875                 return ret;
 876         }
 877
 878         ret = ov6650_s_power(&priv->subdev, 1);
 879         if (ret < 0)
 880                 goto eclkput;
 881
 882         msleep(20);
 883
 884         /*
 885          * check and show product ID and manufacturer ID
 886          */
 887         ret = ov6650_reg_read(client, REG_PIDH, &pidh);
 888         if (!ret)
 889                 ret = ov6650_reg_read(client, REG_PIDL, &pidl);
 890         if (!ret)
 891                 ret = ov6650_reg_read(client, REG_MIDH, &midh);
 892         if (!ret)
 893                 ret = ov6650_reg_read(client, REG_MIDL, &midl);
 894
 895         if (ret)
 896                 goto done;
 897
 898         if ((pidh != OV6650_PIDH) || (pidl != OV6650_PIDL)) {
 899                 dev_err(&client->dev, "Product ID error 0x%02x:0x%02x\n",
 900                                 pidh, pidl);
 901                 ret = -ENODEV;
 902                 goto done;
 903         }
 904
 905         dev_info(&client->dev,
 906                 "ov6650 Product ID 0x%02x:0x%02x Manufacturer ID 0x%02x:0x%02x\n",
 907                 pidh, pidl, midh, midl);
 908
 909         ret = ov6650_reset(client);
 910         if (!ret)
 911                 ret = ov6650_prog_dflt(client);
 912         if (!ret)
 913                 ret = v4l2_ctrl_handler_setup(&priv->hdl);
 914
 915 done:
 916         ov6650_s_power(&priv->subdev, 0);
 917         if (!ret)
 918                 return 0;
 919 eclkput:
 920         v4l2_clk_put(priv->clk);
 921
 922         return ret;
 923 }
 924
 925 static const struct v4l2_ctrl_ops ov6550_ctrl_ops = {
 926         .g_volatile_ctrl = ov6550_g_volatile_ctrl,
 927         .s_ctrl = ov6550_s_ctrl,
 928 };
 929
 930 static struct v4l2_subdev_core_ops ov6650_core_ops = {
 931 #ifdef CONFIG_VIDEO_ADV_DEBUG
 932         .g_register             = ov6650_get_register,
 933         .s_register             = ov6650_set_register,
 934 #endif
 935         .s_power                = ov6650_s_power,
 936 };
 937
 938 /* Request bus settings on camera side */
 939 static int ov6650_g_mbus_config(struct v4l2_subdev *sd,
 940                                 struct v4l2_mbus_config *cfg)
 941 {
 942         struct i2c_client *client = v4l2_get_subdevdata(sd);
 943         struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
 944
 945         cfg->flags = V4L2_MBUS_MASTER |
 946                 V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_PCLK_SAMPLE_FALLING |
 947                 V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_LOW |
 948                 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_LOW |
 949                 V4L2_MBUS_DATA_ACTIVE_HIGH;
 950         cfg->type = V4L2_MBUS_PARALLEL;
 951         cfg->flags = soc_camera_apply_board_flags(ssdd, cfg);
 952
 953         return 0;
 954 }
 955
 956 /* Alter bus settings on camera side */
 957 static int ov6650_s_mbus_config(struct v4l2_subdev *sd,
 958                                 const struct v4l2_mbus_config *cfg)
 959 {
 960         struct i2c_client *client = v4l2_get_subdevdata(sd);
 961         struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
 962         unsigned long flags = soc_camera_apply_board_flags(ssdd, cfg);
 963         int ret;
 964
 965         if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
 966                 ret = ov6650_reg_rmw(client, REG_COMJ, COMJ_PCLK_RISING, 0);
 967         else
 968                 ret = ov6650_reg_rmw(client, REG_COMJ, 0, COMJ_PCLK_RISING);
 969         if (ret)
 970                 return ret;
 971
 972         if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
 973                 ret = ov6650_reg_rmw(client, REG_COMF, COMF_HREF_LOW, 0);
 974         else
 975                 ret = ov6650_reg_rmw(client, REG_COMF, 0, COMF_HREF_LOW);
 976         if (ret)
 977                 return ret;
 978
 979         if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
 980                 ret = ov6650_reg_rmw(client, REG_COMJ, COMJ_VSYNC_HIGH, 0);
 981         else
 982                 ret = ov6650_reg_rmw(client, REG_COMJ, 0, COMJ_VSYNC_HIGH);
 983
 984         return ret;
 985 }
 986
 987 static struct v4l2_subdev_video_ops ov6650_video_ops = {
 988         .s_stream       = ov6650_s_stream,
 989         .g_parm         = ov6650_g_parm,
 990         .s_parm         = ov6650_s_parm,
 991         .g_mbus_config  = ov6650_g_mbus_config,
 992         .s_mbus_config  = ov6650_s_mbus_config,
 993 };
 994
 995 static const struct v4l2_subdev_pad_ops ov6650_pad_ops = {
 996         .enum_mbus_code = ov6650_enum_mbus_code,
 997         .get_selection  = ov6650_get_selection,
 998         .set_selection  = ov6650_set_selection,
 999         .get_fmt        = ov6650_get_fmt,
1000         .set_fmt        = ov6650_set_fmt,
1001 };
1002
1003 static struct v4l2_subdev_ops ov6650_subdev_ops = {
1004         .core   = &ov6650_core_ops,
1005         .video  = &ov6650_video_ops,
1006         .pad    = &ov6650_pad_ops,
1007 };
1008
1009 /*
1010  * i2c_driver function
1011  */
1012 static int ov6650_probe(struct i2c_client *client,
1013                         const struct i2c_device_id *did)
1014 {
1015         struct ov6650 *priv;
1016         struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
1017         int ret;
1018
1019         if (!ssdd) {
1020                 dev_err(&client->dev, "Missing platform_data for driver\n");
1021                 return -EINVAL;
1022         }
1023
1024         priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
1025         if (!priv) {
1026                 dev_err(&client->dev,
1027                         "Failed to allocate memory for private data!\n");
1028                 return -ENOMEM;
1029         }
1030
1031         v4l2_i2c_subdev_init(&priv->subdev, client, &ov6650_subdev_ops);
1032         v4l2_ctrl_handler_init(&priv->hdl, 13);
1033         v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1034                         V4L2_CID_VFLIP, 0, 1, 1, 0);
1035         v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1036                         V4L2_CID_HFLIP, 0, 1, 1, 0);
1037         priv->autogain = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1038                         V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
1039         priv->gain = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1040                         V4L2_CID_GAIN, 0, 0x3f, 1, DEF_GAIN);
1041         priv->autowb = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1042                         V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
1043         priv->blue = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1044                         V4L2_CID_BLUE_BALANCE, 0, 0xff, 1, DEF_BLUE);
1045         priv->red = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1046                         V4L2_CID_RED_BALANCE, 0, 0xff, 1, DEF_RED);
1047         v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1048                         V4L2_CID_SATURATION, 0, 0xf, 1, 0x8);
1049         v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1050                         V4L2_CID_HUE, 0, HUE_MASK, 1, DEF_HUE);
1051         v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1052                         V4L2_CID_BRIGHTNESS, 0, 0xff, 1, 0x80);
1053         priv->autoexposure = v4l2_ctrl_new_std_menu(&priv->hdl,
1054                         &ov6550_ctrl_ops, V4L2_CID_EXPOSURE_AUTO,
1055                         V4L2_EXPOSURE_MANUAL, 0, V4L2_EXPOSURE_AUTO);
1056         priv->exposure = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1057                         V4L2_CID_EXPOSURE, 0, 0xff, 1, DEF_AECH);
1058         v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1059                         V4L2_CID_GAMMA, 0, 0xff, 1, 0x12);
1060
1061         priv->subdev.ctrl_handler = &priv->hdl;
1062         if (priv->hdl.error)
1063                 return priv->hdl.error;
1064
1065         v4l2_ctrl_auto_cluster(2, &priv->autogain, 0, true);
1066         v4l2_ctrl_auto_cluster(3, &priv->autowb, 0, true);
1067         v4l2_ctrl_auto_cluster(2, &priv->autoexposure,
1068                                 V4L2_EXPOSURE_MANUAL, true);
1069
1070         priv->rect.left   = DEF_HSTRT << 1;
1071         priv->rect.top    = DEF_VSTRT << 1;
1072         priv->rect.width  = W_CIF;
1073         priv->rect.height = H_CIF;
1074         priv->half_scale  = false;
1075         priv->code        = MEDIA_BUS_FMT_YUYV8_2X8;
1076
1077         ret = ov6650_video_probe(client);
1078         if (ret)
1079                 v4l2_ctrl_handler_free(&priv->hdl);
1080
1081         return ret;
1082 }
1083
1084 static int ov6650_remove(struct i2c_client *client)
1085 {
1086         struct ov6650 *priv = to_ov6650(client);
1087
1088         v4l2_clk_put(priv->clk);
1089         v4l2_device_unregister_subdev(&priv->subdev);
1090         v4l2_ctrl_handler_free(&priv->hdl);
1091         return 0;
1092 }
1093
1094 static const struct i2c_device_id ov6650_id[] = {
1095         { "ov6650", 0 },
1096         { }
1097 };
1098 MODULE_DEVICE_TABLE(i2c, ov6650_id);
1099
1100 static struct i2c_driver ov6650_i2c_driver = {
1101         .driver = {
1102                 .name = "ov6650",
1103         },
1104         .probe    = ov6650_probe,
1105         .remove   = ov6650_remove,
1106         .id_table = ov6650_id,
1107 };
1108
1109 module_i2c_driver(ov6650_i2c_driver);
1110
1111 MODULE_DESCRIPTION("SoC Camera driver for OmniVision OV6650");
1112 MODULE_AUTHOR("Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>");
1113 MODULE_LICENSE("GPL v2");