drivers/media/i2c/tc358743.c

   1 /*
   2  * tc358743 - Toshiba HDMI to CSI-2 bridge
   3  *
   4  * Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights
   5  * reserved.
   6  *
   7  * This program is free software; you may redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  12  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  13  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  14  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  15  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  16  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  17  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  18  * SOFTWARE.
  19  *
  20  */
  21
  22 /*
  23  * References (c = chapter, p = page):
  24  * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60
  25  * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls
  26  */
  27
  28 #include <linux/kernel.h>
  29 #include <linux/module.h>
  30 #include <linux/slab.h>
  31 #include <linux/i2c.h>
  32 #include <linux/clk.h>
  33 #include <linux/delay.h>
  34 #include <linux/gpio/consumer.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/videodev2.h>
  37 #include <linux/workqueue.h>
  38 #include <linux/v4l2-dv-timings.h>
  39 #include <linux/hdmi.h>
  40 #include <media/v4l2-dv-timings.h>
  41 #include <media/v4l2-device.h>
  42 #include <media/v4l2-ctrls.h>
  43 #include <media/v4l2-event.h>
  44 #include <media/v4l2-of.h>
  45 #include <media/i2c/tc358743.h>
  46
  47 #include "tc358743_regs.h"
  48
  49 static int debug;
  50 module_param(debug, int, 0644);
  51 MODULE_PARM_DESC(debug, "debug level (0-3)");
  52
  53 MODULE_DESCRIPTION("Toshiba TC358743 HDMI to CSI-2 bridge driver");
  54 MODULE_AUTHOR("Ramakrishnan Muthukrishnan <ram@rkrishnan.org>");
  55 MODULE_AUTHOR("Mikhail Khelik <mkhelik@cisco.com>");
  56 MODULE_AUTHOR("Mats Randgaard <matrandg@cisco.com>");
  57 MODULE_LICENSE("GPL");
  58
  59 #define EDID_NUM_BLOCKS_MAX 8
  60 #define EDID_BLOCK_SIZE 128
  61
  62 #define I2C_MAX_XFER_SIZE  (EDID_BLOCK_SIZE + 2)
  63
  64 static const struct v4l2_dv_timings_cap tc358743_timings_cap = {
  65         .type = V4L2_DV_BT_656_1120,
  66         /* keep this initialization for compatibility with GCC < 4.4.6 */
  67         .reserved = { 0 },
  68         /* Pixel clock from REF_01 p. 20. Min/max height/width are unknown */
  69         V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 13000000, 165000000,
  70                         V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
  71                         V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
  72                         V4L2_DV_BT_CAP_PROGRESSIVE |
  73                         V4L2_DV_BT_CAP_REDUCED_BLANKING |
  74                         V4L2_DV_BT_CAP_CUSTOM)
  75 };
  76
  77 struct tc358743_state {
  78         struct tc358743_platform_data pdata;
  79         struct v4l2_of_bus_mipi_csi2 bus;
  80         struct v4l2_subdev sd;
  81         struct media_pad pad;
  82         struct v4l2_ctrl_handler hdl;
  83         struct i2c_client *i2c_client;
  84         /* CONFCTL is modified in ops and tc358743_hdmi_sys_int_handler */
  85         struct mutex confctl_mutex;
  86
  87         /* controls */
  88         struct v4l2_ctrl *detect_tx_5v_ctrl;
  89         struct v4l2_ctrl *audio_sampling_rate_ctrl;
  90         struct v4l2_ctrl *audio_present_ctrl;
  91
  92         struct delayed_work delayed_work_enable_hotplug;
  93
  94         /* edid  */
  95         u8 edid_blocks_written;
  96
  97         struct v4l2_dv_timings timings;
  98         u32 mbus_fmt_code;
  99
 100         struct gpio_desc *reset_gpio;
 101 };
 102
 103 static void tc358743_enable_interrupts(struct v4l2_subdev *sd,
 104                 bool cable_connected);
 105 static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd);
 106
 107 static inline struct tc358743_state *to_state(struct v4l2_subdev *sd)
 108 {
 109         return container_of(sd, struct tc358743_state, sd);
 110 }
 111
 112 /* --------------- I2C --------------- */
 113
 114 static void i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
 115 {
 116         struct tc358743_state *state = to_state(sd);
 117         struct i2c_client *client = state->i2c_client;
 118         int err;
 119         u8 buf[2] = { reg >> 8, reg & 0xff };
 120         struct i2c_msg msgs[] = {
 121                 {
 122                         .addr = client->addr,
 123                         .flags = 0,
 124                         .len = 2,
 125                         .buf = buf,
 126                 },
 127                 {
 128                         .addr = client->addr,
 129                         .flags = I2C_M_RD,
 130                         .len = n,
 131                         .buf = values,
 132                 },
 133         };
 134
 135         err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
 136         if (err != ARRAY_SIZE(msgs)) {
 137                 v4l2_err(sd, "%s: reading register 0x%x from 0x%x failed\n",
 138                                 __func__, reg, client->addr);
 139         }
 140 }
 141
 142 static void i2c_wr(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
 143 {
 144         struct tc358743_state *state = to_state(sd);
 145         struct i2c_client *client = state->i2c_client;
 146         int err, i;
 147         struct i2c_msg msg;
 148         u8 data[I2C_MAX_XFER_SIZE];
 149
 150         if ((2 + n) > I2C_MAX_XFER_SIZE) {
 151                 n = I2C_MAX_XFER_SIZE - 2;
 152                 v4l2_warn(sd, "i2c wr reg=%04x: len=%d is too big!\n",
 153                           reg, 2 + n);
 154         }
 155
 156         msg.addr = client->addr;
 157         msg.buf = data;
 158         msg.len = 2 + n;
 159         msg.flags = 0;
 160
 161         data[0] = reg >> 8;
 162         data[1] = reg & 0xff;
 163
 164         for (i = 0; i < n; i++)
 165                 data[2 + i] = values[i];
 166
 167         err = i2c_transfer(client->adapter, &msg, 1);
 168         if (err != 1) {
 169                 v4l2_err(sd, "%s: writing register 0x%x from 0x%x failed\n",
 170                                 __func__, reg, client->addr);
 171                 return;
 172         }
 173
 174         if (debug < 3)
 175                 return;
 176
 177         switch (n) {
 178         case 1:
 179                 v4l2_info(sd, "I2C write 0x%04x = 0x%02x",
 180                                 reg, data[2]);
 181                 break;
 182         case 2:
 183                 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x",
 184                                 reg, data[3], data[2]);
 185                 break;
 186         case 4:
 187                 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x%02x%02x",
 188                                 reg, data[5], data[4], data[3], data[2]);
 189                 break;
 190         default:
 191                 v4l2_info(sd, "I2C write %d bytes from address 0x%04x\n",
 192                                 n, reg);
 193         }
 194 }
 195
 196 static noinline u32 i2c_rdreg(struct v4l2_subdev *sd, u16 reg, u32 n)
 197 {
 198         __le32 val = 0;
 199
 200         i2c_rd(sd, reg, (u8 __force *)&val, n);
 201
 202         return le32_to_cpu(val);
 203 }
 204
 205 static noinline void i2c_wrreg(struct v4l2_subdev *sd, u16 reg, u32 val, u32 n)
 206 {
 207         __le32 raw = cpu_to_le32(val);
 208
 209         i2c_wr(sd, reg, (u8 __force *)&raw, n);
 210 }
 211
 212 static u8 i2c_rd8(struct v4l2_subdev *sd, u16 reg)
 213 {
 214         return i2c_rdreg(sd, reg, 1);
 215 }
 216
 217 static void i2c_wr8(struct v4l2_subdev *sd, u16 reg, u8 val)
 218 {
 219         i2c_wrreg(sd, reg, val, 1);
 220 }
 221
 222 static void i2c_wr8_and_or(struct v4l2_subdev *sd, u16 reg,
 223                 u8 mask, u8 val)
 224 {
 225         i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 1) & mask) | val, 1);
 226 }
 227
 228 static u16 i2c_rd16(struct v4l2_subdev *sd, u16 reg)
 229 {
 230         return i2c_rdreg(sd, reg, 2);
 231 }
 232
 233 static void i2c_wr16(struct v4l2_subdev *sd, u16 reg, u16 val)
 234 {
 235         i2c_wrreg(sd, reg, val, 2);
 236 }
 237
 238 static void i2c_wr16_and_or(struct v4l2_subdev *sd, u16 reg, u16 mask, u16 val)
 239 {
 240         i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 1) & mask) | val, 1);
 241 }
 242
 243 static u32 i2c_rd32(struct v4l2_subdev *sd, u16 reg)
 244 {
 245         return i2c_rdreg(sd, reg, 4);
 246 }
 247
 248 static void i2c_wr32(struct v4l2_subdev *sd, u16 reg, u32 val)
 249 {
 250         i2c_wrreg(sd, reg, val, 4);
 251 }
 252
 253 /* --------------- STATUS --------------- */
 254
 255 static inline bool is_hdmi(struct v4l2_subdev *sd)
 256 {
 257         return i2c_rd8(sd, SYS_STATUS) & MASK_S_HDMI;
 258 }
 259
 260 static inline bool tx_5v_power_present(struct v4l2_subdev *sd)
 261 {
 262         return i2c_rd8(sd, SYS_STATUS) & MASK_S_DDC5V;
 263 }
 264
 265 static inline bool no_signal(struct v4l2_subdev *sd)
 266 {
 267         return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_TMDS);
 268 }
 269
 270 static inline bool no_sync(struct v4l2_subdev *sd)
 271 {
 272         return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_SYNC);
 273 }
 274
 275 static inline bool audio_present(struct v4l2_subdev *sd)
 276 {
 277         return i2c_rd8(sd, AU_STATUS0) & MASK_S_A_SAMPLE;
 278 }
 279
 280 static int get_audio_sampling_rate(struct v4l2_subdev *sd)
 281 {
 282         static const int code_to_rate[] = {
 283                 44100, 0, 48000, 32000, 22050, 384000, 24000, 352800,
 284                 88200, 768000, 96000, 705600, 176400, 0, 192000, 0
 285         };
 286
 287         /* Register FS_SET is not cleared when the cable is disconnected */
 288         if (no_signal(sd))
 289                 return 0;
 290
 291         return code_to_rate[i2c_rd8(sd, FS_SET) & MASK_FS];
 292 }
 293
 294 static unsigned tc358743_num_csi_lanes_in_use(struct v4l2_subdev *sd)
 295 {
 296         return ((i2c_rd32(sd, CSI_CONTROL) & MASK_NOL) >> 1) + 1;
 297 }
 298
 299 /* --------------- TIMINGS --------------- */
 300
 301 static inline unsigned fps(const struct v4l2_bt_timings *t)
 302 {
 303         if (!V4L2_DV_BT_FRAME_HEIGHT(t) || !V4L2_DV_BT_FRAME_WIDTH(t))
 304                 return 0;
 305
 306         return DIV_ROUND_CLOSEST((unsigned)t->pixelclock,
 307                         V4L2_DV_BT_FRAME_HEIGHT(t) * V4L2_DV_BT_FRAME_WIDTH(t));
 308 }
 309
 310 static int tc358743_get_detected_timings(struct v4l2_subdev *sd,
 311                                      struct v4l2_dv_timings *timings)
 312 {
 313         struct v4l2_bt_timings *bt = &timings->bt;
 314         unsigned width, height, frame_width, frame_height, frame_interval, fps;
 315
 316         memset(timings, 0, sizeof(struct v4l2_dv_timings));
 317
 318         if (no_signal(sd)) {
 319                 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
 320                 return -ENOLINK;
 321         }
 322         if (no_sync(sd)) {
 323                 v4l2_dbg(1, debug, sd, "%s: no sync on signal\n", __func__);
 324                 return -ENOLCK;
 325         }
 326
 327         timings->type = V4L2_DV_BT_656_1120;
 328         bt->interlaced = i2c_rd8(sd, VI_STATUS1) & MASK_S_V_INTERLACE ?
 329                 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
 330
 331         width = ((i2c_rd8(sd, DE_WIDTH_H_HI) & 0x1f) << 8) +
 332                 i2c_rd8(sd, DE_WIDTH_H_LO);
 333         height = ((i2c_rd8(sd, DE_WIDTH_V_HI) & 0x1f) << 8) +
 334                 i2c_rd8(sd, DE_WIDTH_V_LO);
 335         frame_width = ((i2c_rd8(sd, H_SIZE_HI) & 0x1f) << 8) +
 336                 i2c_rd8(sd, H_SIZE_LO);
 337         frame_height = (((i2c_rd8(sd, V_SIZE_HI) & 0x3f) << 8) +
 338                 i2c_rd8(sd, V_SIZE_LO)) / 2;
 339         /* frame interval in milliseconds * 10
 340          * Require SYS_FREQ0 and SYS_FREQ1 are precisely set */
 341         frame_interval = ((i2c_rd8(sd, FV_CNT_HI) & 0x3) << 8) +
 342                 i2c_rd8(sd, FV_CNT_LO);
 343         fps = (frame_interval > 0) ?
 344                 DIV_ROUND_CLOSEST(10000, frame_interval) : 0;
 345
 346         bt->width = width;
 347         bt->height = height;
 348         bt->vsync = frame_height - height;
 349         bt->hsync = frame_width - width;
 350         bt->pixelclock = frame_width * frame_height * fps;
 351         if (bt->interlaced == V4L2_DV_INTERLACED) {
 352                 bt->height *= 2;
 353                 bt->il_vsync = bt->vsync + 1;
 354                 bt->pixelclock /= 2;
 355         }
 356
 357         return 0;
 358 }
 359
 360 /* --------------- HOTPLUG / HDCP / EDID --------------- */
 361
 362 static void tc358743_delayed_work_enable_hotplug(struct work_struct *work)
 363 {
 364         struct delayed_work *dwork = to_delayed_work(work);
 365         struct tc358743_state *state = container_of(dwork,
 366                         struct tc358743_state, delayed_work_enable_hotplug);
 367         struct v4l2_subdev *sd = &state->sd;
 368
 369         v4l2_dbg(2, debug, sd, "%s:\n", __func__);
 370
 371         i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, MASK_HPD_OUT0);
 372 }
 373
 374 static void tc358743_set_hdmi_hdcp(struct v4l2_subdev *sd, bool enable)
 375 {
 376         v4l2_dbg(2, debug, sd, "%s: %s\n", __func__, enable ?
 377                                 "enable" : "disable");
 378
 379         i2c_wr8_and_or(sd, HDCP_REG1,
 380                         ~(MASK_AUTH_UNAUTH_SEL | MASK_AUTH_UNAUTH),
 381                         MASK_AUTH_UNAUTH_SEL_16_FRAMES | MASK_AUTH_UNAUTH_AUTO);
 382
 383         i2c_wr8_and_or(sd, HDCP_REG2, ~MASK_AUTO_P3_RESET,
 384                         SET_AUTO_P3_RESET_FRAMES(0x0f));
 385
 386         /* HDCP is disabled by configuring the receiver as HDCP repeater. The
 387          * repeater mode require software support to work, so HDCP
 388          * authentication will fail.
 389          */
 390         i2c_wr8_and_or(sd, HDCP_REG3, ~KEY_RD_CMD, enable ? KEY_RD_CMD : 0);
 391         i2c_wr8_and_or(sd, HDCP_MODE, ~(MASK_AUTO_CLR | MASK_MODE_RST_TN),
 392                         enable ?  (MASK_AUTO_CLR | MASK_MODE_RST_TN) : 0);
 393
 394         /* Apple MacBook Pro gen.8 has a bug that makes it freeze every fifth
 395          * second when HDCP is disabled, but the MAX_EXCED bit is handled
 396          * correctly and HDCP is disabled on the HDMI output.
 397          */
 398         i2c_wr8_and_or(sd, BSTATUS1, ~MASK_MAX_EXCED,
 399                         enable ? 0 : MASK_MAX_EXCED);
 400         i2c_wr8_and_or(sd, BCAPS, ~(MASK_REPEATER | MASK_READY),
 401                         enable ? 0 : MASK_REPEATER | MASK_READY);
 402 }
 403
 404 static void tc358743_disable_edid(struct v4l2_subdev *sd)
 405 {
 406         struct tc358743_state *state = to_state(sd);
 407
 408         v4l2_dbg(2, debug, sd, "%s:\n", __func__);
 409
 410         cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
 411
 412         /* DDC access to EDID is also disabled when hotplug is disabled. See
 413          * register DDC_CTL */
 414         i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, 0x0);
 415 }
 416
 417 static void tc358743_enable_edid(struct v4l2_subdev *sd)
 418 {
 419         struct tc358743_state *state = to_state(sd);
 420
 421         if (state->edid_blocks_written == 0) {
 422                 v4l2_dbg(2, debug, sd, "%s: no EDID -> no hotplug\n", __func__);
 423                 return;
 424         }
 425
 426         v4l2_dbg(2, debug, sd, "%s:\n", __func__);
 427
 428         /* Enable hotplug after 100 ms. DDC access to EDID is also enabled when
 429          * hotplug is enabled. See register DDC_CTL */
 430         schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 10);
 431
 432         tc358743_enable_interrupts(sd, true);
 433         tc358743_s_ctrl_detect_tx_5v(sd);
 434 }
 435
 436 static void tc358743_erase_bksv(struct v4l2_subdev *sd)
 437 {
 438         int i;
 439
 440         for (i = 0; i < 5; i++)
 441                 i2c_wr8(sd, BKSV + i, 0);
 442 }
 443
 444 /* --------------- AVI infoframe --------------- */
 445
 446 static void print_avi_infoframe(struct v4l2_subdev *sd)
 447 {
 448         struct i2c_client *client = v4l2_get_subdevdata(sd);
 449         struct device *dev = &client->dev;
 450         union hdmi_infoframe frame;
 451         u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
 452
 453         if (!is_hdmi(sd)) {
 454                 v4l2_info(sd, "DVI-D signal - AVI infoframe not supported\n");
 455                 return;
 456         }
 457
 458         i2c_rd(sd, PK_AVI_0HEAD, buffer, HDMI_INFOFRAME_SIZE(AVI));
 459
 460         if (hdmi_infoframe_unpack(&frame, buffer) < 0) {
 461                 v4l2_err(sd, "%s: unpack of AVI infoframe failed\n", __func__);
 462                 return;
 463         }
 464
 465         hdmi_infoframe_log(KERN_INFO, dev, &frame);
 466 }
 467
 468 /* --------------- CTRLS --------------- */
 469
 470 static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd)
 471 {
 472         struct tc358743_state *state = to_state(sd);
 473
 474         return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
 475                         tx_5v_power_present(sd));
 476 }
 477
 478 static int tc358743_s_ctrl_audio_sampling_rate(struct v4l2_subdev *sd)
 479 {
 480         struct tc358743_state *state = to_state(sd);
 481
 482         return v4l2_ctrl_s_ctrl(state->audio_sampling_rate_ctrl,
 483                         get_audio_sampling_rate(sd));
 484 }
 485
 486 static int tc358743_s_ctrl_audio_present(struct v4l2_subdev *sd)
 487 {
 488         struct tc358743_state *state = to_state(sd);
 489
 490         return v4l2_ctrl_s_ctrl(state->audio_present_ctrl,
 491                         audio_present(sd));
 492 }
 493
 494 static int tc358743_update_controls(struct v4l2_subdev *sd)
 495 {
 496         int ret = 0;
 497
 498         ret |= tc358743_s_ctrl_detect_tx_5v(sd);
 499         ret |= tc358743_s_ctrl_audio_sampling_rate(sd);
 500         ret |= tc358743_s_ctrl_audio_present(sd);
 501
 502         return ret;
 503 }
 504
 505 /* --------------- INIT --------------- */
 506
 507 static void tc358743_reset_phy(struct v4l2_subdev *sd)
 508 {
 509         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
 510
 511         i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, 0);
 512         i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, MASK_RESET_CTRL);
 513 }
 514
 515 static void tc358743_reset(struct v4l2_subdev *sd, uint16_t mask)
 516 {
 517         u16 sysctl = i2c_rd16(sd, SYSCTL);
 518
 519         i2c_wr16(sd, SYSCTL, sysctl | mask);
 520         i2c_wr16(sd, SYSCTL, sysctl & ~mask);
 521 }
 522
 523 static inline void tc358743_sleep_mode(struct v4l2_subdev *sd, bool enable)
 524 {
 525         i2c_wr16_and_or(sd, SYSCTL, ~MASK_SLEEP,
 526                         enable ? MASK_SLEEP : 0);
 527 }
 528
 529 static inline void enable_stream(struct v4l2_subdev *sd, bool enable)
 530 {
 531         struct tc358743_state *state = to_state(sd);
 532
 533         v4l2_dbg(3, debug, sd, "%s: %sable\n",
 534                         __func__, enable ? "en" : "dis");
 535
 536         if (enable) {
 537                 /* It is critical for CSI receiver to see lane transition
 538                  * LP11->HS. Set to non-continuous mode to enable clock lane
 539                  * LP11 state. */
 540                 i2c_wr32(sd, TXOPTIONCNTRL, 0);
 541                 /* Set to continuous mode to trigger LP11->HS transition */
 542                 i2c_wr32(sd, TXOPTIONCNTRL, MASK_CONTCLKMODE);
 543                 /* Unmute video */
 544                 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE);
 545         } else {
 546                 /* Mute video so that all data lanes go to LSP11 state.
 547                  * No data is output to CSI Tx block. */
 548                 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE | MASK_VI_MUTE);
 549         }
 550
 551         mutex_lock(&state->confctl_mutex);
 552         i2c_wr16_and_or(sd, CONFCTL, ~(MASK_VBUFEN | MASK_ABUFEN),
 553                         enable ? (MASK_VBUFEN | MASK_ABUFEN) : 0x0);
 554         mutex_unlock(&state->confctl_mutex);
 555 }
 556
 557 static void tc358743_set_pll(struct v4l2_subdev *sd)
 558 {
 559         struct tc358743_state *state = to_state(sd);
 560         struct tc358743_platform_data *pdata = &state->pdata;
 561         u16 pllctl0 = i2c_rd16(sd, PLLCTL0);
 562         u16 pllctl1 = i2c_rd16(sd, PLLCTL1);
 563         u16 pllctl0_new = SET_PLL_PRD(pdata->pll_prd) |
 564                 SET_PLL_FBD(pdata->pll_fbd);
 565         u32 hsck = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd;
 566
 567         v4l2_dbg(2, debug, sd, "%s:\n", __func__);
 568
 569         /* Only rewrite when needed (new value or disabled), since rewriting
 570          * triggers another format change event. */
 571         if ((pllctl0 != pllctl0_new) || ((pllctl1 & MASK_PLL_EN) == 0)) {
 572                 u16 pll_frs;
 573
 574                 if (hsck > 500000000)
 575                         pll_frs = 0x0;
 576                 else if (hsck > 250000000)
 577                         pll_frs = 0x1;
 578                 else if (hsck > 125000000)
 579                         pll_frs = 0x2;
 580                 else
 581                         pll_frs = 0x3;
 582
 583                 v4l2_dbg(1, debug, sd, "%s: updating PLL clock\n", __func__);
 584                 tc358743_sleep_mode(sd, true);
 585                 i2c_wr16(sd, PLLCTL0, pllctl0_new);
 586                 i2c_wr16_and_or(sd, PLLCTL1,
 587                                 ~(MASK_PLL_FRS | MASK_RESETB | MASK_PLL_EN),
 588                                 (SET_PLL_FRS(pll_frs) | MASK_RESETB |
 589                                  MASK_PLL_EN));
 590                 udelay(10); /* REF_02, Sheet "Source HDMI" */
 591                 i2c_wr16_and_or(sd, PLLCTL1, ~MASK_CKEN, MASK_CKEN);
 592                 tc358743_sleep_mode(sd, false);
 593         }
 594 }
 595
 596 static void tc358743_set_ref_clk(struct v4l2_subdev *sd)
 597 {
 598         struct tc358743_state *state = to_state(sd);
 599         struct tc358743_platform_data *pdata = &state->pdata;
 600         u32 sys_freq;
 601         u32 lockdet_ref;
 602         u16 fh_min;
 603         u16 fh_max;
 604
 605         BUG_ON(!(pdata->refclk_hz == 26000000 ||
 606                  pdata->refclk_hz == 27000000 ||
 607                  pdata->refclk_hz == 42000000));
 608
 609         sys_freq = pdata->refclk_hz / 10000;
 610         i2c_wr8(sd, SYS_FREQ0, sys_freq & 0x00ff);
 611         i2c_wr8(sd, SYS_FREQ1, (sys_freq & 0xff00) >> 8);
 612
 613         i2c_wr8_and_or(sd, PHY_CTL0, ~MASK_PHY_SYSCLK_IND,
 614                         (pdata->refclk_hz == 42000000) ?
 615                         MASK_PHY_SYSCLK_IND : 0x0);
 616
 617         fh_min = pdata->refclk_hz / 100000;
 618         i2c_wr8(sd, FH_MIN0, fh_min & 0x00ff);
 619         i2c_wr8(sd, FH_MIN1, (fh_min & 0xff00) >> 8);
 620
 621         fh_max = (fh_min * 66) / 10;
 622         i2c_wr8(sd, FH_MAX0, fh_max & 0x00ff);
 623         i2c_wr8(sd, FH_MAX1, (fh_max & 0xff00) >> 8);
 624
 625         lockdet_ref = pdata->refclk_hz / 100;
 626         i2c_wr8(sd, LOCKDET_REF0, lockdet_ref & 0x0000ff);
 627         i2c_wr8(sd, LOCKDET_REF1, (lockdet_ref & 0x00ff00) >> 8);
 628         i2c_wr8(sd, LOCKDET_REF2, (lockdet_ref & 0x0f0000) >> 16);
 629
 630         i2c_wr8_and_or(sd, NCO_F0_MOD, ~MASK_NCO_F0_MOD,
 631                         (pdata->refclk_hz == 27000000) ?
 632                         MASK_NCO_F0_MOD_27MHZ : 0x0);
 633 }
 634
 635 static void tc358743_set_csi_color_space(struct v4l2_subdev *sd)
 636 {
 637         struct tc358743_state *state = to_state(sd);
 638
 639         switch (state->mbus_fmt_code) {
 640         case MEDIA_BUS_FMT_UYVY8_1X16:
 641                 v4l2_dbg(2, debug, sd, "%s: YCbCr 422 16-bit\n", __func__);
 642                 i2c_wr8_and_or(sd, VOUT_SET2,
 643                                 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff,
 644                                 MASK_SEL422 | MASK_VOUT_422FIL_100);
 645                 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff,
 646                                 MASK_VOUT_COLOR_601_YCBCR_LIMITED);
 647                 mutex_lock(&state->confctl_mutex);
 648                 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT,
 649                                 MASK_YCBCRFMT_422_8_BIT);
 650                 mutex_unlock(&state->confctl_mutex);
 651                 break;
 652         case MEDIA_BUS_FMT_RGB888_1X24:
 653                 v4l2_dbg(2, debug, sd, "%s: RGB 888 24-bit\n", __func__);
 654                 i2c_wr8_and_or(sd, VOUT_SET2,
 655                                 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff,
 656                                 0x00);
 657                 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff,
 658                                 MASK_VOUT_COLOR_RGB_FULL);
 659                 mutex_lock(&state->confctl_mutex);
 660                 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT, 0);
 661                 mutex_unlock(&state->confctl_mutex);
 662                 break;
 663         default:
 664                 v4l2_dbg(2, debug, sd, "%s: Unsupported format code 0x%x\n",
 665                                 __func__, state->mbus_fmt_code);
 666         }
 667 }
 668
 669 static unsigned tc358743_num_csi_lanes_needed(struct v4l2_subdev *sd)
 670 {
 671         struct tc358743_state *state = to_state(sd);
 672         struct v4l2_bt_timings *bt = &state->timings.bt;
 673         struct tc358743_platform_data *pdata = &state->pdata;
 674         u32 bits_pr_pixel =
 675                 (state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16) ?  16 : 24;
 676         u32 bps = bt->width * bt->height * fps(bt) * bits_pr_pixel;
 677         u32 bps_pr_lane = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd;
 678
 679         return DIV_ROUND_UP(bps, bps_pr_lane);
 680 }
 681
 682 static void tc358743_set_csi(struct v4l2_subdev *sd)
 683 {
 684         struct tc358743_state *state = to_state(sd);
 685         struct tc358743_platform_data *pdata = &state->pdata;
 686         unsigned lanes = tc358743_num_csi_lanes_needed(sd);
 687
 688         v4l2_dbg(3, debug, sd, "%s:\n", __func__);
 689
 690         tc358743_reset(sd, MASK_CTXRST);
 691
 692         if (lanes < 1)
 693                 i2c_wr32(sd, CLW_CNTRL, MASK_CLW_LANEDISABLE);
 694         if (lanes < 1)
 695                 i2c_wr32(sd, D0W_CNTRL, MASK_D0W_LANEDISABLE);
 696         if (lanes < 2)
 697                 i2c_wr32(sd, D1W_CNTRL, MASK_D1W_LANEDISABLE);
 698         if (lanes < 3)
 699                 i2c_wr32(sd, D2W_CNTRL, MASK_D2W_LANEDISABLE);
 700         if (lanes < 4)
 701                 i2c_wr32(sd, D3W_CNTRL, MASK_D3W_LANEDISABLE);
 702
 703         i2c_wr32(sd, LINEINITCNT, pdata->lineinitcnt);
 704         i2c_wr32(sd, LPTXTIMECNT, pdata->lptxtimecnt);
 705         i2c_wr32(sd, TCLK_HEADERCNT, pdata->tclk_headercnt);
 706         i2c_wr32(sd, TCLK_TRAILCNT, pdata->tclk_trailcnt);
 707         i2c_wr32(sd, THS_HEADERCNT, pdata->ths_headercnt);
 708         i2c_wr32(sd, TWAKEUP, pdata->twakeup);
 709         i2c_wr32(sd, TCLK_POSTCNT, pdata->tclk_postcnt);
 710         i2c_wr32(sd, THS_TRAILCNT, pdata->ths_trailcnt);
 711         i2c_wr32(sd, HSTXVREGCNT, pdata->hstxvregcnt);
 712
 713         i2c_wr32(sd, HSTXVREGEN,
 714                         ((lanes > 0) ? MASK_CLM_HSTXVREGEN : 0x0) |
 715                         ((lanes > 0) ? MASK_D0M_HSTXVREGEN : 0x0) |
 716                         ((lanes > 1) ? MASK_D1M_HSTXVREGEN : 0x0) |
 717                         ((lanes > 2) ? MASK_D2M_HSTXVREGEN : 0x0) |
 718                         ((lanes > 3) ? MASK_D3M_HSTXVREGEN : 0x0));
 719
 720         i2c_wr32(sd, TXOPTIONCNTRL, (state->bus.flags &
 721                  V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) ? MASK_CONTCLKMODE : 0);
 722         i2c_wr32(sd, STARTCNTRL, MASK_START);
 723         i2c_wr32(sd, CSI_START, MASK_STRT);
 724
 725         i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
 726                         MASK_ADDRESS_CSI_CONTROL |
 727                         MASK_CSI_MODE |
 728                         MASK_TXHSMD |
 729                         ((lanes == 4) ? MASK_NOL_4 :
 730                          (lanes == 3) ? MASK_NOL_3 :
 731                          (lanes == 2) ? MASK_NOL_2 : MASK_NOL_1));
 732
 733         i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
 734                         MASK_ADDRESS_CSI_ERR_INTENA | MASK_TXBRK | MASK_QUNK |
 735                         MASK_WCER | MASK_INER);
 736
 737         i2c_wr32(sd, CSI_CONFW, MASK_MODE_CLEAR |
 738                         MASK_ADDRESS_CSI_ERR_HALT | MASK_TXBRK | MASK_QUNK);
 739
 740         i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
 741                         MASK_ADDRESS_CSI_INT_ENA | MASK_INTER);
 742 }
 743
 744 static void tc358743_set_hdmi_phy(struct v4l2_subdev *sd)
 745 {
 746         struct tc358743_state *state = to_state(sd);
 747         struct tc358743_platform_data *pdata = &state->pdata;
 748
 749         /* Default settings from REF_02, sheet "Source HDMI"
 750          * and custom settings as platform data */
 751         i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, 0x0);
 752         i2c_wr8(sd, PHY_CTL1, SET_PHY_AUTO_RST1_US(1600) |
 753                         SET_FREQ_RANGE_MODE_CYCLES(1));
 754         i2c_wr8_and_or(sd, PHY_CTL2, ~MASK_PHY_AUTO_RSTn,
 755                         (pdata->hdmi_phy_auto_reset_tmds_detected ?
 756                          MASK_PHY_AUTO_RST2 : 0) |
 757                         (pdata->hdmi_phy_auto_reset_tmds_in_range ?
 758                          MASK_PHY_AUTO_RST3 : 0) |
 759                         (pdata->hdmi_phy_auto_reset_tmds_valid ?
 760                          MASK_PHY_AUTO_RST4 : 0));
 761         i2c_wr8(sd, PHY_BIAS, 0x40);
 762         i2c_wr8(sd, PHY_CSQ, SET_CSQ_CNT_LEVEL(0x0a));
 763         i2c_wr8(sd, AVM_CTL, 45);
 764         i2c_wr8_and_or(sd, HDMI_DET, ~MASK_HDMI_DET_V,
 765                         pdata->hdmi_detection_delay << 4);
 766         i2c_wr8_and_or(sd, HV_RST, ~(MASK_H_PI_RST | MASK_V_PI_RST),
 767                         (pdata->hdmi_phy_auto_reset_hsync_out_of_range ?
 768                          MASK_H_PI_RST : 0) |
 769                         (pdata->hdmi_phy_auto_reset_vsync_out_of_range ?
 770                          MASK_V_PI_RST : 0));
 771         i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, MASK_ENABLE_PHY);
 772 }
 773
 774 static void tc358743_set_hdmi_audio(struct v4l2_subdev *sd)
 775 {
 776         struct tc358743_state *state = to_state(sd);
 777
 778         /* Default settings from REF_02, sheet "Source HDMI" */
 779         i2c_wr8(sd, FORCE_MUTE, 0x00);
 780         i2c_wr8(sd, AUTO_CMD0, MASK_AUTO_MUTE7 | MASK_AUTO_MUTE6 |
 781                         MASK_AUTO_MUTE5 | MASK_AUTO_MUTE4 |
 782                         MASK_AUTO_MUTE1 | MASK_AUTO_MUTE0);
 783         i2c_wr8(sd, AUTO_CMD1, MASK_AUTO_MUTE9);
 784         i2c_wr8(sd, AUTO_CMD2, MASK_AUTO_PLAY3 | MASK_AUTO_PLAY2);
 785         i2c_wr8(sd, BUFINIT_START, SET_BUFINIT_START_MS(500));
 786         i2c_wr8(sd, FS_MUTE, 0x00);
 787         i2c_wr8(sd, FS_IMODE, MASK_NLPCM_SMODE | MASK_FS_SMODE);
 788         i2c_wr8(sd, ACR_MODE, MASK_CTS_MODE);
 789         i2c_wr8(sd, ACR_MDF0, MASK_ACR_L2MDF_1976_PPM | MASK_ACR_L1MDF_976_PPM);
 790         i2c_wr8(sd, ACR_MDF1, MASK_ACR_L3MDF_3906_PPM);
 791         i2c_wr8(sd, SDO_MODE1, MASK_SDO_FMT_I2S);
 792         i2c_wr8(sd, DIV_MODE, SET_DIV_DLY_MS(100));
 793
 794         mutex_lock(&state->confctl_mutex);
 795         i2c_wr16_and_or(sd, CONFCTL, 0xffff, MASK_AUDCHNUM_2 |
 796                         MASK_AUDOUTSEL_I2S | MASK_AUTOINDEX);
 797         mutex_unlock(&state->confctl_mutex);
 798 }
 799
 800 static void tc358743_set_hdmi_info_frame_mode(struct v4l2_subdev *sd)
 801 {
 802         /* Default settings from REF_02, sheet "Source HDMI" */
 803         i2c_wr8(sd, PK_INT_MODE, MASK_ISRC2_INT_MODE | MASK_ISRC_INT_MODE |
 804                         MASK_ACP_INT_MODE | MASK_VS_INT_MODE |
 805                         MASK_SPD_INT_MODE | MASK_MS_INT_MODE |
 806                         MASK_AUD_INT_MODE | MASK_AVI_INT_MODE);
 807         i2c_wr8(sd, NO_PKT_LIMIT, 0x2c);
 808         i2c_wr8(sd, NO_PKT_CLR, 0x53);
 809         i2c_wr8(sd, ERR_PK_LIMIT, 0x01);
 810         i2c_wr8(sd, NO_PKT_LIMIT2, 0x30);
 811         i2c_wr8(sd, NO_GDB_LIMIT, 0x10);
 812 }
 813
 814 static void tc358743_initial_setup(struct v4l2_subdev *sd)
 815 {
 816         struct tc358743_state *state = to_state(sd);
 817         struct tc358743_platform_data *pdata = &state->pdata;
 818
 819         /* CEC and IR are not supported by this driver */
 820         i2c_wr16_and_or(sd, SYSCTL, ~(MASK_CECRST | MASK_IRRST),
 821                         (MASK_CECRST | MASK_IRRST));
 822
 823         tc358743_reset(sd, MASK_CTXRST | MASK_HDMIRST);
 824         tc358743_sleep_mode(sd, false);
 825
 826         i2c_wr16(sd, FIFOCTL, pdata->fifo_level);
 827
 828         tc358743_set_ref_clk(sd);
 829
 830         i2c_wr8_and_or(sd, DDC_CTL, ~MASK_DDC5V_MODE,
 831                         pdata->ddc5v_delay & MASK_DDC5V_MODE);
 832         i2c_wr8_and_or(sd, EDID_MODE, ~MASK_EDID_MODE, MASK_EDID_MODE_E_DDC);
 833
 834         tc358743_set_hdmi_phy(sd);
 835         tc358743_set_hdmi_hdcp(sd, pdata->enable_hdcp);
 836         tc358743_set_hdmi_audio(sd);
 837         tc358743_set_hdmi_info_frame_mode(sd);
 838
 839         /* All CE and IT formats are detected as RGB full range in DVI mode */
 840         i2c_wr8_and_or(sd, VI_MODE, ~MASK_RGB_DVI, 0);
 841
 842         i2c_wr8_and_or(sd, VOUT_SET2, ~MASK_VOUTCOLORMODE,
 843                         MASK_VOUTCOLORMODE_AUTO);
 844         i2c_wr8(sd, VOUT_SET3, MASK_VOUT_EXTCNT);
 845 }
 846
 847 /* --------------- IRQ --------------- */
 848
 849 static void tc358743_format_change(struct v4l2_subdev *sd)
 850 {
 851         struct tc358743_state *state = to_state(sd);
 852         struct v4l2_dv_timings timings;
 853         const struct v4l2_event tc358743_ev_fmt = {
 854                 .type = V4L2_EVENT_SOURCE_CHANGE,
 855                 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
 856         };
 857
 858         if (tc358743_get_detected_timings(sd, &timings)) {
 859                 enable_stream(sd, false);
 860
 861                 v4l2_dbg(1, debug, sd, "%s: No signal\n",
 862                                 __func__);
 863         } else {
 864                 if (!v4l2_match_dv_timings(&state->timings, &timings, 0, false))
 865                         enable_stream(sd, false);
 866
 867                 if (debug)
 868                         v4l2_print_dv_timings(sd->name,
 869                                         "tc358743_format_change: New format: ",
 870                                         &timings, false);
 871         }
 872
 873         if (sd->devnode)
 874                 v4l2_subdev_notify_event(sd, &tc358743_ev_fmt);
 875 }
 876
 877 static void tc358743_init_interrupts(struct v4l2_subdev *sd)
 878 {
 879         u16 i;
 880
 881         /* clear interrupt status registers */
 882         for (i = SYS_INT; i <= KEY_INT; i++)
 883                 i2c_wr8(sd, i, 0xff);
 884
 885         i2c_wr16(sd, INTSTATUS, 0xffff);
 886 }
 887
 888 static void tc358743_enable_interrupts(struct v4l2_subdev *sd,
 889                 bool cable_connected)
 890 {
 891         v4l2_dbg(2, debug, sd, "%s: cable connected = %d\n", __func__,
 892                         cable_connected);
 893
 894         if (cable_connected) {
 895                 i2c_wr8(sd, SYS_INTM, ~(MASK_M_DDC | MASK_M_DVI_DET |
 896                                         MASK_M_HDMI_DET) & 0xff);
 897                 i2c_wr8(sd, CLK_INTM, ~MASK_M_IN_DE_CHG);
 898                 i2c_wr8(sd, CBIT_INTM, ~(MASK_M_CBIT_FS | MASK_M_AF_LOCK |
 899                                         MASK_M_AF_UNLOCK) & 0xff);
 900                 i2c_wr8(sd, AUDIO_INTM, ~MASK_M_BUFINIT_END);
 901                 i2c_wr8(sd, MISC_INTM, ~MASK_M_SYNC_CHG);
 902         } else {
 903                 i2c_wr8(sd, SYS_INTM, ~MASK_M_DDC & 0xff);
 904                 i2c_wr8(sd, CLK_INTM, 0xff);
 905                 i2c_wr8(sd, CBIT_INTM, 0xff);
 906                 i2c_wr8(sd, AUDIO_INTM, 0xff);
 907                 i2c_wr8(sd, MISC_INTM, 0xff);
 908         }
 909 }
 910
 911 static void tc358743_hdmi_audio_int_handler(struct v4l2_subdev *sd,
 912                 bool *handled)
 913 {
 914         u8 audio_int_mask = i2c_rd8(sd, AUDIO_INTM);
 915         u8 audio_int = i2c_rd8(sd, AUDIO_INT) & ~audio_int_mask;
 916
 917         i2c_wr8(sd, AUDIO_INT, audio_int);
 918
 919         v4l2_dbg(3, debug, sd, "%s: AUDIO_INT = 0x%02x\n", __func__, audio_int);
 920
 921         tc358743_s_ctrl_audio_sampling_rate(sd);
 922         tc358743_s_ctrl_audio_present(sd);
 923 }
 924
 925 static void tc358743_csi_err_int_handler(struct v4l2_subdev *sd, bool *handled)
 926 {
 927         v4l2_err(sd, "%s: CSI_ERR = 0x%x\n", __func__, i2c_rd32(sd, CSI_ERR));
 928
 929         i2c_wr32(sd, CSI_INT_CLR, MASK_ICRER);
 930 }
 931
 932 static void tc358743_hdmi_misc_int_handler(struct v4l2_subdev *sd,
 933                 bool *handled)
 934 {
 935         u8 misc_int_mask = i2c_rd8(sd, MISC_INTM);
 936         u8 misc_int = i2c_rd8(sd, MISC_INT) & ~misc_int_mask;
 937
 938         i2c_wr8(sd, MISC_INT, misc_int);
 939
 940         v4l2_dbg(3, debug, sd, "%s: MISC_INT = 0x%02x\n", __func__, misc_int);
 941
 942         if (misc_int & MASK_I_SYNC_CHG) {
 943                 /* Reset the HDMI PHY to try to trigger proper lock on the
 944                  * incoming video format. Erase BKSV to prevent that old keys
 945                  * are used when a new source is connected. */
 946                 if (no_sync(sd) || no_signal(sd)) {
 947                         tc358743_reset_phy(sd);
 948                         tc358743_erase_bksv(sd);
 949                 }
 950
 951                 tc358743_format_change(sd);
 952
 953                 misc_int &= ~MASK_I_SYNC_CHG;
 954                 if (handled)
 955                         *handled = true;
 956         }
 957
 958         if (misc_int) {
 959                 v4l2_err(sd, "%s: Unhandled MISC_INT interrupts: 0x%02x\n",
 960                                 __func__, misc_int);
 961         }
 962 }
 963
 964 static void tc358743_hdmi_cbit_int_handler(struct v4l2_subdev *sd,
 965                 bool *handled)
 966 {
 967         u8 cbit_int_mask = i2c_rd8(sd, CBIT_INTM);
 968         u8 cbit_int = i2c_rd8(sd, CBIT_INT) & ~cbit_int_mask;
 969
 970         i2c_wr8(sd, CBIT_INT, cbit_int);
 971
 972         v4l2_dbg(3, debug, sd, "%s: CBIT_INT = 0x%02x\n", __func__, cbit_int);
 973
 974         if (cbit_int & MASK_I_CBIT_FS) {
 975
 976                 v4l2_dbg(1, debug, sd, "%s: Audio sample rate changed\n",
 977                                 __func__);
 978                 tc358743_s_ctrl_audio_sampling_rate(sd);
 979
 980                 cbit_int &= ~MASK_I_CBIT_FS;
 981                 if (handled)
 982                         *handled = true;
 983         }
 984
 985         if (cbit_int & (MASK_I_AF_LOCK | MASK_I_AF_UNLOCK)) {
 986
 987                 v4l2_dbg(1, debug, sd, "%s: Audio present changed\n",
 988                                 __func__);
 989                 tc358743_s_ctrl_audio_present(sd);
 990
 991                 cbit_int &= ~(MASK_I_AF_LOCK | MASK_I_AF_UNLOCK);
 992                 if (handled)
 993                         *handled = true;
 994         }
 995
 996         if (cbit_int) {
 997                 v4l2_err(sd, "%s: Unhandled CBIT_INT interrupts: 0x%02x\n",
 998                                 __func__, cbit_int);
 999         }
1000 }
1001
1002 static void tc358743_hdmi_clk_int_handler(struct v4l2_subdev *sd, bool *handled)
1003 {
1004         u8 clk_int_mask = i2c_rd8(sd, CLK_INTM);
1005         u8 clk_int = i2c_rd8(sd, CLK_INT) & ~clk_int_mask;
1006
1007         /* Bit 7 and bit 6 are set even when they are masked */
1008         i2c_wr8(sd, CLK_INT, clk_int | 0x80 | MASK_I_OUT_H_CHG);
1009
1010         v4l2_dbg(3, debug, sd, "%s: CLK_INT = 0x%02x\n", __func__, clk_int);
1011
1012         if (clk_int & (MASK_I_IN_DE_CHG)) {
1013
1014                 v4l2_dbg(1, debug, sd, "%s: DE size or position has changed\n",
1015                                 __func__);
1016
1017                 /* If the source switch to a new resolution with the same pixel
1018                  * frequency as the existing (e.g. 1080p25 -> 720p50), the
1019                  * I_SYNC_CHG interrupt is not always triggered, while the
1020                  * I_IN_DE_CHG interrupt seems to work fine. Format change
1021                  * notifications are only sent when the signal is stable to
1022                  * reduce the number of notifications. */
1023                 if (!no_signal(sd) && !no_sync(sd))
1024                         tc358743_format_change(sd);
1025
1026                 clk_int &= ~(MASK_I_IN_DE_CHG);
1027                 if (handled)
1028                         *handled = true;
1029         }
1030
1031         if (clk_int) {
1032                 v4l2_err(sd, "%s: Unhandled CLK_INT interrupts: 0x%02x\n",
1033                                 __func__, clk_int);
1034         }
1035 }
1036
1037 static void tc358743_hdmi_sys_int_handler(struct v4l2_subdev *sd, bool *handled)
1038 {
1039         struct tc358743_state *state = to_state(sd);
1040         u8 sys_int_mask = i2c_rd8(sd, SYS_INTM);
1041         u8 sys_int = i2c_rd8(sd, SYS_INT) & ~sys_int_mask;
1042
1043         i2c_wr8(sd, SYS_INT, sys_int);
1044
1045         v4l2_dbg(3, debug, sd, "%s: SYS_INT = 0x%02x\n", __func__, sys_int);
1046
1047         if (sys_int & MASK_I_DDC) {
1048                 bool tx_5v = tx_5v_power_present(sd);
1049
1050                 v4l2_dbg(1, debug, sd, "%s: Tx 5V power present: %s\n",
1051                                 __func__, tx_5v ?  "yes" : "no");
1052
1053                 if (tx_5v) {
1054                         tc358743_enable_edid(sd);
1055                 } else {
1056                         tc358743_enable_interrupts(sd, false);
1057                         tc358743_disable_edid(sd);
1058                         memset(&state->timings, 0, sizeof(state->timings));
1059                         tc358743_erase_bksv(sd);
1060                         tc358743_update_controls(sd);
1061                 }
1062
1063                 sys_int &= ~MASK_I_DDC;
1064                 if (handled)
1065                         *handled = true;
1066         }
1067
1068         if (sys_int & MASK_I_DVI) {
1069                 v4l2_dbg(1, debug, sd, "%s: HDMI->DVI change detected\n",
1070                                 __func__);
1071
1072                 /* Reset the HDMI PHY to try to trigger proper lock on the
1073                  * incoming video format. Erase BKSV to prevent that old keys
1074                  * are used when a new source is connected. */
1075                 if (no_sync(sd) || no_signal(sd)) {
1076                         tc358743_reset_phy(sd);
1077                         tc358743_erase_bksv(sd);
1078                 }
1079
1080                 sys_int &= ~MASK_I_DVI;
1081                 if (handled)
1082                         *handled = true;
1083         }
1084
1085         if (sys_int & MASK_I_HDMI) {
1086                 v4l2_dbg(1, debug, sd, "%s: DVI->HDMI change detected\n",
1087                                 __func__);
1088
1089                 /* Register is reset in DVI mode (REF_01, c. 6.6.41) */
1090                 i2c_wr8(sd, ANA_CTL, MASK_APPL_PCSX_NORMAL | MASK_ANALOG_ON);
1091
1092                 sys_int &= ~MASK_I_HDMI;
1093                 if (handled)
1094                         *handled = true;
1095         }
1096
1097         if (sys_int) {
1098                 v4l2_err(sd, "%s: Unhandled SYS_INT interrupts: 0x%02x\n",
1099                                 __func__, sys_int);
1100         }
1101 }
1102
1103 /* --------------- CORE OPS --------------- */
1104
1105 static int tc358743_log_status(struct v4l2_subdev *sd)
1106 {
1107         struct tc358743_state *state = to_state(sd);
1108         struct v4l2_dv_timings timings;
1109         uint8_t hdmi_sys_status =  i2c_rd8(sd, SYS_STATUS);
1110         uint16_t sysctl = i2c_rd16(sd, SYSCTL);
1111         u8 vi_status3 =  i2c_rd8(sd, VI_STATUS3);
1112         const int deep_color_mode[4] = { 8, 10, 12, 16 };
1113         static const char * const input_color_space[] = {
1114                 "RGB", "YCbCr 601", "Adobe RGB", "YCbCr 709", "NA (4)",
1115                 "xvYCC 601", "NA(6)", "xvYCC 709", "NA(8)", "sYCC601",
1116                 "NA(10)", "NA(11)", "NA(12)", "Adobe YCC 601"};
1117
1118         v4l2_info(sd, "-----Chip status-----\n");
1119         v4l2_info(sd, "Chip ID: 0x%02x\n",
1120                         (i2c_rd16(sd, CHIPID) & MASK_CHIPID) >> 8);
1121         v4l2_info(sd, "Chip revision: 0x%02x\n",
1122                         i2c_rd16(sd, CHIPID) & MASK_REVID);
1123         v4l2_info(sd, "Reset: IR: %d, CEC: %d, CSI TX: %d, HDMI: %d\n",
1124                         !!(sysctl & MASK_IRRST),
1125                         !!(sysctl & MASK_CECRST),
1126                         !!(sysctl & MASK_CTXRST),
1127                         !!(sysctl & MASK_HDMIRST));
1128         v4l2_info(sd, "Sleep mode: %s\n", sysctl & MASK_SLEEP ? "on" : "off");
1129         v4l2_info(sd, "Cable detected (+5V power): %s\n",
1130                         hdmi_sys_status & MASK_S_DDC5V ? "yes" : "no");
1131         v4l2_info(sd, "DDC lines enabled: %s\n",
1132                         (i2c_rd8(sd, EDID_MODE) & MASK_EDID_MODE_E_DDC) ?
1133                         "yes" : "no");
1134         v4l2_info(sd, "Hotplug enabled: %s\n",
1135                         (i2c_rd8(sd, HPD_CTL) & MASK_HPD_OUT0) ?
1136                         "yes" : "no");
1137         v4l2_info(sd, "CEC enabled: %s\n",
1138                         (i2c_rd16(sd, CECEN) & MASK_CECEN) ?  "yes" : "no");
1139         v4l2_info(sd, "-----Signal status-----\n");
1140         v4l2_info(sd, "TMDS signal detected: %s\n",
1141                         hdmi_sys_status & MASK_S_TMDS ? "yes" : "no");
1142         v4l2_info(sd, "Stable sync signal: %s\n",
1143                         hdmi_sys_status & MASK_S_SYNC ? "yes" : "no");
1144         v4l2_info(sd, "PHY PLL locked: %s\n",
1145                         hdmi_sys_status & MASK_S_PHY_PLL ? "yes" : "no");
1146         v4l2_info(sd, "PHY DE detected: %s\n",
1147                         hdmi_sys_status & MASK_S_PHY_SCDT ? "yes" : "no");
1148
1149         if (tc358743_get_detected_timings(sd, &timings)) {
1150                 v4l2_info(sd, "No video detected\n");
1151         } else {
1152                 v4l2_print_dv_timings(sd->name, "Detected format: ", &timings,
1153                                 true);
1154         }
1155         v4l2_print_dv_timings(sd->name, "Configured format: ", &state->timings,
1156                         true);
1157
1158         v4l2_info(sd, "-----CSI-TX status-----\n");
1159         v4l2_info(sd, "Lanes needed: %d\n",
1160                         tc358743_num_csi_lanes_needed(sd));
1161         v4l2_info(sd, "Lanes in use: %d\n",
1162                         tc358743_num_csi_lanes_in_use(sd));
1163         v4l2_info(sd, "Waiting for particular sync signal: %s\n",
1164                         (i2c_rd16(sd, CSI_STATUS) & MASK_S_WSYNC) ?
1165                         "yes" : "no");
1166         v4l2_info(sd, "Transmit mode: %s\n",
1167                         (i2c_rd16(sd, CSI_STATUS) & MASK_S_TXACT) ?
1168                         "yes" : "no");
1169         v4l2_info(sd, "Receive mode: %s\n",
1170                         (i2c_rd16(sd, CSI_STATUS) & MASK_S_RXACT) ?
1171                         "yes" : "no");
1172         v4l2_info(sd, "Stopped: %s\n",
1173                         (i2c_rd16(sd, CSI_STATUS) & MASK_S_HLT) ?
1174                         "yes" : "no");
1175         v4l2_info(sd, "Color space: %s\n",
1176                         state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16 ?
1177                         "YCbCr 422 16-bit" :
1178                         state->mbus_fmt_code == MEDIA_BUS_FMT_RGB888_1X24 ?
1179                         "RGB 888 24-bit" : "Unsupported");
1180
1181         v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
1182         v4l2_info(sd, "HDCP encrypted content: %s\n",
1183                         hdmi_sys_status & MASK_S_HDCP ? "yes" : "no");
1184         v4l2_info(sd, "Input color space: %s %s range\n",
1185                         input_color_space[(vi_status3 & MASK_S_V_COLOR) >> 1],
1186                         (vi_status3 & MASK_LIMITED) ? "limited" : "full");
1187         if (!is_hdmi(sd))
1188                 return 0;
1189         v4l2_info(sd, "AV Mute: %s\n", hdmi_sys_status & MASK_S_AVMUTE ? "on" :
1190                         "off");
1191         v4l2_info(sd, "Deep color mode: %d-bits per channel\n",
1192                         deep_color_mode[(i2c_rd8(sd, VI_STATUS1) &
1193                                 MASK_S_DEEPCOLOR) >> 2]);
1194         print_avi_infoframe(sd);
1195
1196         return 0;
1197 }
1198
1199 #ifdef CONFIG_VIDEO_ADV_DEBUG
1200 static void tc358743_print_register_map(struct v4l2_subdev *sd)
1201 {
1202         v4l2_info(sd, "0x0000-0x00FF: Global Control Register\n");
1203         v4l2_info(sd, "0x0100-0x01FF: CSI2-TX PHY Register\n");
1204         v4l2_info(sd, "0x0200-0x03FF: CSI2-TX PPI Register\n");
1205         v4l2_info(sd, "0x0400-0x05FF: Reserved\n");
1206         v4l2_info(sd, "0x0600-0x06FF: CEC Register\n");
1207         v4l2_info(sd, "0x0700-0x84FF: Reserved\n");
1208         v4l2_info(sd, "0x8500-0x85FF: HDMIRX System Control Register\n");
1209         v4l2_info(sd, "0x8600-0x86FF: HDMIRX Audio Control Register\n");
1210         v4l2_info(sd, "0x8700-0x87FF: HDMIRX InfoFrame packet data Register\n");
1211         v4l2_info(sd, "0x8800-0x88FF: HDMIRX HDCP Port Register\n");
1212         v4l2_info(sd, "0x8900-0x89FF: HDMIRX Video Output Port & 3D Register\n");
1213         v4l2_info(sd, "0x8A00-0x8BFF: Reserved\n");
1214         v4l2_info(sd, "0x8C00-0x8FFF: HDMIRX EDID-RAM (1024bytes)\n");
1215         v4l2_info(sd, "0x9000-0x90FF: HDMIRX GBD Extraction Control\n");
1216         v4l2_info(sd, "0x9100-0x92FF: HDMIRX GBD RAM read\n");
1217         v4l2_info(sd, "0x9300-      : Reserved\n");
1218 }
1219
1220 static int tc358743_get_reg_size(u16 address)
1221 {
1222         /* REF_01 p. 66-72 */
1223         if (address <= 0x00ff)
1224                 return 2;
1225         else if ((address >= 0x0100) && (address <= 0x06FF))
1226                 return 4;
1227         else if ((address >= 0x0700) && (address <= 0x84ff))
1228                 return 2;
1229         else
1230                 return 1;
1231 }
1232
1233 static int tc358743_g_register(struct v4l2_subdev *sd,
1234                                struct v4l2_dbg_register *reg)
1235 {
1236         if (reg->reg > 0xffff) {
1237                 tc358743_print_register_map(sd);
1238                 return -EINVAL;
1239         }
1240
1241         reg->size = tc358743_get_reg_size(reg->reg);
1242
1243         reg->val = i2c_rdreg(sd, reg->reg, reg->size);
1244
1245         return 0;
1246 }
1247
1248 static int tc358743_s_register(struct v4l2_subdev *sd,
1249                                const struct v4l2_dbg_register *reg)
1250 {
1251         if (reg->reg > 0xffff) {
1252                 tc358743_print_register_map(sd);
1253                 return -EINVAL;
1254         }
1255
1256         /* It should not be possible for the user to enable HDCP with a simple
1257          * v4l2-dbg command.
1258          *
1259          * DO NOT REMOVE THIS unless all other issues with HDCP have been
1260          * resolved.
1261          */
1262         if (reg->reg == HDCP_MODE ||
1263             reg->reg == HDCP_REG1 ||
1264             reg->reg == HDCP_REG2 ||
1265             reg->reg == HDCP_REG3 ||
1266             reg->reg == BCAPS)
1267                 return 0;
1268
1269         i2c_wrreg(sd, (u16)reg->reg, reg->val,
1270                         tc358743_get_reg_size(reg->reg));
1271
1272         return 0;
1273 }
1274 #endif
1275
1276 static int tc358743_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1277 {
1278         u16 intstatus = i2c_rd16(sd, INTSTATUS);
1279
1280         v4l2_dbg(1, debug, sd, "%s: IntStatus = 0x%04x\n", __func__, intstatus);
1281
1282         if (intstatus & MASK_HDMI_INT) {
1283                 u8 hdmi_int0 = i2c_rd8(sd, HDMI_INT0);
1284                 u8 hdmi_int1 = i2c_rd8(sd, HDMI_INT1);
1285
1286                 if (hdmi_int0 & MASK_I_MISC)
1287                         tc358743_hdmi_misc_int_handler(sd, handled);
1288                 if (hdmi_int1 & MASK_I_CBIT)
1289                         tc358743_hdmi_cbit_int_handler(sd, handled);
1290                 if (hdmi_int1 & MASK_I_CLK)
1291                         tc358743_hdmi_clk_int_handler(sd, handled);
1292                 if (hdmi_int1 & MASK_I_SYS)
1293                         tc358743_hdmi_sys_int_handler(sd, handled);
1294                 if (hdmi_int1 & MASK_I_AUD)
1295                         tc358743_hdmi_audio_int_handler(sd, handled);
1296
1297                 i2c_wr16(sd, INTSTATUS, MASK_HDMI_INT);
1298                 intstatus &= ~MASK_HDMI_INT;
1299         }
1300
1301         if (intstatus & MASK_CSI_INT) {
1302                 u32 csi_int = i2c_rd32(sd, CSI_INT);
1303
1304                 if (csi_int & MASK_INTER)
1305                         tc358743_csi_err_int_handler(sd, handled);
1306
1307                 i2c_wr16(sd, INTSTATUS, MASK_CSI_INT);
1308                 intstatus &= ~MASK_CSI_INT;
1309         }
1310
1311         intstatus = i2c_rd16(sd, INTSTATUS);
1312         if (intstatus) {
1313                 v4l2_dbg(1, debug, sd,
1314                                 "%s: Unhandled IntStatus interrupts: 0x%02x\n",
1315                                 __func__, intstatus);
1316         }
1317
1318         return 0;
1319 }
1320
1321 static irqreturn_t tc358743_irq_handler(int irq, void *dev_id)
1322 {
1323         struct tc358743_state *state = dev_id;
1324         bool handled = false;
1325
1326         tc358743_isr(&state->sd, 0, &handled);
1327
1328         return handled ? IRQ_HANDLED : IRQ_NONE;
1329 }
1330
1331 static int tc358743_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
1332                                     struct v4l2_event_subscription *sub)
1333 {
1334         switch (sub->type) {
1335         case V4L2_EVENT_SOURCE_CHANGE:
1336                 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
1337         case V4L2_EVENT_CTRL:
1338                 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
1339         default:
1340                 return -EINVAL;
1341         }
1342 }
1343
1344 /* --------------- VIDEO OPS --------------- */
1345
1346 static int tc358743_g_input_status(struct v4l2_subdev *sd, u32 *status)
1347 {
1348         *status = 0;
1349         *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1350         *status |= no_sync(sd) ? V4L2_IN_ST_NO_SYNC : 0;
1351
1352         v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1353
1354         return 0;
1355 }
1356
1357 static int tc358743_s_dv_timings(struct v4l2_subdev *sd,
1358                                  struct v4l2_dv_timings *timings)
1359 {
1360         struct tc358743_state *state = to_state(sd);
1361
1362         if (!timings)
1363                 return -EINVAL;
1364
1365         if (debug)
1366                 v4l2_print_dv_timings(sd->name, "tc358743_s_dv_timings: ",
1367                                 timings, false);
1368
1369         if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) {
1370                 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1371                 return 0;
1372         }
1373
1374         if (!v4l2_valid_dv_timings(timings,
1375                                 &tc358743_timings_cap, NULL, NULL)) {
1376                 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
1377                 return -ERANGE;
1378         }
1379
1380         state->timings = *timings;
1381
1382         enable_stream(sd, false);
1383         tc358743_set_pll(sd);
1384         tc358743_set_csi(sd);
1385
1386         return 0;
1387 }
1388
1389 static int tc358743_g_dv_timings(struct v4l2_subdev *sd,
1390                                  struct v4l2_dv_timings *timings)
1391 {
1392         struct tc358743_state *state = to_state(sd);
1393
1394         *timings = state->timings;
1395
1396         return 0;
1397 }
1398
1399 static int tc358743_enum_dv_timings(struct v4l2_subdev *sd,
1400                                     struct v4l2_enum_dv_timings *timings)
1401 {
1402         if (timings->pad != 0)
1403                 return -EINVAL;
1404
1405         return v4l2_enum_dv_timings_cap(timings,
1406                         &tc358743_timings_cap, NULL, NULL);
1407 }
1408
1409 static int tc358743_query_dv_timings(struct v4l2_subdev *sd,
1410                 struct v4l2_dv_timings *timings)
1411 {
1412         int ret;
1413
1414         ret = tc358743_get_detected_timings(sd, timings);
1415         if (ret)
1416                 return ret;
1417
1418         if (debug)
1419                 v4l2_print_dv_timings(sd->name, "tc358743_query_dv_timings: ",
1420                                 timings, false);
1421
1422         if (!v4l2_valid_dv_timings(timings,
1423                                 &tc358743_timings_cap, NULL, NULL)) {
1424                 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
1425                 return -ERANGE;
1426         }
1427
1428         return 0;
1429 }
1430
1431 static int tc358743_dv_timings_cap(struct v4l2_subdev *sd,
1432                 struct v4l2_dv_timings_cap *cap)
1433 {
1434         if (cap->pad != 0)
1435                 return -EINVAL;
1436
1437         *cap = tc358743_timings_cap;
1438
1439         return 0;
1440 }
1441
1442 static int tc358743_g_mbus_config(struct v4l2_subdev *sd,
1443                              struct v4l2_mbus_config *cfg)
1444 {
1445         cfg->type = V4L2_MBUS_CSI2;
1446
1447         /* Support for non-continuous CSI-2 clock is missing in the driver */
1448         cfg->flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1449
1450         switch (tc358743_num_csi_lanes_in_use(sd)) {
1451         case 1:
1452                 cfg->flags |= V4L2_MBUS_CSI2_1_LANE;
1453                 break;
1454         case 2:
1455                 cfg->flags |= V4L2_MBUS_CSI2_2_LANE;
1456                 break;
1457         case 3:
1458                 cfg->flags |= V4L2_MBUS_CSI2_3_LANE;
1459                 break;
1460         case 4:
1461                 cfg->flags |= V4L2_MBUS_CSI2_4_LANE;
1462                 break;
1463         default:
1464                 return -EINVAL;
1465         }
1466
1467         return 0;
1468 }
1469
1470 static int tc358743_s_stream(struct v4l2_subdev *sd, int enable)
1471 {
1472         enable_stream(sd, enable);
1473
1474         return 0;
1475 }
1476
1477 /* --------------- PAD OPS --------------- */
1478
1479 static int tc358743_get_fmt(struct v4l2_subdev *sd,
1480                 struct v4l2_subdev_pad_config *cfg,
1481                 struct v4l2_subdev_format *format)
1482 {
1483         struct tc358743_state *state = to_state(sd);
1484         u8 vi_rep = i2c_rd8(sd, VI_REP);
1485
1486         if (format->pad != 0)
1487                 return -EINVAL;
1488
1489         format->format.code = state->mbus_fmt_code;
1490         format->format.width = state->timings.bt.width;
1491         format->format.height = state->timings.bt.height;
1492         format->format.field = V4L2_FIELD_NONE;
1493
1494         switch (vi_rep & MASK_VOUT_COLOR_SEL) {
1495         case MASK_VOUT_COLOR_RGB_FULL:
1496         case MASK_VOUT_COLOR_RGB_LIMITED:
1497                 format->format.colorspace = V4L2_COLORSPACE_SRGB;
1498                 break;
1499         case MASK_VOUT_COLOR_601_YCBCR_LIMITED:
1500         case MASK_VOUT_COLOR_601_YCBCR_FULL:
1501                 format->format.colorspace = V4L2_COLORSPACE_SMPTE170M;
1502                 break;
1503         case MASK_VOUT_COLOR_709_YCBCR_FULL:
1504         case MASK_VOUT_COLOR_709_YCBCR_LIMITED:
1505                 format->format.colorspace = V4L2_COLORSPACE_REC709;
1506                 break;
1507         default:
1508                 format->format.colorspace = 0;
1509                 break;
1510         }
1511
1512         return 0;
1513 }
1514
1515 static int tc358743_set_fmt(struct v4l2_subdev *sd,
1516                 struct v4l2_subdev_pad_config *cfg,
1517                 struct v4l2_subdev_format *format)
1518 {
1519         struct tc358743_state *state = to_state(sd);
1520
1521         u32 code = format->format.code; /* is overwritten by get_fmt */
1522         int ret = tc358743_get_fmt(sd, cfg, format);
1523
1524         format->format.code = code;
1525
1526         if (ret)
1527                 return ret;
1528
1529         switch (code) {
1530         case MEDIA_BUS_FMT_RGB888_1X24:
1531         case MEDIA_BUS_FMT_UYVY8_1X16:
1532                 break;
1533         default:
1534                 return -EINVAL;
1535         }
1536
1537         if (format->which == V4L2_SUBDEV_FORMAT_TRY)
1538                 return 0;
1539
1540         state->mbus_fmt_code = format->format.code;
1541
1542         enable_stream(sd, false);
1543         tc358743_set_pll(sd);
1544         tc358743_set_csi(sd);
1545         tc358743_set_csi_color_space(sd);
1546
1547         return 0;
1548 }
1549
1550 static int tc358743_g_edid(struct v4l2_subdev *sd,
1551                 struct v4l2_subdev_edid *edid)
1552 {
1553         struct tc358743_state *state = to_state(sd);
1554
1555         memset(edid->reserved, 0, sizeof(edid->reserved));
1556
1557         if (edid->pad != 0)
1558                 return -EINVAL;
1559
1560         if (edid->start_block == 0 && edid->blocks == 0) {
1561                 edid->blocks = state->edid_blocks_written;
1562                 return 0;
1563         }
1564
1565         if (state->edid_blocks_written == 0)
1566                 return -ENODATA;
1567
1568         if (edid->start_block >= state->edid_blocks_written ||
1569                         edid->blocks == 0)
1570                 return -EINVAL;
1571
1572         if (edid->start_block + edid->blocks > state->edid_blocks_written)
1573                 edid->blocks = state->edid_blocks_written - edid->start_block;
1574
1575         i2c_rd(sd, EDID_RAM + (edid->start_block * EDID_BLOCK_SIZE), edid->edid,
1576                         edid->blocks * EDID_BLOCK_SIZE);
1577
1578         return 0;
1579 }
1580
1581 static int tc358743_s_edid(struct v4l2_subdev *sd,
1582                                 struct v4l2_subdev_edid *edid)
1583 {
1584         struct tc358743_state *state = to_state(sd);
1585         u16 edid_len = edid->blocks * EDID_BLOCK_SIZE;
1586         int i;
1587
1588         v4l2_dbg(2, debug, sd, "%s, pad %d, start block %d, blocks %d\n",
1589                  __func__, edid->pad, edid->start_block, edid->blocks);
1590
1591         memset(edid->reserved, 0, sizeof(edid->reserved));
1592
1593         if (edid->pad != 0)
1594                 return -EINVAL;
1595
1596         if (edid->start_block != 0)
1597                 return -EINVAL;
1598
1599         if (edid->blocks > EDID_NUM_BLOCKS_MAX) {
1600                 edid->blocks = EDID_NUM_BLOCKS_MAX;
1601                 return -E2BIG;
1602         }
1603
1604         tc358743_disable_edid(sd);
1605
1606         i2c_wr8(sd, EDID_LEN1, edid_len & 0xff);
1607         i2c_wr8(sd, EDID_LEN2, edid_len >> 8);
1608
1609         if (edid->blocks == 0) {
1610                 state->edid_blocks_written = 0;
1611                 return 0;
1612         }
1613
1614         for (i = 0; i < edid_len; i += EDID_BLOCK_SIZE)
1615                 i2c_wr(sd, EDID_RAM + i, edid->edid + i, EDID_BLOCK_SIZE);
1616
1617         state->edid_blocks_written = edid->blocks;
1618
1619         if (tx_5v_power_present(sd))
1620                 tc358743_enable_edid(sd);
1621
1622         return 0;
1623 }
1624
1625 /* -------------------------------------------------------------------------- */
1626
1627 static const struct v4l2_subdev_core_ops tc358743_core_ops = {
1628         .log_status = tc358743_log_status,
1629 #ifdef CONFIG_VIDEO_ADV_DEBUG
1630         .g_register = tc358743_g_register,
1631         .s_register = tc358743_s_register,
1632 #endif
1633         .interrupt_service_routine = tc358743_isr,
1634         .subscribe_event = tc358743_subscribe_event,
1635         .unsubscribe_event = v4l2_event_subdev_unsubscribe,
1636 };
1637
1638 static const struct v4l2_subdev_video_ops tc358743_video_ops = {
1639         .g_input_status = tc358743_g_input_status,
1640         .s_dv_timings = tc358743_s_dv_timings,
1641         .g_dv_timings = tc358743_g_dv_timings,
1642         .query_dv_timings = tc358743_query_dv_timings,
1643         .g_mbus_config = tc358743_g_mbus_config,
1644         .s_stream = tc358743_s_stream,
1645 };
1646
1647 static const struct v4l2_subdev_pad_ops tc358743_pad_ops = {
1648         .set_fmt = tc358743_set_fmt,
1649         .get_fmt = tc358743_get_fmt,
1650         .get_edid = tc358743_g_edid,
1651         .set_edid = tc358743_s_edid,
1652         .enum_dv_timings = tc358743_enum_dv_timings,
1653         .dv_timings_cap = tc358743_dv_timings_cap,
1654 };
1655
1656 static const struct v4l2_subdev_ops tc358743_ops = {
1657         .core = &tc358743_core_ops,
1658         .video = &tc358743_video_ops,
1659         .pad = &tc358743_pad_ops,
1660 };
1661
1662 /* --------------- CUSTOM CTRLS --------------- */
1663
1664 static const struct v4l2_ctrl_config tc358743_ctrl_audio_sampling_rate = {
1665         .id = TC358743_CID_AUDIO_SAMPLING_RATE,
1666         .name = "Audio sampling rate",
1667         .type = V4L2_CTRL_TYPE_INTEGER,
1668         .min = 0,
1669         .max = 768000,
1670         .step = 1,
1671         .def = 0,
1672         .flags = V4L2_CTRL_FLAG_READ_ONLY,
1673 };
1674
1675 static const struct v4l2_ctrl_config tc358743_ctrl_audio_present = {
1676         .id = TC358743_CID_AUDIO_PRESENT,
1677         .name = "Audio present",
1678         .type = V4L2_CTRL_TYPE_BOOLEAN,
1679         .min = 0,
1680         .max = 1,
1681         .step = 1,
1682         .def = 0,
1683         .flags = V4L2_CTRL_FLAG_READ_ONLY,
1684 };
1685
1686 /* --------------- PROBE / REMOVE --------------- */
1687
1688 #ifdef CONFIG_OF
1689 static void tc358743_gpio_reset(struct tc358743_state *state)
1690 {
1691         usleep_range(5000, 10000);
1692         gpiod_set_value(state->reset_gpio, 1);
1693         usleep_range(1000, 2000);
1694         gpiod_set_value(state->reset_gpio, 0);
1695         msleep(20);
1696 }
1697
1698 static int tc358743_probe_of(struct tc358743_state *state)
1699 {
1700         struct device *dev = &state->i2c_client->dev;
1701         struct v4l2_of_endpoint *endpoint;
1702         struct device_node *ep;
1703         struct clk *refclk;
1704         u32 bps_pr_lane;
1705         int ret = -EINVAL;
1706
1707         refclk = devm_clk_get(dev, "refclk");
1708         if (IS_ERR(refclk)) {
1709                 if (PTR_ERR(refclk) != -EPROBE_DEFER)
1710                         dev_err(dev, "failed to get refclk: %ld\n",
1711                                 PTR_ERR(refclk));
1712                 return PTR_ERR(refclk);
1713         }
1714
1715         ep = of_graph_get_next_endpoint(dev->of_node, NULL);
1716         if (!ep) {
1717                 dev_err(dev, "missing endpoint node\n");
1718                 return -EINVAL;
1719         }
1720
1721         endpoint = v4l2_of_alloc_parse_endpoint(ep);
1722         if (IS_ERR(endpoint)) {
1723                 dev_err(dev, "failed to parse endpoint\n");
1724                 return PTR_ERR(endpoint);
1725         }
1726
1727         if (endpoint->bus_type != V4L2_MBUS_CSI2 ||
1728             endpoint->bus.mipi_csi2.num_data_lanes == 0 ||
1729             endpoint->nr_of_link_frequencies == 0) {
1730                 dev_err(dev, "missing CSI-2 properties in endpoint\n");
1731                 goto free_endpoint;
1732         }
1733
1734         state->bus = endpoint->bus.mipi_csi2;
1735
1736         clk_prepare_enable(refclk);
1737
1738         state->pdata.refclk_hz = clk_get_rate(refclk);
1739         state->pdata.ddc5v_delay = DDC5V_DELAY_100_MS;
1740         state->pdata.enable_hdcp = false;
1741         /* A FIFO level of 16 should be enough for 2-lane 720p60 at 594 MHz. */
1742         state->pdata.fifo_level = 16;
1743         /*
1744          * The PLL input clock is obtained by dividing refclk by pll_prd.
1745          * It must be between 6 MHz and 40 MHz, lower frequency is better.
1746          */
1747         switch (state->pdata.refclk_hz) {
1748         case 26000000:
1749         case 27000000:
1750         case 42000000:
1751                 state->pdata.pll_prd = state->pdata.refclk_hz / 6000000;
1752                 break;
1753         default:
1754                 dev_err(dev, "unsupported refclk rate: %u Hz\n",
1755                         state->pdata.refclk_hz);
1756                 goto disable_clk;
1757         }
1758
1759         /*
1760          * The CSI bps per lane must be between 62.5 Mbps and 1 Gbps.
1761          * The default is 594 Mbps for 4-lane 1080p60 or 2-lane 720p60.
1762          */
1763         bps_pr_lane = 2 * endpoint->link_frequencies[0];
1764         if (bps_pr_lane < 62500000U || bps_pr_lane > 1000000000U) {
1765                 dev_err(dev, "unsupported bps per lane: %u bps\n", bps_pr_lane);
1766                 ret = -EINVAL;
1767                 goto disable_clk;
1768         }
1769
1770         /* The CSI speed per lane is refclk / pll_prd * pll_fbd */
1771         state->pdata.pll_fbd = bps_pr_lane /
1772                                state->pdata.refclk_hz * state->pdata.pll_prd;
1773
1774         /*
1775          * FIXME: These timings are from REF_02 for 594 Mbps per lane (297 MHz
1776          * link frequency). In principle it should be possible to calculate
1777          * them based on link frequency and resolution.
1778          */
1779         if (bps_pr_lane != 594000000U)
1780                 dev_warn(dev, "untested bps per lane: %u bps\n", bps_pr_lane);
1781         state->pdata.lineinitcnt = 0xe80;
1782         state->pdata.lptxtimecnt = 0x003;
1783         /* tclk-preparecnt: 3, tclk-zerocnt: 20 */
1784         state->pdata.tclk_headercnt = 0x1403;
1785         state->pdata.tclk_trailcnt = 0x00;
1786         /* ths-preparecnt: 3, ths-zerocnt: 1 */
1787         state->pdata.ths_headercnt = 0x0103;
1788         state->pdata.twakeup = 0x4882;
1789         state->pdata.tclk_postcnt = 0x008;
1790         state->pdata.ths_trailcnt = 0x2;
1791         state->pdata.hstxvregcnt = 0;
1792
1793         state->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1794                                                     GPIOD_OUT_LOW);
1795         if (IS_ERR(state->reset_gpio)) {
1796                 dev_err(dev, "failed to get reset gpio\n");
1797                 ret = PTR_ERR(state->reset_gpio);
1798                 goto disable_clk;
1799         }
1800
1801         if (state->reset_gpio)
1802                 tc358743_gpio_reset(state);
1803
1804         ret = 0;
1805         goto free_endpoint;
1806
1807 disable_clk:
1808         clk_disable_unprepare(refclk);
1809 free_endpoint:
1810         v4l2_of_free_endpoint(endpoint);
1811         return ret;
1812 }
1813 #else
1814 static inline int tc358743_probe_of(struct tc358743_state *state)
1815 {
1816         return -ENODEV;
1817 }
1818 #endif
1819
1820 static int tc358743_probe(struct i2c_client *client,
1821                           const struct i2c_device_id *id)
1822 {
1823         static struct v4l2_dv_timings default_timing =
1824                 V4L2_DV_BT_CEA_640X480P59_94;
1825         struct tc358743_state *state;
1826         struct tc358743_platform_data *pdata = client->dev.platform_data;
1827         struct v4l2_subdev *sd;
1828         int err;
1829
1830         if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1831                 return -EIO;
1832         v4l_dbg(1, debug, client, "chip found @ 0x%x (%s)\n",
1833                 client->addr << 1, client->adapter->name);
1834
1835         state = devm_kzalloc(&client->dev, sizeof(struct tc358743_state),
1836                         GFP_KERNEL);
1837         if (!state)
1838                 return -ENOMEM;
1839
1840         state->i2c_client = client;
1841
1842         /* platform data */
1843         if (pdata) {
1844                 state->pdata = *pdata;
1845                 state->bus.flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1846         } else {
1847                 err = tc358743_probe_of(state);
1848                 if (err == -ENODEV)
1849                         v4l_err(client, "No platform data!\n");
1850                 if (err)
1851                         return err;
1852         }
1853
1854         sd = &state->sd;
1855         v4l2_i2c_subdev_init(sd, client, &tc358743_ops);
1856         sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
1857
1858         /* i2c access */
1859         if ((i2c_rd16(sd, CHIPID) & MASK_CHIPID) != 0) {
1860                 v4l2_info(sd, "not a TC358743 on address 0x%x\n",
1861                           client->addr << 1);
1862                 return -ENODEV;
1863         }
1864
1865         /* control handlers */
1866         v4l2_ctrl_handler_init(&state->hdl, 3);
1867
1868         state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(&state->hdl, NULL,
1869                         V4L2_CID_DV_RX_POWER_PRESENT, 0, 1, 0, 0);
1870
1871         /* custom controls */
1872         state->audio_sampling_rate_ctrl = v4l2_ctrl_new_custom(&state->hdl,
1873                         &tc358743_ctrl_audio_sampling_rate, NULL);
1874
1875         state->audio_present_ctrl = v4l2_ctrl_new_custom(&state->hdl,
1876                         &tc358743_ctrl_audio_present, NULL);
1877
1878         sd->ctrl_handler = &state->hdl;
1879         if (state->hdl.error) {
1880                 err = state->hdl.error;
1881                 goto err_hdl;
1882         }
1883
1884         if (tc358743_update_controls(sd)) {
1885                 err = -ENODEV;
1886                 goto err_hdl;
1887         }
1888
1889         state->pad.flags = MEDIA_PAD_FL_SOURCE;
1890         err = media_entity_pads_init(&sd->entity, 1, &state->pad);
1891         if (err < 0)
1892                 goto err_hdl;
1893
1894         sd->dev = &client->dev;
1895         err = v4l2_async_register_subdev(sd);
1896         if (err < 0)
1897                 goto err_hdl;
1898
1899         mutex_init(&state->confctl_mutex);
1900
1901         INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
1902                         tc358743_delayed_work_enable_hotplug);
1903
1904         tc358743_initial_setup(sd);
1905
1906         tc358743_s_dv_timings(sd, &default_timing);
1907
1908         state->mbus_fmt_code = MEDIA_BUS_FMT_RGB888_1X24;
1909         tc358743_set_csi_color_space(sd);
1910
1911         tc358743_init_interrupts(sd);
1912
1913         if (state->i2c_client->irq) {
1914                 err = devm_request_threaded_irq(&client->dev,
1915                                                 state->i2c_client->irq,
1916                                                 NULL, tc358743_irq_handler,
1917                                                 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1918                                                 "tc358743", state);
1919                 if (err)
1920                         goto err_work_queues;
1921         }
1922
1923         tc358743_enable_interrupts(sd, tx_5v_power_present(sd));
1924         i2c_wr16(sd, INTMASK, ~(MASK_HDMI_MSK | MASK_CSI_MSK) & 0xffff);
1925
1926         err = v4l2_ctrl_handler_setup(sd->ctrl_handler);
1927         if (err)
1928                 goto err_work_queues;
1929
1930         v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
1931                   client->addr << 1, client->adapter->name);
1932
1933         return 0;
1934
1935 err_work_queues:
1936         cancel_delayed_work(&state->delayed_work_enable_hotplug);
1937         mutex_destroy(&state->confctl_mutex);
1938 err_hdl:
1939         media_entity_cleanup(&sd->entity);
1940         v4l2_ctrl_handler_free(&state->hdl);
1941         return err;
1942 }
1943
1944 static int tc358743_remove(struct i2c_client *client)
1945 {
1946         struct v4l2_subdev *sd = i2c_get_clientdata(client);
1947         struct tc358743_state *state = to_state(sd);
1948
1949         cancel_delayed_work(&state->delayed_work_enable_hotplug);
1950         v4l2_async_unregister_subdev(sd);
1951         v4l2_device_unregister_subdev(sd);
1952         mutex_destroy(&state->confctl_mutex);
1953         media_entity_cleanup(&sd->entity);
1954         v4l2_ctrl_handler_free(&state->hdl);
1955
1956         return 0;
1957 }
1958
1959 static struct i2c_device_id tc358743_id[] = {
1960         {"tc358743", 0},
1961         {}
1962 };
1963
1964 MODULE_DEVICE_TABLE(i2c, tc358743_id);
1965
1966 static struct i2c_driver tc358743_driver = {
1967         .driver = {
1968                 .name = "tc358743",
1969         },
1970         .probe = tc358743_probe,
1971         .remove = tc358743_remove,
1972         .id_table = tc358743_id,
1973 };
1974
1975 module_i2c_driver(tc358743_driver);