drivers/media/i2c/tc358743.c

   1 /*
   2  * tc358743 - Toshiba HDMI to CSI-2 bridge
   3  *
   4  * Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights
   5  * reserved.
   6  *
   7  * This program is free software; you may redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  12  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  13  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  14  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  15  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  16  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  17  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  18  * SOFTWARE.
  19  *
  20  */
  21
  22 /*
  23  * References (c = chapter, p = page):
  24  * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60
  25  * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls
  26  */
  27
  28 #include <linux/kernel.h>
  29 #include <linux/module.h>
  30 #include <linux/slab.h>
  31 #include <linux/i2c.h>
  32 #include <linux/clk.h>
  33 #include <linux/delay.h>
  34 #include <linux/gpio/consumer.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/videodev2.h>
  37 #include <linux/workqueue.h>
  38 #include <linux/v4l2-dv-timings.h>
  39 #include <linux/hdmi.h>
  40 #include <media/v4l2-dv-timings.h>
  41 #include <media/v4l2-device.h>
  42 #include <media/v4l2-ctrls.h>
  43 #include <media/v4l2-event.h>
  44 #include <media/v4l2-of.h>
  45 #include <media/tc358743.h>
  46
  47 #include "tc358743_regs.h"
  48
  49 static int debug;
  50 module_param(debug, int, 0644);
  51 MODULE_PARM_DESC(debug, "debug level (0-3)");
  52
  53 MODULE_DESCRIPTION("Toshiba TC358743 HDMI to CSI-2 bridge driver");
  54 MODULE_AUTHOR("Ramakrishnan Muthukrishnan <ram@rkrishnan.org>");
  55 MODULE_AUTHOR("Mikhail Khelik <mkhelik@cisco.com>");
  56 MODULE_AUTHOR("Mats Randgaard <matrandg@cisco.com>");
  57 MODULE_LICENSE("GPL");
  58
  59 #define EDID_NUM_BLOCKS_MAX 8
  60 #define EDID_BLOCK_SIZE 128
  61
  62 /* Max transfer size done by I2C transfer functions */
  63 #define MAX_XFER_SIZE  (EDID_NUM_BLOCKS_MAX * EDID_BLOCK_SIZE + 2)
  64
  65 static const struct v4l2_dv_timings_cap tc358743_timings_cap = {
  66         .type = V4L2_DV_BT_656_1120,
  67         /* keep this initialization for compatibility with GCC < 4.4.6 */
  68         .reserved = { 0 },
  69         /* Pixel clock from REF_01 p. 20. Min/max height/width are unknown */
  70         V4L2_INIT_BT_TIMINGS(1, 10000, 1, 10000, 0, 165000000,
  71                         V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
  72                         V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
  73                         V4L2_DV_BT_CAP_PROGRESSIVE |
  74                         V4L2_DV_BT_CAP_REDUCED_BLANKING |
  75                         V4L2_DV_BT_CAP_CUSTOM)
  76 };
  77
  78 struct tc358743_state {
  79         struct tc358743_platform_data pdata;
  80         struct v4l2_of_bus_mipi_csi2 bus;
  81         struct v4l2_subdev sd;
  82         struct media_pad pad;
  83         struct v4l2_ctrl_handler hdl;
  84         struct i2c_client *i2c_client;
  85         /* CONFCTL is modified in ops and tc358743_hdmi_sys_int_handler */
  86         struct mutex confctl_mutex;
  87
  88         /* controls */
  89         struct v4l2_ctrl *detect_tx_5v_ctrl;
  90         struct v4l2_ctrl *audio_sampling_rate_ctrl;
  91         struct v4l2_ctrl *audio_present_ctrl;
  92
  93         /* work queues */
  94         struct workqueue_struct *work_queues;
  95         struct delayed_work delayed_work_enable_hotplug;
  96
  97         /* edid  */
  98         u8 edid_blocks_written;
  99
 100         /* used by i2c_wr() */
 101         u8 wr_data[MAX_XFER_SIZE];
 102
 103         struct v4l2_dv_timings timings;
 104         u32 mbus_fmt_code;
 105
 106         struct gpio_desc *reset_gpio;
 107 };
 108
 109 static void tc358743_enable_interrupts(struct v4l2_subdev *sd,
 110                 bool cable_connected);
 111 static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd);
 112
 113 static inline struct tc358743_state *to_state(struct v4l2_subdev *sd)
 114 {
 115         return container_of(sd, struct tc358743_state, sd);
 116 }
 117
 118 /* --------------- I2C --------------- */
 119
 120 static void i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
 121 {
 122         struct tc358743_state *state = to_state(sd);
 123         struct i2c_client *client = state->i2c_client;
 124         int err;
 125         u8 buf[2] = { reg >> 8, reg & 0xff };
 126         struct i2c_msg msgs[] = {
 127                 {
 128                         .addr = client->addr,
 129                         .flags = 0,
 130                         .len = 2,
 131                         .buf = buf,
 132                 },
 133                 {
 134                         .addr = client->addr,
 135                         .flags = I2C_M_RD,
 136                         .len = n,
 137                         .buf = values,
 138                 },
 139         };
 140
 141         err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
 142         if (err != ARRAY_SIZE(msgs)) {
 143                 v4l2_err(sd, "%s: reading register 0x%x from 0x%x failed\n",
 144                                 __func__, reg, client->addr);
 145         }
 146 }
 147
 148 static void i2c_wr(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
 149 {
 150         struct tc358743_state *state = to_state(sd);
 151         struct i2c_client *client = state->i2c_client;
 152         u8 *data = state->wr_data;
 153         int err, i;
 154         struct i2c_msg msg;
 155
 156         if ((2 + n) > sizeof(state->wr_data))
 157                 v4l2_warn(sd, "i2c wr reg=%04x: len=%d is too big!\n",
 158                           reg, 2 + n);
 159
 160         msg.addr = client->addr;
 161         msg.buf = data;
 162         msg.len = 2 + n;
 163         msg.flags = 0;
 164
 165         data[0] = reg >> 8;
 166         data[1] = reg & 0xff;
 167
 168         for (i = 0; i < n; i++)
 169                 data[2 + i] = values[i];
 170
 171         err = i2c_transfer(client->adapter, &msg, 1);
 172         if (err != 1) {
 173                 v4l2_err(sd, "%s: writing register 0x%x from 0x%x failed\n",
 174                                 __func__, reg, client->addr);
 175                 return;
 176         }
 177
 178         if (debug < 3)
 179                 return;
 180
 181         switch (n) {
 182         case 1:
 183                 v4l2_info(sd, "I2C write 0x%04x = 0x%02x",
 184                                 reg, data[2]);
 185                 break;
 186         case 2:
 187                 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x",
 188                                 reg, data[3], data[2]);
 189                 break;
 190         case 4:
 191                 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x%02x%02x",
 192                                 reg, data[5], data[4], data[3], data[2]);
 193                 break;
 194         default:
 195                 v4l2_info(sd, "I2C write %d bytes from address 0x%04x\n",
 196                                 n, reg);
 197         }
 198 }
 199
 200 static noinline u32 i2c_rdreg(struct v4l2_subdev *sd, u16 reg, u32 n)
 201 {
 202         __le32 val = 0;
 203
 204         i2c_rd(sd, reg, (u8 __force *)&val, n);
 205
 206         return le32_to_cpu(val);
 207 }
 208
 209 static noinline void i2c_wrreg(struct v4l2_subdev *sd, u16 reg, u32 val, u32 n)
 210 {
 211         __le32 raw = cpu_to_le32(val);
 212
 213         i2c_wr(sd, reg, (u8 __force *)&raw, n);
 214 }
 215
 216 static u8 i2c_rd8(struct v4l2_subdev *sd, u16 reg)
 217 {
 218         return i2c_rdreg(sd, reg, 1);
 219 }
 220
 221 static void i2c_wr8(struct v4l2_subdev *sd, u16 reg, u8 val)
 222 {
 223         i2c_wrreg(sd, reg, val, 1);
 224 }
 225
 226 static void i2c_wr8_and_or(struct v4l2_subdev *sd, u16 reg,
 227                 u8 mask, u8 val)
 228 {
 229         i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 1) & mask) | val, 1);
 230 }
 231
 232 static u16 i2c_rd16(struct v4l2_subdev *sd, u16 reg)
 233 {
 234         return i2c_rdreg(sd, reg, 2);
 235 }
 236
 237 static void i2c_wr16(struct v4l2_subdev *sd, u16 reg, u16 val)
 238 {
 239         i2c_wrreg(sd, reg, val, 2);
 240 }
 241
 242 static void i2c_wr16_and_or(struct v4l2_subdev *sd, u16 reg, u16 mask, u16 val)
 243 {
 244         i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 1) & mask) | val, 1);
 245 }
 246
 247 static u32 i2c_rd32(struct v4l2_subdev *sd, u16 reg)
 248 {
 249         return i2c_rdreg(sd, reg, 4);
 250 }
 251
 252 static void i2c_wr32(struct v4l2_subdev *sd, u16 reg, u32 val)
 253 {
 254         i2c_wrreg(sd, reg, val, 4);
 255 }
 256
 257 /* --------------- STATUS --------------- */
 258
 259 static inline bool is_hdmi(struct v4l2_subdev *sd)
 260 {
 261         return i2c_rd8(sd, SYS_STATUS) & MASK_S_HDMI;
 262 }
 263
 264 static inline bool tx_5v_power_present(struct v4l2_subdev *sd)
 265 {
 266         return i2c_rd8(sd, SYS_STATUS) & MASK_S_DDC5V;
 267 }
 268
 269 static inline bool no_signal(struct v4l2_subdev *sd)
 270 {
 271         return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_TMDS);
 272 }
 273
 274 static inline bool no_sync(struct v4l2_subdev *sd)
 275 {
 276         return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_SYNC);
 277 }
 278
 279 static inline bool audio_present(struct v4l2_subdev *sd)
 280 {
 281         return i2c_rd8(sd, AU_STATUS0) & MASK_S_A_SAMPLE;
 282 }
 283
 284 static int get_audio_sampling_rate(struct v4l2_subdev *sd)
 285 {
 286         static const int code_to_rate[] = {
 287                 44100, 0, 48000, 32000, 22050, 384000, 24000, 352800,
 288                 88200, 768000, 96000, 705600, 176400, 0, 192000, 0
 289         };
 290
 291         /* Register FS_SET is not cleared when the cable is disconnected */
 292         if (no_signal(sd))
 293                 return 0;
 294
 295         return code_to_rate[i2c_rd8(sd, FS_SET) & MASK_FS];
 296 }
 297
 298 static unsigned tc358743_num_csi_lanes_in_use(struct v4l2_subdev *sd)
 299 {
 300         return ((i2c_rd32(sd, CSI_CONTROL) & MASK_NOL) >> 1) + 1;
 301 }
 302
 303 /* --------------- TIMINGS --------------- */
 304
 305 static inline unsigned fps(const struct v4l2_bt_timings *t)
 306 {
 307         if (!V4L2_DV_BT_FRAME_HEIGHT(t) || !V4L2_DV_BT_FRAME_WIDTH(t))
 308                 return 0;
 309
 310         return DIV_ROUND_CLOSEST((unsigned)t->pixelclock,
 311                         V4L2_DV_BT_FRAME_HEIGHT(t) * V4L2_DV_BT_FRAME_WIDTH(t));
 312 }
 313
 314 static int tc358743_get_detected_timings(struct v4l2_subdev *sd,
 315                                      struct v4l2_dv_timings *timings)
 316 {
 317         struct v4l2_bt_timings *bt = &timings->bt;
 318         unsigned width, height, frame_width, frame_height, frame_interval, fps;
 319
 320         memset(timings, 0, sizeof(struct v4l2_dv_timings));
 321
 322         if (no_signal(sd)) {
 323                 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
 324                 return -ENOLINK;
 325         }
 326         if (no_sync(sd)) {
 327                 v4l2_dbg(1, debug, sd, "%s: no sync on signal\n", __func__);
 328                 return -ENOLCK;
 329         }
 330
 331         timings->type = V4L2_DV_BT_656_1120;
 332         bt->interlaced = i2c_rd8(sd, VI_STATUS1) & MASK_S_V_INTERLACE ?
 333                 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
 334
 335         width = ((i2c_rd8(sd, DE_WIDTH_H_HI) & 0x1f) << 8) +
 336                 i2c_rd8(sd, DE_WIDTH_H_LO);
 337         height = ((i2c_rd8(sd, DE_WIDTH_V_HI) & 0x1f) << 8) +
 338                 i2c_rd8(sd, DE_WIDTH_V_LO);
 339         frame_width = ((i2c_rd8(sd, H_SIZE_HI) & 0x1f) << 8) +
 340                 i2c_rd8(sd, H_SIZE_LO);
 341         frame_height = (((i2c_rd8(sd, V_SIZE_HI) & 0x3f) << 8) +
 342                 i2c_rd8(sd, V_SIZE_LO)) / 2;
 343         /* frame interval in milliseconds * 10
 344          * Require SYS_FREQ0 and SYS_FREQ1 are precisely set */
 345         frame_interval = ((i2c_rd8(sd, FV_CNT_HI) & 0x3) << 8) +
 346                 i2c_rd8(sd, FV_CNT_LO);
 347         fps = (frame_interval > 0) ?
 348                 DIV_ROUND_CLOSEST(10000, frame_interval) : 0;
 349
 350         bt->width = width;
 351         bt->height = height;
 352         bt->vsync = frame_height - height;
 353         bt->hsync = frame_width - width;
 354         bt->pixelclock = frame_width * frame_height * fps;
 355         if (bt->interlaced == V4L2_DV_INTERLACED) {
 356                 bt->height *= 2;
 357                 bt->il_vsync = bt->vsync + 1;
 358                 bt->pixelclock /= 2;
 359         }
 360
 361         return 0;
 362 }
 363
 364 /* --------------- HOTPLUG / HDCP / EDID --------------- */
 365
 366 static void tc358743_delayed_work_enable_hotplug(struct work_struct *work)
 367 {
 368         struct delayed_work *dwork = to_delayed_work(work);
 369         struct tc358743_state *state = container_of(dwork,
 370                         struct tc358743_state, delayed_work_enable_hotplug);
 371         struct v4l2_subdev *sd = &state->sd;
 372
 373         v4l2_dbg(2, debug, sd, "%s:\n", __func__);
 374
 375         i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, MASK_HPD_OUT0);
 376 }
 377
 378 static void tc358743_set_hdmi_hdcp(struct v4l2_subdev *sd, bool enable)
 379 {
 380         v4l2_dbg(2, debug, sd, "%s: %s\n", __func__, enable ?
 381                                 "enable" : "disable");
 382
 383         i2c_wr8_and_or(sd, HDCP_REG1,
 384                         ~(MASK_AUTH_UNAUTH_SEL | MASK_AUTH_UNAUTH),
 385                         MASK_AUTH_UNAUTH_SEL_16_FRAMES | MASK_AUTH_UNAUTH_AUTO);
 386
 387         i2c_wr8_and_or(sd, HDCP_REG2, ~MASK_AUTO_P3_RESET,
 388                         SET_AUTO_P3_RESET_FRAMES(0x0f));
 389
 390         /* HDCP is disabled by configuring the receiver as HDCP repeater. The
 391          * repeater mode require software support to work, so HDCP
 392          * authentication will fail.
 393          */
 394         i2c_wr8_and_or(sd, HDCP_REG3, ~KEY_RD_CMD, enable ? KEY_RD_CMD : 0);
 395         i2c_wr8_and_or(sd, HDCP_MODE, ~(MASK_AUTO_CLR | MASK_MODE_RST_TN),
 396                         enable ?  (MASK_AUTO_CLR | MASK_MODE_RST_TN) : 0);
 397
 398         /* Apple MacBook Pro gen.8 has a bug that makes it freeze every fifth
 399          * second when HDCP is disabled, but the MAX_EXCED bit is handled
 400          * correctly and HDCP is disabled on the HDMI output.
 401          */
 402         i2c_wr8_and_or(sd, BSTATUS1, ~MASK_MAX_EXCED,
 403                         enable ? 0 : MASK_MAX_EXCED);
 404         i2c_wr8_and_or(sd, BCAPS, ~(MASK_REPEATER | MASK_READY),
 405                         enable ? 0 : MASK_REPEATER | MASK_READY);
 406 }
 407
 408 static void tc358743_disable_edid(struct v4l2_subdev *sd)
 409 {
 410         struct tc358743_state *state = to_state(sd);
 411
 412         v4l2_dbg(2, debug, sd, "%s:\n", __func__);
 413
 414         cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
 415
 416         /* DDC access to EDID is also disabled when hotplug is disabled. See
 417          * register DDC_CTL */
 418         i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, 0x0);
 419 }
 420
 421 static void tc358743_enable_edid(struct v4l2_subdev *sd)
 422 {
 423         struct tc358743_state *state = to_state(sd);
 424
 425         if (state->edid_blocks_written == 0) {
 426                 v4l2_dbg(2, debug, sd, "%s: no EDID -> no hotplug\n", __func__);
 427                 return;
 428         }
 429
 430         v4l2_dbg(2, debug, sd, "%s:\n", __func__);
 431
 432         /* Enable hotplug after 100 ms. DDC access to EDID is also enabled when
 433          * hotplug is enabled. See register DDC_CTL */
 434         queue_delayed_work(state->work_queues,
 435                            &state->delayed_work_enable_hotplug, HZ / 10);
 436
 437         tc358743_enable_interrupts(sd, true);
 438         tc358743_s_ctrl_detect_tx_5v(sd);
 439 }
 440
 441 static void tc358743_erase_bksv(struct v4l2_subdev *sd)
 442 {
 443         int i;
 444
 445         for (i = 0; i < 5; i++)
 446                 i2c_wr8(sd, BKSV + i, 0);
 447 }
 448
 449 /* --------------- AVI infoframe --------------- */
 450
 451 static void print_avi_infoframe(struct v4l2_subdev *sd)
 452 {
 453         struct i2c_client *client = v4l2_get_subdevdata(sd);
 454         struct device *dev = &client->dev;
 455         union hdmi_infoframe frame;
 456         u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
 457
 458         if (!is_hdmi(sd)) {
 459                 v4l2_info(sd, "DVI-D signal - AVI infoframe not supported\n");
 460                 return;
 461         }
 462
 463         i2c_rd(sd, PK_AVI_0HEAD, buffer, HDMI_INFOFRAME_SIZE(AVI));
 464
 465         if (hdmi_infoframe_unpack(&frame, buffer) < 0) {
 466                 v4l2_err(sd, "%s: unpack of AVI infoframe failed\n", __func__);
 467                 return;
 468         }
 469
 470         hdmi_infoframe_log(KERN_INFO, dev, &frame);
 471 }
 472
 473 /* --------------- CTRLS --------------- */
 474
 475 static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd)
 476 {
 477         struct tc358743_state *state = to_state(sd);
 478
 479         return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
 480                         tx_5v_power_present(sd));
 481 }
 482
 483 static int tc358743_s_ctrl_audio_sampling_rate(struct v4l2_subdev *sd)
 484 {
 485         struct tc358743_state *state = to_state(sd);
 486
 487         return v4l2_ctrl_s_ctrl(state->audio_sampling_rate_ctrl,
 488                         get_audio_sampling_rate(sd));
 489 }
 490
 491 static int tc358743_s_ctrl_audio_present(struct v4l2_subdev *sd)
 492 {
 493         struct tc358743_state *state = to_state(sd);
 494
 495         return v4l2_ctrl_s_ctrl(state->audio_present_ctrl,
 496                         audio_present(sd));
 497 }
 498
 499 static int tc358743_update_controls(struct v4l2_subdev *sd)
 500 {
 501         int ret = 0;
 502
 503         ret |= tc358743_s_ctrl_detect_tx_5v(sd);
 504         ret |= tc358743_s_ctrl_audio_sampling_rate(sd);
 505         ret |= tc358743_s_ctrl_audio_present(sd);
 506
 507         return ret;
 508 }
 509
 510 /* --------------- INIT --------------- */
 511
 512 static void tc358743_reset_phy(struct v4l2_subdev *sd)
 513 {
 514         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
 515
 516         i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, 0);
 517         i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, MASK_RESET_CTRL);
 518 }
 519
 520 static void tc358743_reset(struct v4l2_subdev *sd, uint16_t mask)
 521 {
 522         u16 sysctl = i2c_rd16(sd, SYSCTL);
 523
 524         i2c_wr16(sd, SYSCTL, sysctl | mask);
 525         i2c_wr16(sd, SYSCTL, sysctl & ~mask);
 526 }
 527
 528 static inline void tc358743_sleep_mode(struct v4l2_subdev *sd, bool enable)
 529 {
 530         i2c_wr16_and_or(sd, SYSCTL, ~MASK_SLEEP,
 531                         enable ? MASK_SLEEP : 0);
 532 }
 533
 534 static inline void enable_stream(struct v4l2_subdev *sd, bool enable)
 535 {
 536         struct tc358743_state *state = to_state(sd);
 537
 538         v4l2_dbg(3, debug, sd, "%s: %sable\n",
 539                         __func__, enable ? "en" : "dis");
 540
 541         if (enable) {
 542                 /* It is critical for CSI receiver to see lane transition
 543                  * LP11->HS. Set to non-continuous mode to enable clock lane
 544                  * LP11 state. */
 545                 i2c_wr32(sd, TXOPTIONCNTRL, 0);
 546                 /* Set to continuous mode to trigger LP11->HS transition */
 547                 i2c_wr32(sd, TXOPTIONCNTRL, MASK_CONTCLKMODE);
 548                 /* Unmute video */
 549                 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE);
 550         } else {
 551                 /* Mute video so that all data lanes go to LSP11 state.
 552                  * No data is output to CSI Tx block. */
 553                 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE | MASK_VI_MUTE);
 554         }
 555
 556         mutex_lock(&state->confctl_mutex);
 557         i2c_wr16_and_or(sd, CONFCTL, ~(MASK_VBUFEN | MASK_ABUFEN),
 558                         enable ? (MASK_VBUFEN | MASK_ABUFEN) : 0x0);
 559         mutex_unlock(&state->confctl_mutex);
 560 }
 561
 562 static void tc358743_set_pll(struct v4l2_subdev *sd)
 563 {
 564         struct tc358743_state *state = to_state(sd);
 565         struct tc358743_platform_data *pdata = &state->pdata;
 566         u16 pllctl0 = i2c_rd16(sd, PLLCTL0);
 567         u16 pllctl1 = i2c_rd16(sd, PLLCTL1);
 568         u16 pllctl0_new = SET_PLL_PRD(pdata->pll_prd) |
 569                 SET_PLL_FBD(pdata->pll_fbd);
 570         u32 hsck = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd;
 571
 572         v4l2_dbg(2, debug, sd, "%s:\n", __func__);
 573
 574         /* Only rewrite when needed (new value or disabled), since rewriting
 575          * triggers another format change event. */
 576         if ((pllctl0 != pllctl0_new) || ((pllctl1 & MASK_PLL_EN) == 0)) {
 577                 u16 pll_frs;
 578
 579                 if (hsck > 500000000)
 580                         pll_frs = 0x0;
 581                 else if (hsck > 250000000)
 582                         pll_frs = 0x1;
 583                 else if (hsck > 125000000)
 584                         pll_frs = 0x2;
 585                 else
 586                         pll_frs = 0x3;
 587
 588                 v4l2_dbg(1, debug, sd, "%s: updating PLL clock\n", __func__);
 589                 tc358743_sleep_mode(sd, true);
 590                 i2c_wr16(sd, PLLCTL0, pllctl0_new);
 591                 i2c_wr16_and_or(sd, PLLCTL1,
 592                                 ~(MASK_PLL_FRS | MASK_RESETB | MASK_PLL_EN),
 593                                 (SET_PLL_FRS(pll_frs) | MASK_RESETB |
 594                                  MASK_PLL_EN));
 595                 udelay(10); /* REF_02, Sheet "Source HDMI" */
 596                 i2c_wr16_and_or(sd, PLLCTL1, ~MASK_CKEN, MASK_CKEN);
 597                 tc358743_sleep_mode(sd, false);
 598         }
 599 }
 600
 601 static void tc358743_set_ref_clk(struct v4l2_subdev *sd)
 602 {
 603         struct tc358743_state *state = to_state(sd);
 604         struct tc358743_platform_data *pdata = &state->pdata;
 605         u32 sys_freq;
 606         u32 lockdet_ref;
 607         u16 fh_min;
 608         u16 fh_max;
 609
 610         BUG_ON(!(pdata->refclk_hz == 26000000 ||
 611                  pdata->refclk_hz == 27000000 ||
 612                  pdata->refclk_hz == 42000000));
 613
 614         sys_freq = pdata->refclk_hz / 10000;
 615         i2c_wr8(sd, SYS_FREQ0, sys_freq & 0x00ff);
 616         i2c_wr8(sd, SYS_FREQ1, (sys_freq & 0xff00) >> 8);
 617
 618         i2c_wr8_and_or(sd, PHY_CTL0, ~MASK_PHY_SYSCLK_IND,
 619                         (pdata->refclk_hz == 42000000) ?
 620                         MASK_PHY_SYSCLK_IND : 0x0);
 621
 622         fh_min = pdata->refclk_hz / 100000;
 623         i2c_wr8(sd, FH_MIN0, fh_min & 0x00ff);
 624         i2c_wr8(sd, FH_MIN1, (fh_min & 0xff00) >> 8);
 625
 626         fh_max = (fh_min * 66) / 10;
 627         i2c_wr8(sd, FH_MAX0, fh_max & 0x00ff);
 628         i2c_wr8(sd, FH_MAX1, (fh_max & 0xff00) >> 8);
 629
 630         lockdet_ref = pdata->refclk_hz / 100;
 631         i2c_wr8(sd, LOCKDET_REF0, lockdet_ref & 0x0000ff);
 632         i2c_wr8(sd, LOCKDET_REF1, (lockdet_ref & 0x00ff00) >> 8);
 633         i2c_wr8(sd, LOCKDET_REF2, (lockdet_ref & 0x0f0000) >> 16);
 634
 635         i2c_wr8_and_or(sd, NCO_F0_MOD, ~MASK_NCO_F0_MOD,
 636                         (pdata->refclk_hz == 27000000) ?
 637                         MASK_NCO_F0_MOD_27MHZ : 0x0);
 638 }
 639
 640 static void tc358743_set_csi_color_space(struct v4l2_subdev *sd)
 641 {
 642         struct tc358743_state *state = to_state(sd);
 643
 644         switch (state->mbus_fmt_code) {
 645         case MEDIA_BUS_FMT_UYVY8_1X16:
 646                 v4l2_dbg(2, debug, sd, "%s: YCbCr 422 16-bit\n", __func__);
 647                 i2c_wr8_and_or(sd, VOUT_SET2,
 648                                 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff,
 649                                 MASK_SEL422 | MASK_VOUT_422FIL_100);
 650                 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff,
 651                                 MASK_VOUT_COLOR_601_YCBCR_LIMITED);
 652                 mutex_lock(&state->confctl_mutex);
 653                 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT,
 654                                 MASK_YCBCRFMT_422_8_BIT);
 655                 mutex_unlock(&state->confctl_mutex);
 656                 break;
 657         case MEDIA_BUS_FMT_RGB888_1X24:
 658                 v4l2_dbg(2, debug, sd, "%s: RGB 888 24-bit\n", __func__);
 659                 i2c_wr8_and_or(sd, VOUT_SET2,
 660                                 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff,
 661                                 0x00);
 662                 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff,
 663                                 MASK_VOUT_COLOR_RGB_FULL);
 664                 mutex_lock(&state->confctl_mutex);
 665                 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT, 0);
 666                 mutex_unlock(&state->confctl_mutex);
 667                 break;
 668         default:
 669                 v4l2_dbg(2, debug, sd, "%s: Unsupported format code 0x%x\n",
 670                                 __func__, state->mbus_fmt_code);
 671         }
 672 }
 673
 674 static unsigned tc358743_num_csi_lanes_needed(struct v4l2_subdev *sd)
 675 {
 676         struct tc358743_state *state = to_state(sd);
 677         struct v4l2_bt_timings *bt = &state->timings.bt;
 678         struct tc358743_platform_data *pdata = &state->pdata;
 679         u32 bits_pr_pixel =
 680                 (state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16) ?  16 : 24;
 681         u32 bps = bt->width * bt->height * fps(bt) * bits_pr_pixel;
 682         u32 bps_pr_lane = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd;
 683
 684         return DIV_ROUND_UP(bps, bps_pr_lane);
 685 }
 686
 687 static void tc358743_set_csi(struct v4l2_subdev *sd)
 688 {
 689         struct tc358743_state *state = to_state(sd);
 690         struct tc358743_platform_data *pdata = &state->pdata;
 691         unsigned lanes = tc358743_num_csi_lanes_needed(sd);
 692
 693         v4l2_dbg(3, debug, sd, "%s:\n", __func__);
 694
 695         tc358743_reset(sd, MASK_CTXRST);
 696
 697         if (lanes < 1)
 698                 i2c_wr32(sd, CLW_CNTRL, MASK_CLW_LANEDISABLE);
 699         if (lanes < 1)
 700                 i2c_wr32(sd, D0W_CNTRL, MASK_D0W_LANEDISABLE);
 701         if (lanes < 2)
 702                 i2c_wr32(sd, D1W_CNTRL, MASK_D1W_LANEDISABLE);
 703         if (lanes < 3)
 704                 i2c_wr32(sd, D2W_CNTRL, MASK_D2W_LANEDISABLE);
 705         if (lanes < 4)
 706                 i2c_wr32(sd, D3W_CNTRL, MASK_D3W_LANEDISABLE);
 707
 708         i2c_wr32(sd, LINEINITCNT, pdata->lineinitcnt);
 709         i2c_wr32(sd, LPTXTIMECNT, pdata->lptxtimecnt);
 710         i2c_wr32(sd, TCLK_HEADERCNT, pdata->tclk_headercnt);
 711         i2c_wr32(sd, TCLK_TRAILCNT, pdata->tclk_trailcnt);
 712         i2c_wr32(sd, THS_HEADERCNT, pdata->ths_headercnt);
 713         i2c_wr32(sd, TWAKEUP, pdata->twakeup);
 714         i2c_wr32(sd, TCLK_POSTCNT, pdata->tclk_postcnt);
 715         i2c_wr32(sd, THS_TRAILCNT, pdata->ths_trailcnt);
 716         i2c_wr32(sd, HSTXVREGCNT, pdata->hstxvregcnt);
 717
 718         i2c_wr32(sd, HSTXVREGEN,
 719                         ((lanes > 0) ? MASK_CLM_HSTXVREGEN : 0x0) |
 720                         ((lanes > 0) ? MASK_D0M_HSTXVREGEN : 0x0) |
 721                         ((lanes > 1) ? MASK_D1M_HSTXVREGEN : 0x0) |
 722                         ((lanes > 2) ? MASK_D2M_HSTXVREGEN : 0x0) |
 723                         ((lanes > 3) ? MASK_D3M_HSTXVREGEN : 0x0));
 724
 725         i2c_wr32(sd, TXOPTIONCNTRL, (state->bus.flags &
 726                  V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) ? MASK_CONTCLKMODE : 0);
 727         i2c_wr32(sd, STARTCNTRL, MASK_START);
 728         i2c_wr32(sd, CSI_START, MASK_STRT);
 729
 730         i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
 731                         MASK_ADDRESS_CSI_CONTROL |
 732                         MASK_CSI_MODE |
 733                         MASK_TXHSMD |
 734                         ((lanes == 4) ? MASK_NOL_4 :
 735                          (lanes == 3) ? MASK_NOL_3 :
 736                          (lanes == 2) ? MASK_NOL_2 : MASK_NOL_1));
 737
 738         i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
 739                         MASK_ADDRESS_CSI_ERR_INTENA | MASK_TXBRK | MASK_QUNK |
 740                         MASK_WCER | MASK_INER);
 741
 742         i2c_wr32(sd, CSI_CONFW, MASK_MODE_CLEAR |
 743                         MASK_ADDRESS_CSI_ERR_HALT | MASK_TXBRK | MASK_QUNK);
 744
 745         i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
 746                         MASK_ADDRESS_CSI_INT_ENA | MASK_INTER);
 747 }
 748
 749 static void tc358743_set_hdmi_phy(struct v4l2_subdev *sd)
 750 {
 751         struct tc358743_state *state = to_state(sd);
 752         struct tc358743_platform_data *pdata = &state->pdata;
 753
 754         /* Default settings from REF_02, sheet "Source HDMI"
 755          * and custom settings as platform data */
 756         i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, 0x0);
 757         i2c_wr8(sd, PHY_CTL1, SET_PHY_AUTO_RST1_US(1600) |
 758                         SET_FREQ_RANGE_MODE_CYCLES(1));
 759         i2c_wr8_and_or(sd, PHY_CTL2, ~MASK_PHY_AUTO_RSTn,
 760                         (pdata->hdmi_phy_auto_reset_tmds_detected ?
 761                          MASK_PHY_AUTO_RST2 : 0) |
 762                         (pdata->hdmi_phy_auto_reset_tmds_in_range ?
 763                          MASK_PHY_AUTO_RST3 : 0) |
 764                         (pdata->hdmi_phy_auto_reset_tmds_valid ?
 765                          MASK_PHY_AUTO_RST4 : 0));
 766         i2c_wr8(sd, PHY_BIAS, 0x40);
 767         i2c_wr8(sd, PHY_CSQ, SET_CSQ_CNT_LEVEL(0x0a));
 768         i2c_wr8(sd, AVM_CTL, 45);
 769         i2c_wr8_and_or(sd, HDMI_DET, ~MASK_HDMI_DET_V,
 770                         pdata->hdmi_detection_delay << 4);
 771         i2c_wr8_and_or(sd, HV_RST, ~(MASK_H_PI_RST | MASK_V_PI_RST),
 772                         (pdata->hdmi_phy_auto_reset_hsync_out_of_range ?
 773                          MASK_H_PI_RST : 0) |
 774                         (pdata->hdmi_phy_auto_reset_vsync_out_of_range ?
 775                          MASK_V_PI_RST : 0));
 776         i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, MASK_ENABLE_PHY);
 777 }
 778
 779 static void tc358743_set_hdmi_audio(struct v4l2_subdev *sd)
 780 {
 781         struct tc358743_state *state = to_state(sd);
 782
 783         /* Default settings from REF_02, sheet "Source HDMI" */
 784         i2c_wr8(sd, FORCE_MUTE, 0x00);
 785         i2c_wr8(sd, AUTO_CMD0, MASK_AUTO_MUTE7 | MASK_AUTO_MUTE6 |
 786                         MASK_AUTO_MUTE5 | MASK_AUTO_MUTE4 |
 787                         MASK_AUTO_MUTE1 | MASK_AUTO_MUTE0);
 788         i2c_wr8(sd, AUTO_CMD1, MASK_AUTO_MUTE9);
 789         i2c_wr8(sd, AUTO_CMD2, MASK_AUTO_PLAY3 | MASK_AUTO_PLAY2);
 790         i2c_wr8(sd, BUFINIT_START, SET_BUFINIT_START_MS(500));
 791         i2c_wr8(sd, FS_MUTE, 0x00);
 792         i2c_wr8(sd, FS_IMODE, MASK_NLPCM_SMODE | MASK_FS_SMODE);
 793         i2c_wr8(sd, ACR_MODE, MASK_CTS_MODE);
 794         i2c_wr8(sd, ACR_MDF0, MASK_ACR_L2MDF_1976_PPM | MASK_ACR_L1MDF_976_PPM);
 795         i2c_wr8(sd, ACR_MDF1, MASK_ACR_L3MDF_3906_PPM);
 796         i2c_wr8(sd, SDO_MODE1, MASK_SDO_FMT_I2S);
 797         i2c_wr8(sd, DIV_MODE, SET_DIV_DLY_MS(100));
 798
 799         mutex_lock(&state->confctl_mutex);
 800         i2c_wr16_and_or(sd, CONFCTL, 0xffff, MASK_AUDCHNUM_2 |
 801                         MASK_AUDOUTSEL_I2S | MASK_AUTOINDEX);
 802         mutex_unlock(&state->confctl_mutex);
 803 }
 804
 805 static void tc358743_set_hdmi_info_frame_mode(struct v4l2_subdev *sd)
 806 {
 807         /* Default settings from REF_02, sheet "Source HDMI" */
 808         i2c_wr8(sd, PK_INT_MODE, MASK_ISRC2_INT_MODE | MASK_ISRC_INT_MODE |
 809                         MASK_ACP_INT_MODE | MASK_VS_INT_MODE |
 810                         MASK_SPD_INT_MODE | MASK_MS_INT_MODE |
 811                         MASK_AUD_INT_MODE | MASK_AVI_INT_MODE);
 812         i2c_wr8(sd, NO_PKT_LIMIT, 0x2c);
 813         i2c_wr8(sd, NO_PKT_CLR, 0x53);
 814         i2c_wr8(sd, ERR_PK_LIMIT, 0x01);
 815         i2c_wr8(sd, NO_PKT_LIMIT2, 0x30);
 816         i2c_wr8(sd, NO_GDB_LIMIT, 0x10);
 817 }
 818
 819 static void tc358743_initial_setup(struct v4l2_subdev *sd)
 820 {
 821         struct tc358743_state *state = to_state(sd);
 822         struct tc358743_platform_data *pdata = &state->pdata;
 823
 824         /* CEC and IR are not supported by this driver */
 825         i2c_wr16_and_or(sd, SYSCTL, ~(MASK_CECRST | MASK_IRRST),
 826                         (MASK_CECRST | MASK_IRRST));
 827
 828         tc358743_reset(sd, MASK_CTXRST | MASK_HDMIRST);
 829         tc358743_sleep_mode(sd, false);
 830
 831         i2c_wr16(sd, FIFOCTL, pdata->fifo_level);
 832
 833         tc358743_set_ref_clk(sd);
 834
 835         i2c_wr8_and_or(sd, DDC_CTL, ~MASK_DDC5V_MODE,
 836                         pdata->ddc5v_delay & MASK_DDC5V_MODE);
 837         i2c_wr8_and_or(sd, EDID_MODE, ~MASK_EDID_MODE, MASK_EDID_MODE_E_DDC);
 838
 839         tc358743_set_hdmi_phy(sd);
 840         tc358743_set_hdmi_hdcp(sd, pdata->enable_hdcp);
 841         tc358743_set_hdmi_audio(sd);
 842         tc358743_set_hdmi_info_frame_mode(sd);
 843
 844         /* All CE and IT formats are detected as RGB full range in DVI mode */
 845         i2c_wr8_and_or(sd, VI_MODE, ~MASK_RGB_DVI, 0);
 846
 847         i2c_wr8_and_or(sd, VOUT_SET2, ~MASK_VOUTCOLORMODE,
 848                         MASK_VOUTCOLORMODE_AUTO);
 849         i2c_wr8(sd, VOUT_SET3, MASK_VOUT_EXTCNT);
 850 }
 851
 852 /* --------------- IRQ --------------- */
 853
 854 static void tc358743_format_change(struct v4l2_subdev *sd)
 855 {
 856         struct tc358743_state *state = to_state(sd);
 857         struct v4l2_dv_timings timings;
 858         const struct v4l2_event tc358743_ev_fmt = {
 859                 .type = V4L2_EVENT_SOURCE_CHANGE,
 860                 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
 861         };
 862
 863         if (tc358743_get_detected_timings(sd, &timings)) {
 864                 enable_stream(sd, false);
 865
 866                 v4l2_dbg(1, debug, sd, "%s: Format changed. No signal\n",
 867                                 __func__);
 868         } else {
 869                 if (!v4l2_match_dv_timings(&state->timings, &timings, 0))
 870                         enable_stream(sd, false);
 871
 872                 v4l2_print_dv_timings(sd->name,
 873                                 "tc358743_format_change: Format changed. New format: ",
 874                                 &timings, false);
 875         }
 876
 877         if (sd->devnode)
 878                 v4l2_subdev_notify_event(sd, &tc358743_ev_fmt);
 879 }
 880
 881 static void tc358743_init_interrupts(struct v4l2_subdev *sd)
 882 {
 883         u16 i;
 884
 885         /* clear interrupt status registers */
 886         for (i = SYS_INT; i <= KEY_INT; i++)
 887                 i2c_wr8(sd, i, 0xff);
 888
 889         i2c_wr16(sd, INTSTATUS, 0xffff);
 890 }
 891
 892 static void tc358743_enable_interrupts(struct v4l2_subdev *sd,
 893                 bool cable_connected)
 894 {
 895         v4l2_dbg(2, debug, sd, "%s: cable connected = %d\n", __func__,
 896                         cable_connected);
 897
 898         if (cable_connected) {
 899                 i2c_wr8(sd, SYS_INTM, ~(MASK_M_DDC | MASK_M_DVI_DET |
 900                                         MASK_M_HDMI_DET) & 0xff);
 901                 i2c_wr8(sd, CLK_INTM, ~MASK_M_IN_DE_CHG);
 902                 i2c_wr8(sd, CBIT_INTM, ~(MASK_M_CBIT_FS | MASK_M_AF_LOCK |
 903                                         MASK_M_AF_UNLOCK) & 0xff);
 904                 i2c_wr8(sd, AUDIO_INTM, ~MASK_M_BUFINIT_END);
 905                 i2c_wr8(sd, MISC_INTM, ~MASK_M_SYNC_CHG);
 906         } else {
 907                 i2c_wr8(sd, SYS_INTM, ~MASK_M_DDC & 0xff);
 908                 i2c_wr8(sd, CLK_INTM, 0xff);
 909                 i2c_wr8(sd, CBIT_INTM, 0xff);
 910                 i2c_wr8(sd, AUDIO_INTM, 0xff);
 911                 i2c_wr8(sd, MISC_INTM, 0xff);
 912         }
 913 }
 914
 915 static void tc358743_hdmi_audio_int_handler(struct v4l2_subdev *sd,
 916                 bool *handled)
 917 {
 918         u8 audio_int_mask = i2c_rd8(sd, AUDIO_INTM);
 919         u8 audio_int = i2c_rd8(sd, AUDIO_INT) & ~audio_int_mask;
 920
 921         i2c_wr8(sd, AUDIO_INT, audio_int);
 922
 923         v4l2_dbg(3, debug, sd, "%s: AUDIO_INT = 0x%02x\n", __func__, audio_int);
 924
 925         tc358743_s_ctrl_audio_sampling_rate(sd);
 926         tc358743_s_ctrl_audio_present(sd);
 927 }
 928
 929 static void tc358743_csi_err_int_handler(struct v4l2_subdev *sd, bool *handled)
 930 {
 931         v4l2_err(sd, "%s: CSI_ERR = 0x%x\n", __func__, i2c_rd32(sd, CSI_ERR));
 932
 933         i2c_wr32(sd, CSI_INT_CLR, MASK_ICRER);
 934 }
 935
 936 static void tc358743_hdmi_misc_int_handler(struct v4l2_subdev *sd,
 937                 bool *handled)
 938 {
 939         u8 misc_int_mask = i2c_rd8(sd, MISC_INTM);
 940         u8 misc_int = i2c_rd8(sd, MISC_INT) & ~misc_int_mask;
 941
 942         i2c_wr8(sd, MISC_INT, misc_int);
 943
 944         v4l2_dbg(3, debug, sd, "%s: MISC_INT = 0x%02x\n", __func__, misc_int);
 945
 946         if (misc_int & MASK_I_SYNC_CHG) {
 947                 /* Reset the HDMI PHY to try to trigger proper lock on the
 948                  * incoming video format. Erase BKSV to prevent that old keys
 949                  * are used when a new source is connected. */
 950                 if (no_sync(sd) || no_signal(sd)) {
 951                         tc358743_reset_phy(sd);
 952                         tc358743_erase_bksv(sd);
 953                 }
 954
 955                 tc358743_format_change(sd);
 956
 957                 misc_int &= ~MASK_I_SYNC_CHG;
 958                 if (handled)
 959                         *handled = true;
 960         }
 961
 962         if (misc_int) {
 963                 v4l2_err(sd, "%s: Unhandled MISC_INT interrupts: 0x%02x\n",
 964                                 __func__, misc_int);
 965         }
 966 }
 967
 968 static void tc358743_hdmi_cbit_int_handler(struct v4l2_subdev *sd,
 969                 bool *handled)
 970 {
 971         u8 cbit_int_mask = i2c_rd8(sd, CBIT_INTM);
 972         u8 cbit_int = i2c_rd8(sd, CBIT_INT) & ~cbit_int_mask;
 973
 974         i2c_wr8(sd, CBIT_INT, cbit_int);
 975
 976         v4l2_dbg(3, debug, sd, "%s: CBIT_INT = 0x%02x\n", __func__, cbit_int);
 977
 978         if (cbit_int & MASK_I_CBIT_FS) {
 979
 980                 v4l2_dbg(1, debug, sd, "%s: Audio sample rate changed\n",
 981                                 __func__);
 982                 tc358743_s_ctrl_audio_sampling_rate(sd);
 983
 984                 cbit_int &= ~MASK_I_CBIT_FS;
 985                 if (handled)
 986                         *handled = true;
 987         }
 988
 989         if (cbit_int & (MASK_I_AF_LOCK | MASK_I_AF_UNLOCK)) {
 990
 991                 v4l2_dbg(1, debug, sd, "%s: Audio present changed\n",
 992                                 __func__);
 993                 tc358743_s_ctrl_audio_present(sd);
 994
 995                 cbit_int &= ~(MASK_I_AF_LOCK | MASK_I_AF_UNLOCK);
 996                 if (handled)
 997                         *handled = true;
 998         }
 999
1000         if (cbit_int) {
1001                 v4l2_err(sd, "%s: Unhandled CBIT_INT interrupts: 0x%02x\n",
1002                                 __func__, cbit_int);
1003         }
1004 }
1005
1006 static void tc358743_hdmi_clk_int_handler(struct v4l2_subdev *sd, bool *handled)
1007 {
1008         u8 clk_int_mask = i2c_rd8(sd, CLK_INTM);
1009         u8 clk_int = i2c_rd8(sd, CLK_INT) & ~clk_int_mask;
1010
1011         /* Bit 7 and bit 6 are set even when they are masked */
1012         i2c_wr8(sd, CLK_INT, clk_int | 0x80 | MASK_I_OUT_H_CHG);
1013
1014         v4l2_dbg(3, debug, sd, "%s: CLK_INT = 0x%02x\n", __func__, clk_int);
1015
1016         if (clk_int & (MASK_I_IN_DE_CHG)) {
1017
1018                 v4l2_dbg(1, debug, sd, "%s: DE size or position has changed\n",
1019                                 __func__);
1020
1021                 /* If the source switch to a new resolution with the same pixel
1022                  * frequency as the existing (e.g. 1080p25 -> 720p50), the
1023                  * I_SYNC_CHG interrupt is not always triggered, while the
1024                  * I_IN_DE_CHG interrupt seems to work fine. Format change
1025                  * notifications are only sent when the signal is stable to
1026                  * reduce the number of notifications. */
1027                 if (!no_signal(sd) && !no_sync(sd))
1028                         tc358743_format_change(sd);
1029
1030                 clk_int &= ~(MASK_I_IN_DE_CHG);
1031                 if (handled)
1032                         *handled = true;
1033         }
1034
1035         if (clk_int) {
1036                 v4l2_err(sd, "%s: Unhandled CLK_INT interrupts: 0x%02x\n",
1037                                 __func__, clk_int);
1038         }
1039 }
1040
1041 static void tc358743_hdmi_sys_int_handler(struct v4l2_subdev *sd, bool *handled)
1042 {
1043         struct tc358743_state *state = to_state(sd);
1044         u8 sys_int_mask = i2c_rd8(sd, SYS_INTM);
1045         u8 sys_int = i2c_rd8(sd, SYS_INT) & ~sys_int_mask;
1046
1047         i2c_wr8(sd, SYS_INT, sys_int);
1048
1049         v4l2_dbg(3, debug, sd, "%s: SYS_INT = 0x%02x\n", __func__, sys_int);
1050
1051         if (sys_int & MASK_I_DDC) {
1052                 bool tx_5v = tx_5v_power_present(sd);
1053
1054                 v4l2_dbg(1, debug, sd, "%s: Tx 5V power present: %s\n",
1055                                 __func__, tx_5v ?  "yes" : "no");
1056
1057                 if (tx_5v) {
1058                         tc358743_enable_edid(sd);
1059                 } else {
1060                         tc358743_enable_interrupts(sd, false);
1061                         tc358743_disable_edid(sd);
1062                         memset(&state->timings, 0, sizeof(state->timings));
1063                         tc358743_erase_bksv(sd);
1064                         tc358743_update_controls(sd);
1065                 }
1066
1067                 sys_int &= ~MASK_I_DDC;
1068                 if (handled)
1069                         *handled = true;
1070         }
1071
1072         if (sys_int & MASK_I_DVI) {
1073                 v4l2_dbg(1, debug, sd, "%s: HDMI->DVI change detected\n",
1074                                 __func__);
1075
1076                 /* Reset the HDMI PHY to try to trigger proper lock on the
1077                  * incoming video format. Erase BKSV to prevent that old keys
1078                  * are used when a new source is connected. */
1079                 if (no_sync(sd) || no_signal(sd)) {
1080                         tc358743_reset_phy(sd);
1081                         tc358743_erase_bksv(sd);
1082                 }
1083
1084                 sys_int &= ~MASK_I_DVI;
1085                 if (handled)
1086                         *handled = true;
1087         }
1088
1089         if (sys_int & MASK_I_HDMI) {
1090                 v4l2_dbg(1, debug, sd, "%s: DVI->HDMI change detected\n",
1091                                 __func__);
1092
1093                 /* Register is reset in DVI mode (REF_01, c. 6.6.41) */
1094                 i2c_wr8(sd, ANA_CTL, MASK_APPL_PCSX_NORMAL | MASK_ANALOG_ON);
1095
1096                 sys_int &= ~MASK_I_HDMI;
1097                 if (handled)
1098                         *handled = true;
1099         }
1100
1101         if (sys_int) {
1102                 v4l2_err(sd, "%s: Unhandled SYS_INT interrupts: 0x%02x\n",
1103                                 __func__, sys_int);
1104         }
1105 }
1106
1107 /* --------------- CORE OPS --------------- */
1108
1109 static int tc358743_log_status(struct v4l2_subdev *sd)
1110 {
1111         struct tc358743_state *state = to_state(sd);
1112         struct v4l2_dv_timings timings;
1113         uint8_t hdmi_sys_status =  i2c_rd8(sd, SYS_STATUS);
1114         uint16_t sysctl = i2c_rd16(sd, SYSCTL);
1115         u8 vi_status3 =  i2c_rd8(sd, VI_STATUS3);
1116         const int deep_color_mode[4] = { 8, 10, 12, 16 };
1117         static const char * const input_color_space[] = {
1118                 "RGB", "YCbCr 601", "Adobe RGB", "YCbCr 709", "NA (4)",
1119                 "xvYCC 601", "NA(6)", "xvYCC 709", "NA(8)", "sYCC601",
1120                 "NA(10)", "NA(11)", "NA(12)", "Adobe YCC 601"};
1121
1122         v4l2_info(sd, "-----Chip status-----\n");
1123         v4l2_info(sd, "Chip ID: 0x%02x\n",
1124                         (i2c_rd16(sd, CHIPID) & MASK_CHIPID) >> 8);
1125         v4l2_info(sd, "Chip revision: 0x%02x\n",
1126                         i2c_rd16(sd, CHIPID) & MASK_REVID);
1127         v4l2_info(sd, "Reset: IR: %d, CEC: %d, CSI TX: %d, HDMI: %d\n",
1128                         !!(sysctl & MASK_IRRST),
1129                         !!(sysctl & MASK_CECRST),
1130                         !!(sysctl & MASK_CTXRST),
1131                         !!(sysctl & MASK_HDMIRST));
1132         v4l2_info(sd, "Sleep mode: %s\n", sysctl & MASK_SLEEP ? "on" : "off");
1133         v4l2_info(sd, "Cable detected (+5V power): %s\n",
1134                         hdmi_sys_status & MASK_S_DDC5V ? "yes" : "no");
1135         v4l2_info(sd, "DDC lines enabled: %s\n",
1136                         (i2c_rd8(sd, EDID_MODE) & MASK_EDID_MODE_E_DDC) ?
1137                         "yes" : "no");
1138         v4l2_info(sd, "Hotplug enabled: %s\n",
1139                         (i2c_rd8(sd, HPD_CTL) & MASK_HPD_OUT0) ?
1140                         "yes" : "no");
1141         v4l2_info(sd, "CEC enabled: %s\n",
1142                         (i2c_rd16(sd, CECEN) & MASK_CECEN) ?  "yes" : "no");
1143         v4l2_info(sd, "-----Signal status-----\n");
1144         v4l2_info(sd, "TMDS signal detected: %s\n",
1145                         hdmi_sys_status & MASK_S_TMDS ? "yes" : "no");
1146         v4l2_info(sd, "Stable sync signal: %s\n",
1147                         hdmi_sys_status & MASK_S_SYNC ? "yes" : "no");
1148         v4l2_info(sd, "PHY PLL locked: %s\n",
1149                         hdmi_sys_status & MASK_S_PHY_PLL ? "yes" : "no");
1150         v4l2_info(sd, "PHY DE detected: %s\n",
1151                         hdmi_sys_status & MASK_S_PHY_SCDT ? "yes" : "no");
1152
1153         if (tc358743_get_detected_timings(sd, &timings)) {
1154                 v4l2_info(sd, "No video detected\n");
1155         } else {
1156                 v4l2_print_dv_timings(sd->name, "Detected format: ", &timings,
1157                                 true);
1158         }
1159         v4l2_print_dv_timings(sd->name, "Configured format: ", &state->timings,
1160                         true);
1161
1162         v4l2_info(sd, "-----CSI-TX status-----\n");
1163         v4l2_info(sd, "Lanes needed: %d\n",
1164                         tc358743_num_csi_lanes_needed(sd));
1165         v4l2_info(sd, "Lanes in use: %d\n",
1166                         tc358743_num_csi_lanes_in_use(sd));
1167         v4l2_info(sd, "Waiting for particular sync signal: %s\n",
1168                         (i2c_rd16(sd, CSI_STATUS) & MASK_S_WSYNC) ?
1169                         "yes" : "no");
1170         v4l2_info(sd, "Transmit mode: %s\n",
1171                         (i2c_rd16(sd, CSI_STATUS) & MASK_S_TXACT) ?
1172                         "yes" : "no");
1173         v4l2_info(sd, "Receive mode: %s\n",
1174                         (i2c_rd16(sd, CSI_STATUS) & MASK_S_RXACT) ?
1175                         "yes" : "no");
1176         v4l2_info(sd, "Stopped: %s\n",
1177                         (i2c_rd16(sd, CSI_STATUS) & MASK_S_HLT) ?
1178                         "yes" : "no");
1179         v4l2_info(sd, "Color space: %s\n",
1180                         state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16 ?
1181                         "YCbCr 422 16-bit" :
1182                         state->mbus_fmt_code == MEDIA_BUS_FMT_RGB888_1X24 ?
1183                         "RGB 888 24-bit" : "Unsupported");
1184
1185         v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
1186         v4l2_info(sd, "HDCP encrypted content: %s\n",
1187                         hdmi_sys_status & MASK_S_HDCP ? "yes" : "no");
1188         v4l2_info(sd, "Input color space: %s %s range\n",
1189                         input_color_space[(vi_status3 & MASK_S_V_COLOR) >> 1],
1190                         (vi_status3 & MASK_LIMITED) ? "limited" : "full");
1191         if (!is_hdmi(sd))
1192                 return 0;
1193         v4l2_info(sd, "AV Mute: %s\n", hdmi_sys_status & MASK_S_AVMUTE ? "on" :
1194                         "off");
1195         v4l2_info(sd, "Deep color mode: %d-bits per channel\n",
1196                         deep_color_mode[(i2c_rd8(sd, VI_STATUS1) &
1197                                 MASK_S_DEEPCOLOR) >> 2]);
1198         print_avi_infoframe(sd);
1199
1200         return 0;
1201 }
1202
1203 #ifdef CONFIG_VIDEO_ADV_DEBUG
1204 static void tc358743_print_register_map(struct v4l2_subdev *sd)
1205 {
1206         v4l2_info(sd, "0x0000–0x00FF: Global Control Register\n");
1207         v4l2_info(sd, "0x0100–0x01FF: CSI2-TX PHY Register\n");
1208         v4l2_info(sd, "0x0200–0x03FF: CSI2-TX PPI Register\n");
1209         v4l2_info(sd, "0x0400–0x05FF: Reserved\n");
1210         v4l2_info(sd, "0x0600–0x06FF: CEC Register\n");
1211         v4l2_info(sd, "0x0700–0x84FF: Reserved\n");
1212         v4l2_info(sd, "0x8500–0x85FF: HDMIRX System Control Register\n");
1213         v4l2_info(sd, "0x8600–0x86FF: HDMIRX Audio Control Register\n");
1214         v4l2_info(sd, "0x8700–0x87FF: HDMIRX InfoFrame packet data Register\n");
1215         v4l2_info(sd, "0x8800–0x88FF: HDMIRX HDCP Port Register\n");
1216         v4l2_info(sd, "0x8900–0x89FF: HDMIRX Video Output Port & 3D Register\n");
1217         v4l2_info(sd, "0x8A00–0x8BFF: Reserved\n");
1218         v4l2_info(sd, "0x8C00–0x8FFF: HDMIRX EDID-RAM (1024bytes)\n");
1219         v4l2_info(sd, "0x9000–0x90FF: HDMIRX GBD Extraction Control\n");
1220         v4l2_info(sd, "0x9100–0x92FF: HDMIRX GBD RAM read\n");
1221         v4l2_info(sd, "0x9300-      : Reserved\n");
1222 }
1223
1224 static int tc358743_get_reg_size(u16 address)
1225 {
1226         /* REF_01 p. 66-72 */
1227         if (address <= 0x00ff)
1228                 return 2;
1229         else if ((address >= 0x0100) && (address <= 0x06FF))
1230                 return 4;
1231         else if ((address >= 0x0700) && (address <= 0x84ff))
1232                 return 2;
1233         else
1234                 return 1;
1235 }
1236
1237 static int tc358743_g_register(struct v4l2_subdev *sd,
1238                                struct v4l2_dbg_register *reg)
1239 {
1240         if (reg->reg > 0xffff) {
1241                 tc358743_print_register_map(sd);
1242                 return -EINVAL;
1243         }
1244
1245         reg->size = tc358743_get_reg_size(reg->reg);
1246
1247         reg->val = i2c_rdreg(sd, reg->reg, reg->size);
1248
1249         return 0;
1250 }
1251
1252 static int tc358743_s_register(struct v4l2_subdev *sd,
1253                                const struct v4l2_dbg_register *reg)
1254 {
1255         if (reg->reg > 0xffff) {
1256                 tc358743_print_register_map(sd);
1257                 return -EINVAL;
1258         }
1259
1260         /* It should not be possible for the user to enable HDCP with a simple
1261          * v4l2-dbg command.
1262          *
1263          * DO NOT REMOVE THIS unless all other issues with HDCP have been
1264          * resolved.
1265          */
1266         if (reg->reg == HDCP_MODE ||
1267             reg->reg == HDCP_REG1 ||
1268             reg->reg == HDCP_REG2 ||
1269             reg->reg == HDCP_REG3 ||
1270             reg->reg == BCAPS)
1271                 return 0;
1272
1273         i2c_wrreg(sd, (u16)reg->reg, reg->val,
1274                         tc358743_get_reg_size(reg->reg));
1275
1276         return 0;
1277 }
1278 #endif
1279
1280 static int tc358743_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1281 {
1282         u16 intstatus = i2c_rd16(sd, INTSTATUS);
1283
1284         v4l2_dbg(1, debug, sd, "%s: IntStatus = 0x%04x\n", __func__, intstatus);
1285
1286         if (intstatus & MASK_HDMI_INT) {
1287                 u8 hdmi_int0 = i2c_rd8(sd, HDMI_INT0);
1288                 u8 hdmi_int1 = i2c_rd8(sd, HDMI_INT1);
1289
1290                 if (hdmi_int0 & MASK_I_MISC)
1291                         tc358743_hdmi_misc_int_handler(sd, handled);
1292                 if (hdmi_int1 & MASK_I_CBIT)
1293                         tc358743_hdmi_cbit_int_handler(sd, handled);
1294                 if (hdmi_int1 & MASK_I_CLK)
1295                         tc358743_hdmi_clk_int_handler(sd, handled);
1296                 if (hdmi_int1 & MASK_I_SYS)
1297                         tc358743_hdmi_sys_int_handler(sd, handled);
1298                 if (hdmi_int1 & MASK_I_AUD)
1299                         tc358743_hdmi_audio_int_handler(sd, handled);
1300
1301                 i2c_wr16(sd, INTSTATUS, MASK_HDMI_INT);
1302                 intstatus &= ~MASK_HDMI_INT;
1303         }
1304
1305         if (intstatus & MASK_CSI_INT) {
1306                 u32 csi_int = i2c_rd32(sd, CSI_INT);
1307
1308                 if (csi_int & MASK_INTER)
1309                         tc358743_csi_err_int_handler(sd, handled);
1310
1311                 i2c_wr16(sd, INTSTATUS, MASK_CSI_INT);
1312                 intstatus &= ~MASK_CSI_INT;
1313         }
1314
1315         intstatus = i2c_rd16(sd, INTSTATUS);
1316         if (intstatus) {
1317                 v4l2_dbg(1, debug, sd,
1318                                 "%s: Unhandled IntStatus interrupts: 0x%02x\n",
1319                                 __func__, intstatus);
1320         }
1321
1322         return 0;
1323 }
1324
1325 static irqreturn_t tc358743_irq_handler(int irq, void *dev_id)
1326 {
1327         struct tc358743_state *state = dev_id;
1328         bool handled = false;
1329
1330         tc358743_isr(&state->sd, 0, &handled);
1331
1332         return handled ? IRQ_HANDLED : IRQ_NONE;
1333 }
1334
1335 static int tc358743_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
1336                                     struct v4l2_event_subscription *sub)
1337 {
1338         switch (sub->type) {
1339         case V4L2_EVENT_SOURCE_CHANGE:
1340                 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
1341         case V4L2_EVENT_CTRL:
1342                 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
1343         default:
1344                 return -EINVAL;
1345         }
1346 }
1347
1348 /* --------------- VIDEO OPS --------------- */
1349
1350 static int tc358743_g_input_status(struct v4l2_subdev *sd, u32 *status)
1351 {
1352         *status = 0;
1353         *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1354         *status |= no_sync(sd) ? V4L2_IN_ST_NO_SYNC : 0;
1355
1356         v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1357
1358         return 0;
1359 }
1360
1361 static int tc358743_s_dv_timings(struct v4l2_subdev *sd,
1362                                  struct v4l2_dv_timings *timings)
1363 {
1364         struct tc358743_state *state = to_state(sd);
1365
1366         if (!timings)
1367                 return -EINVAL;
1368
1369         if (debug)
1370                 v4l2_print_dv_timings(sd->name, "tc358743_s_dv_timings: ",
1371                                 timings, false);
1372
1373         if (v4l2_match_dv_timings(&state->timings, timings, 0)) {
1374                 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1375                 return 0;
1376         }
1377
1378         if (!v4l2_valid_dv_timings(timings,
1379                                 &tc358743_timings_cap, NULL, NULL)) {
1380                 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
1381                 return -ERANGE;
1382         }
1383
1384         state->timings = *timings;
1385
1386         enable_stream(sd, false);
1387         tc358743_set_pll(sd);
1388         tc358743_set_csi(sd);
1389
1390         return 0;
1391 }
1392
1393 static int tc358743_g_dv_timings(struct v4l2_subdev *sd,
1394                                  struct v4l2_dv_timings *timings)
1395 {
1396         struct tc358743_state *state = to_state(sd);
1397
1398         *timings = state->timings;
1399
1400         return 0;
1401 }
1402
1403 static int tc358743_enum_dv_timings(struct v4l2_subdev *sd,
1404                                     struct v4l2_enum_dv_timings *timings)
1405 {
1406         if (timings->pad != 0)
1407                 return -EINVAL;
1408
1409         return v4l2_enum_dv_timings_cap(timings,
1410                         &tc358743_timings_cap, NULL, NULL);
1411 }
1412
1413 static int tc358743_query_dv_timings(struct v4l2_subdev *sd,
1414                 struct v4l2_dv_timings *timings)
1415 {
1416         int ret;
1417
1418         ret = tc358743_get_detected_timings(sd, timings);
1419         if (ret)
1420                 return ret;
1421
1422         if (debug)
1423                 v4l2_print_dv_timings(sd->name, "tc358743_query_dv_timings: ",
1424                                 timings, false);
1425
1426         if (!v4l2_valid_dv_timings(timings,
1427                                 &tc358743_timings_cap, NULL, NULL)) {
1428                 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
1429                 return -ERANGE;
1430         }
1431
1432         return 0;
1433 }
1434
1435 static int tc358743_dv_timings_cap(struct v4l2_subdev *sd,
1436                 struct v4l2_dv_timings_cap *cap)
1437 {
1438         if (cap->pad != 0)
1439                 return -EINVAL;
1440
1441         *cap = tc358743_timings_cap;
1442
1443         return 0;
1444 }
1445
1446 static int tc358743_g_mbus_config(struct v4l2_subdev *sd,
1447                              struct v4l2_mbus_config *cfg)
1448 {
1449         cfg->type = V4L2_MBUS_CSI2;
1450
1451         /* Support for non-continuous CSI-2 clock is missing in the driver */
1452         cfg->flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1453
1454         switch (tc358743_num_csi_lanes_in_use(sd)) {
1455         case 1:
1456                 cfg->flags |= V4L2_MBUS_CSI2_1_LANE;
1457                 break;
1458         case 2:
1459                 cfg->flags |= V4L2_MBUS_CSI2_2_LANE;
1460                 break;
1461         case 3:
1462                 cfg->flags |= V4L2_MBUS_CSI2_3_LANE;
1463                 break;
1464         case 4:
1465                 cfg->flags |= V4L2_MBUS_CSI2_4_LANE;
1466                 break;
1467         default:
1468                 return -EINVAL;
1469         }
1470
1471         return 0;
1472 }
1473
1474 static int tc358743_s_stream(struct v4l2_subdev *sd, int enable)
1475 {
1476         enable_stream(sd, enable);
1477
1478         return 0;
1479 }
1480
1481 /* --------------- PAD OPS --------------- */
1482
1483 static int tc358743_get_fmt(struct v4l2_subdev *sd,
1484                 struct v4l2_subdev_pad_config *cfg,
1485                 struct v4l2_subdev_format *format)
1486 {
1487         struct tc358743_state *state = to_state(sd);
1488         u8 vi_rep = i2c_rd8(sd, VI_REP);
1489
1490         if (format->pad != 0)
1491                 return -EINVAL;
1492
1493         format->format.code = state->mbus_fmt_code;
1494         format->format.width = state->timings.bt.width;
1495         format->format.height = state->timings.bt.height;
1496         format->format.field = V4L2_FIELD_NONE;
1497
1498         switch (vi_rep & MASK_VOUT_COLOR_SEL) {
1499         case MASK_VOUT_COLOR_RGB_FULL:
1500         case MASK_VOUT_COLOR_RGB_LIMITED:
1501                 format->format.colorspace = V4L2_COLORSPACE_SRGB;
1502                 break;
1503         case MASK_VOUT_COLOR_601_YCBCR_LIMITED:
1504         case MASK_VOUT_COLOR_601_YCBCR_FULL:
1505                 format->format.colorspace = V4L2_COLORSPACE_SMPTE170M;
1506                 break;
1507         case MASK_VOUT_COLOR_709_YCBCR_FULL:
1508         case MASK_VOUT_COLOR_709_YCBCR_LIMITED:
1509                 format->format.colorspace = V4L2_COLORSPACE_REC709;
1510                 break;
1511         default:
1512                 format->format.colorspace = 0;
1513                 break;
1514         }
1515
1516         return 0;
1517 }
1518
1519 static int tc358743_set_fmt(struct v4l2_subdev *sd,
1520                 struct v4l2_subdev_pad_config *cfg,
1521                 struct v4l2_subdev_format *format)
1522 {
1523         struct tc358743_state *state = to_state(sd);
1524
1525         u32 code = format->format.code; /* is overwritten by get_fmt */
1526         int ret = tc358743_get_fmt(sd, cfg, format);
1527
1528         format->format.code = code;
1529
1530         if (ret)
1531                 return ret;
1532
1533         switch (code) {
1534         case MEDIA_BUS_FMT_RGB888_1X24:
1535         case MEDIA_BUS_FMT_UYVY8_1X16:
1536                 break;
1537         default:
1538                 return -EINVAL;
1539         }
1540
1541         if (format->which == V4L2_SUBDEV_FORMAT_TRY)
1542                 return 0;
1543
1544         state->mbus_fmt_code = format->format.code;
1545
1546         enable_stream(sd, false);
1547         tc358743_set_pll(sd);
1548         tc358743_set_csi(sd);
1549         tc358743_set_csi_color_space(sd);
1550
1551         return 0;
1552 }
1553
1554 static int tc358743_g_edid(struct v4l2_subdev *sd,
1555                 struct v4l2_subdev_edid *edid)
1556 {
1557         struct tc358743_state *state = to_state(sd);
1558
1559         if (edid->pad != 0)
1560                 return -EINVAL;
1561
1562         if (edid->start_block == 0 && edid->blocks == 0) {
1563                 edid->blocks = state->edid_blocks_written;
1564                 return 0;
1565         }
1566
1567         if (state->edid_blocks_written == 0)
1568                 return -ENODATA;
1569
1570         if (edid->start_block >= state->edid_blocks_written ||
1571                         edid->blocks == 0)
1572                 return -EINVAL;
1573
1574         if (edid->start_block + edid->blocks > state->edid_blocks_written)
1575                 edid->blocks = state->edid_blocks_written - edid->start_block;
1576
1577         i2c_rd(sd, EDID_RAM + (edid->start_block * EDID_BLOCK_SIZE), edid->edid,
1578                         edid->blocks * EDID_BLOCK_SIZE);
1579
1580         return 0;
1581 }
1582
1583 static int tc358743_s_edid(struct v4l2_subdev *sd,
1584                                 struct v4l2_subdev_edid *edid)
1585 {
1586         struct tc358743_state *state = to_state(sd);
1587         u16 edid_len = edid->blocks * EDID_BLOCK_SIZE;
1588
1589         v4l2_dbg(2, debug, sd, "%s, pad %d, start block %d, blocks %d\n",
1590                  __func__, edid->pad, edid->start_block, edid->blocks);
1591
1592         if (edid->pad != 0)
1593                 return -EINVAL;
1594
1595         if (edid->start_block != 0)
1596                 return -EINVAL;
1597
1598         if (edid->blocks > EDID_NUM_BLOCKS_MAX) {
1599                 edid->blocks = EDID_NUM_BLOCKS_MAX;
1600                 return -E2BIG;
1601         }
1602
1603         tc358743_disable_edid(sd);
1604
1605         i2c_wr8(sd, EDID_LEN1, edid_len & 0xff);
1606         i2c_wr8(sd, EDID_LEN2, edid_len >> 8);
1607
1608         if (edid->blocks == 0) {
1609                 state->edid_blocks_written = 0;
1610                 return 0;
1611         }
1612
1613         i2c_wr(sd, EDID_RAM, edid->edid, edid_len);
1614
1615         state->edid_blocks_written = edid->blocks;
1616
1617         if (tx_5v_power_present(sd))
1618                 tc358743_enable_edid(sd);
1619
1620         return 0;
1621 }
1622
1623 /* -------------------------------------------------------------------------- */
1624
1625 static const struct v4l2_subdev_core_ops tc358743_core_ops = {
1626         .log_status = tc358743_log_status,
1627 #ifdef CONFIG_VIDEO_ADV_DEBUG
1628         .g_register = tc358743_g_register,
1629         .s_register = tc358743_s_register,
1630 #endif
1631         .interrupt_service_routine = tc358743_isr,
1632         .subscribe_event = tc358743_subscribe_event,
1633         .unsubscribe_event = v4l2_event_subdev_unsubscribe,
1634 };
1635
1636 static const struct v4l2_subdev_video_ops tc358743_video_ops = {
1637         .g_input_status = tc358743_g_input_status,
1638         .s_dv_timings = tc358743_s_dv_timings,
1639         .g_dv_timings = tc358743_g_dv_timings,
1640         .query_dv_timings = tc358743_query_dv_timings,
1641         .g_mbus_config = tc358743_g_mbus_config,
1642         .s_stream = tc358743_s_stream,
1643 };
1644
1645 static const struct v4l2_subdev_pad_ops tc358743_pad_ops = {
1646         .set_fmt = tc358743_set_fmt,
1647         .get_fmt = tc358743_get_fmt,
1648         .get_edid = tc358743_g_edid,
1649         .set_edid = tc358743_s_edid,
1650         .enum_dv_timings = tc358743_enum_dv_timings,
1651         .dv_timings_cap = tc358743_dv_timings_cap,
1652 };
1653
1654 static const struct v4l2_subdev_ops tc358743_ops = {
1655         .core = &tc358743_core_ops,
1656         .video = &tc358743_video_ops,
1657         .pad = &tc358743_pad_ops,
1658 };
1659
1660 /* --------------- CUSTOM CTRLS --------------- */
1661
1662 static const struct v4l2_ctrl_config tc358743_ctrl_audio_sampling_rate = {
1663         .id = TC358743_CID_AUDIO_SAMPLING_RATE,
1664         .name = "Audio sampling rate",
1665         .type = V4L2_CTRL_TYPE_INTEGER,
1666         .min = 0,
1667         .max = 768000,
1668         .step = 1,
1669         .def = 0,
1670         .flags = V4L2_CTRL_FLAG_READ_ONLY,
1671 };
1672
1673 static const struct v4l2_ctrl_config tc358743_ctrl_audio_present = {
1674         .id = TC358743_CID_AUDIO_PRESENT,
1675         .name = "Audio present",
1676         .type = V4L2_CTRL_TYPE_BOOLEAN,
1677         .min = 0,
1678         .max = 1,
1679         .step = 1,
1680         .def = 0,
1681         .flags = V4L2_CTRL_FLAG_READ_ONLY,
1682 };
1683
1684 /* --------------- PROBE / REMOVE --------------- */
1685
1686 #ifdef CONFIG_OF
1687 static void tc358743_gpio_reset(struct tc358743_state *state)
1688 {
1689         usleep_range(5000, 10000);
1690         gpiod_set_value(state->reset_gpio, 1);
1691         usleep_range(1000, 2000);
1692         gpiod_set_value(state->reset_gpio, 0);
1693         msleep(20);
1694 }
1695
1696 static int tc358743_probe_of(struct tc358743_state *state)
1697 {
1698         struct device *dev = &state->i2c_client->dev;
1699         struct v4l2_of_endpoint *endpoint;
1700         struct device_node *ep;
1701         struct clk *refclk;
1702         u32 bps_pr_lane;
1703         int ret = -EINVAL;
1704
1705         refclk = devm_clk_get(dev, "refclk");
1706         if (IS_ERR(refclk)) {
1707                 if (PTR_ERR(refclk) != -EPROBE_DEFER)
1708                         dev_err(dev, "failed to get refclk: %ld\n",
1709                                 PTR_ERR(refclk));
1710                 return PTR_ERR(refclk);
1711         }
1712
1713         ep = of_graph_get_next_endpoint(dev->of_node, NULL);
1714         if (!ep) {
1715                 dev_err(dev, "missing endpoint node\n");
1716                 return -EINVAL;
1717         }
1718
1719         endpoint = v4l2_of_alloc_parse_endpoint(ep);
1720         if (IS_ERR(endpoint)) {
1721                 dev_err(dev, "failed to parse endpoint\n");
1722                 return PTR_ERR(endpoint);
1723         }
1724
1725         if (endpoint->bus_type != V4L2_MBUS_CSI2 ||
1726             endpoint->bus.mipi_csi2.num_data_lanes == 0 ||
1727             endpoint->nr_of_link_frequencies == 0) {
1728                 dev_err(dev, "missing CSI-2 properties in endpoint\n");
1729                 goto free_endpoint;
1730         }
1731
1732         state->bus = endpoint->bus.mipi_csi2;
1733
1734         clk_prepare_enable(refclk);
1735
1736         state->pdata.refclk_hz = clk_get_rate(refclk);
1737         state->pdata.ddc5v_delay = DDC5V_DELAY_100_MS;
1738         state->pdata.enable_hdcp = false;
1739         /* A FIFO level of 16 should be enough for 2-lane 720p60 at 594 MHz. */
1740         state->pdata.fifo_level = 16;
1741         /*
1742          * The PLL input clock is obtained by dividing refclk by pll_prd.
1743          * It must be between 6 MHz and 40 MHz, lower frequency is better.
1744          */
1745         switch (state->pdata.refclk_hz) {
1746         case 26000000:
1747         case 27000000:
1748         case 42000000:
1749                 state->pdata.pll_prd = state->pdata.refclk_hz / 6000000;
1750                 break;
1751         default:
1752                 dev_err(dev, "unsupported refclk rate: %u Hz\n",
1753                         state->pdata.refclk_hz);
1754                 goto disable_clk;
1755         }
1756
1757         /*
1758          * The CSI bps per lane must be between 62.5 Mbps and 1 Gbps.
1759          * The default is 594 Mbps for 4-lane 1080p60 or 2-lane 720p60.
1760          */
1761         bps_pr_lane = 2 * endpoint->link_frequencies[0];
1762         if (bps_pr_lane < 62500000U || bps_pr_lane > 1000000000U) {
1763                 dev_err(dev, "unsupported bps per lane: %u bps\n", bps_pr_lane);
1764                 ret = -EINVAL;
1765                 goto disable_clk;
1766         }
1767
1768         /* The CSI speed per lane is refclk / pll_prd * pll_fbd */
1769         state->pdata.pll_fbd = bps_pr_lane /
1770                                state->pdata.refclk_hz * state->pdata.pll_prd;
1771
1772         /*
1773          * FIXME: These timings are from REF_02 for 594 Mbps per lane (297 MHz
1774          * link frequency). In principle it should be possible to calculate
1775          * them based on link frequency and resolution.
1776          */
1777         if (bps_pr_lane != 594000000U)
1778                 dev_warn(dev, "untested bps per lane: %u bps\n", bps_pr_lane);
1779         state->pdata.lineinitcnt = 0xe80;
1780         state->pdata.lptxtimecnt = 0x003;
1781         /* tclk-preparecnt: 3, tclk-zerocnt: 20 */
1782         state->pdata.tclk_headercnt = 0x1403;
1783         state->pdata.tclk_trailcnt = 0x00;
1784         /* ths-preparecnt: 3, ths-zerocnt: 1 */
1785         state->pdata.ths_headercnt = 0x0103;
1786         state->pdata.twakeup = 0x4882;
1787         state->pdata.tclk_postcnt = 0x008;
1788         state->pdata.ths_trailcnt = 0x2;
1789         state->pdata.hstxvregcnt = 0;
1790
1791         state->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1792                                                     GPIOD_OUT_LOW);
1793         if (IS_ERR(state->reset_gpio)) {
1794                 dev_err(dev, "failed to get reset gpio\n");
1795                 ret = PTR_ERR(state->reset_gpio);
1796                 goto disable_clk;
1797         }
1798
1799         if (state->reset_gpio)
1800                 tc358743_gpio_reset(state);
1801
1802         ret = 0;
1803         goto free_endpoint;
1804
1805 disable_clk:
1806         clk_disable_unprepare(refclk);
1807 free_endpoint:
1808         v4l2_of_free_endpoint(endpoint);
1809         return ret;
1810 }
1811 #else
1812 static inline int tc358743_probe_of(struct tc358743_state *state)
1813 {
1814         return -ENODEV;
1815 }
1816 #endif
1817
1818 static int tc358743_probe(struct i2c_client *client,
1819                           const struct i2c_device_id *id)
1820 {
1821         static struct v4l2_dv_timings default_timing =
1822                 V4L2_DV_BT_CEA_640X480P59_94;
1823         struct tc358743_state *state;
1824         struct tc358743_platform_data *pdata = client->dev.platform_data;
1825         struct v4l2_subdev *sd;
1826         int err;
1827
1828         if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1829                 return -EIO;
1830         v4l_dbg(1, debug, client, "chip found @ 0x%x (%s)\n",
1831                 client->addr << 1, client->adapter->name);
1832
1833         state = devm_kzalloc(&client->dev, sizeof(struct tc358743_state),
1834                         GFP_KERNEL);
1835         if (!state)
1836                 return -ENOMEM;
1837
1838         state->i2c_client = client;
1839
1840         /* platform data */
1841         if (pdata) {
1842                 state->pdata = *pdata;
1843                 state->bus.flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1844         } else {
1845                 err = tc358743_probe_of(state);
1846                 if (err == -ENODEV)
1847                         v4l_err(client, "No platform data!\n");
1848                 if (err)
1849                         return err;
1850         }
1851
1852         sd = &state->sd;
1853         v4l2_i2c_subdev_init(sd, client, &tc358743_ops);
1854         sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
1855
1856         /* i2c access */
1857         if ((i2c_rd16(sd, CHIPID) & MASK_CHIPID) != 0) {
1858                 v4l2_info(sd, "not a TC358743 on address 0x%x\n",
1859                           client->addr << 1);
1860                 return -ENODEV;
1861         }
1862
1863         /* control handlers */
1864         v4l2_ctrl_handler_init(&state->hdl, 3);
1865
1866         /* private controls */
1867         state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(&state->hdl, NULL,
1868                         V4L2_CID_DV_RX_POWER_PRESENT, 0, 1, 0, 0);
1869
1870         /* custom controls */
1871         state->audio_sampling_rate_ctrl = v4l2_ctrl_new_custom(&state->hdl,
1872                         &tc358743_ctrl_audio_sampling_rate, NULL);
1873
1874         state->audio_present_ctrl = v4l2_ctrl_new_custom(&state->hdl,
1875                         &tc358743_ctrl_audio_present, NULL);
1876
1877         sd->ctrl_handler = &state->hdl;
1878         if (state->hdl.error) {
1879                 err = state->hdl.error;
1880                 goto err_hdl;
1881         }
1882
1883         if (tc358743_update_controls(sd)) {
1884                 err = -ENODEV;
1885                 goto err_hdl;
1886         }
1887
1888         /* work queues */
1889         state->work_queues = create_singlethread_workqueue(client->name);
1890         if (!state->work_queues) {
1891                 v4l2_err(sd, "Could not create work queue\n");
1892                 err = -ENOMEM;
1893                 goto err_hdl;
1894         }
1895
1896         state->pad.flags = MEDIA_PAD_FL_SOURCE;
1897         err = media_entity_init(&sd->entity, 1, &state->pad, 0);
1898         if (err < 0)
1899                 goto err_hdl;
1900
1901         sd->dev = &client->dev;
1902         err = v4l2_async_register_subdev(sd);
1903         if (err < 0)
1904                 goto err_hdl;
1905
1906         mutex_init(&state->confctl_mutex);
1907
1908         INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
1909                         tc358743_delayed_work_enable_hotplug);
1910
1911         tc358743_initial_setup(sd);
1912
1913         tc358743_s_dv_timings(sd, &default_timing);
1914
1915         state->mbus_fmt_code = MEDIA_BUS_FMT_RGB888_1X24;
1916         tc358743_set_csi_color_space(sd);
1917
1918         tc358743_init_interrupts(sd);
1919
1920         if (state->i2c_client->irq) {
1921                 err = devm_request_threaded_irq(&client->dev,
1922                                                 state->i2c_client->irq,
1923                                                 NULL, tc358743_irq_handler,
1924                                                 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1925                                                 "tc358743", state);
1926                 if (err)
1927                         goto err_work_queues;
1928         }
1929
1930         tc358743_enable_interrupts(sd, tx_5v_power_present(sd));
1931         i2c_wr16(sd, INTMASK, ~(MASK_HDMI_MSK | MASK_CSI_MSK) & 0xffff);
1932
1933         err = v4l2_ctrl_handler_setup(sd->ctrl_handler);
1934         if (err)
1935                 goto err_work_queues;
1936
1937         v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
1938                   client->addr << 1, client->adapter->name);
1939
1940         return 0;
1941
1942 err_work_queues:
1943         cancel_delayed_work(&state->delayed_work_enable_hotplug);
1944         destroy_workqueue(state->work_queues);
1945         mutex_destroy(&state->confctl_mutex);
1946 err_hdl:
1947         media_entity_cleanup(&sd->entity);
1948         v4l2_ctrl_handler_free(&state->hdl);
1949         return err;
1950 }
1951
1952 static int tc358743_remove(struct i2c_client *client)
1953 {
1954         struct v4l2_subdev *sd = i2c_get_clientdata(client);
1955         struct tc358743_state *state = to_state(sd);
1956
1957         cancel_delayed_work(&state->delayed_work_enable_hotplug);
1958         destroy_workqueue(state->work_queues);
1959         v4l2_async_unregister_subdev(sd);
1960         v4l2_device_unregister_subdev(sd);
1961         mutex_destroy(&state->confctl_mutex);
1962         media_entity_cleanup(&sd->entity);
1963         v4l2_ctrl_handler_free(&state->hdl);
1964
1965         return 0;
1966 }
1967
1968 static struct i2c_device_id tc358743_id[] = {
1969         {"tc358743", 0},
1970         {}
1971 };
1972
1973 MODULE_DEVICE_TABLE(i2c, tc358743_id);
1974
1975 static struct i2c_driver tc358743_driver = {
1976         .driver = {
1977                 .name = "tc358743",
1978         },
1979         .probe = tc358743_probe,
1980         .remove = tc358743_remove,
1981         .id_table = tc358743_id,
1982 };
1983
1984 module_i2c_driver(tc358743_driver);