drivers/media/pci/ngene/ngene-core.c

   1 /*
   2  * ngene.c: nGene PCIe bridge driver
   3  *
   4  * Copyright (C) 2005-2007 Micronas
   5  *
   6  * Copyright (C) 2008-2009 Ralph Metzler <rjkm@metzlerbros.de>
   7  *                         Modifications for new nGene firmware,
   8  *                         support for EEPROM-copying,
   9  *                         support for new dual DVB-S2 card prototype
  10  *
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * version 2 only, as published by the Free Software Foundation.
  15  *
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * To obtain the license, point your browser to
  23  * http://www.gnu.org/copyleft/gpl.html
  24  */
  25
  26 #include <linux/module.h>
  27 #include <linux/init.h>
  28 #include <linux/delay.h>
  29 #include <linux/poll.h>
  30 #include <linux/io.h>
  31 #include <asm/div64.h>
  32 #include <linux/pci.h>
  33 #include <linux/timer.h>
  34 #include <linux/byteorder/generic.h>
  35 #include <linux/firmware.h>
  36 #include <linux/vmalloc.h>
  37
  38 #include "ngene.h"
  39
  40 static int one_adapter;
  41 module_param(one_adapter, int, 0444);
  42 MODULE_PARM_DESC(one_adapter, "Use only one adapter.");
  43
  44 static int shutdown_workaround;
  45 module_param(shutdown_workaround, int, 0644);
  46 MODULE_PARM_DESC(shutdown_workaround, "Activate workaround for shutdown problem with some chipsets.");
  47
  48 static int debug;
  49 module_param(debug, int, 0444);
  50 MODULE_PARM_DESC(debug, "Print debugging information.");
  51
  52 DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  53
  54 #define ngwriteb(dat, adr)         writeb((dat), dev->iomem + (adr))
  55 #define ngwritel(dat, adr)         writel((dat), dev->iomem + (adr))
  56 #define ngwriteb(dat, adr)         writeb((dat), dev->iomem + (adr))
  57 #define ngreadl(adr)               readl(dev->iomem + (adr))
  58 #define ngreadb(adr)               readb(dev->iomem + (adr))
  59 #define ngcpyto(adr, src, count)   memcpy_toio(dev->iomem + (adr), (src), (count))
  60 #define ngcpyfrom(dst, adr, count) memcpy_fromio((dst), dev->iomem + (adr), (count))
  61
  62 /****************************************************************************/
  63 /* nGene interrupt handler **************************************************/
  64 /****************************************************************************/
  65
  66 static void event_tasklet(unsigned long data)
  67 {
  68         struct ngene *dev = (struct ngene *)data;
  69
  70         while (dev->EventQueueReadIndex != dev->EventQueueWriteIndex) {
  71                 struct EVENT_BUFFER Event =
  72                         dev->EventQueue[dev->EventQueueReadIndex];
  73                 dev->EventQueueReadIndex =
  74                         (dev->EventQueueReadIndex + 1) & (EVENT_QUEUE_SIZE - 1);
  75
  76                 if ((Event.UARTStatus & 0x01) && (dev->TxEventNotify))
  77                         dev->TxEventNotify(dev, Event.TimeStamp);
  78                 if ((Event.UARTStatus & 0x02) && (dev->RxEventNotify))
  79                         dev->RxEventNotify(dev, Event.TimeStamp,
  80                                            Event.RXCharacter);
  81         }
  82 }
  83
  84 static void demux_tasklet(unsigned long data)
  85 {
  86         struct ngene_channel *chan = (struct ngene_channel *)data;
  87         struct device *pdev = &chan->dev->pci_dev->dev;
  88         struct SBufferHeader *Cur = chan->nextBuffer;
  89
  90         spin_lock_irq(&chan->state_lock);
  91
  92         while (Cur->ngeneBuffer.SR.Flags & 0x80) {
  93                 if (chan->mode & NGENE_IO_TSOUT) {
  94                         u32 Flags = chan->DataFormatFlags;
  95                         if (Cur->ngeneBuffer.SR.Flags & 0x20)
  96                                 Flags |= BEF_OVERFLOW;
  97                         if (chan->pBufferExchange) {
  98                                 if (!chan->pBufferExchange(chan,
  99                                                            Cur->Buffer1,
 100                                                            chan->Capture1Length,
 101                                                            Cur->ngeneBuffer.SR.
 102                                                            Clock, Flags)) {
 103                                         /*
 104                                            We didn't get data
 105                                            Clear in service flag to make sure we
 106                                            get called on next interrupt again.
 107                                            leave fill/empty (0x80) flag alone
 108                                            to avoid hardware running out of
 109                                            buffers during startup, we hold only
 110                                            in run state ( the source may be late
 111                                            delivering data )
 112                                         */
 113
 114                                         if (chan->HWState == HWSTATE_RUN) {
 115                                                 Cur->ngeneBuffer.SR.Flags &=
 116                                                         ~0x40;
 117                                                 break;
 118                                                 /* Stop processing stream */
 119                                         }
 120                                 } else {
 121                                         /* We got a valid buffer,
 122                                            so switch to run state */
 123                                         chan->HWState = HWSTATE_RUN;
 124                                 }
 125                         } else {
 126                                 dev_err(pdev, "OOPS\n");
 127                                 if (chan->HWState == HWSTATE_RUN) {
 128                                         Cur->ngeneBuffer.SR.Flags &= ~0x40;
 129                                         break;  /* Stop processing stream */
 130                                 }
 131                         }
 132                         if (chan->AudioDTOUpdated) {
 133                                 dev_info(pdev, "Update AudioDTO = %d\n",
 134                                          chan->AudioDTOValue);
 135                                 Cur->ngeneBuffer.SR.DTOUpdate =
 136                                         chan->AudioDTOValue;
 137                                 chan->AudioDTOUpdated = 0;
 138                         }
 139                 } else {
 140                         if (chan->HWState == HWSTATE_RUN) {
 141                                 u32 Flags = chan->DataFormatFlags;
 142                                 IBufferExchange *exch1 = chan->pBufferExchange;
 143                                 IBufferExchange *exch2 = chan->pBufferExchange2;
 144                                 if (Cur->ngeneBuffer.SR.Flags & 0x01)
 145                                         Flags |= BEF_EVEN_FIELD;
 146                                 if (Cur->ngeneBuffer.SR.Flags & 0x20)
 147                                         Flags |= BEF_OVERFLOW;
 148                                 spin_unlock_irq(&chan->state_lock);
 149                                 if (exch1)
 150                                         exch1(chan, Cur->Buffer1,
 151                                                 chan->Capture1Length,
 152                                                 Cur->ngeneBuffer.SR.Clock,
 153                                                 Flags);
 154                                 if (exch2)
 155                                         exch2(chan, Cur->Buffer2,
 156                                                 chan->Capture2Length,
 157                                                 Cur->ngeneBuffer.SR.Clock,
 158                                                 Flags);
 159                                 spin_lock_irq(&chan->state_lock);
 160                         } else if (chan->HWState != HWSTATE_STOP)
 161                                 chan->HWState = HWSTATE_RUN;
 162                 }
 163                 Cur->ngeneBuffer.SR.Flags = 0x00;
 164                 Cur = Cur->Next;
 165         }
 166         chan->nextBuffer = Cur;
 167
 168         spin_unlock_irq(&chan->state_lock);
 169 }
 170
 171 static irqreturn_t irq_handler(int irq, void *dev_id)
 172 {
 173         struct ngene *dev = (struct ngene *)dev_id;
 174         struct device *pdev = &dev->pci_dev->dev;
 175         u32 icounts = 0;
 176         irqreturn_t rc = IRQ_NONE;
 177         u32 i = MAX_STREAM;
 178         u8 *tmpCmdDoneByte;
 179
 180         if (dev->BootFirmware) {
 181                 icounts = ngreadl(NGENE_INT_COUNTS);
 182                 if (icounts != dev->icounts) {
 183                         ngwritel(0, FORCE_NMI);
 184                         dev->cmd_done = 1;
 185                         wake_up(&dev->cmd_wq);
 186                         dev->icounts = icounts;
 187                         rc = IRQ_HANDLED;
 188                 }
 189                 return rc;
 190         }
 191
 192         ngwritel(0, FORCE_NMI);
 193
 194         spin_lock(&dev->cmd_lock);
 195         tmpCmdDoneByte = dev->CmdDoneByte;
 196         if (tmpCmdDoneByte &&
 197             (*tmpCmdDoneByte ||
 198             (dev->ngenetohost[0] == 1 && dev->ngenetohost[1] != 0))) {
 199                 dev->CmdDoneByte = NULL;
 200                 dev->cmd_done = 1;
 201                 wake_up(&dev->cmd_wq);
 202                 rc = IRQ_HANDLED;
 203         }
 204         spin_unlock(&dev->cmd_lock);
 205
 206         if (dev->EventBuffer->EventStatus & 0x80) {
 207                 u8 nextWriteIndex =
 208                         (dev->EventQueueWriteIndex + 1) &
 209                         (EVENT_QUEUE_SIZE - 1);
 210                 if (nextWriteIndex != dev->EventQueueReadIndex) {
 211                         dev->EventQueue[dev->EventQueueWriteIndex] =
 212                                 *(dev->EventBuffer);
 213                         dev->EventQueueWriteIndex = nextWriteIndex;
 214                 } else {
 215                         dev_err(pdev, "event overflow\n");
 216                         dev->EventQueueOverflowCount += 1;
 217                         dev->EventQueueOverflowFlag = 1;
 218                 }
 219                 dev->EventBuffer->EventStatus &= ~0x80;
 220                 tasklet_schedule(&dev->event_tasklet);
 221                 rc = IRQ_HANDLED;
 222         }
 223
 224         while (i > 0) {
 225                 i--;
 226                 spin_lock(&dev->channel[i].state_lock);
 227                 /* if (dev->channel[i].State>=KSSTATE_RUN) { */
 228                 if (dev->channel[i].nextBuffer) {
 229                         if ((dev->channel[i].nextBuffer->
 230                              ngeneBuffer.SR.Flags & 0xC0) == 0x80) {
 231                                 dev->channel[i].nextBuffer->
 232                                         ngeneBuffer.SR.Flags |= 0x40;
 233                                 tasklet_schedule(
 234                                         &dev->channel[i].demux_tasklet);
 235                                 rc = IRQ_HANDLED;
 236                         }
 237                 }
 238                 spin_unlock(&dev->channel[i].state_lock);
 239         }
 240
 241         /* Request might have been processed by a previous call. */
 242         return IRQ_HANDLED;
 243 }
 244
 245 /****************************************************************************/
 246 /* nGene command interface **************************************************/
 247 /****************************************************************************/
 248
 249 static void dump_command_io(struct ngene *dev)
 250 {
 251         struct device *pdev = &dev->pci_dev->dev;
 252         u8 buf[8], *b;
 253
 254         ngcpyfrom(buf, HOST_TO_NGENE, 8);
 255         dev_err(pdev, "host_to_ngene (%04x): %*ph\n", HOST_TO_NGENE, 8, buf);
 256
 257         ngcpyfrom(buf, NGENE_TO_HOST, 8);
 258         dev_err(pdev, "ngene_to_host (%04x): %*ph\n", NGENE_TO_HOST, 8, buf);
 259
 260         b = dev->hosttongene;
 261         dev_err(pdev, "dev->hosttongene (%p): %*ph\n", b, 8, b);
 262
 263         b = dev->ngenetohost;
 264         dev_err(pdev, "dev->ngenetohost (%p): %*ph\n", b, 8, b);
 265 }
 266
 267 static int ngene_command_mutex(struct ngene *dev, struct ngene_command *com)
 268 {
 269         struct device *pdev = &dev->pci_dev->dev;
 270         int ret;
 271         u8 *tmpCmdDoneByte;
 272
 273         dev->cmd_done = 0;
 274
 275         if (com->cmd.hdr.Opcode == CMD_FWLOAD_PREPARE) {
 276                 dev->BootFirmware = 1;
 277                 dev->icounts = ngreadl(NGENE_INT_COUNTS);
 278                 ngwritel(0, NGENE_COMMAND);
 279                 ngwritel(0, NGENE_COMMAND_HI);
 280                 ngwritel(0, NGENE_STATUS);
 281                 ngwritel(0, NGENE_STATUS_HI);
 282                 ngwritel(0, NGENE_EVENT);
 283                 ngwritel(0, NGENE_EVENT_HI);
 284         } else if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH) {
 285                 u64 fwio = dev->PAFWInterfaceBuffer;
 286
 287                 ngwritel(fwio & 0xffffffff, NGENE_COMMAND);
 288                 ngwritel(fwio >> 32, NGENE_COMMAND_HI);
 289                 ngwritel((fwio + 256) & 0xffffffff, NGENE_STATUS);
 290                 ngwritel((fwio + 256) >> 32, NGENE_STATUS_HI);
 291                 ngwritel((fwio + 512) & 0xffffffff, NGENE_EVENT);
 292                 ngwritel((fwio + 512) >> 32, NGENE_EVENT_HI);
 293         }
 294
 295         memcpy(dev->FWInterfaceBuffer, com->cmd.raw8, com->in_len + 2);
 296
 297         if (dev->BootFirmware)
 298                 ngcpyto(HOST_TO_NGENE, com->cmd.raw8, com->in_len + 2);
 299
 300         spin_lock_irq(&dev->cmd_lock);
 301         tmpCmdDoneByte = dev->ngenetohost + com->out_len;
 302         if (!com->out_len)
 303                 tmpCmdDoneByte++;
 304         *tmpCmdDoneByte = 0;
 305         dev->ngenetohost[0] = 0;
 306         dev->ngenetohost[1] = 0;
 307         dev->CmdDoneByte = tmpCmdDoneByte;
 308         spin_unlock_irq(&dev->cmd_lock);
 309
 310         /* Notify 8051. */
 311         ngwritel(1, FORCE_INT);
 312
 313         ret = wait_event_timeout(dev->cmd_wq, dev->cmd_done == 1, 2 * HZ);
 314         if (!ret) {
 315                 /*ngwritel(0, FORCE_NMI);*/
 316
 317                 dev_err(pdev, "Command timeout cmd=%02x prev=%02x\n",
 318                         com->cmd.hdr.Opcode, dev->prev_cmd);
 319                 dump_command_io(dev);
 320                 return -1;
 321         }
 322         if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH)
 323                 dev->BootFirmware = 0;
 324
 325         dev->prev_cmd = com->cmd.hdr.Opcode;
 326
 327         if (!com->out_len)
 328                 return 0;
 329
 330         memcpy(com->cmd.raw8, dev->ngenetohost, com->out_len);
 331
 332         return 0;
 333 }
 334
 335 int ngene_command(struct ngene *dev, struct ngene_command *com)
 336 {
 337         int result;
 338
 339         mutex_lock(&dev->cmd_mutex);
 340         result = ngene_command_mutex(dev, com);
 341         mutex_unlock(&dev->cmd_mutex);
 342         return result;
 343 }
 344
 345
 346 static int ngene_command_load_firmware(struct ngene *dev,
 347                                        u8 *ngene_fw, u32 size)
 348 {
 349 #define FIRSTCHUNK (1024)
 350         u32 cleft;
 351         struct ngene_command com;
 352
 353         com.cmd.hdr.Opcode = CMD_FWLOAD_PREPARE;
 354         com.cmd.hdr.Length = 0;
 355         com.in_len = 0;
 356         com.out_len = 0;
 357
 358         ngene_command(dev, &com);
 359
 360         cleft = (size + 3) & ~3;
 361         if (cleft > FIRSTCHUNK) {
 362                 ngcpyto(PROGRAM_SRAM + FIRSTCHUNK, ngene_fw + FIRSTCHUNK,
 363                         cleft - FIRSTCHUNK);
 364                 cleft = FIRSTCHUNK;
 365         }
 366         ngcpyto(DATA_FIFO_AREA, ngene_fw, cleft);
 367
 368         memset(&com, 0, sizeof(struct ngene_command));
 369         com.cmd.hdr.Opcode = CMD_FWLOAD_FINISH;
 370         com.cmd.hdr.Length = 4;
 371         com.cmd.FWLoadFinish.Address = DATA_FIFO_AREA;
 372         com.cmd.FWLoadFinish.Length = (unsigned short)cleft;
 373         com.in_len = 4;
 374         com.out_len = 0;
 375
 376         return ngene_command(dev, &com);
 377 }
 378
 379
 380 static int ngene_command_config_buf(struct ngene *dev, u8 config)
 381 {
 382         struct ngene_command com;
 383
 384         com.cmd.hdr.Opcode = CMD_CONFIGURE_BUFFER;
 385         com.cmd.hdr.Length = 1;
 386         com.cmd.ConfigureBuffers.config = config;
 387         com.in_len = 1;
 388         com.out_len = 0;
 389
 390         if (ngene_command(dev, &com) < 0)
 391                 return -EIO;
 392         return 0;
 393 }
 394
 395 static int ngene_command_config_free_buf(struct ngene *dev, u8 *config)
 396 {
 397         struct ngene_command com;
 398
 399         com.cmd.hdr.Opcode = CMD_CONFIGURE_FREE_BUFFER;
 400         com.cmd.hdr.Length = 6;
 401         memcpy(&com.cmd.ConfigureFreeBuffers.config, config, 6);
 402         com.in_len = 6;
 403         com.out_len = 0;
 404
 405         if (ngene_command(dev, &com) < 0)
 406                 return -EIO;
 407
 408         return 0;
 409 }
 410
 411 int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level)
 412 {
 413         struct ngene_command com;
 414
 415         com.cmd.hdr.Opcode = CMD_SET_GPIO_PIN;
 416         com.cmd.hdr.Length = 1;
 417         com.cmd.SetGpioPin.select = select | (level << 7);
 418         com.in_len = 1;
 419         com.out_len = 0;
 420
 421         return ngene_command(dev, &com);
 422 }
 423
 424
 425 /*
 426  02000640 is sample on rising edge.
 427  02000740 is sample on falling edge.
 428  02000040 is ignore "valid" signal
 429
 430  0: FD_CTL1 Bit 7,6 must be 0,1
 431     7   disable(fw controlled)
 432     6   0-AUX,1-TS
 433     5   0-par,1-ser
 434     4   0-lsb/1-msb
 435     3,2 reserved
 436     1,0 0-no sync, 1-use ext. start, 2-use 0x47, 3-both
 437  1: FD_CTL2 has 3-valid must be hi, 2-use valid, 1-edge
 438  2: FD_STA is read-only. 0-sync
 439  3: FD_INSYNC is number of 47s to trigger "in sync".
 440  4: FD_OUTSYNC is number of 47s to trigger "out of sync".
 441  5: FD_MAXBYTE1 is low-order of bytes per packet.
 442  6: FD_MAXBYTE2 is high-order of bytes per packet.
 443  7: Top byte is unused.
 444 */
 445
 446 /****************************************************************************/
 447
 448 static u8 TSFeatureDecoderSetup[8 * 5] = {
 449         0x42, 0x00, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00,
 450         0x40, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXH */
 451         0x71, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXHser */
 452         0x72, 0x00, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* S2ser */
 453         0x40, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* LGDT3303 */
 454 };
 455
 456 /* Set NGENE I2S Config to 16 bit packed */
 457 static u8 I2SConfiguration[] = {
 458         0x00, 0x10, 0x00, 0x00,
 459         0x80, 0x10, 0x00, 0x00,
 460 };
 461
 462 static u8 SPDIFConfiguration[10] = {
 463         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
 464 };
 465
 466 /* Set NGENE I2S Config to transport stream compatible mode */
 467
 468 static u8 TS_I2SConfiguration[4] = { 0x3E, 0x18, 0x00, 0x00 };
 469
 470 static u8 TS_I2SOutConfiguration[4] = { 0x80, 0x04, 0x00, 0x00 };
 471
 472 static u8 ITUDecoderSetup[4][16] = {
 473         {0x1c, 0x13, 0x01, 0x68, 0x3d, 0x90, 0x14, 0x20,  /* SDTV */
 474          0x00, 0x00, 0x01, 0xb0, 0x9c, 0x00, 0x00, 0x00},
 475         {0x9c, 0x03, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00,
 476          0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
 477         {0x9f, 0x00, 0x23, 0xC0, 0x60, 0x0F, 0x13, 0x00,  /* HDTV 1080i50 */
 478          0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
 479         {0x9c, 0x01, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00,  /* HDTV 1080i60 */
 480          0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
 481 };
 482
 483 /*
 484  * 50 48 60 gleich
 485  * 27p50 9f 00 22 80 42 69 18 ...
 486  * 27p60 93 00 22 80 82 69 1c ...
 487  */
 488
 489 /* Maxbyte to 1144 (for raw data) */
 490 static u8 ITUFeatureDecoderSetup[8] = {
 491         0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x04, 0x00
 492 };
 493
 494 void FillTSBuffer(void *Buffer, int Length, u32 Flags)
 495 {
 496         u32 *ptr = Buffer;
 497
 498         memset(Buffer, TS_FILLER, Length);
 499         while (Length > 0) {
 500                 if (Flags & DF_SWAP32)
 501                         *ptr = 0x471FFF10;
 502                 else
 503                         *ptr = 0x10FF1F47;
 504                 ptr += (188 / 4);
 505                 Length -= 188;
 506         }
 507 }
 508
 509
 510 static void flush_buffers(struct ngene_channel *chan)
 511 {
 512         u8 val;
 513
 514         do {
 515                 msleep(1);
 516                 spin_lock_irq(&chan->state_lock);
 517                 val = chan->nextBuffer->ngeneBuffer.SR.Flags & 0x80;
 518                 spin_unlock_irq(&chan->state_lock);
 519         } while (val);
 520 }
 521
 522 static void clear_buffers(struct ngene_channel *chan)
 523 {
 524         struct SBufferHeader *Cur = chan->nextBuffer;
 525
 526         do {
 527                 memset(&Cur->ngeneBuffer.SR, 0, sizeof(Cur->ngeneBuffer.SR));
 528                 if (chan->mode & NGENE_IO_TSOUT)
 529                         FillTSBuffer(Cur->Buffer1,
 530                                      chan->Capture1Length,
 531                                      chan->DataFormatFlags);
 532                 Cur = Cur->Next;
 533         } while (Cur != chan->nextBuffer);
 534
 535         if (chan->mode & NGENE_IO_TSOUT) {
 536                 chan->nextBuffer->ngeneBuffer.SR.DTOUpdate =
 537                         chan->AudioDTOValue;
 538                 chan->AudioDTOUpdated = 0;
 539
 540                 Cur = chan->TSIdleBuffer.Head;
 541
 542                 do {
 543                         memset(&Cur->ngeneBuffer.SR, 0,
 544                                sizeof(Cur->ngeneBuffer.SR));
 545                         FillTSBuffer(Cur->Buffer1,
 546                                      chan->Capture1Length,
 547                                      chan->DataFormatFlags);
 548                         Cur = Cur->Next;
 549                 } while (Cur != chan->TSIdleBuffer.Head);
 550         }
 551 }
 552
 553 static int ngene_command_stream_control(struct ngene *dev, u8 stream,
 554                                         u8 control, u8 mode, u8 flags)
 555 {
 556         struct device *pdev = &dev->pci_dev->dev;
 557         struct ngene_channel *chan = &dev->channel[stream];
 558         struct ngene_command com;
 559         u16 BsUVI = ((stream & 1) ? 0x9400 : 0x9300);
 560         u16 BsSDI = ((stream & 1) ? 0x9600 : 0x9500);
 561         u16 BsSPI = ((stream & 1) ? 0x9800 : 0x9700);
 562         u16 BsSDO = 0x9B00;
 563
 564         memset(&com, 0, sizeof(com));
 565         com.cmd.hdr.Opcode = CMD_CONTROL;
 566         com.cmd.hdr.Length = sizeof(struct FW_STREAM_CONTROL) - 2;
 567         com.cmd.StreamControl.Stream = stream | (control ? 8 : 0);
 568         if (chan->mode & NGENE_IO_TSOUT)
 569                 com.cmd.StreamControl.Stream |= 0x07;
 570         com.cmd.StreamControl.Control = control |
 571                 (flags & SFLAG_ORDER_LUMA_CHROMA);
 572         com.cmd.StreamControl.Mode = mode;
 573         com.in_len = sizeof(struct FW_STREAM_CONTROL);
 574         com.out_len = 0;
 575
 576         dev_dbg(pdev, "Stream=%02x, Control=%02x, Mode=%02x\n",
 577                 com.cmd.StreamControl.Stream, com.cmd.StreamControl.Control,
 578                 com.cmd.StreamControl.Mode);
 579
 580         chan->Mode = mode;
 581
 582         if (!(control & 0x80)) {
 583                 spin_lock_irq(&chan->state_lock);
 584                 if (chan->State == KSSTATE_RUN) {
 585                         chan->State = KSSTATE_ACQUIRE;
 586                         chan->HWState = HWSTATE_STOP;
 587                         spin_unlock_irq(&chan->state_lock);
 588                         if (ngene_command(dev, &com) < 0)
 589                                 return -1;
 590                         /* clear_buffers(chan); */
 591                         flush_buffers(chan);
 592                         return 0;
 593                 }
 594                 spin_unlock_irq(&chan->state_lock);
 595                 return 0;
 596         }
 597
 598         if (mode & SMODE_AUDIO_CAPTURE) {
 599                 com.cmd.StreamControl.CaptureBlockCount =
 600                         chan->Capture1Length / AUDIO_BLOCK_SIZE;
 601                 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
 602         } else if (mode & SMODE_TRANSPORT_STREAM) {
 603                 com.cmd.StreamControl.CaptureBlockCount =
 604                         chan->Capture1Length / TS_BLOCK_SIZE;
 605                 com.cmd.StreamControl.MaxLinesPerField =
 606                         chan->Capture1Length / TS_BLOCK_SIZE;
 607                 com.cmd.StreamControl.Buffer_Address =
 608                         chan->TSRingBuffer.PAHead;
 609                 if (chan->mode & NGENE_IO_TSOUT) {
 610                         com.cmd.StreamControl.BytesPerVBILine =
 611                                 chan->Capture1Length / TS_BLOCK_SIZE;
 612                         com.cmd.StreamControl.Stream |= 0x07;
 613                 }
 614         } else {
 615                 com.cmd.StreamControl.BytesPerVideoLine = chan->nBytesPerLine;
 616                 com.cmd.StreamControl.MaxLinesPerField = chan->nLines;
 617                 com.cmd.StreamControl.MinLinesPerField = 100;
 618                 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
 619
 620                 if (mode & SMODE_VBI_CAPTURE) {
 621                         com.cmd.StreamControl.MaxVBILinesPerField =
 622                                 chan->nVBILines;
 623                         com.cmd.StreamControl.MinVBILinesPerField = 0;
 624                         com.cmd.StreamControl.BytesPerVBILine =
 625                                 chan->nBytesPerVBILine;
 626                 }
 627                 if (flags & SFLAG_COLORBAR)
 628                         com.cmd.StreamControl.Stream |= 0x04;
 629         }
 630
 631         spin_lock_irq(&chan->state_lock);
 632         if (mode & SMODE_AUDIO_CAPTURE) {
 633                 chan->nextBuffer = chan->RingBuffer.Head;
 634                 if (mode & SMODE_AUDIO_SPDIF) {
 635                         com.cmd.StreamControl.SetupDataLen =
 636                                 sizeof(SPDIFConfiguration);
 637                         com.cmd.StreamControl.SetupDataAddr = BsSPI;
 638                         memcpy(com.cmd.StreamControl.SetupData,
 639                                SPDIFConfiguration, sizeof(SPDIFConfiguration));
 640                 } else {
 641                         com.cmd.StreamControl.SetupDataLen = 4;
 642                         com.cmd.StreamControl.SetupDataAddr = BsSDI;
 643                         memcpy(com.cmd.StreamControl.SetupData,
 644                                I2SConfiguration +
 645                                4 * dev->card_info->i2s[stream], 4);
 646                 }
 647         } else if (mode & SMODE_TRANSPORT_STREAM) {
 648                 chan->nextBuffer = chan->TSRingBuffer.Head;
 649                 if (stream >= STREAM_AUDIOIN1) {
 650                         if (chan->mode & NGENE_IO_TSOUT) {
 651                                 com.cmd.StreamControl.SetupDataLen =
 652                                         sizeof(TS_I2SOutConfiguration);
 653                                 com.cmd.StreamControl.SetupDataAddr = BsSDO;
 654                                 memcpy(com.cmd.StreamControl.SetupData,
 655                                        TS_I2SOutConfiguration,
 656                                        sizeof(TS_I2SOutConfiguration));
 657                         } else {
 658                                 com.cmd.StreamControl.SetupDataLen =
 659                                         sizeof(TS_I2SConfiguration);
 660                                 com.cmd.StreamControl.SetupDataAddr = BsSDI;
 661                                 memcpy(com.cmd.StreamControl.SetupData,
 662                                        TS_I2SConfiguration,
 663                                        sizeof(TS_I2SConfiguration));
 664                         }
 665                 } else {
 666                         com.cmd.StreamControl.SetupDataLen = 8;
 667                         com.cmd.StreamControl.SetupDataAddr = BsUVI + 0x10;
 668                         memcpy(com.cmd.StreamControl.SetupData,
 669                                TSFeatureDecoderSetup +
 670                                8 * dev->card_info->tsf[stream], 8);
 671                 }
 672         } else {
 673                 chan->nextBuffer = chan->RingBuffer.Head;
 674                 com.cmd.StreamControl.SetupDataLen =
 675                         16 + sizeof(ITUFeatureDecoderSetup);
 676                 com.cmd.StreamControl.SetupDataAddr = BsUVI;
 677                 memcpy(com.cmd.StreamControl.SetupData,
 678                        ITUDecoderSetup[chan->itumode], 16);
 679                 memcpy(com.cmd.StreamControl.SetupData + 16,
 680                        ITUFeatureDecoderSetup, sizeof(ITUFeatureDecoderSetup));
 681         }
 682         clear_buffers(chan);
 683         chan->State = KSSTATE_RUN;
 684         if (mode & SMODE_TRANSPORT_STREAM)
 685                 chan->HWState = HWSTATE_RUN;
 686         else
 687                 chan->HWState = HWSTATE_STARTUP;
 688         spin_unlock_irq(&chan->state_lock);
 689
 690         if (ngene_command(dev, &com) < 0)
 691                 return -1;
 692
 693         return 0;
 694 }
 695
 696 void set_transfer(struct ngene_channel *chan, int state)
 697 {
 698         struct device *pdev = &chan->dev->pci_dev->dev;
 699         u8 control = 0, mode = 0, flags = 0;
 700         struct ngene *dev = chan->dev;
 701         int ret;
 702
 703         /*
 704         dev_info(pdev, "st %d\n", state);
 705         msleep(100);
 706         */
 707
 708         if (state) {
 709                 if (chan->running) {
 710                         dev_info(pdev, "already running\n");
 711                         return;
 712                 }
 713         } else {
 714                 if (!chan->running) {
 715                         dev_info(pdev, "already stopped\n");
 716                         return;
 717                 }
 718         }
 719
 720         if (dev->card_info->switch_ctrl)
 721                 dev->card_info->switch_ctrl(chan, 1, state ^ 1);
 722
 723         if (state) {
 724                 spin_lock_irq(&chan->state_lock);
 725
 726                 /* dev_info(pdev, "lock=%08x\n",
 727                           ngreadl(0x9310)); */
 728                 dvb_ringbuffer_flush(&dev->tsout_rbuf);
 729                 control = 0x80;
 730                 if (chan->mode & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
 731                         chan->Capture1Length = 512 * 188;
 732                         mode = SMODE_TRANSPORT_STREAM;
 733                 }
 734                 if (chan->mode & NGENE_IO_TSOUT) {
 735                         chan->pBufferExchange = tsout_exchange;
 736                         /* 0x66666666 = 50MHz *2^33 /250MHz */
 737                         chan->AudioDTOValue = 0x80000000;
 738                         chan->AudioDTOUpdated = 1;
 739                 }
 740                 if (chan->mode & NGENE_IO_TSIN)
 741                         chan->pBufferExchange = tsin_exchange;
 742                 spin_unlock_irq(&chan->state_lock);
 743         }
 744                 /* else dev_info(pdev, "lock=%08x\n",
 745                            ngreadl(0x9310)); */
 746
 747         mutex_lock(&dev->stream_mutex);
 748         ret = ngene_command_stream_control(dev, chan->number,
 749                                            control, mode, flags);
 750         mutex_unlock(&dev->stream_mutex);
 751
 752         if (!ret)
 753                 chan->running = state;
 754         else
 755                 dev_err(pdev, "%s %d failed\n", __func__, state);
 756         if (!state) {
 757                 spin_lock_irq(&chan->state_lock);
 758                 chan->pBufferExchange = NULL;
 759                 dvb_ringbuffer_flush(&dev->tsout_rbuf);
 760                 spin_unlock_irq(&chan->state_lock);
 761         }
 762 }
 763
 764
 765 /****************************************************************************/
 766 /* nGene hardware init and release functions ********************************/
 767 /****************************************************************************/
 768
 769 static void free_ringbuffer(struct ngene *dev, struct SRingBufferDescriptor *rb)
 770 {
 771         struct SBufferHeader *Cur = rb->Head;
 772         u32 j;
 773
 774         if (!Cur)
 775                 return;
 776
 777         for (j = 0; j < rb->NumBuffers; j++, Cur = Cur->Next) {
 778                 if (Cur->Buffer1)
 779                         pci_free_consistent(dev->pci_dev,
 780                                             rb->Buffer1Length,
 781                                             Cur->Buffer1,
 782                                             Cur->scList1->Address);
 783
 784                 if (Cur->Buffer2)
 785                         pci_free_consistent(dev->pci_dev,
 786                                             rb->Buffer2Length,
 787                                             Cur->Buffer2,
 788                                             Cur->scList2->Address);
 789         }
 790
 791         if (rb->SCListMem)
 792                 pci_free_consistent(dev->pci_dev, rb->SCListMemSize,
 793                                     rb->SCListMem, rb->PASCListMem);
 794
 795         pci_free_consistent(dev->pci_dev, rb->MemSize, rb->Head, rb->PAHead);
 796 }
 797
 798 static void free_idlebuffer(struct ngene *dev,
 799                      struct SRingBufferDescriptor *rb,
 800                      struct SRingBufferDescriptor *tb)
 801 {
 802         int j;
 803         struct SBufferHeader *Cur = tb->Head;
 804
 805         if (!rb->Head)
 806                 return;
 807         free_ringbuffer(dev, rb);
 808         for (j = 0; j < tb->NumBuffers; j++, Cur = Cur->Next) {
 809                 Cur->Buffer2 = NULL;
 810                 Cur->scList2 = NULL;
 811                 Cur->ngeneBuffer.Address_of_first_entry_2 = 0;
 812                 Cur->ngeneBuffer.Number_of_entries_2 = 0;
 813         }
 814 }
 815
 816 static void free_common_buffers(struct ngene *dev)
 817 {
 818         u32 i;
 819         struct ngene_channel *chan;
 820
 821         for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
 822                 chan = &dev->channel[i];
 823                 free_idlebuffer(dev, &chan->TSIdleBuffer, &chan->TSRingBuffer);
 824                 free_ringbuffer(dev, &chan->RingBuffer);
 825                 free_ringbuffer(dev, &chan->TSRingBuffer);
 826         }
 827
 828         if (dev->OverflowBuffer)
 829                 pci_free_consistent(dev->pci_dev,
 830                                     OVERFLOW_BUFFER_SIZE,
 831                                     dev->OverflowBuffer, dev->PAOverflowBuffer);
 832
 833         if (dev->FWInterfaceBuffer)
 834                 pci_free_consistent(dev->pci_dev,
 835                                     4096,
 836                                     dev->FWInterfaceBuffer,
 837                                     dev->PAFWInterfaceBuffer);
 838 }
 839
 840 /****************************************************************************/
 841 /* Ring buffer handling *****************************************************/
 842 /****************************************************************************/
 843
 844 static int create_ring_buffer(struct pci_dev *pci_dev,
 845                        struct SRingBufferDescriptor *descr, u32 NumBuffers)
 846 {
 847         dma_addr_t tmp;
 848         struct SBufferHeader *Head;
 849         u32 i;
 850         u32 MemSize = SIZEOF_SBufferHeader * NumBuffers;
 851         u64 PARingBufferHead;
 852         u64 PARingBufferCur;
 853         u64 PARingBufferNext;
 854         struct SBufferHeader *Cur, *Next;
 855
 856         descr->Head = NULL;
 857         descr->MemSize = 0;
 858         descr->PAHead = 0;
 859         descr->NumBuffers = 0;
 860
 861         if (MemSize < 4096)
 862                 MemSize = 4096;
 863
 864         Head = pci_alloc_consistent(pci_dev, MemSize, &tmp);
 865         PARingBufferHead = tmp;
 866
 867         if (!Head)
 868                 return -ENOMEM;
 869
 870         memset(Head, 0, MemSize);
 871
 872         PARingBufferCur = PARingBufferHead;
 873         Cur = Head;
 874
 875         for (i = 0; i < NumBuffers - 1; i++) {
 876                 Next = (struct SBufferHeader *)
 877                         (((u8 *) Cur) + SIZEOF_SBufferHeader);
 878                 PARingBufferNext = PARingBufferCur + SIZEOF_SBufferHeader;
 879                 Cur->Next = Next;
 880                 Cur->ngeneBuffer.Next = PARingBufferNext;
 881                 Cur = Next;
 882                 PARingBufferCur = PARingBufferNext;
 883         }
 884         /* Last Buffer points back to first one */
 885         Cur->Next = Head;
 886         Cur->ngeneBuffer.Next = PARingBufferHead;
 887
 888         descr->Head       = Head;
 889         descr->MemSize    = MemSize;
 890         descr->PAHead     = PARingBufferHead;
 891         descr->NumBuffers = NumBuffers;
 892
 893         return 0;
 894 }
 895
 896 static int AllocateRingBuffers(struct pci_dev *pci_dev,
 897                                dma_addr_t of,
 898                                struct SRingBufferDescriptor *pRingBuffer,
 899                                u32 Buffer1Length, u32 Buffer2Length)
 900 {
 901         dma_addr_t tmp;
 902         u32 i, j;
 903         u32 SCListMemSize = pRingBuffer->NumBuffers
 904                 * ((Buffer2Length != 0) ? (NUM_SCATTER_GATHER_ENTRIES * 2) :
 905                     NUM_SCATTER_GATHER_ENTRIES)
 906                 * sizeof(struct HW_SCATTER_GATHER_ELEMENT);
 907
 908         u64 PASCListMem;
 909         struct HW_SCATTER_GATHER_ELEMENT *SCListEntry;
 910         u64 PASCListEntry;
 911         struct SBufferHeader *Cur;
 912         void *SCListMem;
 913
 914         if (SCListMemSize < 4096)
 915                 SCListMemSize = 4096;
 916
 917         SCListMem = pci_alloc_consistent(pci_dev, SCListMemSize, &tmp);
 918
 919         PASCListMem = tmp;
 920         if (SCListMem == NULL)
 921                 return -ENOMEM;
 922
 923         memset(SCListMem, 0, SCListMemSize);
 924
 925         pRingBuffer->SCListMem = SCListMem;
 926         pRingBuffer->PASCListMem = PASCListMem;
 927         pRingBuffer->SCListMemSize = SCListMemSize;
 928         pRingBuffer->Buffer1Length = Buffer1Length;
 929         pRingBuffer->Buffer2Length = Buffer2Length;
 930
 931         SCListEntry = SCListMem;
 932         PASCListEntry = PASCListMem;
 933         Cur = pRingBuffer->Head;
 934
 935         for (i = 0; i < pRingBuffer->NumBuffers; i += 1, Cur = Cur->Next) {
 936                 u64 PABuffer;
 937
 938                 void *Buffer = pci_alloc_consistent(pci_dev, Buffer1Length,
 939                                                     &tmp);
 940                 PABuffer = tmp;
 941
 942                 if (Buffer == NULL)
 943                         return -ENOMEM;
 944
 945                 Cur->Buffer1 = Buffer;
 946
 947                 SCListEntry->Address = PABuffer;
 948                 SCListEntry->Length  = Buffer1Length;
 949
 950                 Cur->scList1 = SCListEntry;
 951                 Cur->ngeneBuffer.Address_of_first_entry_1 = PASCListEntry;
 952                 Cur->ngeneBuffer.Number_of_entries_1 =
 953                         NUM_SCATTER_GATHER_ENTRIES;
 954
 955                 SCListEntry += 1;
 956                 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
 957
 958 #if NUM_SCATTER_GATHER_ENTRIES > 1
 959                 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j += 1) {
 960                         SCListEntry->Address = of;
 961                         SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
 962                         SCListEntry += 1;
 963                         PASCListEntry +=
 964                                 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
 965                 }
 966 #endif
 967
 968                 if (!Buffer2Length)
 969                         continue;
 970
 971                 Buffer = pci_alloc_consistent(pci_dev, Buffer2Length, &tmp);
 972                 PABuffer = tmp;
 973
 974                 if (Buffer == NULL)
 975                         return -ENOMEM;
 976
 977                 Cur->Buffer2 = Buffer;
 978
 979                 SCListEntry->Address = PABuffer;
 980                 SCListEntry->Length  = Buffer2Length;
 981
 982                 Cur->scList2 = SCListEntry;
 983                 Cur->ngeneBuffer.Address_of_first_entry_2 = PASCListEntry;
 984                 Cur->ngeneBuffer.Number_of_entries_2 =
 985                         NUM_SCATTER_GATHER_ENTRIES;
 986
 987                 SCListEntry   += 1;
 988                 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
 989
 990 #if NUM_SCATTER_GATHER_ENTRIES > 1
 991                 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j++) {
 992                         SCListEntry->Address = of;
 993                         SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
 994                         SCListEntry += 1;
 995                         PASCListEntry +=
 996                                 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
 997                 }
 998 #endif
 999
1000         }
1001
1002         return 0;
1003 }
1004
1005 static int FillTSIdleBuffer(struct SRingBufferDescriptor *pIdleBuffer,
1006                             struct SRingBufferDescriptor *pRingBuffer)
1007 {
1008         /* Copy pointer to scatter gather list in TSRingbuffer
1009            structure for buffer 2
1010            Load number of buffer
1011         */
1012         u32 n = pRingBuffer->NumBuffers;
1013
1014         /* Point to first buffer entry */
1015         struct SBufferHeader *Cur = pRingBuffer->Head;
1016         int i;
1017         /* Loop thru all buffer and set Buffer 2 pointers to TSIdlebuffer */
1018         for (i = 0; i < n; i++) {
1019                 Cur->Buffer2 = pIdleBuffer->Head->Buffer1;
1020                 Cur->scList2 = pIdleBuffer->Head->scList1;
1021                 Cur->ngeneBuffer.Address_of_first_entry_2 =
1022                         pIdleBuffer->Head->ngeneBuffer.
1023                         Address_of_first_entry_1;
1024                 Cur->ngeneBuffer.Number_of_entries_2 =
1025                         pIdleBuffer->Head->ngeneBuffer.Number_of_entries_1;
1026                 Cur = Cur->Next;
1027         }
1028         return 0;
1029 }
1030
1031 static u32 RingBufferSizes[MAX_STREAM] = {
1032         RING_SIZE_VIDEO,
1033         RING_SIZE_VIDEO,
1034         RING_SIZE_AUDIO,
1035         RING_SIZE_AUDIO,
1036         RING_SIZE_AUDIO,
1037 };
1038
1039 static u32 Buffer1Sizes[MAX_STREAM] = {
1040         MAX_VIDEO_BUFFER_SIZE,
1041         MAX_VIDEO_BUFFER_SIZE,
1042         MAX_AUDIO_BUFFER_SIZE,
1043         MAX_AUDIO_BUFFER_SIZE,
1044         MAX_AUDIO_BUFFER_SIZE
1045 };
1046
1047 static u32 Buffer2Sizes[MAX_STREAM] = {
1048         MAX_VBI_BUFFER_SIZE,
1049         MAX_VBI_BUFFER_SIZE,
1050         0,
1051         0,
1052         0
1053 };
1054
1055
1056 static int AllocCommonBuffers(struct ngene *dev)
1057 {
1058         int status = 0, i;
1059
1060         dev->FWInterfaceBuffer = pci_alloc_consistent(dev->pci_dev, 4096,
1061                                                      &dev->PAFWInterfaceBuffer);
1062         if (!dev->FWInterfaceBuffer)
1063                 return -ENOMEM;
1064         dev->hosttongene = dev->FWInterfaceBuffer;
1065         dev->ngenetohost = dev->FWInterfaceBuffer + 256;
1066         dev->EventBuffer = dev->FWInterfaceBuffer + 512;
1067
1068         dev->OverflowBuffer = pci_zalloc_consistent(dev->pci_dev,
1069                                                     OVERFLOW_BUFFER_SIZE,
1070                                                     &dev->PAOverflowBuffer);
1071         if (!dev->OverflowBuffer)
1072                 return -ENOMEM;
1073
1074         for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
1075                 int type = dev->card_info->io_type[i];
1076
1077                 dev->channel[i].State = KSSTATE_STOP;
1078
1079                 if (type & (NGENE_IO_TV | NGENE_IO_HDTV | NGENE_IO_AIN)) {
1080                         status = create_ring_buffer(dev->pci_dev,
1081                                                     &dev->channel[i].RingBuffer,
1082                                                     RingBufferSizes[i]);
1083                         if (status < 0)
1084                                 break;
1085
1086                         if (type & (NGENE_IO_TV | NGENE_IO_AIN)) {
1087                                 status = AllocateRingBuffers(dev->pci_dev,
1088                                                              dev->
1089                                                              PAOverflowBuffer,
1090                                                              &dev->channel[i].
1091                                                              RingBuffer,
1092                                                              Buffer1Sizes[i],
1093                                                              Buffer2Sizes[i]);
1094                                 if (status < 0)
1095                                         break;
1096                         } else if (type & NGENE_IO_HDTV) {
1097                                 status = AllocateRingBuffers(dev->pci_dev,
1098                                                              dev->
1099                                                              PAOverflowBuffer,
1100                                                              &dev->channel[i].
1101                                                              RingBuffer,
1102                                                            MAX_HDTV_BUFFER_SIZE,
1103                                                              0);
1104                                 if (status < 0)
1105                                         break;
1106                         }
1107                 }
1108
1109                 if (type & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1110
1111                         status = create_ring_buffer(dev->pci_dev,
1112                                                     &dev->channel[i].
1113                                                     TSRingBuffer, RING_SIZE_TS);
1114                         if (status < 0)
1115                                 break;
1116
1117                         status = AllocateRingBuffers(dev->pci_dev,
1118                                                      dev->PAOverflowBuffer,
1119                                                      &dev->channel[i].
1120                                                      TSRingBuffer,
1121                                                      MAX_TS_BUFFER_SIZE, 0);
1122                         if (status)
1123                                 break;
1124                 }
1125
1126                 if (type & NGENE_IO_TSOUT) {
1127                         status = create_ring_buffer(dev->pci_dev,
1128                                                     &dev->channel[i].
1129                                                     TSIdleBuffer, 1);
1130                         if (status < 0)
1131                                 break;
1132                         status = AllocateRingBuffers(dev->pci_dev,
1133                                                      dev->PAOverflowBuffer,
1134                                                      &dev->channel[i].
1135                                                      TSIdleBuffer,
1136                                                      MAX_TS_BUFFER_SIZE, 0);
1137                         if (status)
1138                                 break;
1139                         FillTSIdleBuffer(&dev->channel[i].TSIdleBuffer,
1140                                          &dev->channel[i].TSRingBuffer);
1141                 }
1142         }
1143         return status;
1144 }
1145
1146 static void ngene_release_buffers(struct ngene *dev)
1147 {
1148         if (dev->iomem)
1149                 iounmap(dev->iomem);
1150         free_common_buffers(dev);
1151         vfree(dev->tsout_buf);
1152         vfree(dev->tsin_buf);
1153         vfree(dev->ain_buf);
1154         vfree(dev->vin_buf);
1155         vfree(dev);
1156 }
1157
1158 static int ngene_get_buffers(struct ngene *dev)
1159 {
1160         if (AllocCommonBuffers(dev))
1161                 return -ENOMEM;
1162         if (dev->card_info->io_type[4] & NGENE_IO_TSOUT) {
1163                 dev->tsout_buf = vmalloc(TSOUT_BUF_SIZE);
1164                 if (!dev->tsout_buf)
1165                         return -ENOMEM;
1166                 dvb_ringbuffer_init(&dev->tsout_rbuf,
1167                                     dev->tsout_buf, TSOUT_BUF_SIZE);
1168         }
1169         if (dev->card_info->io_type[2]&NGENE_IO_TSIN) {
1170                 dev->tsin_buf = vmalloc(TSIN_BUF_SIZE);
1171                 if (!dev->tsin_buf)
1172                         return -ENOMEM;
1173                 dvb_ringbuffer_init(&dev->tsin_rbuf,
1174                                     dev->tsin_buf, TSIN_BUF_SIZE);
1175         }
1176         if (dev->card_info->io_type[2] & NGENE_IO_AIN) {
1177                 dev->ain_buf = vmalloc(AIN_BUF_SIZE);
1178                 if (!dev->ain_buf)
1179                         return -ENOMEM;
1180                 dvb_ringbuffer_init(&dev->ain_rbuf, dev->ain_buf, AIN_BUF_SIZE);
1181         }
1182         if (dev->card_info->io_type[0] & NGENE_IO_HDTV) {
1183                 dev->vin_buf = vmalloc(VIN_BUF_SIZE);
1184                 if (!dev->vin_buf)
1185                         return -ENOMEM;
1186                 dvb_ringbuffer_init(&dev->vin_rbuf, dev->vin_buf, VIN_BUF_SIZE);
1187         }
1188         dev->iomem = ioremap(pci_resource_start(dev->pci_dev, 0),
1189                              pci_resource_len(dev->pci_dev, 0));
1190         if (!dev->iomem)
1191                 return -ENOMEM;
1192
1193         return 0;
1194 }
1195
1196 static void ngene_init(struct ngene *dev)
1197 {
1198         struct device *pdev = &dev->pci_dev->dev;
1199         int i;
1200
1201         tasklet_init(&dev->event_tasklet, event_tasklet, (unsigned long)dev);
1202
1203         memset_io(dev->iomem + 0xc000, 0x00, 0x220);
1204         memset_io(dev->iomem + 0xc400, 0x00, 0x100);
1205
1206         for (i = 0; i < MAX_STREAM; i++) {
1207                 dev->channel[i].dev = dev;
1208                 dev->channel[i].number = i;
1209         }
1210
1211         dev->fw_interface_version = 0;
1212
1213         ngwritel(0, NGENE_INT_ENABLE);
1214
1215         dev->icounts = ngreadl(NGENE_INT_COUNTS);
1216
1217         dev->device_version = ngreadl(DEV_VER) & 0x0f;
1218         dev_info(pdev, "Device version %d\n", dev->device_version);
1219 }
1220
1221 static int ngene_load_firm(struct ngene *dev)
1222 {
1223         struct device *pdev = &dev->pci_dev->dev;
1224         u32 size;
1225         const struct firmware *fw = NULL;
1226         u8 *ngene_fw;
1227         char *fw_name;
1228         int err, version;
1229
1230         version = dev->card_info->fw_version;
1231
1232         switch (version) {
1233         default:
1234         case 15:
1235                 version = 15;
1236                 size = 23466;
1237                 fw_name = "/*(DEBLOBBED)*/";
1238                 dev->cmd_timeout_workaround = true;
1239                 break;
1240         case 16:
1241                 size = 23498;
1242                 fw_name = "/*(DEBLOBBED)*/";
1243                 dev->cmd_timeout_workaround = true;
1244                 break;
1245         case 17:
1246                 size = 24446;
1247                 fw_name = "/*(DEBLOBBED)*/";
1248                 dev->cmd_timeout_workaround = true;
1249                 break;
1250         case 18:
1251                 size = 0;
1252                 fw_name = "/*(DEBLOBBED)*/";
1253                 break;
1254         }
1255
1256         if (reject_firmware(&fw, fw_name, &dev->pci_dev->dev) < 0) {
1257                 dev_err(pdev, "Could not load firmware file %s.\n", fw_name);
1258                 dev_info(pdev, "Copy %s to your hotplug directory!\n",
1259                          fw_name);
1260                 return -1;
1261         }
1262         if (size == 0)
1263                 size = fw->size;
1264         if (size != fw->size) {
1265                 dev_err(pdev, "Firmware %s has invalid size!", fw_name);
1266                 err = -1;
1267         } else {
1268                 dev_info(pdev, "Loading firmware file %s.\n", fw_name);
1269                 ngene_fw = (u8 *) fw->data;
1270                 err = ngene_command_load_firmware(dev, ngene_fw, size);
1271         }
1272
1273         release_firmware(fw);
1274
1275         return err;
1276 }
1277
1278 static void ngene_stop(struct ngene *dev)
1279 {
1280         mutex_destroy(&dev->cmd_mutex);
1281         i2c_del_adapter(&(dev->channel[0].i2c_adapter));
1282         i2c_del_adapter(&(dev->channel[1].i2c_adapter));
1283         ngwritel(0, NGENE_INT_ENABLE);
1284         ngwritel(0, NGENE_COMMAND);
1285         ngwritel(0, NGENE_COMMAND_HI);
1286         ngwritel(0, NGENE_STATUS);
1287         ngwritel(0, NGENE_STATUS_HI);
1288         ngwritel(0, NGENE_EVENT);
1289         ngwritel(0, NGENE_EVENT_HI);
1290         free_irq(dev->pci_dev->irq, dev);
1291 #ifdef CONFIG_PCI_MSI
1292         if (dev->msi_enabled)
1293                 pci_disable_msi(dev->pci_dev);
1294 #endif
1295 }
1296
1297 static int ngene_buffer_config(struct ngene *dev)
1298 {
1299         int stat;
1300
1301         if (dev->card_info->fw_version >= 17) {
1302                 u8 tsin12_config[6]   = { 0x60, 0x60, 0x00, 0x00, 0x00, 0x00 };
1303                 u8 tsin1234_config[6] = { 0x30, 0x30, 0x00, 0x30, 0x30, 0x00 };
1304                 u8 tsio1235_config[6] = { 0x30, 0x30, 0x00, 0x28, 0x00, 0x38 };
1305                 u8 *bconf = tsin12_config;
1306
1307                 if (dev->card_info->io_type[2]&NGENE_IO_TSIN &&
1308                     dev->card_info->io_type[3]&NGENE_IO_TSIN) {
1309                         bconf = tsin1234_config;
1310                         if (dev->card_info->io_type[4]&NGENE_IO_TSOUT &&
1311                             dev->ci.en)
1312                                 bconf = tsio1235_config;
1313                 }
1314                 stat = ngene_command_config_free_buf(dev, bconf);
1315         } else {
1316                 int bconf = BUFFER_CONFIG_4422;
1317
1318                 if (dev->card_info->io_type[3] == NGENE_IO_TSIN)
1319                         bconf = BUFFER_CONFIG_3333;
1320                 stat = ngene_command_config_buf(dev, bconf);
1321         }
1322         return stat;
1323 }
1324
1325
1326 static int ngene_start(struct ngene *dev)
1327 {
1328         int stat;
1329         int i;
1330
1331         pci_set_master(dev->pci_dev);
1332         ngene_init(dev);
1333
1334         stat = request_irq(dev->pci_dev->irq, irq_handler,
1335                            IRQF_SHARED, "nGene",
1336                            (void *)dev);
1337         if (stat < 0)
1338                 return stat;
1339
1340         init_waitqueue_head(&dev->cmd_wq);
1341         init_waitqueue_head(&dev->tx_wq);
1342         init_waitqueue_head(&dev->rx_wq);
1343         mutex_init(&dev->cmd_mutex);
1344         mutex_init(&dev->stream_mutex);
1345         sema_init(&dev->pll_mutex, 1);
1346         mutex_init(&dev->i2c_switch_mutex);
1347         spin_lock_init(&dev->cmd_lock);
1348         for (i = 0; i < MAX_STREAM; i++)
1349                 spin_lock_init(&dev->channel[i].state_lock);
1350         ngwritel(1, TIMESTAMPS);
1351
1352         ngwritel(1, NGENE_INT_ENABLE);
1353
1354         stat = ngene_load_firm(dev);
1355         if (stat < 0)
1356                 goto fail;
1357
1358 #ifdef CONFIG_PCI_MSI
1359         /* enable MSI if kernel and card support it */
1360         if (pci_msi_enabled() && dev->card_info->msi_supported) {
1361                 struct device *pdev = &dev->pci_dev->dev;
1362                 unsigned long flags;
1363
1364                 ngwritel(0, NGENE_INT_ENABLE);
1365                 free_irq(dev->pci_dev->irq, dev);
1366                 stat = pci_enable_msi(dev->pci_dev);
1367                 if (stat) {
1368                         dev_info(pdev, "MSI not available\n");
1369                         flags = IRQF_SHARED;
1370                 } else {
1371                         flags = 0;
1372                         dev->msi_enabled = true;
1373                 }
1374                 stat = request_irq(dev->pci_dev->irq, irq_handler,
1375                                         flags, "nGene", dev);
1376                 if (stat < 0)
1377                         goto fail2;
1378                 ngwritel(1, NGENE_INT_ENABLE);
1379         }
1380 #endif
1381
1382         stat = ngene_i2c_init(dev, 0);
1383         if (stat < 0)
1384                 goto fail;
1385
1386         stat = ngene_i2c_init(dev, 1);
1387         if (stat < 0)
1388                 goto fail;
1389
1390         return 0;
1391
1392 fail:
1393         ngwritel(0, NGENE_INT_ENABLE);
1394         free_irq(dev->pci_dev->irq, dev);
1395 #ifdef CONFIG_PCI_MSI
1396 fail2:
1397         if (dev->msi_enabled)
1398                 pci_disable_msi(dev->pci_dev);
1399 #endif
1400         return stat;
1401 }
1402
1403 /****************************************************************************/
1404 /****************************************************************************/
1405 /****************************************************************************/
1406
1407 static void release_channel(struct ngene_channel *chan)
1408 {
1409         struct dvb_demux *dvbdemux = &chan->demux;
1410         struct ngene *dev = chan->dev;
1411
1412         if (chan->running)
1413                 set_transfer(chan, 0);
1414
1415         tasklet_kill(&chan->demux_tasklet);
1416
1417         if (chan->ci_dev) {
1418                 dvb_unregister_device(chan->ci_dev);
1419                 chan->ci_dev = NULL;
1420         }
1421
1422         if (chan->fe2)
1423                 dvb_unregister_frontend(chan->fe2);
1424
1425         if (chan->fe) {
1426                 dvb_unregister_frontend(chan->fe);
1427
1428                 /* release I2C client (tuner) if needed */
1429                 if (chan->i2c_client_fe) {
1430                         dvb_module_release(chan->i2c_client[0]);
1431                         chan->i2c_client[0] = NULL;
1432                 }
1433
1434                 dvb_frontend_detach(chan->fe);
1435                 chan->fe = NULL;
1436         }
1437
1438         if (chan->has_demux) {
1439                 dvb_net_release(&chan->dvbnet);
1440                 dvbdemux->dmx.close(&dvbdemux->dmx);
1441                 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
1442                                               &chan->hw_frontend);
1443                 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
1444                                               &chan->mem_frontend);
1445                 dvb_dmxdev_release(&chan->dmxdev);
1446                 dvb_dmx_release(&chan->demux);
1447                 chan->has_demux = false;
1448         }
1449
1450         if (chan->has_adapter) {
1451                 dvb_unregister_adapter(&dev->adapter[chan->number]);
1452                 chan->has_adapter = false;
1453         }
1454 }
1455
1456 static int init_channel(struct ngene_channel *chan)
1457 {
1458         int ret = 0, nr = chan->number;
1459         struct dvb_adapter *adapter = NULL;
1460         struct dvb_demux *dvbdemux = &chan->demux;
1461         struct ngene *dev = chan->dev;
1462         struct ngene_info *ni = dev->card_info;
1463         int io = ni->io_type[nr];
1464
1465         tasklet_init(&chan->demux_tasklet, demux_tasklet, (unsigned long)chan);
1466         chan->users = 0;
1467         chan->type = io;
1468         chan->mode = chan->type;        /* for now only one mode */
1469         chan->i2c_client_fe = 0;        /* be sure this is set to zero */
1470
1471         if (io & NGENE_IO_TSIN) {
1472                 chan->fe = NULL;
1473                 if (ni->demod_attach[nr]) {
1474                         ret = ni->demod_attach[nr](chan);
1475                         if (ret < 0)
1476                                 goto err;
1477                 }
1478                 if (chan->fe && ni->tuner_attach[nr]) {
1479                         ret = ni->tuner_attach[nr](chan);
1480                         if (ret < 0)
1481                                 goto err;
1482                 }
1483         }
1484
1485         if (!dev->ci.en && (io & NGENE_IO_TSOUT))
1486                 return 0;
1487
1488         if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1489                 if (nr >= STREAM_AUDIOIN1)
1490                         chan->DataFormatFlags = DF_SWAP32;
1491
1492                 if (nr == 0 || !one_adapter || dev->first_adapter == NULL) {
1493                         adapter = &dev->adapter[nr];
1494                         ret = dvb_register_adapter(adapter, "nGene",
1495                                                    THIS_MODULE,
1496                                                    &chan->dev->pci_dev->dev,
1497                                                    adapter_nr);
1498                         if (ret < 0)
1499                                 goto err;
1500                         if (dev->first_adapter == NULL)
1501                                 dev->first_adapter = adapter;
1502                         chan->has_adapter = true;
1503                 } else
1504                         adapter = dev->first_adapter;
1505         }
1506
1507         if (dev->ci.en && (io & NGENE_IO_TSOUT)) {
1508                 dvb_ca_en50221_init(adapter, dev->ci.en, 0, 1);
1509                 set_transfer(chan, 1);
1510                 chan->dev->channel[2].DataFormatFlags = DF_SWAP32;
1511                 set_transfer(&chan->dev->channel[2], 1);
1512                 dvb_register_device(adapter, &chan->ci_dev,
1513                                     &ngene_dvbdev_ci, (void *) chan,
1514                                     DVB_DEVICE_SEC, 0);
1515                 if (!chan->ci_dev)
1516                         goto err;
1517         }
1518
1519         if (chan->fe) {
1520                 if (dvb_register_frontend(adapter, chan->fe) < 0)
1521                         goto err;
1522                 chan->has_demux = true;
1523         }
1524         if (chan->fe2) {
1525                 if (dvb_register_frontend(adapter, chan->fe2) < 0)
1526                         goto err;
1527                 if (chan->fe) {
1528                         chan->fe2->tuner_priv = chan->fe->tuner_priv;
1529                         memcpy(&chan->fe2->ops.tuner_ops,
1530                                &chan->fe->ops.tuner_ops,
1531                                sizeof(struct dvb_tuner_ops));
1532                 }
1533         }
1534
1535         if (chan->has_demux) {
1536                 ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux",
1537                                               ngene_start_feed,
1538                                               ngene_stop_feed, chan);
1539                 ret = my_dvb_dmxdev_ts_card_init(&chan->dmxdev, &chan->demux,
1540                                                  &chan->hw_frontend,
1541                                                  &chan->mem_frontend, adapter);
1542                 ret = dvb_net_init(adapter, &chan->dvbnet, &chan->demux.dmx);
1543         }
1544
1545         return ret;
1546
1547 err:
1548         if (chan->fe) {
1549                 dvb_frontend_detach(chan->fe);
1550                 chan->fe = NULL;
1551         }
1552         release_channel(chan);
1553         return 0;
1554 }
1555
1556 static int init_channels(struct ngene *dev)
1557 {
1558         int i, j;
1559
1560         for (i = 0; i < MAX_STREAM; i++) {
1561                 dev->channel[i].number = i;
1562                 if (init_channel(&dev->channel[i]) < 0) {
1563                         for (j = i - 1; j >= 0; j--)
1564                                 release_channel(&dev->channel[j]);
1565                         return -1;
1566                 }
1567         }
1568         return 0;
1569 }
1570
1571 static const struct cxd2099_cfg cxd_cfgtmpl = {
1572         .bitrate = 62000,
1573         .polarity = 0,
1574         .clock_mode = 0,
1575 };
1576
1577 static void cxd_attach(struct ngene *dev)
1578 {
1579         struct device *pdev = &dev->pci_dev->dev;
1580         struct ngene_ci *ci = &dev->ci;
1581         struct cxd2099_cfg cxd_cfg = cxd_cfgtmpl;
1582         struct i2c_client *client;
1583         int ret;
1584         u8 type;
1585
1586         /* check for CXD2099AR presence before attaching */
1587         ret = ngene_port_has_cxd2099(&dev->channel[0].i2c_adapter, &type);
1588         if (!ret) {
1589                 dev_dbg(pdev, "No CXD2099AR found\n");
1590                 return;
1591         }
1592
1593         if (type != 1) {
1594                 dev_warn(pdev, "CXD2099AR is uninitialized!\n");
1595                 return;
1596         }
1597
1598         cxd_cfg.en = &ci->en;
1599         client = dvb_module_probe("cxd2099", NULL,
1600                                   &dev->channel[0].i2c_adapter,
1601                                   0x40, &cxd_cfg);
1602         if (!client)
1603                 goto err;
1604
1605         ci->dev = dev;
1606         dev->channel[0].i2c_client[0] = client;
1607         return;
1608
1609 err:
1610         dev_err(pdev, "CXD2099AR attach failed\n");
1611         return;
1612 }
1613
1614 static void cxd_detach(struct ngene *dev)
1615 {
1616         struct ngene_ci *ci = &dev->ci;
1617
1618         dvb_ca_en50221_release(ci->en);
1619
1620         dvb_module_release(dev->channel[0].i2c_client[0]);
1621         dev->channel[0].i2c_client[0] = NULL;
1622         ci->en = NULL;
1623 }
1624
1625 /***********************************/
1626 /* workaround for shutdown failure */
1627 /***********************************/
1628
1629 static void ngene_unlink(struct ngene *dev)
1630 {
1631         struct ngene_command com;
1632
1633         com.cmd.hdr.Opcode = CMD_MEM_WRITE;
1634         com.cmd.hdr.Length = 3;
1635         com.cmd.MemoryWrite.address = 0x910c;
1636         com.cmd.MemoryWrite.data = 0xff;
1637         com.in_len = 3;
1638         com.out_len = 1;
1639
1640         mutex_lock(&dev->cmd_mutex);
1641         ngwritel(0, NGENE_INT_ENABLE);
1642         ngene_command_mutex(dev, &com);
1643         mutex_unlock(&dev->cmd_mutex);
1644 }
1645
1646 void ngene_shutdown(struct pci_dev *pdev)
1647 {
1648         struct ngene *dev = pci_get_drvdata(pdev);
1649
1650         if (!dev || !shutdown_workaround)
1651                 return;
1652
1653         dev_info(&pdev->dev, "shutdown workaround...\n");
1654         ngene_unlink(dev);
1655         pci_disable_device(pdev);
1656 }
1657
1658 /****************************************************************************/
1659 /* device probe/remove calls ************************************************/
1660 /****************************************************************************/
1661
1662 void ngene_remove(struct pci_dev *pdev)
1663 {
1664         struct ngene *dev = pci_get_drvdata(pdev);
1665         int i;
1666
1667         tasklet_kill(&dev->event_tasklet);
1668         for (i = MAX_STREAM - 1; i >= 0; i--)
1669                 release_channel(&dev->channel[i]);
1670         if (dev->ci.en)
1671                 cxd_detach(dev);
1672         ngene_stop(dev);
1673         ngene_release_buffers(dev);
1674         pci_disable_device(pdev);
1675 }
1676
1677 int ngene_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
1678 {
1679         struct ngene *dev;
1680         int stat = 0;
1681
1682         if (pci_enable_device(pci_dev) < 0)
1683                 return -ENODEV;
1684
1685         dev = vzalloc(sizeof(struct ngene));
1686         if (dev == NULL) {
1687                 stat = -ENOMEM;
1688                 goto fail0;
1689         }
1690
1691         dev->pci_dev = pci_dev;
1692         dev->card_info = (struct ngene_info *)id->driver_data;
1693         dev_info(&pci_dev->dev, "Found %s\n", dev->card_info->name);
1694
1695         pci_set_drvdata(pci_dev, dev);
1696
1697         /* Alloc buffers and start nGene */
1698         stat = ngene_get_buffers(dev);
1699         if (stat < 0)
1700                 goto fail1;
1701         stat = ngene_start(dev);
1702         if (stat < 0)
1703                 goto fail1;
1704
1705         cxd_attach(dev);
1706
1707         stat = ngene_buffer_config(dev);
1708         if (stat < 0)
1709                 goto fail1;
1710
1711
1712         dev->i2c_current_bus = -1;
1713
1714         /* Register DVB adapters and devices for both channels */
1715         stat = init_channels(dev);
1716         if (stat < 0)
1717                 goto fail2;
1718
1719         return 0;
1720
1721 fail2:
1722         ngene_stop(dev);
1723 fail1:
1724         ngene_release_buffers(dev);
1725 fail0:
1726         pci_disable_device(pci_dev);
1727         return stat;
1728 }